Datasheet ADG1234 Datasheet (ANALOG DEVICES)

Low Capacitance, Triple/Quad SPDT

FEATURES

1.5 pF off capacitance

0.5 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP
Typical power consumption (<0.03 μW)

APPLICATIONS

Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems

±15 V/+12 V i CMOS™ Switches

ADG1233/ADG1234

FUNCTIONAL BLOCK DIAGRAMS

S1A

D1

S1B

S2B

D2

S2A

SWITCHES SHOWN FO R A LOGIC 1 INPUT

S1A

D1

S1B

ADG1233

LOGIC

IN2IN1 IN3

Figure 1.

ADG1234

EN

S3B

D3

S3A

S4A

D4

S4B

05743-001

GENERAL DESCRIPTION

The ADG1233 and ADG1234 are monolithic iCMOS analog
switches comprising three independently selectable single-pole,
double throw SPDT switches and four independently selectable
SPDT switches, respectively.

All channels exhibit break-before-make switching action
preventing momentary shorting when switching channels.

EN

An

input on the ADG1233 and ADG1234 is used to
enable or disable the device. When disabled, all channels are
switched off.

The iCMOS (industrial-CMOS) modular manufacturing process
combines a high voltage complementary metal-oxide semi­conductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation of
high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor­mance, dramatically lowered power consumption, and reduced
package size.

The ultralow capacitance and charge injection of these multiplexers
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.

S2B

D2

S2A

LOGIC

IN2IN1 IN3

SWITCHES SHOWN FO R A LOGIC 1 INPUT

IN4

Figure 2.

EN

S3B

D3

S3A

05743-038

Fast switching speed coupled with high signal bandwidth make the
parts suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the parts ideally
suited for portable and battery-powered instruments.

PRODUCT HIGHLIGHTS

1. 1.5 pF off capacitance (±15 V supply).

2. 0.5 pC charge injection.

3. 3 V logic-compatible digital input, V

4. 16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.

= 2.0 V, VIL = 0.8 V.

IH

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2009 Analog Devices, Inc. All rights reserved.

ADG1233/ADG1234

TABLE OF CONTENTS

Features .............................................................................................. 1

Absolute Maximum Ratings ............................................................7

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagrams ............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 5

REVISION HISTORY

2/09—Rev. A to Rev. B

Change to I
Change to I

Updated Outline Dimensions ....................................................... 16

8/06—Rev. 0 to Rev. A

Updated Format…………………………….….…………Universal
Changes to Table 1…………………………………………….…...3

Changes to Table 2………………………………………………....4

Changes to Figure 11……………………..………………………10
Changes to Figure 12……………………………………………..11

Parameter, Table 1 ................................................... 4

DD

Parameter, Table 2 ................................................... 6

DD

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions ............................8

Terminology .......................................................................................9

Typical Performance Characteristics ........................................... 10

Test Circuits ..................................................................................... 13

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 16

1/06—Revision 0: Initial Version

Rev. B | Page 2 of 16

ADG1233/ADG1234

SPECIFICATIONS

DUAL SUPPLY

VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Y Version

Parameter

ANALOG SWITCH

Analog Signal Range VSS to VDD V
On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 24
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between

Channels (∆R

)

ON

3.5 Ω typ V

6 10 12 Ω max
On Resistance Flatness (R

) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA

FLAT (ON)

60 72 79 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage IS (Off) ±0.02 nA typ VD = ±10 V, VS = −10 V; see Figure 25
±0.1 ±0.6 ±1 nA max
Drain Off Leakage ID (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = ±10 V; see Figure 26
±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V

2.0 V min

INH

0.8 V max

INL

Input Current
I

or I

±0.005 μA typ VIN = V

INL

INH

±0.1 μA max
Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS

t

110 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

2

130 150 170 ns max VS = 10 V; see Figure 27
t

25 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min VS1 = VS2 = +10 V; see Figure 28

tON (EN) 120 ns typ RL = 300 Ω, CL = 35 pF

140 170 195 ns max VS = 10 V; see Figure 29

t

(EN) 40 ns typ RL = 300 Ω, CL = 35 pF

OFF

45 55 60 ns max VS = 10 V; see Figure 29
Charge Injection 0.5 pC typ

Off Isolation −80 dB typ

Channel-to-Channel Crosstalk −85 dB typ

Total Harmonic Distortion, THD + N 0.14 % typ

−3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 32
CS (Off) 1.5 pF typ f = 1 MHz; VS = 0 V

1.7 pF max f = 1 MHz; VS = 0 V
CD (Off) 1.6 pF typ f = 1 MHz; VS = 0 V

1.8 pF max f = 1 MHz; VS = 0 V
CD, CS (On) 3.5 pF typ f = 1 MHz; VS = 0 V
4 pF max f = 1 MHz; VS = 0 V

1

Unit Test Conditions/Comments +25°C −40°C to +85°C −40°C to +125°C

= ±10 V, IS = −1 mA

S

V

= 1 V/10 V, VD = 10 V/1 V;

S

see Figure 25

V

= 0 V, RS = 0 Ω, CL = 1 nF;

S

see Figure 30
R

= 50 Ω, CL = 5 pF, f = 1 MHz; see

L

Figure 31
R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

see Figure 33
R

= 10 kΩ, 5 V rms, f = 20 Hz to

L

20 kHz; see Figure 34

INL

or V

INH

Rev. B | Page 3 of 16

ADG1233/ADG1234

Y Version

Parameter

1

Unit Test Conditions/Comments +25°C −40°C to +85°C −40°C to +125°C

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 260 μA typ Digital inputs = 5 V
475 μA max
ISS 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
ISS 0.002 μA typ Digital inputs = 5 V

1.0 μA max
VDD/VSS ±5/±16.5 V min/max GND = 0 V

1

Temperature range for the Y version: −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

Rev. B | Page 4 of 16

ADG1233/ADG1234

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Y Version
Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range 0 to VDD V
On Resistance (RON) 300 Ω typ

475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between

Channels (∆R

)

ON

5 Ω typ V

16 26 27 Ω max
On Resistance Flatness (R

) 60 Ω typ VS = 3 V, 6 V, 9 V, IS = −1 mA

FLAT (ON)

LEAKAGE CURRENTS VDD = 13.2 V

Source Off Leakage IS (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Drain Off Leakage ID (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V, see Figure 26
±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

±0.001 μA typ

INH

±0.1 μA max VIN = V

Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS

t

135 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

2

170 200 230 VS = 8 V; see Figure 27
t

45 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min VS1 = V

tON (EN) 150 ns typ RL = 300 Ω, CL = 35 pF
195 230 265 VS = 8 V; see Figure 29
t

(EN) 45 ns typ RL = 300 Ω, CL = 35 pF

OFF

60 70 75 VS = 8 V; see Figure 29

Charge Injection −0.3 pC typ

Off Isolation −80 dB typ

Channel-to-Channel Crosstalk −85 dB typ

−3 dB Bandwidth 600 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 32
CS (Off) 1.5 pF typ f = 1 MHz; VS = 6 V

1.7 pF max f = 1 MHz; VS = 6 V
CD (Off) 2 pF typ f = 1 MHz; VS = 6 V

2.2 pF max f = 1 MHz; VS = 6 V
CD, CS (On) 4 pF typ f = 1 MHz; VS = 6 V

4.5 pF max f = 1 MHz; VS = 6 V

1

V

= 0 V to 10 V, IS = −1 mA;

S

see Figure 24

= 0 V to 10 V, IS = −1 mA

S

V

= 1 V/10 V, VD = 10 V/1 V;

S

see Figure 25

V

= 1 V/10 V, VD = 10 V/1 V;

S

see Figure 25

V

= 6 V, RS = 0 Ω, CL = 1 nF; see

S

Figure 30
R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

see Figure 31
R

= 50 Ω, CL = 5 pF, f = 1 MHz;

L

see Figure 33

or V

INL

S2

INH

= 8 V; see Figure 28

Rev. B | Page 5 of 16

ADG1233/ADG1234

Y Version

1

Parameter +25°C −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 260 μA typ Digital inputs = 5 V

475 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range for the Y version: −40°C to +125°C

2

Guaranteed by design, not subject to production test.

Rev. B | Page 6 of 16

ADG1233/ADG1234

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

V

to VSS 35 V

DD

VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Analog, Digital Inputs1

Continuous Current, S or D 24 mA
Peak Current, S or D (Pulsed at

1 ms, 10% Duty Cycle Maximum)

Operating Temperature Range

Automotive Temperature Range

(Y Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP, θJA, Thermal Impedance 112°C/W
LFCSP, θJA, Thermal Impedance 30.4°C/W
Reflow Soldering Peak Temperature,

Pb-Fee

1

Overvoltages at A,
be limited to the maximum ratings given.

EN

, S, or D are clamped by internal diodes. Current should

− 0.3 V to VDD + 0.3 V or

V

SS

30 mA, whichever occurs
first

100 mA

−40°C to +125°C

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating is applied at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 16

ADG1233/ADG1234

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD

2

S1A

3

D1

ADG1233

TOP VIEW

4

S1B

(Not to Scale)

5

S2B

6

D2

7

S2A

8

IN2 IN3

16

GND

15

IN1

14

EN

13

V

SS

12

S3B

11

D3

10

S3A

9

05743-002

Figure 3. 16-Lead TSSOP Pin Configuration

1D1

2S1B

3S2B

4D2

Figure 5. 16-Lead, 4 mm × 4 mm LFCSP Pin Configuration,

Exposed Pad Tied to Substrate, V

DD

S1A

V

GND

14

16

15

PIN 1
INDICAT OR

ADG1233

TOP VIEW

(Not to Scal e)

7

5

6

IN2

IN3

S2A

IN1

13

12 EN

11 V

SS

10 S3B

9D3

8

S3A

05743-004

SS

IN1

S1A

D1

S1B

V

GND

S2B

D2

S2A

IN2

SS

1

2

3

ADG1234

4

(Not to Scale)

5

6

7

8

9

10

TOP VIEW

20

IN4

19

S4A

18

D4

17

S4B

16

V

DD

15

EN

14

S3B

13

D3

12

S3A

11

IN3

05743-003

Figure 4. 20-Lead TSSOP Pin Configuration

Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations

Pin No. ADG1233
16-Lead TSSOP

Pin No. ADG1234
20-Lead TSSOP Mnemonic

1 16 VDD
2 2 S1A
3 3 D1
4 4 S1B
5 7 S2B
6 8 D2
7 9 S2A
8 10 IN2
9 11 IN3
10 12 S3A
11 13 D3
12 14 S3B
13 5 VSS
14 15 EN

15 1 IN1
16 6 GND
N/A 17 S4B
N/A 18 D4
N/A 19 S4A
N/A 20 IN4

Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations

Pin No. ADG1233
16-Lead LFCSP

1 1 D1
2 2 S1B
3 5
4 6
5 7
6 8
7 9
8 10
9 11
10 12
11 3
12 18

13 19 IN1
14 4
15 13
16 20
N/A 14
N/A 15
N/A 16
N/A 17 IN4

EN

IN1

S1A

IN4

S4A

17

16

18

19

20

PIN 1

SS

1D1
2S1B
3V
4GND
5S2B

INDICATOR

ADG1234

TOP VIEW

(Not to Scale)

8

6

7

D2

IN2

S2A

15 D4
14 S4B
13 V

DD

12 S3B
11 D3

9

10
3
IN

S3A

05743-005

Figure 6. 20-Lead, 4 mm × 4 mm LFCSP Pin Configuration,

Exposed Pad Tied to Substrate, V

SS

Pin No. ADG1234
20-Lead LFCSP Mnemonic

S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN

GND
VDD
S1A
S4B
D4
S4A

Table 6. ADG1233/ADG1234 Truth Table

EN

1 X Off Off
0 0 Off On
0 1 On Off

Rev. B | Page 8 of 16

INx Switch xA Switch xB

ADG1233/ADG1234

TERMINOLOGY

VDD

Most positive supply potential.

V

SS

Most negative power supply potential in dual supplies. In
single-supply applications, it can be connected to ground.

GND

Ground (0 V) reference.

R

ON

Ohmic resistance between D and S.

ΔR

ON

Difference between the R

(Off)

I

S

of any two channels.

ON

Source leakage current when switch is off.

I

(Off)

D

Drain leakage current when switch is off.

I

, IS (On)

D

Channel leakage current when switch is on.

V

D, VS

Analog voltage on Terminal D, Terminal S.

C

(Off)

S

Channel input capacitance for off condition.

C

(Off)

D

Channel output capacitance for off condition.

C

, CS (On)

D

On switch capacitance.

C

IN

Digital input capacitance.

t

(EN)

ON

Delay time between the 50% and 90% points of the digital input
and switch on condition.

(EN)

t

OFF

Delay time between the 50% and 90% points of the digital input
and switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

t

BBM

Off time measured between the 80% point of both switches
when switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

I

, I

INL

INH

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of an unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Bandwidth

Frequency at which the output is attenuated by 3 dB.

On Response

Frequency response of the on switch.

THD + N

Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.

Rev. B | Page 9 of 16

ADG1233/ADG1234

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA = 25°C

180

160

140

120

100

80

ON RESISTANCE (Ω)

60

40

20

0

–18 –15 –12 –9 –6 –3 12 1590631

VDD = +13.5V
V

= –13.5V

SS

VDD = +16.5V
V

SS

SOURCE OR DRAIN VO LTAGE (V)

Figure 7. On Resistance as a Function of V

600

TA = 25°C

500

400

300

200

ON RESISTANCE (Ω)

VDD = 5.5V
V

= –5.5V

SS

VDD = 4.5V
V

SS

VDD = +15V
V

= –15V

SS

= –16.5V

(VS ) for Dual Supply

D

= –4.5V

VDD = 5V
V

= –5V

SS

05743-031

8

250

200

150

100

ON RESISTANCE (Ω)

50

0

–15 –10 –5 1005

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

TEMPERATURE ( °C)

Figure 10. On Resistance as a Function of V

Temperatures, Dual Supply

600

500

400

300

200

ON RESISTANCE (Ω)

TA = +125°C

TA = –40°C

VDD = +15V
V

= –15V

SS

(VS ) for Different

D

VDD = 12V
V

= 0V

SS

TA = +85°C

TA = +25°C

05743-034

15

100

0

–6 –4 –2 402

Figure 8. On Resistance as a Function of V

450

TA = 25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

02 46 12810 1

Figure 9. On Resistance as a Function of V

SOURCE OR DRAIN VO LTAGE (V)

(VS ) for Dual Supply

D

VDD = 10.8V
V

= 0V

SS

VDD = 12V
V

= 0V

SS

VDD = 13.2V
V

= 0V

SS

SOURCE OR DRAIN VO LTAGE (V)

(VS ) for Single Supply

D

05743-032

6

05743-033

4

100

0

024 1068

TEMPERATURE ( °C)

Figure 11. On Resistance as a Function of V

(VS ) for Different

D

05743-035

12

Temperatures, Single Supply

250

VDD = +15V

200

V

= –15V

SS

V

= +10V/–10V

BIAS

150

100

50

0

–50

(OFF) + –

–100

LEAKAGE CURRENT ( pA)

–150

–200

–250

I

S

ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +

0 20406080100120

TEMPERATURE (°C)

05743-017

Figure 12. Leakage Currents as a Function of Temperature, Dual Supply

Rev. B | Page 10 of 16

ADG1233/ADG1234

–

130

VDD = 12V
V

= 0V

SS

V

= 1V/10V

BIAS

80

30

–20

(OFF) + –

I

LEAKAGE CURRENT ( pA)

–70

–120

S

ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +

0 20406080100120

TEMPERATURE (°C)

Figure 13. Leakage Currents as a Function of Temperature, Single Supply

200

180

160

140

120

(µA)

100

DD

I

80

60

40

20

0

VDD = +15V
V

= –15V

SS

VDD = 12V
V

= 0V

SS

0 2 4 6 8 10121416

LOGIC, INX (V)

IDD PER CHANNEL
T

= 25°C

A

05743-018

05743-006

220

A

200

180

160

140

120

100

TIME (ns)

80

60

40

20

0

–40 –20 200 40 60 80 100 120

0

–10

–20

–30

–40

–50

–60

–70

OFF ISOLATIO N (dB)

–80

–90

–100

–110

10k 100k 1M 10M 100M 1G

Figure 16. t

VDD = +15V
V

= –15V

SS

T

= 25°C

A

A

OFF BON

15V DS

B

12V DS

OFF AON

TEMPERATURE (°C)

vs. Temperature

TRANSITION

FREQUENCY (Hz)

OFF BON

B

12V DS

OFF AON

15V DS

05743-011

05743-036

Figure 14. I

6

TA = 25°C

4

2

0

–2

CHARGE INJECTIO N (pC)

–4

–6

–15 –10 –5 0 15105

vs. Log ic Level

DD

VDD = +5V
V

SS

Figure 15. Charge Injection vs. Source Voltage

= –5V

VS (V)

VDD = +15V

= –15V

V

SS

VDD = 12V

= 0V

V

SS

Figure 17. Off Isolation vs. Frequency

10

–20

–30

–40

–50

–60

CROSSTALK (dB)

–70

–80

–90

05743-008

–100

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

SxA – SxB

S1x – S2x

VDD = +15V

= –15V

V

SS

= 25°C

T

A

05743-012

Figure 18. Cross talk vs. Frequen cy

Rev. B | Page 11 of 16

ADG1233/ADG1234

0

–5

–10

–15

ON RESPONSE (dB)

–20

–25

10k 100 k 1M 10M 100M 10G1G

FREQUENCY (Hz)

Figure 19. On Response vs. Frequency

10

LOAD = 10kΩ

= 25°C

T

A

1

VDD = +5V, VSS = –5V, VS = +3.5V rms

THD + N (%)

0.10

0.01

VDD = +15V, VSS = –15V, VS = +5V rms

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 20. THD + N vs. Frequency

5.0

4.5

4.0

3.5

3.0

2.5

2.0

CAPACITANCE (pF )

1.5

1.0

0.5

0

–15 –10 –5 0 15105

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

BIAS

(V)

VDD = +15V
V
T

Figure 21. Capacitance vs. Source Voltage for Dual Supply

VDD = +15V

= –15V

V

SS

= 25°C

T

A

= –15V

SS

= 25°C

A

05743-013

05743-037

05743-010

5.0

4.5

4.0

3.5

3.0

2.5

2.0

CAPACITANCE (pF )

1.5

1.0

0.5

0

024 6 810

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

BIAS

(V)

VDD = 12V

= 0V

V

SS

= 25°C

T

A

Figure 22. Capacitance vs. Source Voltage for Single Supply

5.0

4.5

4.0

3.5

3.0

2.5

2.0

CAPACITANCE (pF )

1.5

1.0

0.5

0

–5 –4 –2–3 –1 0 1 2 3 4 5

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

VDD = +5V
V

SS

T

A

Figure 23. Capacitance vs. Source Voltage for Dual Supply

= –5V

= 25°C

05743-009

12

05743-007

Rev. B | Page 12 of 16

ADG1233/ADG1234

V

VDDV

V

TEST CIRCUITS

V

SD

I

V

S

Figure 24. On Resistance

IS (OFF) ID (OFF)

SD

A A

DS

05743-020

S

V

D

05743-021

Figure 25. Off Leakage

SD

NC

NC = NO CONNECT

ID(ON)

A

V

D

05743-022

Figure 26. On Leakage

SS

0.1µF0.1µF

V

V

DD

SS

SxB

V

S

SxA

INx

V

IN

GND

D

R

L

300Ω

C

L

35pF

V

OUT

V

IN

V

IN

V

OUT

t

50%

50%

90%

ON

50%

50%

90%

t

OFF

05743-023

Figure 27. Switching Timing

V

DD

SS

0.1µF0.1µF

V

V

V

DD

SS

V

V

SxB

S

SxA

INx

IN

GND

D

R

L

300Ω

C

L

35pF

V

OUT

IN

80%

V

OUT

t

BBM

t

BBM

05743-024

Figure 28. Break-Before-Make Delay

Rev. B | Page 13 of 16

ADG1233/ADG1234

VDDV

VDDV

V

V

V

V

SS

0.1µF0.1µF

3V

V

V

DD

SS

IN3
IN2
IN1

S1A

S1B

V

S

ADG1233

GND

D1

R

L

300Ω

V

EN

IN

50Ω

Figure 29. Enable Delay, t

C

L

35pF

V

O

ENABLE

DRIVE (V

OUTPUT

)

IN

50%

50%

0V

t

(EN)

V

O

0V

(EN), t

OFF

(EN)

ON

0.9V

O

t

(EN)

ON

0.9V

OFF

O

05743-025

SS

0.1µF0.1µF

VIN(NORMALLY

NC

V

OUT

CLOSED SWITCH)

VIN(NORMALLY
OPEN SWITCH)

V

OUT

ΔV

OUT

ON

Q

= C

× ΔV

L

INJ

OUT

OFF

0.1µF

05743-026

V

DD

SS

0.1µF

0.1µF

V

V

DD

SS

GND

SxB

SxA

C
1nF

L

D

V

S

INx

V

IN

Figure 30. Charge Injection

V

DD

SS

0.1µF

V

DD

INx

V

IN

SxA

GND

DD

0.1µF

V

DD

INx

V

IN

SxA

GND

INSERTION LOSS = 20 log

V

SS

NC

SxB

50Ω

D

OFF ISOLATION = 20 log

Figure 31. Off Isolation

V

SS

0.1µF

V

SS

NC

SxB

D

WITH SWITCH

V

OUT

WITHOUT SWITCH

V

OUT

Figure 32. Bandwidth

NETWORK
ANALYZER

50Ω

V

S

V

OUT

R

L

50Ω

V

OUT

V

S

05743-027

NETWO RK

ANALYZER

V

OUT

R
50Ω

L

V

SxA

SxB

V

S

INx

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

V

DD

SS

D

R
50Ω

GND

V

OUT

V

S

05743-029

Figure 33. Channel-to-Channel Crosstalk

V

NETWORK

ANALYZER

50Ω

V

OUT

R

L

50Ω

DD

0.1µF

V

V

S

05743-028

INx

V

IN

SS

0.1µF

V

DD

SS

AUDIO PRECISIO N

R

S

S

V

S

V p-p

V

OUT

05743-030

GND

D

R

L

10Ω

Figure 34. THD + Noise

Rev. B | Page 14 of 16

ADG1233/ADG1234

Y

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARIT

0.10

20

1

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AC

Figure 36. 20-Lead Thin Shrink Small Outline Package [TSSOP]

11

4.50

4.40

4.30

6.40 BSC

0.20

0.09

1.20 MAX

10

SEATING
PLANE

(RU-20)

Dimensions shown in millimeters

8°
0°

0.75

0.60

0.45

Rev. B | Page 15 of 16

ADG1233/ADG1234

PIN 1

INDICATOR

12° MAX

1.00

0.85

0.80

BSC SQ

SEATING
PLANE

4.00

0.60 MAX

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.35

0.30

0.25

3.75

BSC SQ

0.20 REF

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

0.60 MAX

(BOTTO M VIEW )

13

12

9

8

1.95 BSC

PIN 1

16

5

FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.

INDICATOR

1

4

5

2

.

2

0

1

.

2

S

9

.

1

5

0.25 MIN

Q

072808-A

Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

INDI

CATO R

1.00

0.85

0.80

SEATING

PLANE

PIN 1

4.00

12° MAX

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT

TO

0.60 MAX

3.75

BCS SQ

0.05 MAX

0.02 NOM
CO

0.20 REF

JEDEC STANDARDS MO-220-VGGD-1

Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

0.50

BSC

0.75

0.60

0.50

PLANARITY

0.08

0.60 MAX

15

16

10

11

20

EXPOSED

PAD

(BOTTOM VIEW)

6

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.

1

P

N

I

R

C

I

A

O

T

N

I

2.25

2.10 SQ

1.95

0.25 MIN

D

012508-B

1

5

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1233YRUZ
ADG1233YRUZ-REEL7
ADG1233YCPZ-REEL
ADG1233YCPZ-REEL7
ADG1234YRUZ
ADG1234YRUZ-REEL7
ADG1234YCPZ-REEL
ADG1234YCPZ-REEL7

1

Z = RoHS Compliant Part.

©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05743-0-2/09(B)

1

1

1

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4

1

−40°C to +125°C 16-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-4

−40°C to +125°C 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20

1

−40°C to +125°C 20-Lead Thin Shrink Small Outline Package (TSSOP) RU-20

−40°C to +125°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20-1

1

−40°C to +125°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20-1

Rev. B | Page 16 of 16