Datasheet ADG1211, ADG1212, ADG1213 Datasheet (ANALOG DEVICES)

查询ADG1211供应商

Low Capacitance, Low Charge Injection,

±15 V/+12 V iCMOS™ Quad SPST Switches

FEATURES

1 pF off capacitance

2.6 pF on capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V

supply required

No V

L

3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 16-lead LFCSP
Typical power consumption: <0.03 μW

APPLICATIONS

Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems

GENERAL DESCRIPTION

The ADG1211/ADG1212/ADG1213 are monolithic complemen­tary metal-oxide semiconductor (CMOS) devices containing
four independently selectable switches designed on an iCMOS
(industrial CMOS) process. iCMOS is a modular manufacturing
process combining high voltage CMOS and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lower power consumption,
and reduced package size.

The ultralow capacitance and charge injection of these switches
make them ideal solutions for data acquisition and sample-and­hold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth make
the parts suitable for video signal switching.

ADG1211/ADG1212/ADG1213

FUNCTIONAL BLOCK DIAGRAM

IN1

IN2

IN3

IN4

ADG1211

S1

IN1

D1
S2

IN2

D2
S3

D3
S4

D4

SWITCHES SHOWN FOR A LOGIC 1 INPUT

ADG1212

IN3

IN4

Figure 1.

S1

IN1

D1
S2

IN2

D2
S3

D3
S4

D4

ADG1213

IN3

IN4

iCMOS construction ensures ultralow power dissipation,
making the parts ideally suited for portable and battery­powered instruments.

The ADG1211/ADG1212/ADG1213 contain four independent
single-pole/single-throw (SPST) switches. The ADG1211 and
ADG1212 differ only in that the digital control logic is inverted.
The ADG1211 switches are turned on with Logic 0 on the
appropriate control input, while Logic 1 is required for the
ADG1212. The ADG1213 has two switches with digital control
logic similar to that of the ADG1211; the logic is inverted on
the other two switches. The ADG1213 exhibits break-before­make switching action for use in multiplexer applications.

Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.

PRODUCT HIGHLIGHTS

1. Ultralow capacitance.

2. <1 pC charge injection.

3. 3 V logic-compatible digital inputs: V

4. No V

logic power supply required.

L

5. Ultralow power dissipation: <0.03 μW.

6. 16-lead TSSOP and 3 mm × 3 mm LFCSP packages.

= 2.0 V, VIL = 0.8 V.

IH

S1

D1
S2

D2
S3

D3
S4

D4

04778-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADG1211/ADG1212/ADG1213

TABLE OF CONTENTS

Specifications..................................................................................... 3

Te r mi n ol o g y .......................................................................................8

Dual Supply ................................................................................... 3

Single Supply ................................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

REVISION HISTORY

7/05—Revision 0: Initial Version

Typical Perfor m a n c e Charac t e r isti c s ..............................................9

Test Ci r cu it s ..................................................................................... 12

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

ADG1211/ADG1212/ADG1213

SPECIFICATIONS

DUAL SUPPLY

VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

Y Version

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range VDD to V
On Resistance (RON) 120 Ω typ VS = ±10 V, IS = −1 mA; Figure 20
190 230 260 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between

Channels (∆R

)

ON

2.5 Ω typ VS = ±10 V, IS = −1 mA

6 10 11 Ω max

On Resistance Flatness (R

) 20 Ω typ VS = −5 V/0 V/+5 V; IS = −1 mA

FLAT(ON)

57 72 79 Ω max
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V

Source Off Leakage, IS (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ

±0.1 ±0.6 ±1 nA max

Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V; Figure 22
±0.1 ±0.6 ±1 nA max
DIGITAL INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

INH

0.005 μA typ VIN = V
±0.1 μA max
Digital Input Capacitance, C

IN

2.5 pF typ

DYNAMIC CHARACTERISTICS2

tON 105 ns typ RL = 300 Ω, CL = 35 pF
125 160 185 ns max VS = 10 V; Figure 23
t

40 ns typ RL = 300 Ω, CL = 35 pF

OFF

50 60 60 ns max VS = 10 V; Figure 23
Break-Before-Make Time Delay, tD25 ns typ RL = 300 Ω, CL = 35 pF

(ADG1213 Only) 10 ns min VS1 = VS2 = 10 V; Figure 24
Charge Injection −0.3 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26
Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
Total Harmonic Distortion + Noise 0.15 % typ RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz

−3 dB Bandwidth 1000 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
CS (Off) 0.9 pF typ VS = 0 V, f = 1 MHz

1.1 pF max VS = 0 V, f = 1 MHz
CD (Off) 1 pF typ VS = 0 V, f = 1 MHz

1.2 pF max VS = 0 V, f = 1 MHz
CD, CS (On) 2.6 pF typ VS = 0 V, f = 1 MHz
3 pF max VS = 0 V, f = 1 MHz

1

−40°C to
+125°C

Unit Test Conditions/Comments

V

SS

VS = ±10 V, VD = ∓10 V; Figure 21

VS = ±10 V, VD = ∓10 V; Figure 21

or V

INL

INH

Rev. 0 | Page 3 of 16

ADG1211/ADG1212/ADG1213

Y Version

−40°C to

Parameter 25°C

+85°C

1

−40°C to
+125°C

Unit Test Conditions/Comments

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 220 μA typ Digital inputs = 5 V
320 μA max
ISS 0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
I

SS

0.001 μA typ Digital inputs = 5 V

1.0 μA max

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

Rev. 0 | Page 4 of 16

ADG1211/ADG1212/ADG1213

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.

Table 2.

Y Version

−40°C to

Parameter 25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 V to V
On Resistance (RON) 300 Ω typ VS = 0 V to 10 V, IS = −1 mA; Figure 20
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between

Channels (∆R

)

ON

4.5 Ω typ V

12 26 27 Ω max

On Resistance Flatness (R

) 60 Ω typ VS = 3 V/6 V/9 V, IS = −1 mA

FLAT(ON)

LEAKAGE CURRENTS VDD = 13.2 V, VSS = 0 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
±0.1 ±0.6 ±1 nA max

Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V; Figure 22
±0.1 ±0.6 ±1 nA max
DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

INH

0.001 μA typ VIN = V

±0.1 μA max

Digital Input Capacitance, C

IN

3 pF typ

DYNAMIC CHARACTERISTICS2

t

ON

120 ns typ RL = 300 Ω, CL = 35 pF
155 190 225 ns max VS = 8 V; Figure 23
t

45 ns typ RL = 300 Ω, CL = 35 pF

OFF

65 75 85 ns max VS = 8 V; Figure 23
Break-Before-Make Time Delay, tD 50 ns typ RL = 300 Ω, CL = 35 pF

(ADG1213 Only) 10 ns min VS1 = VS2 = 8 V; Figure 24
Charge Injection 0 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25
Off Isolation 80 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26
Channel-to-Channel Crosstalk 90 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27

−3 dB Bandwidth 900 MHz typ RL = 50 Ω, CL = 5 pF; Figure 28
CS (Off) 1.2 pF typ VS = 6 V, f = 1 MHz

1.4 pF max VS = 6 V, f = 1 MHz
CD (Off) 1.3 pF typ VS = 6 V, f = 1 MHz

1.5 pF max VS = 6 V, f = 1 MHz
CD, CS (On) 3.2 pF typ VS = 6 V, f = 1 MHz

3.9 pF max VS = 6 V, f = 1 MHz

POWER REQUIREMENTS VDD = 13.2 V

I

DD

0.001 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 220 μA typ Digital inputs = 5 V
320 μA max

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

1

−40°C to
+125°C

Unit Test Conditions/Comments

V

DD

= 0 V to 10 V, IS = −1 mA

S

or V

INH

INL

Rev. 0 | Page 5 of 16

ADG1211/ADG1212/ADG1213

ABSOLUTE MAXIMUM RATINGS

T = 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

V to V 35 V

DD SS

V to GND −0.3 V to +25 V

DD

V to GND +0.3 V to −25 V

SS

Analog Inputs

Digital Inputs

Peak Current, S or D

Continuous Current per

Channel, S or D

Operating Temperature Range

Automotive (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead TSSOP, θJA Thermal

Impedance (4-Layer Board)
16-Lead LFCSP, θJA Thermal

Impedance
Reflow Soldering Peak

Temperature, Pb free

1

Overvoltages at IN, S, or D are clamped by internal diodes. Current should be

limited to the maximum ratings given.

1

V – 0.3 V to V

SS DD

+ 0.3 V or

30 mA, whichever occurs first

1

GND – 0.3 V to V

+ 0.3 V or

DD

30 mA, whichever occurs first
100 mA (pulsed at 1 ms,

10% duty cycle max)
25 mA

112°C/W

72.7°C/W

260°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

Table 4. ADG1211/ADG1212 Truth Table

ADG1211 INx ADG1212 INx Switch Condition

0 1 On
1 0 Off

Table 5. ADG1213 Truth Table

ADG1213 INx Switch 1, 4 Switch 2, 3

0 Off On
1 On Off

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 16

ADG1211/ADG1212/ADG1213

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

ADG1211/ADG1212/ADG1213

IN1

D2

D1

IN2

13

14

15

16

1

IN1

2

D1

3

S1

ADG1211/

4

V

GND

ADG1212/

SS

ADG1213

5

TOP VIEW

6

S4

7

D4

8

IN4 IN3

NC = NO CONNECT

16

IN2

15

D2

14

S2

13

V

DD

12

NC

11

S3

10

D3

9

04788-002

SS

NOTES

1. EXPOSED PAD TIED TO SUBSTRATE, V

Figure 2. TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP LFCSP

Mnemonic

Description

1 15 IN1 Logic Control Input.
2 16 D1 Drain Terminal. Can be an input or output.
3 1 S1 Source Terminal. Can be an input or output.
4 2 V

SS

Most Negative Power Supply Potential.
5 3 GND Ground (0 V) Reference.
6 4 S4 Source Terminal. Can be an input or output.
7 5 D4 Drain Terminal. Can be an input or output.
8 6 IN4 Logic Control Input.
9 7 IN3 Logic Control Input.
10 8 D3 Drain Terminal. Can be an input or output.
11 9 S3 Source Terminal. Can be an input or output.
12 10 NC No Connection.
13 11 V

DD

Most Positive Power Supply Potential.
14 12 S2 Source Terminal. Can be an input or output.
15 13 D2 Drain Terminal. Can be an input or output.
16 14 IN2 Logic Control Input.

PIN 1
INDICATOR

1S1
2V
3GND

TOP VIEW

(Not to Scale)

4S4

5

6

D4

IN4

NC = NO CONNECT

12 S2
11 V

DD

10 NC
9S3

8

7
3

D3

IN

Figure 3. LFCSP Pin Configuration

.

SS

04778-003

Rev. 0 | Page 7 of 16

ADG1211/ADG1212/ADG1213

TERMINOLOGY

IDD

The positive supply current.

, CS (On)

C

D

The on switch capacitance, measured with reference to ground.

I

SS

The negative supply current.

(VS)

V

D

The analog voltage on Terminals D and S.

R

ON

The ohmic resistance between D and S.

R

FLAT(ON)

Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.

(Off)

I

S

The source leakage current with the switch off.

(Off)

I

D

The drain leakage current with the switch off.

, IS (On)

I

D

The channel leakage current with the switch on.

V

INL

The maximum input voltage for Logic 0.

V

INH

The minimum input voltage for Logic 1.

(I

INL

INH

)

I

The input current of the digital input.

(Off)

C

S

The off switch source capacitance, measured with reference
to ground.

(Off)

C

D

The off switch drain capacitance, measured with reference
to ground.

C

IN

The digital input capacitance.

t

ON

The delay between applying the digital control input and the
output switching on. See

t

OFF

Figure 23.

The delay between applying the digital control input and the
output switching off. See

Figure 23.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Off Isolation

A measure of unwanted signal coupling through an off switch.

Crosstalk

A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

Insertion Loss

The loss due to the on resistance of the switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

Rev. 0 | Page 8 of 16

ADG1211/ADG1212/ADG1213

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA = +25°C

180

160

140
120

100

80

ON RESISTANCE (Ω)

60
40

20

0

–18–15–12–9–6–33 9150 6 12 18

Figure 4. On Resistance as a Function of V Figure 7. On Resistance as a Function of V

VDD = +13.5V
V

= –13.5V

SS

VDD = +15V
V

= –15V

SS

SOURCE OR DRAIN VOLTAGE (V)

VDD = +16.5V
V

= –16.5V

SS

(V ) for Dual Supply (V

D S D S

04778-008

250

VDD = +15V

= –15V

V

SS

200

150

100

ON RESISTANCE (Ω)

50

0

–15 –10 –5 0 5 10 15

TA = +125°C

TA = +85°C

TA = –40°C

SOURCE OR DRAIN VOLTAGE (V)

TA = +25°C

) for Different Temperatures,

Dual Supply

04778-006

450

TA = +25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

–5 –4 –3 –2 –1 2 401 3 5

SOURCE OR DRAIN VOLTAGE (V)

Figure 5. On Resistance as a Function of V Figure 8. On Resistance as a Function of V

VDD = +5.5V

= –5.5V

V

SS

04778-004

(V ) for Dual Supply (V

D S D S

600

VDD = +12V

= 0V

V

SS

500

TA = +85°C

400

300

200

ON RESISTANCE (Ω)

100

0

02468101

TA = –40°C

SOURCE OR DRAIN VOLTAGE (V)

Single Supply

450

TA = 25°C

400

VDD = 10.8V

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

= 0V

V

SS

VDD = 13.2V

= 0V

V

SS

0

024681012

SOURCE OR DRAIN VOLTAGE (V)

Figure 6. On Resistance as a Function of V

VDD = 12V

= 0V

V

SS

(V ) for Single Supply

D S

04778-005

0.20
VDD = +15V

= –15V

V

SS

–0.05

LEAKAGE (nA)

–0.10

–0.15

–0.20

0.15

0.10

0.05

0

= +10V/–10V

V

BIAS

200 40 60 80 100 120

TEMPERATURE (°C)

Figure 9. Leakage Currents as a Function of Temperature, Dual Supply

TA = +125°C

TA = +25°C

) for Different Temperatures,

ID, IS (ON)

ID (OFF)

IS (OFF)

04778-007

2

04778-012

Rev. 0 | Page 9 of 16

ADG1211/ADG1212/ADG1213

0.30
VDD = 12V

= 0V

V

SS

0.25

0.20

0.15

0.10

0.05

LEAKAGE (nA)

–0.05

–0.10

Figure 10. Leakage Currents as a Function of Temperature, Single Supply

= 1V/10V

V

BIAS

ID, IS (ON)

IS (OFF)

0

ID (OFF)

200 40 60 80 100 120

TEMPERATURE (°C)

200

180

12V SS T

OFF

ON

15V DS T

15V DS T

ON

OFF

160
140

120
100

TIME (ns)

80

60
40

20

04778-013

0

–40 –20 40200 60 80 100 120

Figure 13. T

ON

12V SS T

TEMPERATURE (°C)

/T Times vs. Temperature

OFF

04778-016

60

50

40

30

(μA)

DD

I

20

10

0

0 2 4 6 8 10 12 14

6

4

2

0

–2

CHARGE INJECTION (pC)

–4

–6

–15 –10 –5 0 5 10 15

VDD = +12V, VSS = 0V

Figure 11. I

SOURCE TO DRAIN
DRAIN TO SOURCE
T

= +25°C

A

VDD = +5V, VSS = –5V

VDD = +15V, VSS = –15V

LOGIC, INX (V)

vs. Log ic Level

DD

VS (V)

IDD PER CHANNEL
T

= +25°C

A

VDD = +15V, VSS = –15V

VDD = +12V, VSS = 0V

Figure 12. Charge Injection vs. Source Voltage

04778-011

04778-015

0

VDD = +15V

–10

V

= –15V

SS

T

= +25°C

A

–20
–30
–40
–50
–60
–70

OFF ISOLATION (dB)

–80
–90

–100
–110

10k 100k 1M 10M 100M 1G

FREQUENCY (Hz)

Figure 14. Off Isolation vs. Frequency

0

VDD = +15V

–10

V

= –15V

SS

T

= +25°C

–20

A

–30
–40
–50
–60
–70

CROSSTALK (dB)

–80

–90
–100
–110

–120

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 15. Cross talk vs. Frequency

04778-017

04778-018

Rev. 0 | Page 10 of 16

ADG1211/ADG1212/ADG1213

0

VDD = +15V
V

= –15V

SS

T

= +25°C

A

–5

–10

–15

–20

ATTENUATIOIN (dB)

–25

–30

10k 100k 1M 10M 1G100M 10G

FREQUENCY (Hz)

Figure 16. On Response vs. Frequency

04778-019

3.0
SOURCE/DRAIN ON

VDD = +15V

2.5

V

= –15V

SS

T

= +25°C

A

2.0

1.5

CAPACITANCE (pF)

1.0

0.5

–10 –8 –6 –4 –2 0 2 4 6 8 10

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

Figure 18. Capacitance vs. Source Voltage, Dual Supply

04778-031

10.00
LOAD = +10kΩ

T

= +25°C

A

1.00
VDD = +5V, VSS = –5V, VS = +3.5Vrms

THD+N (%)

0.10

0.01

VDD = +15V, VSS = –15V, VS = +5Vrms

10 100 1k 10k 100k

FREQUENCY (Hz)

Figure 17. THD + N vs. Frequency

04778-029

4.0
VDD = 12V

V

= 0V

SS

3.5
T

= 25°C

A

3.0

2.5

2.0

1.5

CAPACITANCE (pF)

1.0

0.5

0

024 68101

DRAIN OFF

SOURCE OFF

SOURCE/DRAIN ON

V

(V)

BIAS

Figure 19. Capacitance vs. Source Voltage, Single Supply

04778-030

2

Rev. 0 | Page 11 of 16

ADG1211/ADG1212/ADG1213

V

V

V

TEST CIRCUITS

I

DS

V1

SD

IS (OFF) ID (OFF)

SD

A A

SD

NC

ID (ON)

A

V

S

RON = V1/I

DS

04778-020

S

V

D

04778-021

NC = NO CONNECT

Figure 20. Test Circuit 1—On Resistance Figure 21. Test Circuit 2—Off Leakage Figure 22. Test Circuit 3—On Leakage

V

V

DD

SS

0.1μF

V

DD

SD

V

S

IN

GND

0.1μF

ADG1212

V

V

SS

V

OUT

R
300Ω

C

L

L

35pF

IN

V

IN

V

OUT

ADG1211

50% 50%

50% 50%

90% 90%

t

ON

t

OFF

04778-023

Figure 23. Test Circuit 4—Switching Times

V

V

DD

SS

0.1μF

V

DD

IN1,
IN2

S1 D1

S2 D2

ADG1213

GND

S1

S2

0.1μF

V

SS

V

OUT1

C

R

L

300Ω

C

L

35pF

V

OUT2

R
300Ω

L

L

35pF

Figure 24. Test Circuit 5—Break-Before-Make Time Delay

V

V

V

OUT1

OUT2

IN

0V

0V

0V

50% 50%

90%

90%

t

D

t

D

90%

90%

V

D

04778-024

04778-022

V

V

DD

SS

V

V

DD

SS

C
1nF

V

OUT

L

R

S

V

S

SD

IN

GND

V

IN

V

IN

V

OUT

ADG1212

ADG1211

Q

INJ

ON

= CL×ΔV

OUT

OFF

ΔV

OUT

04778-025

Figure 25. Test Circuit 6—Charge Injection

Rev. 0 | Page 12 of 16

ADG1211/ADG1212/ADG1213

V

V

0.1μF

V

DD

SS

0.1μF

0.1μF

V

V

DD

SS

0.1μF

V

IN

V

DD

SS

S

50Ω

D

V

IN

GND

OFF ISOLATION = 20 LOG

Figure 26. Test Circuit 7—Off Isolation Figure 28. Test Circuit 9—Bandwidth

V

DD

0.1μF

NETWORK

ANALYZER

V

OUT

R
50Ω

L



V

DD

S1

S2

V

S

GND

CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG

Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk

NETWORK

ANALYZER

50Ω

R

L

50Ω

V

SS

V

SS

V

OUT

V

S

V

V

OUT

0.1μF

D

V

S

IN

V

DD

SS

S

D

IN

GND

V

OUT

V

04778-026

S

V

0.1μF

R
50Ω

04778-027

IN

V

IN

INSERTION LOSS = 20 LOG

V

DD

V

SS

V

DD

SS

S

D

GND

0.1μF

R
10kΩ

ANALYZER

R
50Ω

V

OUT

WITHOUT SWITCH

V

OUT

AUDIO PRECISION

V

L

NETWORK

50Ω

V

S

V

OUT

L

WITH SWITCH

R

S

V

S

V p-p

OUT

04778-028

04778-032

Figure 29. Test Circuit 10—THD + Noise

Rev. 0 | Page 13 of 16

ADG1211/ADG1212/ADG1213

R

R

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.50

0.40

PIN 1

INDICATO

0.90

0.85

0.80

SEATING

PLANE

12° MAX

3.00

BSC SQ

TOP

VIEW

0.30

0.23

0.18
*

COMPLIANT
EXCEPT FOR EXPOSED PAD DIMENSION.

2.75

BSC SQ

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

TO

JEDEC STANDARDS MO-220-VEED-2

0.45

0.50

BSC

1.50 REF

0.60 MAX

13

12

(BOTTOM VIEW)

9

8

Figure 31. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-16-3)

Dimensions shown in millimeters

EXPOSED

PAD

0.30

16

1

4

5

N

I

P

D

N

I

*

1.65

1.50 SQ

1.35

0.25 MIN

1

O

T

C

I

A

Rev. 0 | Page 14 of 16

ADG1211/ADG1212/ADG1213

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1211YRUZ
ADG1211YRUZ-REEL
ADG1211YRUZ-REEL7
ADG1211YCPZ-500RL71−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3
ADG1211YCPZ-REEL7
ADG1212YRUZ
ADG1212YRUZ-REEL
ADG1212YRUZ-REEL7
ADG1212YCPZ-500RL71−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3
ADG1212YCPZ-REEL7
ADG1213YRUZ
ADG1213YRUZ-REEL
ADG1213YRUZ-REEL7
ADG1213YCPZ-500RL71−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3
ADG1213YCPZ-REEL7

1

Z = Pb-free part.

1

1

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Thin Shrink Small Outline Package (TSSOP) RU-16

1

−40°C to +125°C Lead Frame Chip Scale Package (LFCSP_VQ) CP-16-3

Rev. 0 | Page 15 of 16

ADG1211/ADG1212/ADG1213

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04778–0–7/05(0)

Rev. 0 | Page 16 of 16