Datasheet ADG1208, ADG1209 Datasheet (ANALOG DEVICES)

查询ADG1208供应商

Low Capacitance, 4-/8-Channel

FEATURES

<1 pC charge injection over full signal range
1 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic compatible inputs
Rail-to-rail operation
Break-before-make switching action
Available in 16-lead TSSOP and 4 mm × 4 mm LFCSP_VQ
Typical power consumption < 0.03 μW

APPLICATIONS

Audio and video routing
Automatic test equipment
Data-acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems

±15 V/+12 V iCMOS™ Multiplexers

ADG1208/ADG1209

FUNCTIONAL BLOCK DIAGRAMS

ADG1208

S1

S8

1-OF-8

DECODER

S1A

S4A

D

S1B

S4B

Figure 1.

ADG1209

1-OF-4

DECODER

A0 A1 E NA0 A1 A2 EN

DA

DB

05713-001

GENERAL DESCRIPTION

The ADG1208 and ADG1209 are monolithic, iCMOS analog
multiplexers comprising eight single channels and four differential
channels, respectively. The ADG1208 switches one of eight
inputs to a common output as determined by the 3-bit binary
address lines A0, A1, and A2. The ADG1209 switches one of
four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An
EN input on both devices is used to enable or disable the device.
When disabled, all channels are switched off. When on, each
channel conducts equally well in both directions and has an
input signal range that extends to the supplies.

The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal­oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased
performance, dramatically lower power consumption, and
reduced package size.

The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required.

Figure 2 shows that there is
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery powered instruments.

1.0
MUX (SOURCE TO DRAIN)

=25°C

T

A

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CHARGE INJECTION (pC)

0.2

0.1

0

–15 15

Figure 2. Source to Drain Charge Injection vs. Source Voltage

VDD=+5V
V

= –5V

SS

–10 –5 0 5 10

VS(V)

VDD= +15V

= –15V

V

SS

VDD= +12V
V

=0V

SS

05713-051

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2006 Analog Devices, Inc. All rights reserved.

ADG1208/ADG1209

TABLE OF CONTENTS

Features.............................................................................................. 1

Absolute Maximum Ratings ............................................................7

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Single Supply................................................................................. 5

REVISION HISTORY

4/06—Revision 0: Initial Version

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions............................8

Typical Performance Characteristics........................................... 10

Terminology.................................................................................... 14

Test Circuits..................................................................................... 15

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. 0 | Page 2 of 20

ADG1208/ADG1209

SPECIFICATIONS

DUAL SUPPLY

VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

−40ºC to

Parameter +25ºC

+85ºC

−40ºC to
+125ºC

ANALOG SWITCH

Analog Signal Range VSS to VDD V
On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA, see Figure 29
200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between Channels,

∆R

ON

3.5 Ω typ V

6 10 12 Ω max
On Resistance Flatness, R

(On) 20 Ω typ VS = −5 V, 0 V, +5 V, IS = −1 mA

FLAT

64 76 83 Ω max
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.02 nA typ VD = ±10 V, VS = −10 V, see Figure 30
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 30

ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max

Channel On Leakage, ID, IS (On) ±0.02 nA typ VS = VD = ±10 V, see Figure 31

ADG1208 ±0.2 ±0.6 ±1 nA max
ADG1209 ±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

±0.005 μA max VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

80 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

130 165 185 ns max VS = 10 V, see Figure 32

tON (EN) 75 ns typ RL = 300 Ω, CL = 35 pF

95 105 115 ns max VS = 10 V, see Figure 34

t

(EN) 83 ns typ RL = 300 Ω, CL = 35 pF

OFF

100 125 140 ns max VS = 10 V, see Figure 34

Break-Before-Make Time Delay, t

25 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min VS1 = VS2 = 10 V, see Figure 33
Charge Injection 0.4 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 35
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38
Total Harmonic Distortion + Noise 0.15 % typ

−3 dB Bandwidth 550 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
CS (Off) 1 pF typ f = 1 MHz, VS = 0 V

1.5 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1208 6 pF typ f = 1 MHz, VS = 0 V
7 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1209 3.5 pF typ f = 1 MHz, VS = 0 V

4.5 pF max f = 1 MHz, VS = 0 V

Rev. 0 | Page 3 of 20

1

Unit Test Conditions/Comments

= ±10 V, IS = −1 mA

S

or V

INH

INL

= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz,

R

L

see

Figure 39

ADG1208/ADG1209

−40ºC to

Parameter +25ºC

+85ºC

CD, CS (On) ADG1208 7 pF typ f = 1 MHz, VS = 0 V
8 pF max f = 1 MHz, VS = 0 V
CD, CS (On) ADG1209 5 pF typ f = 1 MHz, VS = 0 V
6 pF max f = 1 MHz, VS = 0 V

POWER REQUIREMENTS

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 220 μA typ Digital inputs = 5 V
320 μA max
ISS 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
ISS 0.002 μA typ Digital inputs = 5 V

1.0 μA max
VDD/VSS ±5/±16.5 V min/max |V

1

Temperature range is as follows: Y version: –40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40ºC to
+125ºC

Unit Test Conditions/Comments

VDD = +16.5 V, VSS = −16.5 V

| = |VSS|

DD

Rev. 0 | Page 4 of 20

ADG1208/ADG1209

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1

Table 2.

−40ºC to

Parameter +25ºC

+85ºC

ANALOG SWITCH

Analog Signal Range 0 to VDD V
On Resistance, RON 300 Ω typ VS = 0 V to10 V, IS = −1 mA, see Figure 29
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between Channels,

∆R

ON

5 Ω typ V

16 26 27 Ω max
On Resistance Flatness, R

(On) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA

FLAT

LEAKAGE CURRENTS VDD = 13.2 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30
±0.1 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 30

ADG1208 ±0.1 ±0.6 ±1 nA max
ADG1209 ±0.1 ±0.6 ±1 nA max

Channel On Leakage ID, IS (On) ±0.02 nA typ VS = VD = 1 V or 10 V; see Figure 31

ADG1208 ±0.2 ±0.6 ±1 nA max
ADG1209 ±0.2 ±0.6 ±1 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

±0.001

INH

±0.1 μA max VIN = V

Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

100 ns typ RL = 300 Ω, CL = 35 pF

170 210 235 VS = 8 V, see Figure 32

tON (EN) 90 ns typ RL = 300 Ω, CL = 35 pF
110 140 160 VS = 8 V, see Figure 34
t

(EN) 105 ns typ RL = 300 Ω, CL = 35 pF

OFF

130 155 175 VS = 8 V, see Figure 34

Break-Before-Make Time Delay, t

45 ns typ RL = 300 Ω, CL = 35 pF

BBM

20 ns min VS1 = V
Charge Injection −0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 35
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 36
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 38

−3 dB Bandwidth 450 MHz typ RL = 50 Ω, CL = 5 pF, see Figure 37
CS (Off) 1.2 pF typ f = 1 MHz, VS = 6 V

1.8 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1208 7.5 pF typ f = 1 MHz, VS = 6 V
9 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1209 4.5 pF typ f = 1 MHz, VS = 6 V

5.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1208 9 pF typ f = 1 MHz, VS = 6 V

10.5 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1209 6 pF typ f = 1 MHz, VS = 6 V

7.5 pF max f = 1 MHz, VS = 6 V

−40ºC to
+125ºC

Rev. 0 | Page 5 of 20

Unit Test Conditions/Comments

= 0 V to 10 V, IS = −1 mA

S

or V

INL

S2

INH

= 8 V, see Figure 33

ADG1208/ADG1209

−40ºC to

Parameter +25ºC

+85ºC

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 220 μA typ Digital inputs = 5 V

330 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range is as follows: Y version: –40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40ºC to
+125ºC Unit Test Conditions/Comments

Rev. 0 | Page 6 of 20

ADG1208/ADG1209

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

V

to VSS 35 V

DD

VDD to GND −0.3 V to +25 V
V

to GND +0.3 V to −25 V

SS

Analog, Digital Inputs

Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at

1 ms, 10% Duty Cycle max)

Operating Temperature Range

Industrial (Y Version) –40°C to +125°C

Storage Temperature –65°C to +150°C
Junction Temperature 150°C
TSSOP, θJA, Thermal Impedance 112°C/W
LFCSP_VQ, θJA, Thermal Impedance 30.4°C/W
Reflow Soldering Peak

Temperature (Pb-Free)

1

Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

1

VSS − 0.3 V to VDD + 0.3 V or
30 mA (whichever occurs first)

100 mA

260(+0/−5)°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 20

ADG1208/ADG1209

V

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

A0

2

EN

3

SS

ADG1208

TOP VI EW

4

S1

(Not t o Scal e)

5

S2

6

S3

7

S4

8

DS

Figure 3. ADG1208 Pin Configuration (TSSOP)

Table 4. ADG1208 Pin Function Descriptions

Pin Number

TSSOP LFCSP_VQ Mnemonic Description

1 15 A0 Logic Control Input.
2 16 EN

3 1 VSS

4 2 S1 Source Terminal 1. Can be an input or an output.
5 3 S2 Source Terminal 2. Can be an input or an output.
6 4 S3 Source Terminal 3. Can be an input or an output.
7 5 S4 Source Terminal 4. Can be an input or an output.
8 6 D Drain Terminal. Can be an input or an output.
9 7 S8 Source Terminal 8. Can be an input or an output.
10 8 S7 Source Terminal 7. Can be an input or an output.
11 9 S6 Source Terminal 6. Can be an input or an output.
12 10 S5 Source Terminal 5. Can be an input or an output.
13 11 VDD Most Positive Power Supply Potential.
14 12 GND Ground (0 V) Reference.
15 13 A2 Logic Control Input.
16 14 A1 Logic Control Input.

Table 5. ADG1208 Truth Table

A2 A1 A0 EN ON SWITCH

X X X 0 NONE
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8

16

A1

15

A2

14

GND

13

V

DD

12

S5

11

S6

10

S7

9

8

5713-002

Figure 4. ADG1208 Pin Configuration (LFCSP_VQ),

1

SS

2S1

3S2

4S3

Exposed Pad Tied to Substrate, V

Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.

Most Negative Power Supply Potential. In single supply applications, it can be
connected to ground.

A0

EN

A1

14

15

16

PIN 1
INDICATOR

ADG1208

TOP VIEW

(Not to Scale)

7

5

6

D

S4

S8

A2

13

12 GND

11 V

DD

10 S5

9S6

8

S7

05713-004

SS

Rev. 0 | Page 8 of 20

ADG1208/ADG1209

GND

A1

EN

1

A0

2

EN

3

V

SS

ADG1209

TOP VIEW

4

S1A

(Not to Scale)

5

S2A

6

S3A

7

S4A

8

DA DB

Figure 5. ADG1209 Pin Configuration (TSSOP)

16

A1

15

GND

14

V

DD

13

S1B

12

S2B

11

S3B

10

S4B

9

5713-003

Figure 6. ADG1209 Pin Configurations (LFCSP_VQ),

Table 6. ADG1209 Pin Function Descriptions

Pin Number

TSSOP LFCSP_VQ Mnemonic Description

1 15 A0 Logic Control Input.
2 16 EN

Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.

3 1 VSS

Most Negative Power Supply Potential. In single supply applications, it can be

connected to ground.
4 2 S1A Source Terminal 1A. Can be an input or an output.
5 3 S2A Source Terminal 2A. Can be an input or an output.
6 4 S3A Source Terminal 3A. Can be an input or an output.
7 5 S4A Source Terminal 4A. Can be an input or an output.
8 6 DA Drain Terminal A. Can be an input or an output.
9 7 DB Drain Terminal B. Can be an input or an output.
10 8 S4B Source Terminal 4B. Can be an input or an output.
11 9 S3B Source Terminal 3B. Can be an input or an output.
12 10 S2B Source Terminal 2B. Can be an input or an output.
13 11 S1B Source Terminal 1B. Can be an input or an output.
14 12 VDD Most Positive Power Supply Potential.
15 13 GND Ground (0 V) Reference.
16 14 A1 Logic Control Input.

Table 7. ADG1209 Truth Table

A1 A0 EN ON SWITCH PAIR

X X 0 NONE
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4

1V

SS

2S1A

3S2A

4S3A

Exposed Pad Tied to Substrate, V

A0

14

16

15

PIN 1
INDICATOR

ADG1209

TOP VIEW

(Not to Scale)

7

5

6

DA

DB

S4A

13

8

S4B

12 V

DD

11 S1 B

10 S2B

9S3B

05713-005

SS

Rev. 0 | Page 9 of 20

ADG1208/ADG1209

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA= 25°C

180

160

140

120

100

80

ON RESISTANCE (Ω)

60

40

20

0

–18 –15 –12 –9 –6 –3 12 1590631

VDD= +13.5V

=–13.5V

V

SS

VDD= +16.5V
V

SS

SOURCE OR DRAIN VO LTAGE (V)

Figure 7. On Resistance as a Function of V

600

TA= 25°C

500

400

300

200

ON RESISTANCE (Ω)

VDD=+5.5V
V

SS

= –5.5V

VDD= +4.5V
V

VDD=+15V

= –15V

V

SS

= –16.5V

(VS) for Dual Supply

D

=–4.5V

SS

VDD=+5V

=–5V

V

SS

8

05713-030

250

200

150

100

ON RESISTANCE ( Ω)

50

0

–15 –10 –5 1005 15

TA= +125°C

TA= +85°C

TA= +25°C

TA= –40°C

TEMPERATURE (°C)

Figure 10. On Resistance as a Function of V

VDD= +15V

= –15V

V

SS

(VS) for Different

D

Temperatures, Dual Supply

600

500

400

300

200

ON RESISTANCE (Ω)

TA= +125°C

TA= –40°C

VDD= 12V
V

SS

TA=+85°C

TA= +25°C

=0V

05713-033

100

0

–6 –4 –2 402 6

Figure 8. On Resistance as a Function of V

450

TA= 25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

02 4 6 12810 14

Figure 9. On Resistance as a Function of V

SOURCE OR DRAIN VOL TAGE (V)

(VS) for Dual Supply

D

VDD= 10.8V

=0V

V

SS

VDD= 12V

=0V

V

SS

VDD= 13.2V

=0V

V

SS

SOURCE OR DRAIN VO LTAGE (V)

(VS) for Single Supply

D

100

0

024 1068 12

05713-031

Figure 11. On Resistance as a Function of V

TEMPERATURE (°C)

(VS) for Different

D

05713-034

Temperatures, Single Supply

400

VDD = +15V

= –15V

V

SS

300

200

100

–100

LEAKAGE CURRENT (p A)

–200

–300

–400

05713-032

= +10V/–10V

V

BIAS

ID, S (ON) + +

ID (OFF) + –

IS (OFF) + –

0

ID, S (ON) – –

ID (OFF) – +

0 102030405060708090100110120

TEMPERATURE (° C)

IS (OFF) – +

05713-057

Figure 12. ADG1208 Leakage Currents as a Function of Temperature,

Dual Supply

Rev. 0 | Page 10 of 20

ADG1208/ADG1209

150

VDD = 12V
V

= 0V

SS

V

= 1V/10V

BIAS

100

50

0

–50

LEAKAGE CURRENT ( pA)

–100

–150

0 102030405060708090100110120

ID, S (ON) + +

ID, S (ON) – –

ID (OFF) – +

TEMPERATURE (° C)

Figure 13. ADG1208 Leakage Currents as a Function of Temperature,

Single Supply

200

180

160

140

120

(µA)

100

DD

I

80

60

40

20

0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CHARGE INJECTION (pC)

0.2

0.1

0

–15 15

VDD=+15V

= –15V

V

SS

VDD= +12V

=0V

V

SS

0 2 4 6 8 10121416

Figure 14. I

MUX (SOURCE TO DRAIN)

=25°C

T

A

–10 –5 0 5 10

LOGIC, INX(V)

VDD=+5V
V

= –5V

SS

vs. Logic Level

DD

VS(V)

VDD= +15V

= –15V

V

SS

IDDPER CHANNEL
T

A

Figure 15. Source-to-Drain Charge Injection vs. Source Voltage

IS (OFF) + –

ID (OFF) + –

IS (OFF) – +

=25°C

VDD= +12V
V

=0V

SS

6

DEMUX (DRAIN T O SOURCE)

=25°C

T

A

4

2

0

VDD= +15V

–2

CHARGE INJECTION (pC)

–4

–6

05713-058

= –15V

V

SS

–10 –5 0 5 10

–15 15

VDD=+5V
V

SS

VS(V)

= –5V

VDD=+12V

=0V

V

SS

05713-041

Figure 16. Drain-to-Source Charge Injection vs. Source Voltage

350

300

250

200

150

TIME (ns)

100

50

0

–40

5713-035

0

–10

–20

–30

–40

–50

–60

–70

OFF ISOLATION (dB)

–80

–90

–100

–110

10k 100k 1M 10M 100M 1G

05713-040

VDD=+5V
V

=–5V

SS

VDD=+12V
V

=0V

SS

VDD= +15V
V

= –15V

SS

–20 0 20 40 60 80 100 120

Figure 17. t

VDD= +15V
V

=–15V

SS

T

=25°C

A

TEMPERATURE (°C)

Times vs. Temperature

ON/tOFF

FREQUENCY (Hz)

Figure 18. Off Isolation vs. Frequency

05713-052

5713-049

Rev. 0 | Page 11 of 20

ADG1208/ADG1209

–

20

VDD=+15V

= –15V

V

SS

= 25°C

T

0

A

10

LOAD = 10kΩ

= 25°C

T

A

–20

–40

–60

CROSSTALK (d B)

–80

–100

–120

10k 1G

ADJACENT CHANNELS

NONADJACENT

CHANNELS

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 19. ADG1208 Crosstalk vs. Frequency

0

–20

–40

–60

CROSST ALK (dB)

–80

–100

–120

10k 1G

ADJACENT CHANNELS

NONADJACENT

CHANNELS

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 20. ADG1209 Crosstalk vs. Frequency

6.0

–6.5

–7.0

–7.5

–8.0

1

VDD=+5V,VSS=–5V,VS= +3.5Vrms

THD + N (%)

0.1

0.01

05713-042

VDD= +15V, VSS= –15V, VS=+5Vrms

10 100 1k 10k 100k

FREQUENCY (Hz)

05713-036

Figure 22. THD + N vs. Frequency

12

10

8

6

4

CAPACITANCE (pF)

2

0

–15 15

05713-053

VDD=+15V
V

= –15V

SS

T

= 25°C

A

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

–10 –5 0 5 10

V

BIAS

(V)

05713-043

Figure 23. ADG1208 Capacitance vs. Source Voltage,

±15 V Dual Supply

12

10

8

6

VDD=12V
V

=0V

SS

T

=25°C

A

SOURCE/DRAIN ON

DRAIN OFF

–8.5

ON RESPONSE (dB)

–9.0

–9.5

–10.0

10k 1G

100k 1M 10M 100M

FREQUENCY (Hz)

Figure 21. On Response vs. Frequency

05713-054

4

CAPACITANCE (pF)

2

0

01

246810

SOURCE OFF

V

(V)

BIAS

2

05713-045

Figure 24. ADG1208 Capacitance vs. Source Voltage,

12 V Single Supply

Rev. 0 | Page 12 of 20

ADG1208/ADG1209

12

10

8

VDD=+5V

6

V

=–5V

SS

= 25°C

T

A

4

CAPACITANCE (pF )

2

0

–5 5

–4–3–2–101234

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

Figure 25. ADG1208 Capacitance vs. Source Voltage, ±5 V Dual Supply

05713-055

8

7

6

5

4

3

CAPACITANCE (pF)

2

1

0

01

VDD= 12V

=0V

V

SS

T

= 25°C

A

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

246810

V

(V)

BIAS

2

Figure 27. ADG1209 Capacitance vs. Source Voltage, 12 V Single Supply

05713-047

8

7

6

5

4

3

CAPACITANCE (pF)

2

1

0

–15 15

VDD=+15V

= –15V

V

SS

T

= 25°C

A

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

–10 –5 0 5 10

V

(V)

BIAS

Figure 26. ADG1209 Capacitance vs. Source Voltage, ±15 V Dual Supply

8

7

6

5

4

VDD=+5V
V

= –5V

SS

=25°C

T

A

3

CAPACITANCE (pF )

2

1

0

–5 5

–4–3–2–101234

05713-046

SOURCE/DRAIN ON

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

05713-056

Figure 28. ADG1209 Capacitance vs. Source Voltage, ±5 V Dual Supply

Rev. 0 | Page 13 of 20

ADG1208/ADG1209

TERMINOLOGY

RON

Ohmic resistance between D and S.

ΔR

ON

Difference between the R

(Off)

I

S

Source leakage current when the switch is off.

(Off)

I

D

Drain leakage current when the switch is off.

, IS (On)

I

D

Channel leakage current when the switch is on.

(VS)

V

D

Analog voltage on terminals D, S.

(Off)

C

S

Channel input capacitance for off condition.

(Off)

C

D

Channel output capacitance for off condition.

, CS (On)

C

D

On switch capacitance.

C

IN

Digital input capacitance.

(EN)

t

ON

Delay time between the 50% and 90% points of the digital input
and switch on condition.

of any two channels.

ON

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

T

BBM

Off time measured between the 80% point of both switches
when switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

(I

INL

INH

)

I

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

(EN)

t

OFF

Delay time between the 50% and 90% points of the digital input
and switch off condition.

Rev. 0 | Page 14 of 20

On Response

The frequency response of the on switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

ADG1208/ADG1209

V

VDDV

VDDV

VDDV

O

R

TEST CIRCUITS

V

SD

I

V

S

DS

05713-037

Figure 29. On Resistance

IS(OFF) ID(OFF)

SD

A A

S

Figure 30. Off Leakage

SD

NC

V

D

05713-038

NC = NO CONNECT

Figure 31. On Leakage

ID(ON)

A

V

D

05713-039

3V

ADDRESS
DRIVE (V

0V

t

TRANSITI ON

OUTPUT

ADDRESS
DRIVE (V

0V

OUTPUT

)

IN

3V

)

IN

50% 50%

90%

80% 80%

t

BBM

t

<20ns

r

t

< 20ns

f

V

t

TRANSITION

90%

IN

50Ω

2.4V EN

1

SIMILAR CONNECTION FOR ADG1209.

Figure 32. Address to Output Switching Times, t

V

IN

50Ω

2.4V EN

A0

A1

A2

TRANSITION

A0

A1

A2

V

V

DD

ADG1208

GND

V

V

DD

ADG1208

GND

SS

SS

S2–S7

1

SS

SS

S2–S7

1

S1

S8

D

S1

S8

D

OUTPUT

OUTPUT

300Ω

V

S1

V

S8

300Ω

35pF

05713-022

V

S

35pF

1

SIMILAR CONNECTI ON FO R ADG1209.

Figure 33. Break-Before-Make Delay, t

BBM

05713-023

SS

3V

ENABLE
D

IVE (VIN)

0V

UTPUT

t

(EN)

ON

50% 50%

0.9V

O

t

(EN)

OFF

0.9V

O

Figure 34. Enable Delay, t

V

IN

50Ω

1

SIMILAR CONNECTI ON FOR ADG1209.

(EN), t

OFF

(EN)

ON

Rev. 0 | Page 15 of 20

V

DD

A0

A1

A2

ADG1208

EN

GND

V

SS

S2–S8

S1

1

D

OUTPUT

300Ω

V

S

35pF

05713-024

ADG1208/ADG1209

VINV

VDDV

V

V

V

V

V

V

SS

V

V

DD

3V

A0

SS

A1

A2

GND

1

DS

C
1nF

V

OUT

L

05713-025

OUT

Q

INJ=CL

× ΔV

OUT

ΔV

OUT

ADG1208

R

S

V

S

EN

V

IN

1

SIMILAR CONNECTION F OR ADG1209.

Figure 35. Charge Injection

V

0.1µF

DD

V

SS

0.1µF

V

DD

SS

S

50Ω

D

GND

NETWO RK

ANALYZER

50Ω

V

OUT

R

L

50Ω

V

S

NETWORK

ANALYZER

V

OUT

R

L

50Ω

V

S

0.1µF

DD

V

S1

S2

SS

0.1µF

V

DD

SS

D

R
50Ω

GND

0.1µF

V

OFF ISOLATION = 20 log

Figure 36. Off Isolation

V

DD

V

SS

0.1µF

NETWORK

V

DD

SS

S

ANALYZER

50Ω

D

R

L

GND

INSERTION LOSS = 20 log

50Ω

V

WITH SWITCH

OUT

WITHOUT SWITCH

V

OUT

Figure 37. Bandwidth

OUT

V

S

05713-026

CHANNEL-TO- CHANNEL CROSSTALK = 20 lo g

Figure 38. Channel-to-Channel Crosstalk

V

DD

SS

0.1µF

V

DD

V

S

V

OUT

IN

IN

S

0.1µF

V

SS

D

GND

05713-027

Figure 39. THD + Noise

V

OUT

V

AUDIO PRECI SION

R

L

10kΩ

S

R

S

V

S

Vp-p

V

OUT

05713-028

05713-029

Rev. 0 | Page 16 of 20

ADG1208/ADG1209

R

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

PIN 1

INDICATO

1.00

0.85

0.80

4.00

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

COMPLIANT TO JEDEC STANDARDS MO-220-VGGC

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.65 BSC

0.05 MAX

0.02 NOM

COPLANARITY

0.75

0.60

0.50

0.08

Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-16-4)

Dimensions shown in millimeters

0.60 MAX

13

12

EXPOSED

(BOTTOM VIEW)

9

8

PAD

16

1

4

5

1.95 BSC

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADG1208YRUZ1
ADG1208YRUZ-REEL71
ADG1208YCPZ-REEL1
ADG1208YCPZ-REEL7
ADG1209YRUZ1
ADG1209YRUZ-REEL71
ADG1209YCPZ-REEL
ADG1209YCPZ-REEL7

1

Z = Pb-free part.

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

1

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

1

−40°C to +125°C

1

−40°C to +125°C

16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4
16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-4

Rev. 0 | Page 17 of 20

ADG1208/ADG1209

NOTES

Rev. 0 | Page 18 of 20

ADG1208/ADG1209

NOTES

Rev. 0 | Page 19 of 20

ADG1208/ADG1209

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05713-0-4/06(0)

Rev. 0 | Page 20 of 20