Datasheet ADG1206, ADG1207 Datasheet (ANALOG DEVICES)

S

查询ADG1206供应商

Low Capacitance, 16- and 8-Channel

FEATURES

<1 pC charge injection over full signal range

1.5 pF off capacitance
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
28-lead TSSOP and 32-lead, 5 mm × 5 mm LFCSP_VQ

APPLICATIONS

Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems

GENERAL DESCRIPTION

The ADG1206 and ADG1207 are monolithic iCMOS analog
multiplexers comprising sixteen single channels and eight
differential channels, respectively. The ADG1206 switches one
of sixteen inputs to a common output, as determined by the 4­bit binary address lines A0, A1, A2, and A3. The ADG1207
switches one of eight differential inputs to a common
differential output, as determined by the 3-bit binary address
lines A0, A1, and A2. An EN input on both devices is used to
enable or disable the device. When disabled, all channels are
switched off. When on, each channel conducts equally well in
both directions and has an input signal range that extends to the
supplies.

The iCMOS (industrial CMOS) modular manufacturing
process combines high voltage CMOS (complementary metal­oxide semiconductor) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation
of high voltage parts has been able to achieve. Unlike analog ICs
using conventional CMOS processes, iCMOS components can
tolerate high supply voltages while providing increased perfor­mance, dramatically lower power consumption, and reduced
package size.

±15 V/+12 V iCMOS™ Multiplexers

ADG1206/ADG1207

FUNCTIONAL BLOCK DIAGRAMS

ADG1206

S1

16

1-OF-16

DECODER

A0 A1 A2 A3 EN

S1A

S8A

D

S1B

S8B

Figure 1.

The ultralow capacitance and exceptionally low charge injection
of these multiplexers make them ideal solutions for data
acquisition and sample-and-hold applications, where low glitch
and fast settling are required.

Figure 2 shows that there is
minimum charge injection over the entire signal range of the
device. iCMOS construction also ensures ultralow power
dissipation, making the parts ideally suited for portable and
battery-powered instruments.

1.0
MUX (SOURCE TO DRAIN)

T

= 25°C

A

0.9

0.8

0.7

0.6

0.5

0.4

0.3

CHARGE INJECTI ON (pC)

0.2

0.1

0

Figure 2. Source-to-Drain Charge Injection vs. Source Voltage

–10 –5 0 5 10

–15 15

= +5V

V

DD

= –5V

V

SS

VS (V)

ADG1207

1-OF-8

DECODER

A0 A1 A2 EN

= +15V

V

DD

= –15V

V

SS

V
V

DD
SS

= +12V
= 0V

DA

DB

06119-001

6119-002

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADG1206/ADG1207

TABLE OF CONTENTS

Features.............................................................................................. 1

Absolute Maximum Ratings ............................................................7

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Dual Supply................................................................................... 3

Single Supply................................................................................. 5

REVISION HISTORY

7/06—Revision 0: Initial Version

ESD Caution...................................................................................7

Pin Configurations and Function Descriptions............................8

Typical Performance Characteristics........................................... 12

Terminology.................................................................................... 16

Test Circuits..................................................................................... 17

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

Rev. 0 | Page 2 of 20

ADG1206/ADG1207

SPECIFICATIONS

DUAL SUPPLY

VDD = +15 V ± 10%, VSS = –15 V ± 10%, GND = 0 V, unless otherwise noted.

Table 1.

−40°C to

Parameter +25°C

+85°C

−40°C to
+125°C

ANALOG SWITCH

Analog Signal Range VSS to VDD V
On Resistance, RON 120 Ω typ VS = ±10 V, IS = −1 mA; see Figure 28
200 240 270 Ω max VDD = +13.5 V, VSS = −13.5 V
On Resistance Match Between

Channels, ∆R

ON

3.5 Ω typ V

6 10 12 Ω max
On Resistance Flatness, R

(On) 20 Ω typ VS = −5 V, 0 V, +5 V; IS = −1 mA

FLAT

64 76 83 Ω max
LEAKAGE CURRENTS

Source Off Leakage, IS (Off) ±0.03 nA typ

±0.2 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V, 10 V; VD = 10 V, 1 V; see Figure 29

±0.2 ±0.6 ±2 nA max

Channel On Leakage, ID, IS (On) ±0.08 nA typ VS = VD = ±10 V; see Figure 30

±0.2 ±0.6 ±2 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

±0.005 μA typ VIN = V

INH

±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ

DYNAMIC CHARACTERISTICS2

Transition Time, t

80 ns typ RL = 300 Ω, CL = 35 pF

TRANSITION

130 165 185 ns max VS = 10 V; see Figure 31

tON (EN) 75 ns typ RL = 300 Ω, CL = 35 pF

95 105 115 ns max VS = 10 V; see Figure 33

t

(EN) 85 ns typ RL = 300 Ω, CL = 35 pF

OFF

100 125 140 ns max VS = 10 V; see Figure 33

Break-Before-Make Time Delay, t

20 ns typ RL = 300 Ω, CL = 35 pF

BBM

10 ns min VS1 = VS2 = 10 V; see Figure 32
Charge Injection 0.5 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 34
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37
Total Harmonic Distortion + Noise 0.15 % typ

−3 dB Bandwidth ADG1206 280 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36

−3 dB Bandwidth ADG1207 490 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36
CS (Off) 1.5 pF typ f = 1 MHz, VS = 0 V
2 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1206 11 pF typ f = 1 MHz, VS = 0 V
12 pF max f = 1 MHz, VS = 0 V
CD (Off) ADG1207 7 pF typ f = 1 MHz, VS = 0 V
9 pF max f = 1 MHz, VS = 0 V

1

Unit Test Conditions/Comments

= ±10 V, IS = −1 mA

S

VD = ±10 V, VS = ∓10 V; see Figure 29

or V

INH

INL

= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;

R

L

see

Figure 38

Rev. 0 | Page 3 of 20

ADG1206/ADG1207

−40°C to

Parameter +25°C

+85°C

CD, CS (On) ADG1206 13 pF typ f = 1 MHz, VS = 0 V
15 pF max f = 1 MHz, VS = 0 V
CD, CS (On) ADG1207 8 pF typ f = 1 MHz, VS = 0 V
10 pF max f = 1 MHz, VS = 0 V

POWER REQUIREMENTS VDD = +16.5 V, VSS = −16.5 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 260 μA typ Digital inputs = 5 V
420 μA max
ISS 0.002 μA typ Digital inputs = 0 V, 5 V, or VDD

1.0 μA max
VDD/VSS ±5/±16.5 V min/max GND = 0V

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40°C to
+125°C Unit Test Conditions/Comments

Rev. 0 | Page 4 of 20

ADG1206/ADG1207

SINGLE SUPPLY

VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.1

Table 2.

−40°C to

Parameter +25°C

+85°C

ANALOG SWITCH

Analog Signal Range 0 to VDD V
On Resistance, RON 300 Ω typ VS = 0 V to10 V, IS = −1 mA; see Figure 28
475 567 625 Ω max VDD = 10.8 V, VSS = 0 V
On Resistance Match Between

Channels, ∆R

ON

5 Ω typ V

16 26 27 Ω max
On Resistance Flatness, R

(On) 60 Ω typ VS = 3 V, 6 V, 9 V; IS = −1 mA

FLAT

LEAKAGE CURRENTS VDD = 13.2 V

Source Off Leakage, IS (Off) ±0.02 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29
±0.2 ±0.6 ±1 nA max
Drain Off Leakage, ID (Off) ±0.05 nA typ VS = 1 V/10 V, VD = 10 V/1 V; see Figure 29

±0.2 ±0.6 ±2 nA max

Channel On Leakage, ID, IS (On) ±0.08 nA typ VS = VD = 1 V or 10 V; see Figure 30

±0.2 ±0.6 ±2 nA max

DIGITAL INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INL

2.0 V min

INH

0.8 V max

INL

or I

±0.001 μA typ

INH

±0.1 μA max VIN = V

Digital Input Capacitance, CIN 3 pF typ

DYNAMIC CHARACTERISTICS

Transition Time, t

TRANSITION

2

100 ns typ RL = 300 Ω, CL = 35 pF

140 175 200 ns max VS = 8 V; see Figure 31

tON (EN) 80 ns typ RL = 300 Ω, CL = 35 pF
100 120 130 ns max VS = 8 V; see Figure 33
t

(EN) 90 ns typ RL = 300 Ω, CL = 35 pF

OFF

110 130 155 ns max VS = 8 V; see Figure 33

Break-Before-Make Time Delay, t

25 ns typ RL = 300 Ω, CL = 35 pF

BBM

15 ns min VS1 = VS2 = 8 V; see Figure 32
Charge Injection 0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 34
Off Isolation −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35
Channel-to-Channel Crosstalk −85 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37

−3 dB Bandwidth ADG1206 185 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36

−3 dB Bandwidth ADG1207 300 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 36
CS (Off) 1.5 pF typ f = 1 MHz, VS = 6 V
2 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1206 13 pF typ f = 1 MHz, VS = 6 V
15 pF max f = 1 MHz, VS = 6 V
CD (Off) ADG1207 9 pF typ f = 1 MHz, VS = 6 V
11 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1206 15 pF typ f = 1 MHz, VS = 6 V
17 pF max f = 1 MHz, VS = 6 V
CD, CS (On) ADG1207 10 pF typ f = 1 MHz, VS = 6 V
12 pF max f = 1 MHz, VS = 6 V

−40°C to
+125°C

Unit Test Conditions/Comments

= 0 V to 10 V, IS = −1 mA

S

or V

INH

INL

Rev. 0 | Page 5 of 20

ADG1206/ADG1207

−40°C to

Parameter +25°C

+85°C

POWER REQUIREMENTS VDD = 13.2 V

IDD 0.002 μA typ Digital inputs = 0 V or VDD

1.0 μA max
IDD 260 μA typ Digital inputs = 5

420 μA max

VDD 5/16.5 V min/max VSS = 0 V, GND = 0 V

1

Temperature range for Y version is −40°C to +125°C.

2

Guaranteed by design, not subject to production test.

−40°C to
+125°C Unit Test Conditions/Comments

Rev. 0 | Page 6 of 20

ADG1206/ADG1207

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

V

to VSS 35 V

DD

VDD to GND −0.3 V to +25 V
V

to GND +0.3 V to −25 V

SS

Analog, Digital Inputs

1

VSS − 0.3 V to VDD + 0.3 V
or 30 mA, whichever

occurs first
Continuous Current, S or D 30 mA
Peak Current, S or D (Pulsed at 1 ms,

100 mA

10% Duty Cycle Maximum)

Operating Temperature Ranges

Industrial (Y Version) –40°C to +125°C

Storage –65°C to +150°C
Junction Temperature 150°C
28-Lead TSSOP

θJA, Thermal Impedance 97.9°C/W

θJC, Thermal Impedance 14°C/W
32-Lead LFCSP_VQ
θJA, Thermal Impedance 27.27°C/W
Reflow Soldering Peak Temperature

260(+0/−5)°C

(Pb-Free)

1

Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should

be limited to the maximum ratings given.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Only one absolute maximum rating may be applied at any
one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 20

ADG1206/ADG1207

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

V

DD

2

NC

3

NC

4

S16

5

S15

6

S14

7

S13

8

S12

9

S11

10

S10

11

S9

12

ND

13

NC

14

A3

NC = NO CONNECT

ADG1206

TOP VIEW

(Not to Scale)

28

D

27

V

SS

26

S8

25

S7

24

S6

23

S5

22

S4

21

S3

20

S2

19

S1

18

EN

17

A0

16

A1

15

A2

06119-003

NC = NO CONNECT

Figure 3. ADG1206 Pin Configuration—TSSOP Figure 4. ADG1206 Pin Configuration—5 mm × 5 mm LFCSP_VQ,

Exposed Pad Tied to Substrate, V

Table 4. ADG1206 Pin Function Descriptions

Pin Number

TSSOP LFCSP_VQ Mnemonic Description

1 31 VDD Most Positive Power Supply Potential.
2 12, 13 NC No Connect.
3

26, 27, 28,

NC No Connect.

30, 32
4 1 S16 Source Terminal 16. Can be an input or an output.
5 2 S15 Source Terminal 15. Can be an input or an output.
6 3 S14 Source Terminal 14. Can be an input or an output.
7 4 S13 Source Terminal 13. Can be an input or an output.
8 5 S12 Source Terminal 12. Can be an input or an output.
9 6 S11 Source Terminal 11. Can be an input or an output.
10 7 S10 Source Terminal 10. Can be an input or an output.
11 8 S9 Source Terminal 9. Can be an input or an output.
12 9 GND Ground (0 V) Reference.
13 – NC No Connect.
14 10 A3 Logic Control Input.
15 11 A2 Logic Control Input.
16 14 A1 Logic Control Input.
17 15 A0 Logic Control Input.
18 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are

turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19 17 S1 Source Terminal 1. Can be an input or an output.
20 18 S2 Source Terminal 2. Can be an input or an output.
21 19 S3 Source Terminal 3. Can be an input or an output.
22 20 S4 Source Terminal 4. Can be an input or an output.
23 21 S5 Source Terminal 5. Can be an input or an output.
24 22 S6 Source Terminal 6. Can be an input or an output.
25 23 S7 Source Terminal 7. Can be an input or an output.
26 24 S8 Source Terminal 8. Can be an input or an output.
27 25 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be

connected to ground.
28 29 D Drain Terminal. Can be an input or an output.

Rev. 0 | Page 8 of 20

1S16
2S15
3S14
4S13
5S12
6S11
7S10
8S9

DD

NC

NC

D

V

29

31

30

32

PIN 1
INDICATO R

ADG1206

TOP VIEW

(Not to Scale)

9

11

12

10
3

A2

A

NC

GND

SS

NC

NC

V

NC

25

26

27

28

24 S8
23 S7
22 S6
21 S5
20 S4
19 S3
18 S2
17 S1

15

14

13

16

C

A0

A1

EN

N

SS

06119-004

ADG1206/ADG1207

Table 5. ADG1206 Truth Table

A3 A2 A1 A0 EN On Switch

X X X X 0 None
0 0 0 0 1 1
0 0 0 1 1 2
0 0 1 0 1 3
0 0 1 1 1 4
0 1 0 0 1 5
0 1 0 1 1 6
0 1 1 0 1 7
0 1 1 1 1 8
1 0 0 0 1 9
1 0 0 1 1 10
1 0 1 0 1 11
1 0 1 1 1 12
1 1 0 0 1 13
1 1 0 1 1 14
1 1 1 0 1 15
1 1 1 1 1 16

Rev. 0 | Page 9 of 20

ADG1206/ADG1207

1

V

DD

2

DB

3

NC

4

S8B

5

S7B

6

S6B

7

S5B

8

S4B

9

S3B

10

S2B

11

S1B

12

GND

13

NC

14

NC

NC = NO CONNECT

ADG1207

TOP VIEW

(Not to Scale)

28

DA

27

V

SS

26

S8A

25

S7A

24

S6A

23

S5A

22

S4A

21

S3A

20

S2A

19

S1A

18

EN

17

A0

16

A1

15

A2

06119-036

NC = NO CONNECT

Figure 5. ADG1207 Pin Configuration—TSSOP Figure 6. ADG1207 Pin Configuration—5 mm × 5 mm LFCSP_VQ

Exposed Pad Tied to Substrate, V

Table 6. ADG1207 Pin Function Descriptions

Pin Number

TSSOP LFCSP_VQ Mnemonic Description

1 29 VDD Most Positive Power Supply Potential.
2 31 DB Drain Terminal B. Can be an input or an output.
3 11, 12, 13 NC No Connect.
4 1 S8B Source Terminal 8B. Can be an input or an output.
5 2 S7B Source Terminal 7B. Can be an input or an output.
6 3 S6B Source Terminal 6B. Can be an input or an output.
7 4 S5B Source Terminal 5B. Can be an input or an output.
8 5 S4B Source Terminal 4B. Can be an input or an output.
9 6 S3B Source Terminal 3B. Can be an input or an output.
10 7 S2B Source Terminal 2B. Can be an input or an output.
11 8 S1B Source Terminal 1B. Can be an input or an output.
12 9 GND Ground (0 V) Reference.
13

26, 28,

NC No Connect.

30, 32
14 – NC No Connect.
15 10 A2 Logic Control Input.
16 14 A1 Logic Control Input.
17 15 A0 Logic Control Input.
18 16 EN

Active High Digital Input. When this pin is low, the device is disabled and all switches are

turned off. When this pin is high, the Ax logic inputs determine which switch is turned on.
19 17 S1A Source Terminal 1A. Can be an input or an output.
20 18 S2A Source Terminal 2A. Can be an input or an output.
21 19 S3A Source Terminal 3A. Can be an input or an output.
22 20 S4A Source Terminal 4A. Can be an input or an output.
23 21 S5A Source Terminal 5A. Can be an input or an output.
24 22 S6A Source Terminal 6A. Can be an input or an output.
25 23 S7A Source Terminal 7A. Can be an input or an output.
26 24 S8A Source Terminal 8A. Can be an input or an output.
27 25 VSS

Most Negative Power Supply Potential. In single-supply applications, this pin can be

connected to ground.
28 27 DA Drain Terminal A. Can be an input or an output.

1S8B
2S7B
3S6B
4S5B
5S4B
6S3B
7S2B
8S1B

DD

NC

NC

V

DB

29

31

30

32

PIN 1
INDICATO R

ADG1207

TOP VIEW

(Not to Scale)

9

11

12

10

A2

NC

NC

GND

C

SS

DA

N

V

NC

25

26

27

28

24 S8A
23 S7A
22 S6A
21 S5A
20 S4A
19 S3A
18 S2A
17 S1A

15

14

13

16

A0

A1

EN

NC

SS

06119-037

Rev. 0 | Page 10 of 20

ADG1206/ADG1207

Table 7. ADG1207 Truth Table

A2 A1 A0 EN On Switch Pair

X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8

Rev. 0 | Page 11 of 20

ADG1206/ADG1207

TYPICAL PERFORMANCE CHARACTERISTICS

200

TA = 25°C

180

160

140

120

100

80

ON RESISTANCE (Ω)

60

40

20

0

–18 –15 –12 –9 –6 –3 12 1590631

VDD = +13.5V
V

= –13.5V

SS

VDD = +16.5V
V

SS

SOURCE OR DRAIN VOL TAGE (V)

Figure 7. On Resistance as a Function of V

VDD = +15V

V

= –15V

SS

= –16.5V

(VS) for Dual Supply

D

8

6119-005

250

200

150

100

ON RESISTANCE (Ω)

50

0

–15 –10 –5 1005 15

TA = +125°C

TA = +85°C

TA = +25°C

TA = –40°C

SOURCE OR DRAIN VO LTAGE (V)

Figure 10. On Resistance as a Function of V

Dual Supply

VDD = +15V
V

= –15V

SS

(VS) for Different Temperatures,

D

06119-008

600

TA = 25°C

500

400

300

200

ON RESISTANCE (Ω)

100

0

–6 –4 –2 402 6

VDD = +5.5V
V

SOURCE OR DRAIN VO LTAGE ( V)

Figure 8. On Resistance as a Function of V

450

TA = 25°C

400

350

300

250

200

150

ON RESISTANCE (Ω)

100

50

0

02 4 6 12810 14

VDD = 13.2V

= 0V

V

SS

SOURCE OR DRAIN VOLTAGE (V)

Figure 9. On Resistance as a Function of V

= –5.5V

SS

VDD = 10.8V
V

= 0V

SS

VDD = +4.5V
V

= –4.5V

SS

VDD = +5V
V

= –5V

SS

(VS) for Dual Supply

D

VDD = 12V

= 0V

V

SS

(VS) for Single Supply

D

600

500

400

300

200

ON RESISTANCE (Ω)

100

0

6119-006

024 1068 12

SOURCE OR DRAIN VOL TAGE (V)

Figure 11. On Resistance as a Function of V

TA = +125°C

TA = –40°C

(VS) for Different Temperatures,

D

VDD = 12V
V

SS

TA = +85°C

TA = +25°C

= 0V

06119-009

Single Supply

1200

VDD = +15V

1000

V

= –15V

SS

V

= +10V/–10V

BIAS

800

600

400

200

0

–200

LEAKAGE (pA)

–400

–600

–800

–1000

–1200

02040 10060 80 120

06119-007

TEMPERATURE (° C)

I

(OFF) – +

S

, IS (ON) + +

I

D

I

(OFF) + –

S

(OFF) + –

I

D

, IS (ON) – –

I

D

(OFF) – +

I

D

6119-010

Figure 12. ADG1206 Leakage Currents as a Function of Temperature,

Dual Supply

Rev. 0 | Page 12 of 20

ADG1206/ADG1207

400

300

200

VDD = 12V
V

= 0V

SS

V

= 1V/10V

BIAS

I

D

IS (OFF) + –

, IS (ON )+ +

I

(OFF) – +

D

100

0

–100

LEAKAGE (pA)

I

(OFF) – +

–200

S

I

(OFF) + –

D

–300

, IS (ON) – –

I

–400

02040 10060 80 120

D

TEMPERATURE (° C)

Figure 13. ADG1206 Leakage Currents as a Function of Temperature,

Single Supply

6119-011

6

DEMUX (DRAIN TO SOURCE)
T

= 25°C

A

4

V

= +5V

DD

V

= –5V

SS

2

0

V

= +15V

DD

–2

V

= –15V

CHARGE INJECTI ON (pC)

SS

V
V

DD
SS

= +12V
= 0V

–4

–6

–15 15–10 –5 0 5 10

VS (V)

Figure 16. Drain-to-Source Charge Injection vs. Source Voltage

6119-014

200

180

IDD PER CHANNEL
T

= 25°C

A

160

140

VDD = +15V
V

= –15V

SS

120

(µA)

100

DD

I

80

60

40

20

0

0 2 4 6 8 10121416

1.0
MUX (SOURCE TO DRAIN)

T

= 25°C

A

0.9

VDD = +12V
V

= 0V

SS

Figure 14. I

LOGIC, INX (V)

vs. Logic Level

DD

0.8

0.7

0.6

0.5

V
V

DD
SS

= +15V
= –15V

0.4

0.3

CHARGE INJECTI ON (pC)

0.2

0.1

0

–15 15

V

= +5V

DD

V

= –5V

SS

–10 –5 0 5 10

V
V

DD
SS

= +12V

= 0V

VS (V)

Figure 15. Source-to-Drain Charge Injection vs. Source Voltage

350

300

250

200

150

TIME (ns)

100

50

0

–40 –20 0 20 40 60 80 100 120

06119-012

VDD = +12V
V

= 0V

SS

TEMPERATURE (°C)

VDD = +5V
V

VDD = +15V
V

= –15V

SS

SS

= –5V

06119-050

Figure 17. Transition Time vs. Temperature

0

VDD = +15V

–10

= –15V

V

SS

= 25°C

T

A

–20

–30

–40

–50

–60

–70

OFF ISOLATIO N (dB)

–80

–90

–100

–110

6119-013

10k 100k 1M 10M 100 M 1G

FREQUENCY (Hz)

06119-016

Figure 18. Off Isolation vs. Frequency

Rev. 0 | Page 13 of 20

ADG1206/ADG1207

–

0

TA = 25°C

–10

–20

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

10k 1G100M10M1M100k

Figure 19. ADG1206 Crosstalk vs. Frequency

FREQUENCY (Hz)

ADJACENT
CHANNELS

NON ADJACENT
CHANNELS

10

LOAD = 10kΩ
T

= 25°C

A

1

VDD = +5V, VSS = –5V, VS = +3.5V rms

THD + N (%)

0.1

0.01

06119-051

VDD = +15V, VSS = –15V, VS = +5V rms

10 100 1k 10k 100k

FREQUENCY (Hz)

6119-020

Figure 22. THD + N vs. Frequency

0

–10

–20

–30

–40

–50

–60

–70

CROSSTALK (d B)

–80

–90

–100

–110

10k 1G100M10M1M100k

4

–6

–8

–10

–12

–14

ON RESPONSE (dB)

–16

–18

–20

10k 1G100M10M1M100k

TA = 25°C

ADJACENT
CHANNELS

FREQUENCY (Hz)

Figure 20. ADG1207 Crosstalk vs. Frequency

VDD = +15V
V

= –15V

SS

= 25°C

T

A

FREQUENCY (Hz)

Figure 21. On Response vs. Frequency

NON ADJACENT
CHANNELS

ADG1207

ADG1206

20

VDD = +15V

18

V

= –15V

SS

T

= 25°C

A

16

14

12

10

8

CAPACITANCE (pF)

6

4

2

0

–15 155100–5–10

06119-052

SOURCE/DRAIN O N

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

06119-054

Figure 23. ADG1206 Capacitance vs. Source Voltage,

±15 V Dual Supply

20

18

16

14

12

10

8

CAPACITANCE (pF)

6

VDD = 12V

= 0V

V

4

SS

= 25°C

T

A

2

0

01810642

06119-053

SOURCE/DRAIN O N

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

2

06119-055

Figure 24. ADG1206 Capacitance vs. Source Voltage, 12 V Single Supply

Rev. 0 | Page 14 of 20

ADG1206/ADG1207

12

VDD = +15V

= –15V

V

SS

= 25°C

T

A

10

SOURCE/DRAIN O N

8

6

4

CAPACITANCE (pF)

2

0

–15 155100–5–10

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

Figure 25. ADG1207 Capacitance vs. Source Voltage, ±15 V Dual Supply

06119-056

0

TA = 25°C
NO DECOUPLING CAPACITORS

–10

V

= +15V

DD

V

= –15V

SS

–20

V p-p = 0.63V

–30

–40

–50

–60

AC PSRR (dB)

–70

–80

–90

–100

100 10M1M100k10k1k

Figure 27. AC PSRR vs. Frequency

FREQUENCY (Hz)

06119-058

14

VDD = 12V

= 0V

V

SS

12

10

CAPACITANCE (pF)

8

6

4

2

0

01810642

T

A

= 25°C

SOURCE/DRAIN O N

DRAIN OFF

SOURCE OFF

V

(V)

BIAS

Figure 26. ADG1207 Capacitance vs. Source Voltage, 12 V Single Supply

2

06119-057

Rev. 0 | Page 15 of 20

ADG1206/ADG1207

TERMINOLOGY

RON

Ohmic resistance between D and S.

ΔR

ON

Difference between the R

FLAT(ON)

R

Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured.

of any two channels.

ON

T

BBM

Off time measured between the 80% points of the switches
when switching from one address state to another.

V

INL

Maximum input voltage for Logic 0.

V

INH

Minimum input voltage for Logic 1.

(Off)

I

S

Source leakage current when the switch is off.

(Off)

I

D

Drain leakage current when the switch is off.

, IS (On)

I

D

Channel leakage current when the switch is on.

(VS)

V

D

Analog voltage on Terminals D and S.

(Off)

C

S

Channel input capacitance for the off condition.

(Off)

C

D

Channel output capacitance for the off condition.

, CS (On)

C

D

On switch capacitance.

C

IN

Digital input capacitance.

(EN)

t

ON

Delay time between the 50% and 90% points of the digital input
and the switch on condition.

(EN)

t

OFF

Delay time between the 50% and 90% points of the digital input
and the switch off condition.

t

TRANSITION

Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.

(I

INL

INH

)

I

Input current of the digital input.

I

DD

Positive supply current.

I

SS

Negative supply current.

Off Isolation

A measure of unwanted signal coupling through an off channel.

Charge Injection

A measure of the glitch impulse transferred from the digital
input to the analog output during switching.

Bandwidth

The frequency at which the output is attenuated by 3 dB.

On Response

The frequency response of the on switch.

THD + N

The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.

ACPSRR (AC Power Supply Rejection Ratio)

Measures the ability of a part to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is the
ACPSRR.

Rev. 0 | Page 16 of 20

ADG1206/ADG1207

V

V

VDDV

A

VDDV

VDDV

TEST CIRCUITS

V

35pF

ID(ON)

A

V

D

06119-027

SD

I

S

DS

06119-025

IS(OFF) ID(OFF)

S

SD

A A

SD

NC

V

D

06119-026

NC = NO CONNECT

Figure 28. On Resistance Figure 29. Off Leakage Figure 30. On Leakage

SS

3V

ADDRESS
DRIVE (V

0V

t

TRANSITION

OUTPUT

)

IN

50% 50%

90%

t

< 20ns

r

t

< 20ns

f

t

TRANSITION

90%

V

V

DD

S2 TO S15

GND

SS

S16

1

S1

D

OUTPUT

300Ω

V

S1

V

S16

A0

V

IN

50Ω

A1

A2

A3

ADG1206

2.4V EN

DDRESS

DRIVE (V

OUTPUT

3V

ENABLE
DRIVE (V

0V

OUTPUT

1

SIMILAR CO NNECTION F OR ADG1207.

Figure 31. Address to Output Switching Times, t

3V

)

IN

0V

80% 80%

t

BBM

V

IN

50Ω

Figure 32. Break-Before-Make Delay, t

)

IN

t

(EN)

ON

50% 50%

0.9V

O

0.9V

t

(EN)

OFF

O

V

IN

TRANSITION

SS

V

V

DD

S2 TO S15

GND

V

DDVSS

A0

A1

A2

A3

ADG1206

EN

GND

SS

S1

S16

1

D

SS

S2 TO S16

1

OUTPUT

S1

D

A0

A1

A2

A3

ADG1206

2.4V EN

1

SIMILAR CO NNECTION F OR ADG1207.

BBM

50Ω

300Ω

OUTPUT

300Ω

V

S

35pF

V

S

35pF

06119-028

06119-029

1

Figure 33. Enable Delay, t

(EN), t

ON

SIMILAR CONNECTION FOR ADG1207.

(EN)

OFF

06119-030

Rev. 0 | Page 17 of 20

ADG1206/ADG1207

V

V

VDDV

V

V

V

V

V

V

V

SS

V

DDVSS

3V

A0

A1

V

IN

A2

A3

ADG1206

S

EN

GND

1

D

C
1nF

V

OUT

L

06119-031

IN

OUT

Q

INJ

= CL × ΔV

OUT

ΔV

OUT

R

S

V

S

1

SIMILAR CO NNECTION F OR ADG1207.

Figure 34. Charge Injection

0.1µF

DD

V

SS

0.1µF

NETWO RK

V

DD

SS

S

50Ω

D

GND

ANALYZER

50Ω

V

V

OUT

R

L

50Ω

S

NETWO RK

ANALYZER

V

OUT

R

L

50Ω

V

S

0.1µF

DD

SS

0.1µF

V

V

DD

SS

S1

D

R

S2

50Ω

GND

V

0.1µF

OFF ISOLATION = 20 log

Figure 35. Off Isolation

DD

SS

0.1µF

NETWORK

V

V

DD

SS

S

ANALYZER

50Ω

D

R

L

GND

INSERTION LOSS = 20 log

50Ω

WITH SWITCH

V

OUT

V

WITHOUT SWITCH

OUT

Figure 36. Bandwidth

OUT

V

S

6119-032

CHANNEL-TO-CHANNEL CROSSTALK = 20 log

Figure 37. Channel-to-Channel Crosstalk

V

DD

0.1µF

V

V

S

V

OUT

IN

V

IN

SS

0.1µF

V

DD

SS

S

D

GND

06119-033

Figure 38. THD + Noise

R

L

10kΩ

V

OUT

V

S

AUDIO PRECISI ON

R

S

V

S

V p-p

V

OUT

06119-034

06119-035

Rev. 0 | Page 18 of 20

ADG1206/ADG1207

C

Y

OUTLINE DIMENSIONS

9.80

9.70

9.60

0.45

BSC

PIN 1

INDICATOR

1.00 MAX

0.85 NOM

PIN 1

0.15

0.05

OPLANARIT

0.10

28

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AE

1.20 MAX

SEATING

PLANE

15

4.50

4.40

4.30

0.20

0.09

6.40 BSC

141

Figure 39. 28-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-28)

Dimensions shown in millimeters

0.60

0.42

0.24

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.05

12° MAX

SEATING
PLANE

5.00

BSC SQ

4.75

*

EXPOSED

PAD

(TOP VIEW)

0.80 MAX

0.65 TYP

0.30

0.23

0.18

*

COMPLIANT TO JEDEC STANDARDS MO-220
WITH EXCEPTION TO PADDLE ORIENTATION.

2.85

2.70 SQ

2.55

0.20 REF

BSC SQ

0.05 MAX

0.02 NOM

Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

8°
0°

0.75

0.60

0.45

0.60

0.42

0.24

25

24

BOTTOM

17

16

3.50 REF

VIEW

32

1

8

9

0.20
MIN

ORDERING GUIDE

Model Temperature Range Description Package Option

ADG1206YRUZ
ADG1206YRUZ-REEL71 −40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
ADG1206YCPZ-REEL71 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2
ADG1207YRUZ
ADG1207YRUZ-REEL7
ADG1207YCPZ-REEL7

1

Z = Pb-free part.

1

1

1

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

1

−40°C to +125°C 28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28

−40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-2

Rev. 0 | Page 19 of 20

ADG1206/ADG1207

NOTES

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06119-0-7/06(0)

Rev. 0 | Page 20 of 20