ANALOG DEVICES ADF9010 Service Manual

900 MHz ISM Band

FEATURES

840 MHz to 960 MHz ISM bands Rx baseband analog low-pass filtering and PGA Integrated RF Tx upconverter Integrated integer-N PLL and VCO Integrated Tx PA preamplifier Differential fully balanced architectures

3.3 V supply Low power mode: <1 mA power-down current Programmable Rx LPF cutoff

330 kHz, 880 kHz, 1.76 MHz, and bypass Rx PGA gain settings: 3 dB to 24 dB in 3 dB steps Low noise BiCMOS technology 48-lead, 7 mm × 7 mm LFCSP

APPLICATIONS

900 MHz RFID readers Unlicensed band 900 MHz applications

RxINIP Rx

IN

Rx

IN

Rx

IN

MUXOUT

R

V

TUNE

LO

OUT

LO

OUT

Tx

OUT

Tx

OUT

Analog RF Front End

FUNCTIONAL BLOCK DIAGRAM

V

AV

QP

QN

SET

CP

RXV

DD

V

CM

IN

CM

CHARGE

PUMP

÷4

P

N

P

N

DC OFFSET

V

CORRECTI ON

CM

DC OFFSET

CORRECTI ON

PHASE

FREQUENCY

DETECTOR

QUADRATURE

PHASE SPLITTER

DD

P

R

COUNTER

B

COUNTER

A

COUNTER

Figure 1.

ADF9010

CE

DV

DD

ADF9010

INPUT SHIFT

REGISTE R

N COUNTER

N = BP + A

PRESCALER

P/P + 1

AGNDDGND

24-BIT

PLL

Rx Rx

OVF

Rx

Rx S

S S

REF

C

Tx

BB

CLK

DATA

LE

EXT

T

BB

IP IN

QP

QN

IN

1

2

3

4

IP

IN

QP

QN

07373-001

GENERAL DESCRIPTION

The ADF9010 is a fully integrated RF Tx modulator and Rx analog baseband front end that operates in the frequency range from 840 MHz to 960 MHz. The receive path consists of a fully differential I/Q baseband PGA, low-pass filter, and general signal conditioning before connecting to an Rx ADC for baseband conversion. The Rx LPF gain ranges from 3 dB to 24 dB, programmable in 3 dB steps. The Rx LPF features four programmable modes with cutoff frequencies of 330 kHz, 880 kHz, and 1.76 MHz, or the filter can be bypassed if necessary.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

The transmit path consists of a fully integrated differential Tx direct I/Q upconverter with a high linearity PA driver amplifier. It converts a baseband I/Q signal to an RF carrier-based signal between 840 MHz and 960 MHz. The highly linear transmit signal path ensures low output distortion.

Complete local oscillator (LO) signal generation is integrated on chip, including the integer-N synthesizer and VCO, which generate the required I and Q signals for transmit I/Q upconversion. The LO signal is also available at the output to drive an external RF demodulator. Control of all the on-chip registers is via a simple 3-wire serial interface. The device operates with a power supply ranging from 3.15 V to 3.45 V and can be powered down when not in use.

ADF9010

REVISION HISTORY

8/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADF9010

SPECIFICATIONS

TRANSMIT CHARACTERISTICS

AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted.

Table 1.

B Version

Parameter

1

Unit Test Conditions/Comments Min Typ Max

TRANSMIT MODULATOR CHARACTERISTICS

Operating Frequency Range 840 960 MHz

Range over which uncompensated sideband

suppression < −30 dBc Output Power 3 dBm VIQ = 1.4 V p-p differential Output P1 dB 10 dBm Carrier Feedthrough −40 dBm Sideband Suppression −46 dBc Output IP3 24 dBm

= −4 dBm per tone, 10 MHz and 12 MHz

P

OUT

baseband input frequencies used. Noise Floor −158 dBm/Hz

TRANSMIT BASEBAND CHARACTERISTICS

Input Impedance of Each Pin 4 kΩ typ Single-ended frequencies up to 2 MHz Input Capacitance of Each Pin 3 pF At 10 MHz Input Signal Level 1.4 V p-p Measured differentially at I or Q Common-Mode Output Level 0.6 V Tx Baseband 3 dB Bandwidth 20 MHz

POWER SUPPLIES

Voltage Supply 3.15 3.45 V IDD

Digital IDD 5 6 mA Rx Baseband 70 80 mA Maximum gain settings Tx Modulator 140 mA Full power, baseband inputs biased at 0.5 V LO Synthesizer and VCO 140 mA + 5 dBm LO power setting selected Tot al IDD 360 410 mA Power-Down Rx VDD 1 mA AVDD 1 20 μA DVDD 1 20 μA

LOGIC INPUTS (SERIAL INTERFACE)

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

1.4 V 1.8 V logic compatible

INH

0.4 V

INL

±1 μA

Input Capacitance, CIN 5 pF

LOGIC OUTPUTS (MUXOUT)

Output High Voltage, VOH DVDD − 0.4 V IOL = 500 μA Output Low Voltage, VOL 0.4 V IOH = 500 μA

1

Operating temperature range for the B version is −40°C to +85°C.

Rev. 0 | Page 3 of 28

ADF9010

RECEIVE BASEBAND CHARACTERISTICS

AVDD = DVDD = 3.3 V ± 5%, AGND = DGND = GND = 0 V, TA = 25°C, dBm refers to 50 Ω, 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias, baseband frequency = 1 MHz, unless otherwise noted.

Table 2.

B Version

Parameter

RECEIVE BASEBAND PGA

Highest Voltage Gain 24 dB Lowest Voltage Gain 3 dB Gain Control Range 18 dB Programmable using 3-bit interface Gain Control Step 3 dB Noise Spectral Density (Referred to Input) 3.5 nV/√Hz At maximum PGA gain

RECEIVE BASEBAND FILTERS

3 dB Cutoff Frequency (Mode 0) 320 kHz After filter calibration

Gain Flatness 0.5 dB Typical from dc to 90 kHz Differential Group Delay 500 μs DC to 360 kHz 150 μs 170 kHz to 310 kHz Attenuation Template After filter calibration

@ 330 kHz Offset −3 dB @ 500 kHz Offset −8 dB @ 1 MHz Offset −28 dB

3 dB Cutoff Frequency (Mode 1) 880 kHz After filter calibration

Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 μs DC to 360 kHz 150 μs 170 kHz to 310 kHz Attenuation Template After filter calibration

@ 880 kHz Offset −3 dB @ 2 MHz Offset −17 dB @ 4 MHz Offset −38 dB

3 dB Cutoff Frequency (Mode 2) 1.76 MHz After filter calibration

Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 μs DC to 360 kHz 150 μs 170 kHz to 310 kHz Attenuation Template After filter calibration

@ 1.76 MHz Offset −3 dB @ 4 MHz Offset −18 dB @ 8 MHz Offset −38 dB @ 16 MHz Offset −60 dB

3 dB Cutoff Frequency (Mode 3) 4 MHz After filter calibration

Gain Flatness 0.5 dB DC to 90 kHz Differential Group Delay 500 μs DC to 360 kHz

@ 2 MHz Offset −0.5 dB @ 4 MHz Offset −2 dB

Input Impedance of Each Pin

@ 24 dB gain 250 Ω

@ 3 dB gain 4 kΩ Input Capacitance of Each Pin 3 pF At 10 MHz Input Signal Level 2 V p-p Measured differentially at I or Q Common-Mode Output Level 1.65 V On Rx baseband outputs Maximum Residual DC 150 mV Baseband gain 0 dB − 27 dB

1

Operating temperature range for the B version is −40°C to +85°C.

1

Unit Test Conditions/Comments Min Typ Max

Rev. 0 | Page 4 of 28

ADF9010

INTEGER-N PLL AND VCO CHARACTERISTICS

Table 3.

B Version

Parameter

1

Unit Test Conditions/Comments Min Typ Max

VCOOPERATING FREQUENCY 3360 3840 MHz

LO OUTPUT CHARACTERISTICS Measured at LO output (900 MHz)

VCO Control Voltage Sensitivity 8 MHz/V

3.6 GHz VCO frequency (taking into account

divide by 4) Harmonic Content (Second) −27 dBc Harmonic Content (Third) −14 dBc Frequency Pushing (Open Loop) 1.2 MHz/V Frequency Pulling (Open Loop) 10 Hz Into 2.00 VSWR load. Lock Time 1000 μs 10 kHz loop bandwidth Output Power −4 to +5 dBm

LO outputs combined in a 1:1 transformer;

programmable in 3 dB steps Output Power Variation ±3 dB

NOISE CHARACTERISTICS Measured at LO output (900 MHz)

VCO Phase Noise Performance

2

@ 100 kHz Offset −120 dBc/Hz @ 1 MHz Offset −141 dBc/Hz

@ 10 MHz Offset −154 dBc/Hz In-Band Phase Noise Normalized In-Band Phase Noise Floor Spurious Frequencies at Output Channel Spacing −70 dBc

3, 4

−96 dBc/Hz @ 1 kHz offset from carrier

3, 4

−220 dBc/Hz

900 MHz offset, 1 MHz PFD frequency, 250 kHz channel spacing; loop bandwidth = 7.5 kHz

PHASE DETECTOR

Phase Detector Frequency5 8 MHz Maximum Allowable Prescaler Output Frequency

6

325 MHz

CHARGE PUMP

ICP Sink/Source With R

= 4.7 kΩ

SET

High Value 5 mA

Low Value 0.625 mA

R

Range 2.7 10 kΩ

SET

ICP Three-State Leakage Current 0.2 nA Sink and Source Current Matching 2 % 1.25 V ≤ VCP ≤ 2.5 V ICP vs. VCP 1.5 % 1.25 V ≤ VCP ≤ 2.5 V ICP vs. Temperature 2 % VCP = 2.0 V

PLL REFERENCE

Reference Clock Frequency 10 104 MHz Reference Clock Sensitivity 0.7 PLL VDD V p-p Reference Input Capacitance 5 pF REFIN Input Current ±100 μA

1

Operating temperature range for the B version is −40°C to +85°C.

2

The noise of the VCO is measured in open-loop conditions.

3

The phase noise is measured with the EVAL-ADF9010EBZ1 evaluation board and the Agilent E5052A spectrum analyzer. The spectrum analyzer provides the REFIN for

the synthesizer; offset frequency = 1 kHz.

4

f

= 10 MHz; f

REFIN

5

Guaranteed by design. Sample tested to ensure compliance.

6

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

= 1000 kHz; N = 3600; loop BW = 25 kHz.

PFD

Rev. 0 | Page 5 of 28

ADF9010

WRITE TIMING CHARACTERISTICS

AVDD = DVDD = 3.3 V ± 5%; AGND = DGND = GND = 0 V; TA = 25°C, guaranteed by design, but not production tested.

Table 4.

Parameter Limit at t

t1 10 ns min S t2 10 ns min S t3 25 ns min S t4 25 ns min S t5 10 ns min S t6 20 ns min SLE pulse width

S

CLCK

MIN

to t

(B Version) Unit Test Conditions/Comments

MAX

to S

DATA

CLK

t

3

4

t

2

1

setup time

CLK

to S

hold time

CLK

high duration low duration to SLE setup time

S

DATA

S

DB22DB23 (MSB)

LE

DB2

DB1

(CONTROL BIT C2)

t

5

DB0 (LSB)

(CONTROL BIT C1)

t

6

7373-002

Figure 2. Write Timing Diagram

Rev. 0 | Page 6 of 28

ADF9010

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted.

Table 5.

Parameter Rating

DVDD, RxVDD , AVDD to GND1 −0.3 V to +3.9 V RxVDD, AVDD to DVDD −0.3 V to +0.3 V VP to GND1 −0.3 V to +5.5 V Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND1 −0.3 V to AVDD + 0.3 V Charge Pump Voltage to GND1 −0.3 V to VP to GND1 REFIN, LO LO

EXT

Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C LCSP θJA Thermal Impedance 26°C/W Reflow Soldering

Peak Temperature 260°C/W Time at Peak Temperature 40 sec

1

GND = AGND = DGND = 0 V.

EXT

P to LO

P, L O

N to GND1 −0.3 V to VDD + 0.3 V

EXT

N ±320 mV

EXT

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high-performance RF integrated circuit with an ESD rating of <0.5 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT

The ADF9010 transistor count is 40,454 (CMOS) and 994 (bipolar).

ESD CAUTION

Rev. 0 | Page 7 of 28

ADF9010

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

QN

QP

LO LO

Rx

IN

Rx

IN

RxV

OUT

AGND

DGND

REF

DV

CP

AGND

DD

IN

Rx

RxV

NC

AGND

OVF

MUXOUT

Rx

4847464544434241403938

1

IP

2

IN

3

DD

4

N

5

P

6

7

8

IN

9

DD

10

V

P

11

12

PIN 1 INDICATOR

ADF9010

TOP VIEW

(Not to Scale)

SLES

DATASCLK

CE

DV

37

DD

Rx

IN36

BB

Rx

35

IP

BB

34

Rx

QP

BB

33

Rx

QN

BB

32

C

3

EXT

31

C

4

EXT

30

R

SET

29

AV

DD

28

TxBBIN

27

Tx

IP

BB

26

Tx

QP

BB

25

Tx

QN

BB

NC = NO CONNECT

13141516171819

T

1

2

DD

C

EXT

AV

C

V

TUNE

2021222324

P

N

EXT

AGND

LO

P

N

DD

EXT

AV

AGND

XOUT

T

07373-004

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1, 2 RxINIP, RxININ Input/Complementary In-Phase Input to the Receive Filter Stage. 3, 46 RxVDD

Receiver Filter Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. RxV

4, 5 LO

OUT

N, LO

OUT

value as AV

P

Buffered Local Oscillator Output. These outputs are used to provide the LO for the external RF

and DVDD.

DD

demodulator. These require an RF choke to AVDD and a dc bypass capacitor before connection to a

demodulator. 6, 12, 18, 24, 44 AGND Analog Ground. This is the ground return path of analog circuitry. 7 DGND Digital Ground. 8 REFIN

PLL Reference Input. This is a CMOS input with a nominal threshold of V

input resistance of 100 kΩ (see Figure 13). This input can be driven from a TTL or CMOS crystal

oscillator, or it should be ac-coupled. 9, 37 DVDD

10 VP

11 CP

Digital Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the digital

ground plane should be placed as close as possible to this pin. DV

DD

This pin supplies the voltage to the charge pump. If the internal VCO is used, it should equal AV

and DV

Charge Pump Output. When enabled, this pin provides ±I

. If an external VCO is used, the voltage can be AVDD < VP < 5.5 V.

DD

to the external loop filter, which in turn

CP

drives the external VCO. 13 CT

A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to

AGND with a value of 10 nF. The output voltage on this part is proportional to temperature. At

ambient temperature, the voltage is 2.0 V. 14 C

EXT

1

A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to

AGND with a value of 10 nF. 15 C

EXT

2

A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to

AGND with a value of 10 nF. 16, 21, 29 AVDD

Analog Power Supply. This voltage ranges from 3.15 V to 3.45 V. Decoupling capacitors to the

analog ground plane should be placed as close as possible to this pin. AV

as DV

.

DD

must be the same

DD

/2 and a dc equivalent

DD

must be the same value as AVDD.

must be the same value

DD

Rev. 0 | Page 8 of 28

ADF9010

Pin No. Mnemonic Description

17 V

19, 20 LO

22, 23 Tx

25, 26 TxBBQN, TxBBQP Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator. 27, 28 TxBBIP, TxBBIN Baseband In-Phase Input/Complementary to the Transmit Modulator. 30 R

31 C

32 C

33, 34 RxBBQN, RxBBQP

35, 36 RxBBIP, RxBBIN

38 CE

39 S

40 S

41 SLE

42 MUXOUT

43 OVF

45 NC No Connect. 47, 48 RxINQP, RxINQN Input/Complementary Quadrature Input to the Receive Filter Stage.

TUNE

OUT

SET

EXT

CLK

DATA

EXT

4

3

P, L O

P, Tx

OUT

EXT

Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the CP output.

N

Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO. These pins are internally dc-biased and must be ac-coupled. AC-couple LO and ac-couple the VCO signal with 100 pF through LO

EXT

P.

N to ground with 100 pF

EXT

Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for best results.

Connecting a resistor between this pin and AGND sets the maximum charge pump output current. The nominal voltage potential at the R

I

CPMAX

= 25.5/R

SET

pin is 0.66 V. The relationship between ICP and R

SET

is

where:

is 5.1 kΩ.

R

SET

I

is 5 mA.

CPMAX

A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled to AGND with a value of 10 nF.

Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip.

Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is passed to the baseband MxFE chip.

Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device depending on the status of the power-down bits.

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the S

rising edge. This is a high impedance CMOS input.

CLK

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into one of the four latches; the latch uses the control bits.

This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled PLL reference frequency to be accessed externally.

A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain if the ADC detects an overload.

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADF9010 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TRANSMIT CHARACTERISTICS

RECEIVE BASEBAND CHARACTERISTICS

INTEGER-N PLL AND VCO CHARACTERISTICS

WRITE TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

TRANSISTOR COUNT

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS