ANALOG DEVICES ADF7023 Service Manual

High Performance, Low Power, ISM Band

http://www.BDTIC.com/ADI

FSK/GFSK/OOK/MSK/GMSK Transceiver IC

FEATURES

Ultralow power, high performance transceiver Frequency bands

862 MHz to 928 MHz 431 MHz to 464 MHz

Data rates supported

1 kbps to 300 kbps

1.8 V to 3.6 V power supply Single-ended and differential PAs Low IF receiver with programmable IF bandwidths

100 kHz, 150 kHz, 200 kHz, 300 kHz

Receiver sensitivity (BER)

−116 dBm at 1.0 kbps, 2FSK, GFSK

−107.5 dBm at 38.4 kbps, 2FSK, GFSK

−102.5 dBm at 150 kbps, GFSK, GMSK

−100 dBm at 300 kbps, GFSK, GMS

−104 dBm at 19.2 kbps, OOK

Very low power consumption

12.8 mA in PHY_RX mode (maximum front-end gain)

24.1 mA in PHY_TX mode (10 dBm output, single-ended PA)

0.75 μA in PHY_SLEEP mode (32 kHz RC oscillator active)

1.28 μA in PHY_SLEEP mode (32 kHz XTAL oscillator active)

0.33 μA in PHY_SLEEP mode (Deep Sleep Mode 1) RF output power of −20 dBm to +13.5 dBm (single-ended PA) RF output power of −20 dBm to +10 dBm (differential PA) Patented fast settling automatic frequency control (AFC) Digital received signal strength indication (RSSI) Integrated PLL loop filter and Tx/Rx switch Fast automatic VCO calibration Automatic synthesizer bandwidth optimization On-chip, low-power, custom 8-bit processor

Radio control

ADF7023

Packet management Smart wake mode

Packet management support

Highly flexible for a wide range of packet formats Insertion/detection of preamble/sync word/CRC/address Manchester and 8b/10b data encoding and decoding Data whitening

Smart wake mode

Current saving low power mode with autonomous receiver

wake up, carrier sense, and packet reception

Downloadable firmware modules

Image rejection calibration, fully automated (patent

pending)

128-bit AES encryption/decryption with hardware

acceleration and key sizes of 128 bits, 192 bits, and 256 bits

Reed Solomon error correction with hardware acceleration 240-byte packet buffer for TX/RX data Efficient SPI control interface with block read/write access Integrated battery alarm and temperature sensor Integrated RC and 32.768 kHz crystal oscillator On-chip, 8-bit ADC 5 mm × 5 mm, 32-pin, LFCSP package

APPLICATIONS

Smart metering IEEE 802.15.4g Wireless MBUS Home automation Process and building control Wireless sensor networks (WSNs) Wireless healthcare

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

8/10—Revision 0: Initial Version

PA/LNA Matching ...................................................................... 81

Command Reference ...................................................................... 83

Register Maps .................................................................................. 84

BBRAM Register Description ................................................... 86

MCR Register Description ......................................................... 98

Outline Dimensions ...................................................................... 106

Ordering Guide ......................................................................... 106

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FUNCTIONAL BLOCK DIAGRAM

ADCIN_ATB3

RFIO_1P RFIO_1N

RFO2

1

GPIO RE FERS TO PINS 17, 18, 1 9, 20, 25, AND 27.

LNA

PA

PA RAMP PROFILE

LDO1

CREGVCO CREGSYNTH

CREGRFx

DIVIDER

ADF7023

LDO2

LDO3

RSSI/

LOGAMP

LOOP

FILTER

CREGDIGx

CHARGE

PUMP

DIVIDER

Σ-Δ

MODULATOR

BIAS

LDO4

8-BIT

ADC

MUX

PFD

ANALOG

TEST

GENERAL DESCRIPTION

The ADF7023 is a very low power, high performance, highly integrated 2FSK/GFSK/OOK/MSK/GMSK transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide licensefree ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC (Part 15), the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported.

The transmit RF synthesizer contains a VCO and a low noise fractional-N PLL with an output channel frequency resolution of 400 Hz. The VCO operates at 2× or 4×, the fundamental frequency to reduce spurious emissions. The receive and transmit synthesizer bandwidths are automatically, and independently, configured to achieve optimum phase noise, modulation quality, and settling time. The transmitter output power is programmable from −20 dBm to +13.5 dBm, with automatic PA ramping to meet transient spurious specifications. The part possesses both single-ended and differential PAs, which allows for Tx antenna diversity.

The receiver is exceptionally linear, achieving an IP3 specification of −12.2 dBm and −11.5 dBm at maximum gain and minimum gain, respectively, and an IP2 specification of 18.5 dBm and 27 dBm at maximum gain and minimum gain, respectively. The receiver achieves an interference blocking specification of 66 dB at ±2 MHz offset and 74 dB at ±10 MHz offset. Thus, the part is extremely resilient to the presence of interferers in spectrally noisy environments. The receiver features a novel, high speed, automatic frequency control (AFC) loop, allowing the PLL to

f

DEV

Figure 1.

FSK ASK

DEMOD

CDR AFC AGC

26MHz OSC

GAUSSIAN

FILTER

TEMP

SENSOR

8-BIT RISC

PROCESSOR

BATTERY MONITOR

4kB ROM

MAC

2kB RAM

256 BYTE

PACKET

RAM

64 BYTE

BBRAM

256 BYTE

MCR RAM

WAKE-UP CONT ROL

TIMER UNIT

32kHz

OSC

32kHz

RCOSC

IRQ

CTRL

SPI

GPIO

TEST

DAC

CLOCK

DIVIDER

26MHz

OSC

XOSC26N XOSC26PXOSC32KP_GP5_ATB1XOSC32KN_ATB2RBIAS

IRQ_GP3

CS MISO SCLK MOSI

GPIO

find and correct any RF frequency errors in the recovered packet. A patent pending, image rejection calibration scheme is available through a program download. The algorithm does not require the use of an external RF source nor does it require any user intervention once initiated. The results of the calibration can be stored in nonvolatile memory for use on subsequent power-ups of the transceiver.

The ADF7023 operates with a power supply range of 1.8 V to

3.6 V and has very low power consumption in both Tx and Rx modes, enabling long lifetimes in battery-operated systems while maintaining excellent RF performance. The device can enter a low power sleep mode in which the configuration settings are retained in BBRAM.

The ADF7023 features an ultralow power, on-chip, communications processor. The communications processor, which is an 8-bit RISC processor, performs the radio control, packet management, and smart wake mode (SWM) functionality. The communications processor eases the processing burden of the companion processor by integrating the lower layers of a typical communication protocol stack. The communications processor also permits the download and execution of a set of firmware modules that include image rejection (IR) calibration, AES encryption, and Reed Solomon coding.

The communications processor provides a simple commandbased radio control interface for the host processor. A singlebyte command transitions the radio between states or performs a radio function.

The communications processor provides support for generic packet formats. The packet format is highly flexible and fully programmable, thereby ensuring its compatibility with

1

08291-001

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proprietary packet profiles. In transmit mode, the communications processor can be configured to add preamble, sync word, and CRC to the payload data stored in packet RAM. In receive mode, the communications processor can detect and interrupt the host processor on reception of preamble, sync word, address, and CRC and store the received payload to packet RAM. The ADF7023 uses an efficient interrupt system comprising MAC level interrupts and PHY level interrupts that can be individually set. The payload data plus the 16-bit CRC can be encoded/decoded using Manchester or 8b/10b encoding. Alternatively, data whitening and dewhitening can be applied.

The smart wake mode (SWM) allows the ADF7023 to wake up autonomously from sleep using the internal wake-up timer without intervention from the host processor. After wake-up, the ADF7023 is controlled by the communications processor. This functionality allows carrier sense, packet sniffing, and packet reception while the host processor is in sleep, thereby reducing overall system current consumption. The smart wake mode can wake the host processor on an interrupt condition. These interrupt conditions can be configured to include the reception of valid preamble, sync word, CRC, or address match.

Wake-up from sleep mode can also be triggered by the host processor. For systems requiring very accurate wake-up timing, a 32 kHz oscillator can be used to drive the wake-up timer. Alternatively, the internal RC oscillator can be used, which gives lower current consumption in sleep.

The ADF7023 features an advanced encryption standard (AES) engine with hardware acceleration that provides 128-bit block encryption and decryption with key sizes of 128 bits, 192 bits, and 256 bits. Both electronic code book (ECB) and Cipher Block Chaining Mode 1 (CBC Mode 1) are supported. The AES engine can be used to encrypt/decrypt packet data and can be used as a standalone engine for encryption/decryption by the host processor. The AES engine is enabled on the ADF7023 by downloading the AES software module to program RAM. The AES software module is available from Analog Devices, Inc.

An on-chip, 8-bit ADC provides readback of an external analog input, the RSSI signal, or an integrated temperature sensor. An integrated battery voltage monitor raises an interrupt flag to the host processor whenever the battery voltage drops below a userdefined threshold.

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SPECIFICATIONS

VDD = VDDBAT1 = VDDBAT2= 1.8 V to 3.6 V, GND = 0 V, TA = T V

= 3 V, TA = 25°C.

DD

RF AND SYNTHESIZER SPECIFICATIONS

Table 1.

Parameter Min Typ Max Unit Test Conditions

RF CHARACTERISTICS

Frequency Ranges 862 928 MHz 431 464 MHz

PHASE-LOCKED LOOP

Channel Frequency Resolution 396.7 Hz Phase Noise (In-Band) −88 dBc/Hz

Phase Noise at Offset of

1 MHz −126 dBc/Hz PA output power = 10 dBm, RF frequency = 868 MHz 2 MHz −131 dBc/Hz PA output power = 10 dBm, RF frequency = 868 MHz

10 MHz −142 dBc/Hz PA output power = 10 dBm, RF frequency = 868 MHz VCO Calibration Time 142 µs Synthesizer Settling Time 56 µs

CRYSTAL OSCILLATOR

Crystal Frequency 26 MHz Parallel load resonant crystal Recommended Load Capacitance 7 18 pF Maximum Crystal ESR 1800 Ω 26 MHz crystal with 18 pF load capacitance Pin Capacitance 2.1 pF Capacitance for XOSC26P and XOSC26N Start-Up Time 310 µs 26 MHz crystal with 7 pF load capacitance 388 µs 26 MHz crystal with 18 pF load capacitance

SPURIOUS EMISSIONS

Integer Boundary Spurious

910.1 MHz −39 dBc

911.0 MHz −79 dBc

Reference Spurious

868 MHz/915 MHz −80 dBc

Clock-Related Spur Level −60 dBc

MIN

to T

, unless otherwise noted. Typical specifications are at

MAX

10 kHz offset, PA output power = 10 dBm, RF = 868 MHz

Frequency synthesizer settles to within ±5 ppm of the target frequency within this time following the VCO calibration, transmit, and receive, 2FSK/GFSK/ MSK/GMSK

Using 130 kHz synthesizer bandwidth, integer boundary spur at 910 MHz (26 MHz × 35), inside synthesizer loop bandwidth

Using 130 kHz synthesizer bandwidth, integer boundary spur at 910 MHz (26 MHz × 35), outside synthesizer loop bandwidth

Using 130 kHz synthesizer bandwidth and using 92 kHz synthesizer bandwidth (default for PHY_RX)

Measured in a span of ±350 MHz for synthesizer bandwidth = 92 kHz, RF frequency = 868.95 MHz, PA output power = 10 dBm, V used

= 3.6 V, single-ended PA

DD

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TRANSMITTER SPECIFICATIONS

Table 2.

Parameter Min Typ Max Unit Test Conditions

DATA RATE

2FSK/GFSK/MSK/GMSK 1 300 kbps OOK 2.4 19.2 kbps

Data Rate Resolution 100 bps

MODULATION ERROR RATE (MER) RF frequency = 928 MHz, GFSK

10 kbps to 49.5 kbps 25.4 dB Modulation index = 1

49.6 kbps to 129.5 kbps 25.3 dB Modulation index = 1

129.6 kbps to 179.1 kbps 23.9 dB Modulation index = 0.5

179.2 kbps to 239.9 kbps 23.3 dB Modulation index = 0.5 240 kbps to 300 kbps 23 dB Modulation index = 0.5

MODULATION

2FSK/GFSK/MSK/GMSK Frequency

Deviation Deviation Frequency Resolution 100 Hz Gaussian Filter BT 0.5 Nonprogrammable

OOK

PA Off Feedthrough −94 dBm VCO Frequency Pulling 30

SINGLE-ENDED PA

Maximum Power Minimum Power −20 dBm Transmit Power Variation vs.

Temperature Transmit Power Variation vs. VDD ±1 dB From 1.8 V to 3.6 V, RF frequency = 868 MHz Transmit Power Flatness ±1 dB

Programmable Step Size

−20 dBm to +13.5 dBm 0.5 dB Programmable in 63 steps

DIFFERENTIAL PA

Maximum Power1 10 dBm Programmable Minimum Power −20 dBm Transmit Power Variation vs.

Temperature Transmit Power Variation vs. VDD ±2 dB From 1.8 V to 3.6 V, RF frequency = 868 MHz Transmit Power Flatness ±1 dB From 863 MHz to 870 MHz Programmable Step Size

−20 dBm to +10 dBm 0.5 dB Programmable in 63 steps

HARMONICS

Single-Ended PA

Second Harmonic −15.1 dBc

Third Harmonic −29.3 dBc

All Other Harmonics −47.6 dBc Differential PA

Second Harmonic −23.2 dBc

Third Harmonic −25.2 dBc

All Other Harmonics −24.2 dBc

1

13.5 dBm Programmable, separate PA and LNA match

0.1 409.5 kHz

kHz rms

±0.5 dB From −40°C to +85°C, RF frequency = 868 MHz

±1 dB From −40°C to +85°C, RF frequency = 868 MHz

Manchester encoding enabled (Manchester chip rate = 2 × data rate)

Data rate = 19.2 kbps (38.4 kcps Manchester encoded), PA output = 10 dBm, PA ramp rate = 64 codes/bit

2

From 902 MHz to 928 MHz and 863 MHz to 870 MHz

868 MHz, unfiltered conductive, PA output power = 10 dBm

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Parameter Min Typ Max Unit Test Conditions

OPTIMUM PA LOAD IMPEDANCE

Single-Ended PA, in Transmit

Mode

fRF = 915 MHz 50.8 + j10.2 Ω fRF = 868 MHz 45.5 + j12.1 Ω fRF = 433 MHz 46.8 + j19.9 Ω

Single-Ended PA, in Receive Mode

fRF = 915 MHz 9.4 − j124 Ω fRF = 868 MHz 9.5 − j130.6 Ω fRF = 433 MHz 11.9 − j260.1 Ω

Differential PA, in Transmit Mode

fRF = 915 MHz 20.5 + j36.4 Ω fRF = 868 MHz 24.7 + j36.5 Ω fRF = 433 MHz 55.6 + j81.5 Ω

1

Measured as the maximum unmodulated power.

2

A combined single-ended PA and LNA match can reduce the maximum achievable output power by up to 1 dB.

Load impedance between RFIO_1P and RFIO_1N to ensure maximum output power

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RECEIVER SPECIFICATIONS

Table 3.

Parameter Min Typ Max Unit Test Conditions

2FSK/GFSK/MSK/GMSK INPUT

SENSITIVITY, BIT ERROR RATE (BER)

1.0 kbps −116 dBm

10 kbps −111 dBm

38.4 kbps −107.5 dBm

50 kbps −106.5 dBm

100 kbps −105 dBm

150 kbps −104 dBm

200 kbps −103 dBm

300 kbps −100.5 dBm

2FSK/GFSK/MSK/GMSK INPUT

SENSITIVITY, PACKET ERROR RATE (PER)

1.0 kbps −115.5 dBm

9.6 kbps −110.6 dBm

38.4 kbps −106 dBm

50 kbps −104.3 dBm

100 kbps −102.6 dBm

150 kbps −101 dBm

200 kbps −99.1 dBm

300 kbps −97.9 dBm

OOK INPUT SENSITIVITY, PACKET ERROR

RATE (PER)

19.2 kbps (38.4 kcps, Manchester

Encoded)

2.4 kbps (4.8 kcps, Manchester

Encoded)

LNA AND MIXER, INPUT IP3

Minimum LNA Gain −11.5 dBm Maximum LNA Gain −12.2 dBm

LNA AND MIXER, INPUT IP2

Max LNA Gain, Max Mixer Gain 18.5 dBm Min LNA Gain, Min Mixer Gain 27 dBm

At BER = 1E − 3, RF frequency = 868 MHz, 915 MHz LNA and PA matched separately

Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz

Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz

Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz

At PER = 1%, RF frequency = 868 MHz, 915 MHz LNA and PA matched separately 128 bits, packet mode

Frequency deviation = 4.8 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 9.6 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 20 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 12.5 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 25 kHz, IF filter bandwidth = 100 kHz

Frequency deviation = 37.5 kHz, IF filter bandwidth = 150 kHz

Frequency deviation = 50 kHz, IF filter bandwidth = 200 kHz

Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz

At PER = 1%, RF frequency = 868 MHz, 915 MHz, 433 MHz, LNA and PA matched separately = 128 bits, packet mode, IF filter bandwidth = 100 kHz

−104.7 dBm

−109.7 dBm

Receiver LO frequency (f

0.4 MHz, f

Receiver LO frequency (f

1.1 MHz, f

= fLO + 0.7 MHz

SOURCE2

= fLO + 1.3 MHz

SOURCE2

1

, packet length =

) = 914.8 MHz, f

LO

) = 920.8 MHz, f

LO

1

, packet length

= fLO +

SOURCE1

= fLO +

SOURCE1

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Parameter Min Typ Max Unit Test Conditions

LNA AND MIXER, 1 dB COMPRESSION

POINT Max LNA Gain, Max Mixer Gain −21.9 dBm Min LNA Gain, Min Mixer Gain −21 dBm

ADJACENT CHANNEL REJECTION

CW Interferer

200 kHz Channel Spacing 38 dB

300 kHz Channel Spacing 39 dB

38 dB

400 kHz Channel Spacing 40 dB

600 kHz Channel Spacing 41 dB

Modulated Interferer

200 kHz Channel Spacing 38 dB

300 kHz Channel Spacing 36 dB

400 kHz Channel Spacing 34 dB

600 kHz Channel Spacing 35 dB

CO-CHANNEL REJECTION −4 dB

BLOCKING

RF Frequency = 433 MHz

±2 MHz 68 dB ±10 MHz 76 dB

RF Frequency = 868 MHz

±2 MHz 66 dB ±10 MHz 74 dB

RF Frequency = 915 MHz

±2 MHz 66 dB ±10 MHz 74 dB

RF frequency = 915 MHz

Wanted signal 3 dB above the input sensitivity level (BER = 10 BER = 10

−3

), CW interferer power level increased until

−3

, image calibrated

IF BW = 100 kHz, wanted signal: F DR = 50 kbps

IF BW = 100 kHz, wanted signal: F DR = 100 kbps

IF BW = 150 kHz, wanted signal: F DR = 150 kbps

IF BW = 200 kHz, wanted signal: F DR = 200 kbps

IF BW = 300 kHz, wanted signal: F DR = 300 kbps

Wanted signal 3 dB above the input sensitivity level (BER = 10−3), modulated interferer with the same modulation as the wanted signal; interferer power level increased until BER = 10−3, image calibrated

IF BW = 100 kHz, wanted signal: F DR = 50 kbps

IF BW = 100 kHz, wanted signal: F DR = 100 kbps

IF BW = 150 kHz, wanted signal: F DR = 150 kbps

IF BW = 200 kHz, wanted signal: F DR = 200 kbps

IF BW = 300 kHz, wanted signal: F DR = 300 kbps

Desired signal 10 dB above the input sensitivity level (BER = 10

−3

), data rate = 38.4 kbps, frequency deviation

= 20 kHz, RF frequency = 868 MHz Desired signal 3 dB above the input sensitivity level

(BER = 10−3) of −107.5 dBm (data rate = 38.4 kbps), modulated interferer power level increased until BER = 10−3 (see the Typical Performance Characteristics section for blocking at other offsets and IF bandwidths)

= 12.5 kHz,

DEV

= 25 kHz,

DEV

= 37.5 kHz,

DEV

= 50 kHz,

DEV

= 75 kHz,

DEV

= 12.5 kHz,

DEV

= 25 kHz,

DEV

= 37.5 kHz,

DEV

= 50 kHz,

DEV

= 75 kHz,

DEV

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Parameter Min Typ Max Unit Test Conditions

BLOCKING, ETSI EN 300 220

±2 MHz −28 dBm ±10 MHz −20.5 dBm

WIDEBAND INTERFERENCE REJECTION 75 dB

IMAGE CHANNEL ATTENUATION

868 MHz, 915 MHz 36/45 dB 433 MHz 40/54 dB Uncalibrated/calibrated

AFC

Accuracy 1 kHz Maximum Pull-In Range

300 kHz IF Filter Bandwidth ±150 kHz 200 kHz IF Filter Bandwidth ±100 kHz 150 kHz IF Filter Bandwidth ±75 kHz 100 kHz IF Filter Bandwidth ±50 kHz

PREAMBLE LENGTH

AFC Off, AGC Lock on Sync Word Detection

38.4 kbps 8 Bits 300 kbps 24 Bits

AFC On, AFC and AGC Lock on Preamble Detection

9.6 kbps 44 Bits

38.4 kbps 44 Bits 50 kbps 50 Bits 100 kbps 52 Bits 150 kbps 54 Bits 200 kbps 58 Bits 300 kbps 64 Bits

AFC On, AFC and AGC Lock on Sync Word Detection

38.4 kbps 14 Bits 300 kbps 32 Bits

RSSI

Range at Input −97 to −26 dBm Linearity ±2 dB Absolute Accuracy ±3 dB

SATURATION (MAXIMUM INPUT LEVEL)

2FSK/GFSK/MSK/GMSK 12 dBm OOK −13 dBm OOK modulation depth = 20 dB

10 dBm OOK modulation depth = 60 dB

Measurement procedure as per ETSI EN 300 220-1 V2.3.1; desired signal 3 dB above the ETSI EN 300 220 reference sensitivity level of −99 dBm, IF bandwidth =100 kHz, data rate = 38.4 kbps, unmodulated interferer; see the Typical Performance Characteristics section for blocking at other offsets and IF bandwidths, RF frequency = 868 MHz

RF frequency = 868 MHz, swept from 10 MHz to 100 MHz either side of the RF frequency

Measured as image attenuation at the IF filter output, carrier wave interferer at 400 kHz below the channel frequency, 100 kHz IF filter bandwidth

Uncalibrated/calibrated

Achievable pull-in range dependent on discriminator bandwidth and modulation

Minimum number of preamble bits to ensure the minimum packet error rate across the full input power range

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Parameter Min Typ Max Unit Test Conditions

LNA INPUT IMPEDANCE

Receive Mode

fRF = 915 MHz 75.9 − j32.3 Ω fRF = 868 MHz 78.0 − j32.4 Ω fRF = 433 MHz 95.5 − j23.9 Ω

Transmit Mode

fRF = 915 MHz 7.6 + j9.2 Ω fRF = 868 MHz 7.7 + j8.6 Ω fRF = 433 MHz 7.9 + j4.6 Ω

RX SPURIOUS EMISSIONS

Maximum <1 GHz −66 dBm

Maximum >1 GHz −62 dBm At antenna input, unfiltered conductive

1

Sensitivity for combined matching network case is typically 1 dB less than separate matching networks.

2

Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

2

At antenna input, unfiltered conductive

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TIMING AND DIGITAL SPECIFICATIONS

Table 4.

Parameter Min Typ Max Unit Test Conditions

RX AND TX TIMING PARAMETERS

PHY_ON to PHY_RX (on CMD_PHY_RX) 300 s Includes VCO calibration and synthesizer settling PHY_ON to PHY_TX (on CMD_PHY_TX) 296 s

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

0.7 × VDD V

INH

0.2 × V

INL

V

DD

±1 µA

Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH V

− 0.4 V IOH = 500 µA

DD

Output Low Voltage, VOL 0.4 V IOL = 500 µA GPIO Rise/Fall 5 ns GPIO Load 10 pF Maximum Output Current 5 mA

ATB OUTPUTS Used for external PA and LNA control

ADCIN_ATB3 and ATB4

Output High Voltage, VOH 1.8 V Output Low Voltage, VOL 0.1 V Maximum Output Current 0.5 mA

XOSC32KP_GP5_ATB1 and

XOSC32KN_ATB2

Output High Voltage, VOH V

V

DD

Output Low Voltage, VOL 0.1 V Maximum Output Current 5 mA

See the State Transition and Command Timing section for more details

Includes VCO calibration and synthesizer settling, does not include PA ramp-up

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AUXILARY BLOCK SPECIFICATIONS

Table 5.

Parameter Min Typ Max Unit Test Conditions

32 kHz RC OSCILLATOR

Frequency 32.768 kHz After calibration

Frequency Accuracy 1.5 % After calibration at 25°C

Frequency Drift

Temperature Coefficient 0.14 %/°C Voltage Coefficient 4 %/V

Calibration Time 1 ms

32 kHz XTAL OSCILLATOR

Frequency 32.768 kHz

Start-Up Time 630 ms 32.768 kHz crystal with 7 pF load capacitance

WAKE UP CONTROLLER (WUC)

Hardware Timer

Wake-Up Period 61 × 10−6 1.31 × 105 sec

Firmware Timer

Wake-Up Period 1 216 Hardware

periods

ADC

Resolution 8 Bits

DNL ±1 LSB From 1.8 V to 3.6 V, TA = 25°C

INL ±1 LSB From 1.8 V to 3.6 V, TA = 25°C

Conversion Time 1

Input Capacitance 12.4 pF

BATTERY MONITOR

Absolute Accuracy ±45 mV

Alarm Voltage Set Point 1.7 2.7 V

Alarm Voltage Step Size 62 mV 5-bit resolution

Start-Up Time 100 µs

Current Consumption 30 µA When enabled

TEMPERATURE SENSOR

Range −40 +85 °C

Resolution 0.3 °C With averaging

Accuracy of Temperature Readback

Single Readback ±14 °C Average of 10 Readbacks ±4.4 °C Average of 50 Readbacks ±2 °C

µs

Firmware counter counts of the number of hardware wake-ups, resolution of 16 bits

With a temperature correction value (determined at a known temperature) applied, from −40°C to +85°C

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GENERAL SPECIFICATIONS

Table 6.

Parameter Min Typ Max Unit Test Conditions

TEMPERATURE RANGE, TA −40 +85 °C VOLTAGE SUPPLY

VDD 1.8 3.6 V Applied to VDDBAT1 and VDDBAT2

TRANSMIT CURRENT CONSUMPTION

Single-Ended PA, 433 MHz

−10 dBm 8.7 mA 0 dBm 12.2 mA 10 dBm 23.3 mA

13.5 dBm 32.1 mA

Differential PA, 433 MHz

−10 dBm 7.9 mA 0 dBm 11 mA 5 dBm 15 mA 10 dBm 22.6 mA

Single-Ended PA, 868 MHz/915 MHz

−10 dBm 10.3 mA 0 dBm 13.3 mA 10 dBm 24.1 mA

13.5 dBm 32.1 mA

Differential PA, 868 MHz/915 MHz

−10 dBm 9.3 mA 0 dBm 12 mA 5 dBm 16.7 mA 10 dBm 28 mA

POWER MODES

PHY_SLEEP (Deep Sleep Mode 2) 0.18 µA

PHY_SLEEP (Deep Sleep Mode 1) 0.33 µA

PHY_SLEEP (RCO Wake Mode)

PHY_SLEEP (XTO Wake Mode) 1.28 µA

PHY_OFF 1 mA

PHY_ON 1 mA

PHY_RX 12.8 mA Device in PHY_RX state

SMART WAKE MODE Average current consumption

21.78 µA

11.75 µA

0.75 µA

In the PHY_TX state, single-ended PA matched to 50 Ω, differential PA matched to 100 Ω, separate single-ended PA and LNA match, combined differential PA and LNA match

Sleep mode, wake-up configuration values (BBRAM) not retained

Sleep mode, wake-up configuration values (BBRAM) retained

WUC active, RC oscillator running, wake-up configuration values retained (BBRAM)

WUC active, 32 kHz crystal running, wake-up configuration values retained (BBRAM)

Device in PHY_OFF state, 26 MHz oscillator running, digital and synthesizer regulators active, all register values retained

Device in PHY_ON state, 26 MHz oscillator running, digital, synthesizer, VCO, and RF regulators active, baseband filter calibration performed, all register values retained

Autonomous reception every 1 sec, with receive dwell time of 1.25 ms, using RC oscillator, data rate = 38.4 kbps

Autonomous reception every 1 sec, with receive dwell time of 0.5 ms, using RC oscillator, data rate = 300 kbps

Rev. 0 | Page 15 of 108

ADF7023

http://www.BDTIC.com/ADI

TIMING SPECIFICATIONS

VDD = VDDBAT1 = VDDBAT2 = 3 V ± 10%, V

Table 7. SPI Interface Timing

Parameter Limit Unit Test Conditions/Comments

t1 15 ns max t2 85 ns min t3 85 ns min SCLK high time t4 85 ns min SCLK low time t5 170 ns min SCLK period t6 10 ns max SCLK falling edge to MISO delay t7 5 ns min MOSI to SCLK rising edge setup time t8 5 ns min MOSI to SCLK rising edge hold time t9 85 ns min t11 270 ns min t12 310 µs typ t13 20 ns max SCLK rise time t14 20 ns max SCLK fall time

Timing Diagrams

= GND = 0 V, TA = T

GND

falling edge to MISO setup time (TRX active)

CS

low to SCLK setup time

CS

SCLK falling edge to CS

high time

CS

low to MISO high wake-up time, 26 MHz crystal with 7 pF load capacitance, T

CS

to T

MIN

hold time

MAX

, unless otherwise noted.

= 25°C

A

SCLK

MISO

MO

CS

t

11

t

3

2

t

1

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X BIT 7

t

7

SI

7 765432107

5

t

6

t

8

t4t

t

13

t

14

t

9

08291-002

Figure 2. SPI Interface timing

CS

t

9

SCLK

MISO

SPI STATE

67

t

12

t

1

SLEEP WAKE UP SPI READY

t

6

Figure 3. PHY_SLEEP to SPI Ready State Timing (SPI Ready T12 After Falling Edge of

012345

X

08291-003

CS

)

Rev. 0 | Page 16 of 108

ADF7023

http://www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 8.

Parameter Rating

VDDBAT1, VDDBAT2 to GND −0.3 V to +3.96 V Operating Temperature Range

Industrial −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance 26°C/W Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

ESD CAUTION

The exposed paddle of the LFCSP package should be connected to ground.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance, RF integrated circuit with an ESD rating of <2 kV; it is ESD sensitive. Proper precautions should be taken for handling and assembly.

Rev. 0 | Page 17 of 108

ADF7023

http://www.BDTIC.com/ADI

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADCVREF

ATB4

ADCIN_ATB3

VDDBAT1

XOSC32KN_ATB2

XOSC32KP_GP5_ATB1

CREGDIG2

32313029282726

CREGRF1

CREGRF2

RFIO_1P RFIO_1N

VDDBAT2

NOTES

1. NC = NO CONNEC T.

2. CONNECT EXPOSED PAD TO GND.

RBIAS

RFO2

NC

1 2 3 4 5 6 7 8

ADF7023

TOP VIEW

(Not to S cale)

EPAD

9

10111213141516

CREGVCO

CWAKEUP

VCOGUARD

CREGSYNTH

Figure 4. Pin Configuration

GP4 25

24 CS 23

MOSI SCLK

22

MISO

21 20

IRQ_GP3

19

GP2

18

GP1

17 GP0

DGUARD

XOSC26P

XOSC26N

CREGDIG1

08291-004

Table 9. Pin Function Descriptions

Pin No. Mnemonic Function

1 CREGRF1

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 2 RBIAS External Bias Resistor. A 36 kΩ resistor with 2% tolerance should be used. 3 CREGRF2

Regulator Voltage for RF. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 4 RFIO_1P LNA Positive Input in Receive Mode. PA positive output in transmit mode with differential PA. 5 RFIO_1N LNA Negative Input in Receive Mode. PA negative output in transmit mode with differential PA. 6 RFO2 Single-Ended PA Output. 7 VDDBAT2

Power Supply Pin Two. Decoupling capacitors to the ground plane should be placed as close as

possible to this pin. 8 NC No Connect. 9 CREGVCO

Regulator Voltage for the VCO. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection. 10 VCOGUARD Guard/Screen for VCO. This pin should be connected to Pin 9. 11 CREGSYNTH

Regulator Voltage for the Synthesizer. A 220 nF capacitor should be placed between this pin and

ground for regulator stability and noise rejection. 12 CWAKEUP

External Capacitor for Wake-Up Control. A 150 nF capacitor should be placed between this pin and

ground. 13 XOSC26P The 26 MHz reference crystal should be connected between this pin and XOSC26N. 14 XOSC26N The 26 MHz reference crystal should be connected between this pin and XOSC26P. 15 DGUARD

Internal Guard/Screen for the Digital Circuitry. A 220 nF capacitor should be placed between this pin

and ground. 16 CREGDIG1

Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this

pin and ground for regulator stability and noise rejection. 17 GP0 Digital GPIO Pin 0. 18 GP1 Digital GPIO Pin 1. 19 GP2 Digital GPIO Pin 2. 20 IRQ_GP3

Interrupt Request, Digital GPIO Test Pin 3. An RC filter should be placed between this pin and the

host processor. Recommended values are R = 1.1 kΩ and C = 1.5 nF. 21 MISO Serial Port Master In/Slave Out.

Rev. 0 | Page 18 of 108

ADF7023

http://www.BDTIC.com/ADI

Pin No. Mnemonic Function

22 SCLK Serial Port Clock. 23 MOSI Serial Port Master Out/Slave In. 24

25 GP4 Digital GPIO Test Pin 4. 26 CREGDIG2

27 XOSC32KP_GP5_ATB1

28 XOSC32KN_ATB2

29 VDDBAT1

30 ADCIN_ATB3

31 ATB4 Analog Test Pin 4. Can be configured as an external LNA enable signal. 32 ADCVREF

EPAD GND Exposed Package Paddle. Connect to GND.

CS

Chip Select (Active Low). A pull-up resistor of 100 kΩ to VDD is recommended to prevent the host processor from inadvertently waking the ADF7023 from sleep.

Regulator Voltage for Digital Section of the Chip. A 220 nF capacitor should be placed between this pin and ground for regulator stability and noise rejection.

Digital GPIO Test Pin 5. A 32 kHz watch crystal can be connected between this pin and XOSC32KN_ATB2. Analog Test Pin 1.

A 32 kHz watch crystal can be connected between this pin and XOSC32KP_GP5_ATB1. Analog Test Pin 2.

Digital Power Supply Pin One. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.

Analog-to-Digital Converter Input. Can be configured as an external PA enable signal. Analog Test Pin 3.

ADC Reference Output. A 220 nF capacitor should be placed between this pin and ground for adequate noise rejection.

Rev. 0 | Page 19 of 108

ADF7023

http://www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

14 12 10

8 6 4 2

0 –2 –4 –6 –8

–10

OUTPUT POWER (dBm)

–12 –14 –16 –18 –20

0 4 8 1216202428323640444852566064

PA SETTING

Figure 5. Single-Ended PA at 433 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

36 34

32 30 28 26 24 22 20 18 16

SUPPLY CURRENT (mA)

14 12 10

8

6

–18

–16

–14

–8–6–4

–12

–10

OUTPUT POWER (dBm)

–40°C, 3.6V –40°C, 1.8V +85°C, 3.6V +85°C, 1.8V

02468

–2

Figure 6. Single-Ended PA at 433 MHz: Supply Current vs. Output Power,

Temperature, and V

15 10

5 0

–5

–10 –15 –20

OUTPUT POWER (dBm)

–25 –30 –35 –40

0 10203040

PA SETTING

Figure 7. Single-Ended PA at 868 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V –40°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V

DD

3.6V, +25°C

3.0V, +25°C

2.4V, +25°C

1.8V, +25°C

3.6V, +85°C

3.0V, +85°C

2.4V, +85°C

1.8V, +85°C

3.6V, –40°C

3.0V, –40°C

2.4V, –40°C

1.8V, –40°C

50 60 70

DD

101214

08291-201

08291-202

08291-043

35

3.0V, 25°C

3.6V, 25°C

1.8V, 25°C

30

25

20

15

10

SUPPLY CURRENT (mA)

5

0

–30 –25 –20 –15 –10 –5 0 5 10 15 20

PA OUTPUT POWER (d Bm)

08291-044

Figure 8. Single-Ended PA at 868 MHz: Supply Current vs. Output Power,

Temperature, and V

14 12 10

8 6 4 2

0 –2 –4 –6 –8

–10

OUTPUT POWER (dBm)

–12 –14 –16 –18 –20

0 4 8 1216202428323640444852566064

PA SETTING

DD

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V –40°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V

08291-205

Figure 9. Single-Ended PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

36 34 32 30 28 26 24 22 20 18 16

SUPPLY CURRENT (mA)

14 12 10

8

6

–18

–16

–14

–8–6–4

–12

–10

OUTPUT POWER (dBm)

–40°C, 3.6V –40°C, 1.8V +85°C, 3.6V +85°C, 1.8V

02468

–2

DD

101214

08291-206

Figure 10. Single-Ended PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V

DD

Rev. 0 | Page 20 of 108

ADF7023

http://www.BDTIC.com/ADI

14 12 10

8 6 4 2

0 –2 –4 –6 –8

–10

OUTPUT POWER (dBm)

–12 –14 –16 –18 –20

0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64

PA SETTI NG

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V

–40°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V

Figure 11. Differential PA at 433 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

28 26 24 22 20 18 16 14 12

SUPPLY CURRENT (mA)

10

8 6

–18

–16

–40°C, 3.6V –40°C, 1.8V +85°C, 3. 6V +85°C, 1. 8V

–14

–12

–10

OUTPUT POWER (dBm)

–8–6–4

–2

DD

0

2

4

6

8

10

12

08291-208

Figure 12. Differential PA at 433 MHz: Supply Current vs. Output Power,

Temperature, and V

DD

08291-207

32 30 28 26 24 22 20 18 16 14

SUPPLY CURRENT (mA)

12 10

8 6

–18

–16

–14

–12

–40°C, 3.6V –40°C, 1.8V +85°C, 3.6V +85°C, 1.8V

–8–6–4

–10

OUTPUT PO WER (dBm)

–2

0

2

468

10

12

08291-210

Figure 14. Differential PA at 915 MHz: Supply Current vs. Output Power,

Temperature, and V

10

0

–10

–20

PA RAMP = 1

–30

–40

PA OUTPUT POWER (dBm)

–50

–60

0 50 100 150 200 250 300 350 400 450 500

PA RAMP = 2 PA RAMP = 3 PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

TIME (µs)

DD

08291-211

Figure 15. PA Ramp-Up at Data Rate =38.4 kbps for Each PA_RAMP Setting,

Differential PA

12 10

8 6 4 2

0 –2 –4 –6 –8

–10

OUTPUT PO WER (dBm)

–12 –14 –16 –18 –20

0 4 8 1216202428323640444852566064

PA LEVEL SETTING

–40°C, 3.6V –40°C, 3.0V –40°C, 2.4V –40°C, 1.8V +85°C, 3.6V +85°C, 3.0V +85°C, 2.4V +85°C, 1.8V +25°C, 3.6V +25°C, 3.0V +25°C, 2.4V +25°C, 1.8V

Figure 13. Differential PA at 915 MHz: Output Power vs. PA_LEVEL_MCR

Setting, Temperature, and V

DD

08291-209

Figure 16. PA Ramp-Down at Data Rate =38.4 kbps for Each PA_RAMP

Rev. 0 | Page 21 of 108

10

0

–10

–20

–30

–40

PA OUTPUT POWER (dBm)

–50

–60

PA RAMP = 1 PA RAMP = 2 PA RAMP = 3 PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

0 50 100 150 200 250 300 350 400 450 500

TIME (µs)

Setting, Differential PA

08291-212

ADF7023

http://www.BDTIC.com/ADI

10

0

–10

–20

–30

–40

PA OUTPUT POWER (dBm)

–50

–60

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

Figure 17. PA Ramp-Up at Data Rate =300 kbps for Each PA_RAMP Setting,

10

0

–10

–20

–30

–40

PA OUTPUT POWER (dBm)

–50

–60

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75

Figure 18. PA Ramp-Down at Data Rate =300 kbps for Each PA_RAMP

10

0

–10

–20

–30

POWER (d Bm)

–40

PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

TIME (µs)

Differential PA

PA RAMP = 4 PA RAMP = 5 PA RAMP = 6 PA RAMP = 7

TIME (µs)

Setting, Differential PA

3.6V, –40°C

1.8V, –40°C

3.6V, +85°C

1.8V, +85°C

10

0

–10

–20

–30

POWER (d Bm)

–40

–50

–60

08291-213

–250 –200 –150 –100 –50 0 50 100 150 200 250

FREQUENCY OFFSET (kHz)

3.6V, –40°C

1.8V, –40°C

3.6V, +85°C

1.8V, +85°C

08291-041

Figure 20. Transmit Spectrum at 868 MHz, GFSK, Data Rate = 38.4 kbps,

Frequency Deviation = 20 kHz

15 10

5

3.6V, +25°C

0

1.8V, +25°C

3.6V, +85°C

–5

1.8V, +85°C

–1000

3.6V, –40°C

1.8V, –40°C

–900

–800

–700

–600

–500

–400

–300

–200

FREQUENCY OF FSET (kHz)

–100

0

100

200

300

400

500

600

700

800

900

1000

08291-217

–10 –15 –20

POWER (dBm)

–25 –30 –35 –40 –45

08291-214

Figure 21. Transmit Spectrum at 928 MHz, GFSK, Data Rate = 300 kbps,

Frequency Deviation = 75 kHz

30

20

10

0

–10

–50

–60

–250 –200 –150 –100 –50 0 50 100 150 200 250

FREQUENCY OFFSET (kHz)

Figure 19. Transmit Spectrum at 868 MHz, FSK, Data Rate = 38.4 kbps,

Frequency Deviation = 20 kHz

08291-040

Figure 22. Transmit Eye at 868 MHz, GFSK, Data Rate = 38.4 kbps, Frequency

Rev. 0 | Page 22 of 108

–20

TRANSMIT F REQUENCY DEVIAT ION (kHz)

–30

0 0.25 0.75 1.25 2.00

0.50 1.00 1.50 1.75 TRANSMIT SY MBOL (Bits)

Deviation = 21 kHz

08291-218

ADF7023

http://www.BDTIC.com/ADI

100

75

50

25

0

–25

–50

–75

TRANSMIT F REQUENCY DEVIAT ION (kHz)

–100

0 0.25 0.75 1.25 2.00

0.50 1.00 1.50 1.75 TRANSMIT SY MBOL (Bits)

08291-219

Figure 23. Transmit Eye at 868 MHz, GFSK, Data Rate = 300 kbps, Frequency

Deviation = 75 kHz

20

10

0

–10

–20

–30

OUTPUT POWER (dBm)

–40

–50

–60

–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5

FREQUENCY OF FSET (MHz)

08291-221

Figure 24. OOK Transmit Spectrum, Max Hold for 100 Sweeps, Single-Ended

PA, 868.95 MHz, Data Rate = 16.4 kbps (32.8 kcps, Manchester Encoded),

PA_RAMP = 1

34

RF FREQUENCY = 868MHz

33

RF FREQUENCY = 928MHz

32 31 30 29 28 27 26 25

130kHz SYNTH

MODUL ATION ERROR RATIO (dB)

24

BANDWIDTH

174kHz SYNTH

BANDWIDTH

223kHz SYNTH

BANDWIDTH

304kHz SYNTH

BANDWIDTH

381kHz SYNTH

BANDWIDTH

23 22

10.0 49.5 49.6 129.5 129.6 179.1 179.2 239.9 240.0 300.0 DATA RATE (kbps)

08291-220

Figure 25. Modulation Error Ratio (MER) vs. Data Rate, Synthesizer Loop

Bandwidth, and RF Frequency at Modulation Index = 1

32

31

30

29

+25°C, 1.8V +85°C, 1.8V

–40°C, 1.8V +25°C, 3.6V +85°C, 3.6V

–40°C, 3.6V

28

27

26

25

MODULATION ERROR RATIO (dB)

24

23

860 870 880 890 900 910 920 930 940

RF TRANSMIT FREQUENCY (M Hz )

08291-222

Figure 26. Modulation Error Ratio (MER) vs. RF Frequency, Temperature, and

at Modulation Index = 1 and Data Rate = 10 kbps

V

DD

30

RF FREQUENCY = 868MHz

29

RF FREQUENCY = 928MHz

28 27 26 25 24 23 22 21 20 19

130kHz

MODULATION ERROR RATIO (dB)

SYNTH

18

BANDWIDTH

17 16

10.0 49.5 49.6 129.5 129.6 179.1 179.2 239.9 240.0 300.0

174kHz SYNTH

BANDWIDTH

223kHz SYNTH

BANDWIDTH

304kHz SYNTH

BANDWIDTH

DATA RATE (kbps)

381kHz SYNTH

BANDWIDTH

08291-223

Figure 27. Modulation Error Ratio (MER) vs. Data Rate, Synthesizer Loop

Bandwidth, and RF Frequency at Modulation Index = 0.5

32

31

30

29

+25°C, 1. 8V +85°C, 1. 8V –40°C, 1.8V +25°C, 3. 6V +85°C, 3. 6V –40°C, 3.6V

28

27

26

25

MODULATION ERROR RATIO (dB)

24

23

860 870 880 890 900 910 920 930 940

RF TRANSMIT FREQUENCY (M Hz )

08291-224

Figure 28. Modulation Error Ratio (MER) vs. RF Frequency, Temperature, and

V

at Modulation Index = 0.5 and Data Rate = 10 kbps

DD

Rev. 0 | Page 23 of 108

ADF7023

http://www.BDTIC.com/ADI

5

0

–5

–10

–15

–20

–25

–30

MIXER OUTP UT POWER (dBm)

–35

–40

–40 –35 –30 –25 –20 –15

Figure 29. LNA/Mixer 1 dB Compression Point, VDD = 3.0 V, Temperature =

25°C, RF Frequency = 915 MHz, LNA Gain = Low, Mixer Gain = Low

20

15

10

5

0

MIXER OUTP UT POWER (dBm)

–5

–10

–40 –35 –30 –25 –20 –15

Figure 30. LNA/Mixer 1 dB Compression Point, V

25°C, RF Frequency = 915 MHz, LNA Gain = High, Mixer Gain = High

10

–10 –20 –30 –40 –50 –60 –70 –80 –90

–100

MIXER OUTPUT POWER (dBm)

–110 –120 –130

Figure 31. LNA/Mixer IIP3, VDD = 3.0 V, Temperature = 25°C, RF Frequency =

915 MHz, LNA Gain = Low, Mixer Gain = Low, Source 1 Frequency =

OUTPUT PO WER (FUNDAMENTAL) OUTPUT POWER IDEAL P1dB

P1dB = –21dBm

LNA INPUT POWER (dBm)

OUTPUT PO WER (FUNDAMENTAL) OUTPUT POWER IDEAL P1dB

P1dB = –21.9dBm

LNA INPUT POWER (dBm)

= 3.0 V, Temperature =

DD

0

IIP3 = –11.5dBm

FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SLOPE FIT IM3 3/1 SLOPE FIT

–50 –45 –40 –35 –30 –25 –20 –15 –10

LNA INPUT POWER (dBm)

(915 + 0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

20 10

0 –10 –20 –30 –40 –50 –60

MIXER OUTPUT POWER (dBm)

–70 –80 –90

–50 –45 –40 –35 –30 –25 –20 –15 –10

08291-225

Figure 32. LNA/Mixer IIP3, V

FUNDAMENTAL TONE IM3 TONE FUNDAMENTAL 1/1 SL OPE FIT IM3 3/1 SL OPE FIT

LNA INPUT POWER (dBm)

= 3.0 V, Temperature = 25°C, RF Frequency =

DD

IIP3 = –12.2dBm

08291-228

915 MHz, LNA Gain = High, Mixer Gain = High, Source 1 Frequency = (915 +

0.4) MHz, Source 2 Frequency = (915+ 0.7) MHz

10

0

–10

–20

–30

–40

–50

ATTENUATION (dB)

–60

–70

–80

–90

08291-226

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

FREQUENCY OFFSET ( MHz)

100kHz 150kHz 200kHz 300kHz

08291-229

Figure 33. IF Filter Profile vs. IF Bandwidth, VDD = 3.0 V, Temperature = 25°C

10

0

–10

–20

–30

–40

–50

ATTENUATION (dB)

–60

–70

–80

–90

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

08291-227

Figure 34. IF Filter Profile vs. V

FREQUENCY OFFSET (MHz)

and Temperature, 100 kHz IF Filter

DD

1.8V, –40°C

2.4V, –40°C

3.0V, –40°C

3.6V, –40°C

1.8V, +25°C

2.4V, +25°C

3.0V, +25°C

3.6V, +25°C

1.8V, +85°C

2.4V, +85°C

3.0V, +85°C

3.6V, +85°C

08291-230

Bandwidth

Rev. 0 | Page 24 of 108

ADF7023

http://www.BDTIC.com/ADI

80

70

60

50

40

30

BLOCKING (d B)

20

10

–10

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–14

–12

–10

–8–6–4

–20

–18

–16

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

02468

–2

1012141618

20

Figure 35. Receiver Wideband Blocking at 433 MHz, Data Rate = 38.4 kbps

80

70

60

50

40

30

20

BLOCKING ( dB)

10

–10

–20

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–20

–18

–16

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

–8–6–4

–14

–12

–10

02468

–2

1012141618

20

Figure 36. Receiver Wideband Blocking at 433 MHz, Data Rate = 100 kbps

70

60

50

40

30

20

BLOCKING ( d B)

10

–10

–20

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–14

–12

–10

–8–6–4

–20

–18

–16

INTERFERE R OFFSET FROM RECEIVER LO F RE QUENCY (MHz)

02468

–2

1012141618

20

Figure 37. Receiver Wideband Blocking at 433 MHz, Data Rate = 300 kbps

80

70

60

50

40

30

BLOCKING (dB)

20

10

0

–10

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60

08291-231

BLOCKER FREQUENCY OF FSET (MHz)

08291-234

Figure 38. Receiver Wideband Blocking to ±60 MHz, at 868 MHz, Data Rate =

38.4 kbps, Carrier Wave Interferer

80

70

60

50

40

30

BLOCKING ( dB)

20

10

–10

08291-232

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–9–8–7–6–5–4–3–2–1

–11

–10

012345678

BLOCKER FREQ UENCY OFFS ET ( MHz )

9

11

10

08291-235

Figure 39. Receiver Wideband Blocking at 868 MHz, Data Rate = 100 kbps

70

60

50

40

30

20

BLOCKING (dB)

10

–10

–20

08291-233

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–9–8–7–6–5–4–3–2–1

–11

–10

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

012345678

9

11

10

08291-236

Figure 40. Receiver Wideband Blocking at 868 MHz, Data Rate = 300 kbps

Rev. 0 | Page 25 of 108

ADF7023

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80

70

60

50

40

30

BLOCKING (dB)

20

10

–10

Figure 41. Receiver Wideband Blocking at 915 MHz, Data Rate = 38.4 kbps

80

70

60

50

40

30

20

BLOCKING (dB)

10

–10

–20

Figure 42. Receiver Wideband Blocking at 915 MHz, Data Rate = 100 kbps

70

60

50

40

30

20

BLOCKING (d B)

10

–10

–20

Figure 43. Receiver Wideband Blocking at 915 MHz, Data Rate = 300 kbps

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–9–8–7–6–5–4–3–2–1

–11

–10

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

MODULATED INTERFERER

CARRIER WAVE INTERFERER

0

–9–8–7–6–5–4–3–2–1

–10

0

–11

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

BLOCKER FREQ UENCY OFFS ET ( MHz )

MODULATED INTERFERER

CARRIER WAVE INTERFERER

–9–8–7–6–5–4–3–2–1

–10

012345678

9

11

10

9

10

9

11

10

70

60

50

40

30

20

BLOCKING (dB)

08291-237

+25°C 1.8V +25°C 3.0V

10

+25°C 3.6V +85°C 1.8V

0

+85°C 3.0V +85°C 3.6V –40°C 1.8V

–10

–40°C 3.0V –40°C 3.6V

–20

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60

INTERFERE R FREQUENCY O FFSET ( MHz )

Figure 44. Receiver Wideband Blocking vs. V

and Temperature,

DD

08291-240

915 MHz, Data Rate = 300 kbps

–10

–20

–30

–40

–50

–60

–70

–80

INTERFERER P OWER (dBm)

–90

–100

–110

–60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60

08291-238

INTERFERE R OFFSET FROM RECEIVER LO FREQUENCY (MHz)

GFSK, 100kHz IF BANDWIDTH GFSK, 200kHz IF BANDWIDTH 2FSK, 100kHz IF BANDWIDTH

08291-241

Figure 45. Receiver Wideband Blocking at 868 MHz, Data Rate = 38.4 kbps,

Measured as per ETSI EN 300 220

65 60 55 50 45 40 35 30 25 20 15

BLOCKING ( d B)

10

5

0

–5

–10

CW INTERFERER

–15

MODULATED I NTERFERER

–20

–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0

08291-239

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

08291-242

Figure 46. Receiver Close-In Blocking at 915 MHz, Data Rate = 50 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated

Rev. 0 | Page 26 of 108

ADF7023

http://www.BDTIC.com/ADI

60 55 50 45 40 35 30 25 20 15 10

BLOCKING (dB)

5 0

–5

–10

CW INTERFERER

–15

MODULATED I NTERFERER

–20

–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 47. Receiver Close-In Blocking at 915 MHz, Data Rate = 100 kbps,

IF Filter Bandwidth = 100 kHz, Image Calibrated

60 55 50 45 40 35 30 25 20 15 10

BLOCKING ( d B)

5 0

–5

–10

CW INTERFERER

–15

MODULATED INTERFERER

–20

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

–0.8 –0.4

Figure 48. Receiver Close-In Blocking at 915 MHz, Data Rate = 150 kbps,

IF Filter Bandwidth = 150 kHz, Image Calibrated

60 55 50 45 40 35 30 25 20 15 10

BLOCKING ( d B)

5 0

–5

–10

CW INTERFE RER

–15

MODULATED I NTERFERER

–20

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

–0.8 –0.4

Figure 49. Receiver Close-In Blocking at 915 MHz, Data Rate = 200 kbps,

IF Filter Bandwidth = 200 kHz, Image Calibrated

08291-243

08291-244

08291-245

60 55 50 45 40 35 30 25 20 15 10

BLOCKING ( d B)

5 0

–5

–10

CW INTERF E RE R

–15

MODULATED INTERFERER

–20

–2.0 –1.6 –1.2 0 0.4 0.8 1.2 1.6 2.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

–0.8 –0.4

Figure 50. Receiver Close-In Blocking at 915 MHz, Data Rate = 300 kbps,

IF Filter Bandwidth = 300 kHz, Image Calibrated

0

CALIBRATED UNCALIBRATED

–10

–20

–30

–40

–50

–60

ATTENUATION (dB)

–70

–80

–90

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

INTERFERER OFFSET FROM RECEIVER LO FREQUENCY (MHz)

Figure 51. Image Attenuation with Calibrated and Uncalibrated Images, 915 MHz, IF Filter Bandwidth = 100 kHz, V

0

CALIBRATED UNCALIBRATED

–10

–20

–30

–40

–50

–60

ATTENUATION (dB)

–70

–80

–90

–100

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

INTERFERE R OFFSET FROM RECEIVER LO F RE QUENCY (MHz)

= 3.0 V, Temperature = 25°C

DD

Figure 52. Image Attenuation with Calibrated and Uncalibrated Images,

433 MHz, IF Filter Bandwidth =100 kHz, V

= 3.0 V, Temperature = 25°C

DD

08291-246

08291-247

08291-248

Rev. 0 | Page 27 of 108

ADF7023

http://www.BDTIC.com/ADI

0

100kHz BW 150kHz BW

–10

200kHz BW 300kHz BW

–20

–30

–40

–50

–60

ATTENUATION (dB)

–70

–80

–90

–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0

OFFSET FROM LO FREQUENCY (MHz)

Figure 53. IF Filter Profile with Calibrated Image vs. IF Filter Bandwidth,

921 MHz, V

–98

–99

–100

–101

= 3.0 V, Temperature = 25°C

DD

915MHz, –40°C 915MHz, +25° C 915MHz, +85° C 868MHz, –40°C 868MHz, +25° C 868MHz, +85° C

100

90

80

70

60

50

40

30

PACKET ERROR RATE (%)

20

10

0

–120 –110 –100 –90 –80 –70 –60 –50 0–10–40 –30 –20

08291-249

APPLIED RECEIVER POWE R ( dBm)

1kbps 10kbps

38.4kbps 50kbps 100kbps 200kbps 300kbps

08291-252

Figure 56. Packet Error Rate vs. RF Input Power and Data Rate, FSK/GFSK,

928 MHz, Preamble Length = 64 Bits, V

–96.0

–96.5

–97.0

–97.5

–98.0

+25°C

–40°C

= 3.0 V, Temperature = 25°C

DD

+85°C

–102

SENSITIVITY (dBm)

–103

–104

1.8 3.0 3.6 VDD (V)

08291-250

Figure 54. Receiver Sensitivity (Bit Error Rate at 1E − 3) vs. VDD, Temperature,

and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency Deviation =

75 kHz, IF Bandwidth = 300 kHz

–95

BIT ERROR RATE (1E-3) PACKET ERROR RATE (1%)

–100

–105

–110

SENSITIVITY (dBm)

–115

–120

0 50 100 150 200 250 300

DATA RATE (kbps)

08291-251

Figure 55. Bit Error Rate Sensitivity (at BER = 1E − 3) and Packet Error Rate

Sensitivity (at PER = 1%) vs. Data Rate, GFSK, V

= 3.0 V,

DD

Temperature = 25°C

–98.5

SENSITIVITY (dBm)

–99.0

–99.5

–100.0

1.8 3.6

VDD (V)

08291-254

Figure 57. Receiver Sensitivity (Packet Error Rate at 1%) vs. VDD,

Temperature, and RF Frequency, Data Rate = 300 kbps, GFSK, Frequency

Deviation = 75 kHz, IF Bandwidth = 300 kHz

10

9

8

7

6

5

PER (%)

4

3

2

1

0

–104 –103 –102 –101 –100 –99 –98 –97 –96 –95 –94

RECEIVER INPUT POWER (dBm)

RS CODED DATA, SYNC_ERROR_TOL = 0, PREAMBLE_MATCH = 0xA

RS CODED DATA, SYNC_ERROR_TOL = 1, PREAMBLE_MATCH = 0x0A

UNCODED DATA, SYNC_ERROR_TOL = 0

3.4dB

2dB

08291-253

Figure 58. Receiver PER Using Reed Solomon (RS) Coding; RF Frequency =

915 MHz, GFSK, Data Rate = 300 kbps, Frequency Deviation =75 kHz, Packet

Length = 28 Bytes (Uncoded); Reed Solomon Configuration: n = 38,

k = 28, t =5

Rev. 0 | Page 28 of 108

ADF7023

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100

90

80

70

60

50

40

30

PACKET ERROR RATE ( %)

20

10

0 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10

APPLIED POWER (dBm)

08291-255

Figu re 59. OOK Packet Error Rate vs. RF Input Power, Data Rate = 19.2 kbps (Chip

Rate = 38.4 kcps, Manchester Encoded), IF Bandwidth = 100 kHz, V

= 3.6 V,

DD

Temperature = 25°C, RF Frequency = 902 MHz, Preamble Length = 100 Bits

100

90

80

70

60

50

40

30

PACKET ERROR RATE ( %)

20

10

0

–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10

APPLIED POWER (dB m )

08291-256

Figu re 60. OOK Packet Error Rate vs. RF Input Power, Data Rate = 2.4 kbps (Chip

Rate = 4.8 kcps, Manchester Encoded), IF Bandwidth = 100 kHz, V

= 3.6 V,

DD

Temperature = 25°C, RF Frequency = 902 MHz, Preamble Length = 100 Bits

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

PACKET ERROR RATE ( %)

1.0

0.5

0

–106 –105 –104 –103 –102 –101

APPLIED POWER (dBm)

Figu re 61. OOK Packet Error Rate vs. RF Input Power, V

TA = –40°C, VDD = 1.8V TA = –40°C, VDD = 3.6V TA = +25°C, VDD = 1.8V TA = +25°C, VDD = 3.6V TA = +85°C, VDD = 1.8V TA = +85°C, VDD = 3.6V

, and Temperature, Data

DD

08291-257

Rate = 19.2 kbps (Chip Rate = 38.4 kcps, Manchester Encoded), IF Bandwidth =

100 kHz, V

= 3.6 V, Temperature = 25°C, RF Frequency =

DD

902 MHz, Preamble Length = 100 Bits

100

90

80

70

60

50

40

30

PACKET ERROR RATE ( %)

20

10

0

–110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 10

OOK MODUL ATION DEPTH = 60dB

OOK MODUL ATION DEPTH = 40dB

OOK MODUL ATION DEPTH = 30dB

OOK MODUL ATION DEPTH = 20dB

APPLIED POWER (dBm)

08291-258

Figure 62. OOK Packet Error Rate vs. RF Input Power and OOK Modulation

Depth, Data Rate = 19.2 kbps (Chip Rate = 38.4 kcps, Manchester Encoded),

IF Bandwidth = 100 kHz, V

= 3.6 V, Temperature = 25°C, RF Frequency =

DD

902 MHz, Preamble Length = 100 Bits

SENSITIVITY (dBm)

–10 –20 –30 –40 –50 –60 –70 –80

–90 –100 –110

0

–60

–70

–80

–140

–130

–90

–100

–110

–120

RF FREQUENCY E RROR (kHz)

–150

–50

–40

–30

100kbps 150kbps 200kbps 300kbps

–10

–20

0

908070605040302010

100

110

120

130

140

150

08291-259

Figure 63. AFC On: Receiver Sensitivity (at PER = 1%) vs. RF Frequency Error,

GFSK, 915 MHz, AFC Enabled (Ki = 7, Kp = 3), AFC Mode = Lock After

Preamble, IF Bandwidth = 100 kHz (at 100 kbps), 150 kHz (at 150 kbps),

200 kHz (at 200 kbps), and 300 kHz (at 300 kbps), Preamble Length = 64 Bits

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25 0

–0.25 –0.50 –0.75

DATA RATE ERROR (%)

–1.00 –1.25 –1.50 –1.75 –2.00

–40 –30 –20 –10 0 10 20 30–35 –25 –15 –5 5 15 25 35 40

>1% <1%

RF FREQUENCY E RROR (kHz)

08291-260

Figure 64. AFC Off: Packet Error Rate vs. RF Frequency Error and Data Rate

Error, AFC Off, Data Rate=300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

Rev. 0 | Page 29 of 108

ADF7023

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2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25 0

–0.25 –0.50 –0.75

DATA RATE ERROR (%)

–1.00 –1.25 –1.50 –1.75 –2.00

–140–120–100 –80 –60 –40 –20 0 20 40 60 80 100 120 140

>1% <1%

RF FREQUENCY E RROR (kHz)

08291-261

Figure 65. AFC On: Packet Error Rate vs. RF Frequency Error and Data Rate Error, AFC Off, Data Rate = 300 kbps, Frequency Deviation = 75 kHz, GFSK,

AGC_LOCK_MODE = Lock After Preamble

–20

–30

–40

–50

–60

–70

–80

RSSI (dBm)

–90

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR

INPUT POWER (dBm)

10

8

6

4

2

0

–2

–4

–6

–8

–10

RSSI ERROR (dB)

Figure 66. RSSI (via CMD_GET_RSSI) vs. RF Input Power, 868 MHz, GFSK, Data

Rate = 38.4 kbps, Frequency Deviation = 20 kHz, IF Bandwidth = 100 kHz,

100 RSSI Measurements at Each Input Power Level

–20

–30

–40

–50

–60

–70

–80

RSSI (dBm)

–90

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR

INPUT POWER (dBm)

10

8

6

4

2

0

–2

–4

–6

–8

–10

RSSI ERROR (dB)

Figure 67. RSSI (via Automatic End of Packet RSSI Measurement) vs. RF Input

Power, 868 MHz, GFSK, Data Rate = 300 kbps, Frequency Deviation = 75 kHz,

IF Bandwidth = 300 kHz, AGC_CLOCK_DIVIDE = 15, 100 RSSI Measurements

at Each Input Power Level

6

4

2

0

RSSI ERROR (dB)

–2

–4

–6

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

INPUT POWER (dBm)

300kbps 200kbps 150kbps 100kbps 50kbps

38.4kbps

9.6kbps

08291-264

Figure 68. Mean RSSI Error (via Automatic End of Packet RSSI Measurement)

vs. RF Input Power vs. Data Rate; RF Frequency = 868 MHz, GFSK, 100 RSSI

Measurements at Each Input Power Level

–20

–30

–40

–50

–60

–70

–80

RSSI (dBm)

–90

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

08291-262

IDEAL RSSI MEAN RSSI MEAN RSSI

(WITH POLYNOMIAL CORRECTI O N)

MEAN RSSI ERROR MEAN RSSI ERROR

(WITH POLYNOMIAL CORRECTI O N)

INPUT POWER (dBm)

10

8

6

4

2

0

–2

–4

–6

–8

–10

RSSI ERROR (dB)

08291-265

Figure 69. RSSI With and Without Cosine Polynomial Correction (via

Automatic End of Packet RSSI Measurement), 100 RSSI Measurements at

Each Input Power Level

–20

–30

–40

–50

–60

–70

–80

RSSI (dBm)

–90

–100

–110

–120

–120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20

08291-263

IDEAL RSSI MEAN RSSI MEAN RSSI ERROR MAX POSITIVE RSSI ERROR MAX NEGATIVE RSSI ERROR

INPUT POWER (dBm)

10

8

6

4

2

0

–2

–4

–6

–8

–10

RSSI ERROR (dB)

08291-266

Figure 70. OOK RSSI and OOK RSSI Error vs. RF Input Power. 915 MHz, Data

Rate = 19.2 kbps (38.4 kcps), 200 RSSI Measurements per Input Power Level

Rev. 0 | Page 30 of 108

ANALOG DEVICES ADF7023 Service Manual

FEATURES

APPLICATIONS

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

SPECIFICATIONS

RF AND SYNTHESIZER SPECIFICATIONS

TRANSMITTER SPECIFICATIONS

RECEIVER SPECIFICATIONS

TIMING AND DIGITAL SPECIFICATIONS

AUXILARY BLOCK SPECIFICATIONS

GENERAL SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS