Datasheet ADF7020 Datasheet (Analog Devices)

High Performance ISM Band

A

Preliminary Technical Data

FEATURES

Low power, low IF transceiver
Frequency bands:

433 MHz to 464 MHz
862 MHz to 928 MHz

Data rates supported:

0.3 kbps to 200 kbps, FSK

0.3 kbps to 64 kbps, ASK

2.3 V to 3.6 V power supply
Programmable output power:

−16 dBm to +13 dBm in 0.3 dBm steps

Receiver sensitivity:

−117.5 dBm at 1 kbps, FSK

−110.5 dBm at 9.6 kbps, FSK

−106.5 dBm at 9.6 kbps, ASK

Low power consumption:

19 mA in receive mode
22 mA in transmit mode (10 dBm output)

FSK/ASK Transceiver IC

ADF7020

On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
±1 ppm RF output frequency accuracy possible from

low cost 100 ppm crystal
Digital RSSI
Leakage current <1 µA in power-down mode
48-lead ultrasmall MLF package (chip scale)

APPLICATIONS

Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice

FUNCTIONAL BLOCK DIAGRAM

MUXOUTADCINRSET VREG(1:4)

RFINB

P

R

LNA

RFIN

OUT

BIAS LDO(1:4)

LNA

GAIN

DIVIDERS/

MUXING

ASK/OOK

MOD CONTROL

GAUSSIAN FILTER

IF FILTER

FSK MOD

CONTROL

VCO

VCOIN CPOUT

OFFSET

CORRECTION

RSSI

OFFSET

CORRECTION

GAUSSIAN

FILTER

CP

MODULATOR

N/N+1DIV P

PFD

TEMP

SENSOR

MUX

Σ-∆

DIV R

7-BIT ADC

Figure 1.

TEST MUX

DEMODULATOR

CONTROL

CONTROL

RING
OSC

OSC

FSK/ASK

AGC

AFC

CLK

DIV

SYNCHRONIZER

CONTROL

OUT

CLK

DATA

Tx/Rx

SERIAL

PORT

CE
RxCLK
Tx/Rx DATA
CLKOUT
INT/LOCK

SLE
SDATA IN
SDATA OUT
SCLK

01975-PrG-001

Rev. PrH

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Tel: [phone]
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ADF7020 Preliminary Technical Data

TABLE OF CONTENTS

General Description......................................................................... 3

Device Programming after Initial Power-Up ......................... 22

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Frequency Synthesizer ................................................................... 11

Reference Input Section............................................................. 11

Choosing Channels for Best System Performance................. 13

Transmitter ...................................................................................... 14

Modulation Schemes.................................................................. 14

Receiver Section.............................................................................. 16

RF Front End............................................................................... 16

RSSI/AGC Section...................................................................... 17

FSK Demodulators on the ADF7020....................................... 17

FSK Correlator/Demodulator................................................... 17

Linear FSK Demodulator.......................................................... 19

AFC Section ................................................................................ 19

Automatic Sync Word Recognition.......................................... 20

Applications Section....................................................................... 21

LNA/PA Matching...................................................................... 21

Transmit Protocol and Coding Considerations ..................... 22

Image Rejection Calibration .....................................................22

Serial Interface................................................................................ 24

Readback Format........................................................................ 24

Register 0—N Register............................................................... 25

Register 1—Oscillator/Filter Register...................................... 26

Register 2—Transmit Modulation Register (ASK/OOK

........................................................................................... 27

Mode)

Register 2—Transmit Modulation Register (FSK Mode) ..... 28

Register 2—Transmit Modulation Register (GFSK/GOOK

........................................................................................... 29

Mode)

Register 3—Receiver Clock Register ....................................... 30

Register 4—Demodulator Setup Register............................... 31

Register 5—Sync Byte Register................................................. 32

Register 6—Correlator/Demodulator Register ...................... 33

Register 7—Readback Setup Register...................................... 34

Register 8—Power-Down Test Register .................................. 35

Register 9—AGC Register......................................................... 36

Register 10—AGC 2 Register.................................................... 37

Register 11—AFC Register ....................................................... 37

Register 12—Test Register......................................................... 38

Register 13—Offset Removal and Signal Gain Register ....... 39

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

Revision PrH: Preliminary Version

Rev. PrH | Page 2 of 40

Preliminary Technical Data ADF7020

GENERAL DESCRIPTION

The ADF7020 is a low power, highly integrated FSK/GFSK/
ASK/OOK/GASK transceiver designed for operation in the
license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It
is suitable for circuit applications that meet either the European
ETSI-300-220 or the North American FCC (Part 15) regulatory
standards. A complete transceiver can be built using a small
number of external discrete components, making the ADF7020
very suitable for price-sensitive and area-sensitive applications.

The transmit section contains a VCO and low noise
fractional-N PLL with output resolution of <1 ppm. The VCO
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.

The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.

A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application. The
receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.

An on-chip ADC provides readback of an integrated tempera­ture sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±5°C over
the full operating temperature range of −40°C to +85°C.

Rev. PrH | Page 3 of 40

ADF7020 Preliminary Technical Data

SPECIFICATIONS

VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T
Typical specifications are at V

= 3 V, TA = 25°C.

DD

All measurements are performed using the test circuit in Figure TBD using PN9 data sequence, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions

RF CHARACTERISTICS

Frequency Ranges 862 928 MHz

Frequency Ranges (Divide-by-2 Mode) 433 464 MHz

Phase Frequency Detector Frequency RF/256 20 MHz
TRANSMISSION PARAMETERS

Data Rate FSK/GFSK 0.3 200 kbps

Data Rate OOK/ASK 0.3 64

Frequency Shift Keying

GFSK/FSK Frequency Deviation

4.88 620 kHz PFD = 20 MHz
Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Adjacent Channel Power, GFSK TBD dBc

−50 dBc

Amplitude Shift Keying

ASK Modulation Depth 30 dB

OOK –PA Off Feedthrough −50 dBm
Transmit Power4 −20 +13 dBm FRF = 915 MHz, VDD = 3.0 V, TA = 25°C
TBD dBm FRF = 868 MHz, VDD = 3.0 V, TA = 25°C
TBD dBm FRF = 433 MHz, VDD = 3.0 V, TA = 25°C
Transmit Power Variation

Highest Power Setting TBD dBm FRF = 915 MHz, VDD = 3.6 V

13 dBm FRF = 915 MHz, VDD = 3.0 V
TBD dBm FRF = 915 MHz, VDD = 2.3 V

Transmit Power Flatness TBD dB From 902 MHz to 928 MHz
Programmable Step Size

−20 dBm to +13 dBm 0.3125 dB

Spurious Emissions during PLL Settling −57 dBm Mute PA until lock enabled (R2_DB5 =1 )

Integer Boundary −55 dBc 50 kHz loop BW

Reference −65 dBc
Harmonics

Second Harmonic −27 −18 dBc

Third Harmonic −21 −18 dBc

All Other Harmonics −35 dBc
VCO Frequency Pulling, OOK mod TBD kHz rms DR = 9.6 kbps
Optimum PA Load Impedance

5

TBD Ω FRF = 868 MHz
TBD Ω FRF = 433 MHz

RECEIVER PARAMETERS

FSK Input Sensitivity6 At BER = 1E − 3, FRF = 915 MHz

High Sensitivity Mode −117.5 dBm DR = 1 kbps, F

Low Current Mode −TBD dBm DR = 1 kbps, F

See notes at end of table.

to T

MIN

2, 3

, unless otherwise noted.

MAX

1

kbps

1 110 kHz PFD = 3.625 MHz

Channel spacing = 25 kHz, measured in
adjacent channel ± 8.5 kHz from center;
DR = 4.8 kbps, F

= 2.4 kHz,

DEV

FRF = 868 MHz

868.95 MHz ± 250 kHz, DR = 38.4 kbps,
= 19.2 kHz

F

DEV

TBD Ω FRF = 915 MHz

= 5 kHz

DEV

= 5 kHz

DEV

Rev. PrH | Page 4 of 40

Preliminary Technical Data ADF7020

Parameter Min Typ Max Unit Test Conditions

High Sensitivity Mode −110.5 dBm DR = 9.6 kbps, FDEV = 10 kHz
Low Current Mode −104 dBm DR = 9.6 kbps, FDEV = 10 kHz
High Sensitivity Mode −99 dBm DR = 200 kbps, FDEV = 50 kHz
Low Current Mode −TBD dBm DR = 200 kbps, FDEV = 50 kHz

OOK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz

High Sensitivity Mode −TBD dBm DR = 1 kbps
Low Current Mode −TBD dBm DR = 1 kbps
High Sensitivity Mode −106.5 dBm DR = 9.6 kbps

Low Current Mode −TBD dBm DR = 9.6 kbps
LNA and Mixer
Input IP3

Rx Spurious Emissions

−47 dBm >1 GHz at antenna input
AFC

Channel Filtering
Adjacent Channel Rejection

Second Adjacent Channel Rejection

Third Adjacent Channel Rejection

Image Channel Rejection 30 dB Uncalibrated

Co-channel Rejection −3 dB
Wide-Band Interference Rejection TBD dB

Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10
Input Impedance TBD Ω FRF = 915 MHz, RFIN, RFIN to GND
TBD Ω FRF = 868 MHz
TBD Ω FRF = 433 MHz
RSSI

PHASE LOCKED LOOP

VCO Gain 65 MHz/V

130 MHz/V

TBD MHz/V At 433MHz, VCO Adjust = 0
Phase Noise (In-Band) −92 dBc/Hz

Phase Noise (Out-of-Band) −110 dBc/Hz At 1 MHz offset
Residual FM TBD Hz From 300 Hz to 5 kHz

See notes at end of table.

7

Enhanced Linearity Mode 6.8 dBm Pin = −20 dBm, 2 CW interferers
Low Current Mode −3.2 dBm FRF = 915 MHz, f1 = FRF + 3 MHz
High Sensitivity Mode −35 dBm F2 = FRF + 6 MHz, maximum gain

8

−57 dBm <1 GHz at antenna input

Pull-In Range ±50 kHz IF_BW = 200 kHz
Response time TBD Bits
Accuracy 1 TBD kHz

27 dB

(Offset = ±1 × IF Filter BW Setting)

50 dB

(Offset = ±2 × IF Filter BW Setting)

TBD dB

(Offset = ±3 × IF Filter BW Setting)

(Image Channel = FRF − 400 kHz) TBD dB Calibrated

IF filter BW settings = 100 kHz, 150 kHz,
200 kHz

Desired signal 3 dB above the input
sensitivity level, CW interferer power
level increased until BER = 10

−3

, image

channel excluded

9

Swept from 100 MHz to 2 GHz, measured
as channel rejection

−3

Range at Input −100 to −36 dBm
Linearity ±3 dB
Absolute Accuracy TBD dB
Response Time 350 µs

Maximum input step change, AGC
included, RSSI ready for readback

902 MHz to 928 MHz band.,
VCO adjust = 0

860MHz to 870 MHz band,
VCO Adjust = 0

PA = 0 dBm, V

= 3.0 V, PFD = 10 MHz,

DD

FRF = 915 MHz, VCO BIAS = 4

Rev. PrH | Page 5 of 40

ADF7020 Preliminary Technical Data

Parameter Min Typ Max Unit Test Conditions

PLL Settling Time 40 µs

REFERENCE INPUT

Crystal Reference 3.625 24 MHz
External Oscillator 3.625 24 MHz
Load capacitance TBD pF

Input Level

CMOS
levels

TIMING INFORMATION

Chip Enabled to Regulator Ready TBD µs C
Crystal Oscillator Startup time 1 ms With 19.2 MHz XTAL
Tx to Rx Turnaround Time

LOGIC INPUTS

V

Input High Voltage 0.7 × V DD V

INH,

V

, Input Low Voltage 0.2 × V

INL

I

Input Current ±1 µA

INH/IINL,

350 µs +
(5 × T

)

BIT

V

DD

CIN, Input Capacitance 10 pF
Control Clock Input 50 MHz

LOGIC OUTPUTS

VOH,Output High Voltage

DV

DD

V I

−

0.4
VOL, Output Low Voltage 0.4 V IOL = 500 µA
CLK

Rise/Fall 5 ns

OUT

CLK

Load 10 pF

OUT

TEMPERATURE RANGE—TA −40 +85 °C
POWER SUPPLIES

Voltage Supply

AV
DV

DD

DD

2.3 3.6 V

AV

DD

AV

DD

Transmit Current Consumption

−20 dBm TBD mA

−10 dBm 12 mA VCO_BIAS_SETTING = 3
0 dBm 15 mA
10 dBm 22 mA

Receive Current Consumption

Low Current Mode 19 TBD mA
High Sensitivity Mode 21 TBD mA

Power-Down Mode

Low Power Sleep Mode

0.1 1 µA

1

Higher data rates are achievable depending on local regulations.

2

For definition of frequency deviation, see the R section. egister 2—Transmit Modulation Register (FSK Mode)

3

For definition of GFSK frequency deviation, see the R section. egister 2—Transmit Modulation Register (GFSK/GOOK Mode)

4

Measured as maximum unmodulated power. Output power varies with both supply and temperature.

5

For matching details, see the LN section. A/PA Matching

6

See Table 5 for description of different receiver modes.

7

See Table 5 for description of different receiver modes.

8

Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

9

See the section. Image Rejection Calibration

Measured for a 10 MHz frequency step to
within 5 ppm accuracy,
PFD = 20 MHz, LBW = TBD

See the Reference Input Section

= 100 nF

REG

Time to synchronized data, includes AGC
settling

= 500 µA

OH

FRF = 915 MHz, V

= 3.0 V, PA is matched

DD

in to 50 Ω

Rev. PrH | Page 6 of 40

Preliminary Technical Data ADF7020

A

TIMING CHARACTERISTICS

VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Guaranteed by design, but not production tested.

Table 2.

Parameter Limit at T

t

1

<10 ns SDATA to SCLK Setup Time

t2 <10 ns SDATA to SCLK Hold Time

t3 <25 ns SCLK High Duration

t4 <25 ns SCLK Low Duration

t5 <10 ns SCLK to SLE Setup Time

t6 <20 ns SLE Pulse Width

t

7

t

8

t

9

t

10

<TBD ns SLE to SCLK Setup Time, Readback

<TBD ns SCLK to SREAD Data Valid, Readback

<TBD ns SREAD Hold Time after SCLK, Readback

<TBD ns SCLK to SLE Disable Time, Readback

MIN

to T

MAX

Unit Test Conditions/Comments

SCLK

SDAT

SLE

t

1

DB31 (MSB) DB30 DB2

t

1

SCLK

SDATA

REG7 DB0

(CONTROL BIT C1)

SLE

t

3

t

2

t

2

t

3

t

4

DB1

(CONTROL BIT C2)

Figure 2. Serial Interface Timing Diagram

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

01975-PrG-002

t

10

SREAD

t

X RV16 RV15 RV2 RV1

t

8

9

Figure 3. Readback Timing Diagram

01975-PrG-003

Rev. PrH | Page 7 of 40

ADF7020 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 125°C
MLF θJA Thermal Impedance
Lead Temperature Soldering

Vapor Phase (60 s) 235°C
Infrared (15 s) 240°C

1

−0.3 V to +5 V

TBD°C/W

1

GND = CPGND = RFGND = DGND = AGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high-performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. PrH | Page 8 of 40

Preliminary Technical Data ADF7020

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVCO

GND1

GND

VCO GND

GND

VDD

CPOUT

VREG3

VDD3

OSC1

OSC2

MUXOUT

VCOIN

VREG1

VDD1
RFOUT
RFGND

RFIN

RFINB

R

LNA

VDD4

RSET

VREG4

GND4

4847464544434241403938

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

10

11

12

ADF7020

TOP VIEW

(Not to Scale)

37

36

CLKOUT

35

DATA CLK

34

DATA I/O
INT/LOCK

33

VDD2

32

VREG2

31

ADCIN

30

GND2

29

SCLK

28

SREAD

27

SDATA

26

SLE

25

1314151617181920212223

MIX_I

MIX_I

MIX_Q

GND4

FILT_I

FILT_I

MIX_Q

FILT_Q

GND4

FILT_Q

24

CE

TEST_A

01975-PrG-004

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.

2 VREG1

Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.

3 VDD1

Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 µF and 0.01 µF should be placed
as close as possible to this pin.

4 RFOUT

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output

should be impedance matched to the desired load using suitable components. See the Transmitter section.
5 RFGND Ground for Output Stage of Transmitter.
6 RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 R

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

LNA

9 VDD4 Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 µF capacitor.
10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
11 VREG4

Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for

regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER block.
13–18 MIX/FILT

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.
19, 22 GND4 Ground for LNA/MIXER block.
20, 21, 23 FILT/TEST_A

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.
24 CE

Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE

is low, and the part must be reprogrammed once CE is brought high.
25 SLE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.
26 SDATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high

impedance CMOS input.
27 SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK

input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
28 SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. PrH | Page 9 of 40

ADF7020 Preliminary Technical Data

Pin No. Mnemonic Function

29 GND2 Ground for Digital Section.
30 ADCIN

31 VREG2

32 VDD2

33 INT/LOCK

34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
35 DATA CLK

36 CLKOUT

37 MUXOUT

38 OSC2

39 OSC1 The reference crystal should be connected between this pin and OSC2.
40 VDD3

41 VREG3

42 CPOUT

43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
44–47 GND Grounds for VCO Block.
48 CVCO A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to

1.9 V. Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor (X7R or Tantalum) of 0.01 µF should be placed as

close as possible to this pin.
Bidirectional Pin. In output mode (INTerrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found

a match for the preamble sequence.
In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid

preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a
demod lock can be asserted with minimum delay.

In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data.

In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the
transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section.

A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.

This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
regulator.

The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.

Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a

0.01 µF capacitor.
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin

and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

Rev. PrH | Page 10 of 40

Preliminary Technical Data ADF7020

A

T

FREQUENCY SYNTHESIZER

REFERENCE INPUT SECTION

The on-board crystal oscillator circuitry (Figure 5) can use an
inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.

R Counter

The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:

PFD [Hz] = XTAL/R

MUXOUT and Lock Detect

OSC1

Figure 5. Oscillator Circuit on the ADF7020

OSC2

CP1CP2

01975-PrG-005

Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 5, and supplies a divided­down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB(8:11). On power-up, the CLKOUT defaults to
divide-by-8.

DV

DD

CLK

OUT

ENABLE BIT

OSC1

DIVIDER

1 TO 15

÷2

Figure 6. CLK

OUT

Stage

CLK

OUT

01975-PrG-006

To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at F

CLK

.

The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB(29:31).

Regulator Ready

REGULATOR READY is the default setting on MUXOUT after
the transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is
powered from the regulator, the regulator must be at its nominal
voltage before the ADF7020 can be programmed. The status of
the regulator can be monitored at MUXOUT. When the
REGULATOR READY signal on MUXOUT is high,
programming of the ADF7020 can begin.

DV

DD

REGULATOR READY

DIGITAL LOCK DETECT

NALOG LOCK DETEC

R COUNTER OUTPUT
N COUNTER OUTPUT

PLL TEST MODES

Σ-∆ TEST MODES

MUX CONTROL

Figure 7. MUXOUT Circuit

DGND

MUXOUT

01975-PrG-007

Digital Lock Detect

Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.

Rev. PrH | Page 11 of 40

ADF7020 Preliminary Technical Data

Analog Lock Detect

This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low-going pulses.

Voltage Regulators

The ADF7020 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
VREG and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the chip-enable pin low disables the
regulators, reduces the supply current to less than 1 µA, and
erases all values held in the registers. The serial interface
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (VREG4) can be monitored using
the regulator ready signal from MUXOUT.

Loop Filter

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times
the data rate be used to ensure that sufficient samples are taken
of the input data while filtering system noise. The free design
tool ADIsimPLL can be used to design loop filters for the
ADF7020.

N Counter

The feedback divider in the ADF7020 PLL consists of an 8-bit
integer counter and a 14-bit Σ-∆ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as

F

REFERENCE IN

OUT

=

4R

XTAL

R

CHARGE

PFD/

PUMP

× (Integer-N +

-NFractional

)

14

2

VCO

The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 8.

CHARGE

PUMP OUT

Figure 8. Typical Loop Filter Configuration

VCO

01975-PrG-008

In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately five times the data rate. Widening the
LBW excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.

For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels might result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW might
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.

Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.

4N

THIRD-ORDER

Σ-∆ MODULATOR

INTEGER-NFRACTIONAL-N

Figure 9. Fractional-N PLL

01975-PrG-009

The combination of the integer-N (maximum = 255) and the
fractional-N (maximum = 16383/16384) give a maximum N
divider of 255 + 1. Therefore, the minimum usable PFD is

PDF

[Hz] = Maximum Required Output Frequency/(255 + 1)

MIN

For example, when operating in the European 868 MHz to
870 MHz band, PFD

equals 3.4 MHz.

MIN

Voltage Controlled Oscillator (VCO)

To minimize spurious emissions, the on-chip VCO operates
from 1732 MHz to 1856 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.

The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB(20:21).

The VCO is enabled as part of the PLL by the PLL-enable bit,
R0_DB28.

A further frequency divide-by-2 is included to allow operation
in the lower 433 MHz and 460 MHz bands. To enable operation
in the these bands, R1_DB13 should be set to 1. The VCO needs
an external 22 nF between the VCO and the regulator to reduce
internal noise.

Rev. PrH | Page 12 of 40

Preliminary Technical Data ADF7020

VCO Bias Current

VCO bias current can be adjusted using Bits R1_DB19 to
R1_DB16. To ensure VCO oscillation, the minimum bias
current setting under typical conditions is 2.5 mA.

VCO BIAS

R1_DB (16:19)

LOOP FILTER

CVCO PIN

VCO

220µF

Figure 10. Voltage Controlled Oscillator (VCO)

÷2

÷2

VCO SELECT BIT

MUX

TO PA AND

N DIVIDER

01975-PrG-010

CHOOSING CHANNELS FOR BEST SYSTEM PERFORMANCE

The fractional-N PLL allows the selection of any channel within
868 MHz to 928 MHz (and 433MHz using divide-by-2) to a
resolution of <100 Hz. This also facilitates frequency hopping
systems.

Careful selection of the RF transmit channels must be made to
achieve best spurious performance. The architecture of
fractional-N results in some level of the nearest integer channel
moving through the loop to the RF output. These “beat-note”
spurs are not attenuated by the loop, if the desired RF channel
and the nearest integer channel are separated by a frequency of
less than the LBW.

The occurrence of beat-note spurs is rare, because the integer
frequencies are at multiples of the reference, which is typically
>10 MHz.

Beat-note spurs can be significantly reduced in amplitude by
avoiding very small or very large values in the fractional
register, using the frequency doubler. By having a channel
1 MHz away from an integer frequency, a 100 kHz loop filter
can reduce the level to <−45 dBc. When using an external VCO,
the fast lock (bleed) function reduces the spurs to <−60 dBc for
the same conditions.

Rev. PrH | Page 13 of 40

ADF7020 Preliminary Technical Data

O

M

TRANSMITTER

RF OUTPUT STAGE

The PA of the ADF7020 is based on a single-ended, controlled
current, open-drain amplifier that has been designed to deliver
up to 13 dBm into a 50 Ω load at a maximum frequency of
928 MHz.

The PA output current and, consequently, the output power are
programmable over a wide range. The PA configurations in
FSK/GFSK and ASK/OOK modulation modes are shown in
Figure 11 and Figure 12, respectively. In FSK/GFSK modulation
mode, the output power is independent of the state of the
DATA_IO pin. In ASK/OOK modulation mode, it is dependent
on the state of the DATA_IO pin and Bit R2_DB29, which
selects the polarity of the TxData input. For each transmission
mode, the output power can be adjusted as follows:

• FSK/GFSK: The output power is set using bits

R2_DB(9:14).

• ASK: The output power for the inactive state of the TxData

input is set by Bits R2_DB(15:20). The output power for the
active state of the TxData input is set by Bits R2_DB(9:14).

• OOK: The output power for the active state of the TxData

input is set by Bits R2_DB(9:14). The PA is muted when the
TxData input is inactive.

R2_DB(30:31)

2

The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the
application, one can design a matching network for the PA to
exhibit optimum efficiency at the desired radiated output power
level for a wide range of different antennas, such as loop or
monopole antennas. See the LNA/PA Matching section for
details.

PA Bias Currents and Mute PA until Lock Bit

Control Bits R2_DB(30:31) facilitate an adjustment of the PA
bias current to further extend the output power control range, if
necessary. If this feature is not required, the default value of
7 µA is recommended. The output stage is powered down by
resetting Bit R2_DB4. To reduce the level of undesired spurious
emissions, the PA can be muted during the PLL lock phase by
setting Bit R2_DB5 (mute PA until lock bit).

MODULATION SCHEMES

Frequency Shift Keying (FSK)

Frequency shift keying is implemented by setting the N value
for the center frequency and then toggling this with the TxData
line. The deviation from the center frequency is set using Bits
R2_DB(15:23). The deviation from the center frequency in Hz
is

odulationPFD

FSK

DEVIATION

Hz][

×

=

Number

14

2

RFOUT

RFGND

DATA I/

RFOUT

RFGND

IDAC

+

FROM VCO

Figure 11. PA Configuration in FSK/GFSK Mode

R2_DB29

R2_DB(30:31)

IDAC

+

FROM VCO

ASK/OOK MODE

6

Figure 12. PA Configuration in ASK/OOK Mode

6

R2_DB(9:14)

R2_DB4
R2_DB5
DIGITAL

LOCK DETECT

6

R2_DB(9:14)

6

R2_DB(15:23)

0

R2_DB4
R2_DB5
DIGITAL

LOCK DETECT

01975-PrG-011

01975-PrG-012

where Modulation Number is a number from 1 to 511
(R2_DB(15:23)) .

Select FSK using Bits R2_DB(6:8).

FSK DEVIATION

FREQUENCY

–F

+F

TxDATA

4R

DEV

DEV

PFD/

CHARGE

PUMP

THIRD-ORDER

Σ-∆ MODULATOR

INTEGER-NFRACTIONAL-N

Figure 13. FSK Implementation

VCO

÷N

PA STAGE

01975-PrG-013

Rev. PrH | Page 14 of 40

Preliminary Technical Data ADF7020

Gaussian Frequency Shift Keying (GFSK)

Gaussian frequency shift keying reduces the bandwidth
occupied by the transmitted spectrum by digitally prefiltering
the TxData. A TxCLK output line is provided from the
ADF7020 for synchronization of TxData from the micro­controller. The TxCLK line can be connected to the clock input
of a shift register that clocks data to the transmitter at the exact
data rate.

Setting Up the ADF7020 for GFSK

To set up the frequency deviation, set the PFD and the mod
control bits:

m

×

2

12

2

GFSK

DEVIATION

PFD

=

]Hz[

where m is GFSK_MOD_CONTROL set using R2_DB(24:26).

To set up the GFSK data rate:

DR__]bps[

=

PFD

×

COUNTERINDEXFACTORDIVIDER

For further information, see the application note, Using GFSK
on the ADF7010, in the EVAL-ADF7010EB1 Technical Note.

Amplitude Shift Keying (ASK)

Amplitude shift keying is implemented by switching the output
stage between two discrete power levels. This is accomplished
by toggling the DAC, which controls the output level between
two 6-bit values set up in Register 2. A zero TxData bit sends
Bits R2_DB(15:20) to the DAC. A high TxData bit sends Bits
R2_DB(9:14) to the DAC. A maximum modulation depth of
30 dB is possible.

On-Off Keying (OOK)

On-off keying is implemented by switching the output stage to a
certain power level for a high TxData bit and switching the
output stage off for a zero. For OOK, the transmitted power for
a high input is programmed using Bits R2_DB(9:14).

Gaussian On-Off Keying (G-OOK)

Gaussian on-off keying represents a prefiltered form of OOK
modulation. The usually sharp symbol transitions are replaced
with smooth Gaussian filtered transitions, the result being a
reduction in frequency pulling of the VCO. Frequency pulling
of the VCO in OOK mode can lead to a wider than desired BW,
especially if it is not possible to increase the loop filter BW >
300 kHz. The G-OOK sampling clock samples data at the data
rate. (See the Setting Up the ADF7020 for GFSK section.)

Rev. PrH | Page 15 of 40

ADF7020 Preliminary Technical Data

RECEIVER SECTION

RF FRONT END

The ADF7020 is based on a fully integrated, low IF receiver
architecture. The low IF architecture facilitates a very low
external component count and does not suffer from power-line­induced interference problems.

Figure 14 shows the structure of the receiver front end. The
many programming options allow users to trade off sensitivity,
linearity, and current consumption against each other in the
way best suitable for their applications. To achieve a high level
of resilience against spurious reception, the LNA features a
differential input. Switch SW2 shorts the LNA input when
transmit mode is selected (R0_DB27 = 0). This feature
facilitates the design of a combined LNA/PA matching network,
avoiding the need for an external Rx/Tx switch. See the LNA/PA
Matching section for details on the design of the matching
network.

Tx/Rx SELECT

RFIN

[R0_DB27]

RFINB

LNA MODE

[R6_DB15]

LNA CURRENT
[R6_DB(16:17)]

LNA GAIN

[R9_DB(20:21)]

LNA/MIXER ENABLE

[R8_DB6]

SW2 LNA

Figure 14. ADF7020 RF Front End

The LNA is followed by a quadrature downconversion mixer,
which converts the RF signal to the IF frequency of 200 kHz. It
is important to consider that the output frequency of the
synthesizer must be programmed to a value 200 kHz below the
center frequency of the received channel.

The LNA has two basic operating modes: high gain/low noise
mode and low gain/low power mode. To switch between these
two modes, use the LNA_mode bit, R6_DB15. The mixer is also
configurable between a low current and an enhanced linearity
mode using the mixer_linearity bit, R6_DB18.

Table 5. LNA/Mixer Modes

Receiver Mode

High Sensitivity Mode
(default)

RxMode2 1 10 0 −104 20 −15.9
Low Current Mode 1 3 0 −91 19 −3.2
Enhanced Linearity Mode 1 3 1 −101 19 6.8
RxMode5 1 10 1 TBD TBD −8.25
RxMode6 0 30 1 TBD TBD −28.8

LNA Mode
(R6_DB15)

0 30 0 −110.5 22 −35

I (TO FILTER)

LO

Q (TO FILTER)

MIXER LINEARITY
[R6_DB18]

LNA Gain Value
R9_DB(21:20)

01975-PrG-014

Based on the specific sensitivity and linearity requirements of
the application, it is recommended to adjust control bits
LNA_mode (R6_DB15) and mixer_linearity (R6_DB18) as
outlined in Table 5.

The gain of the LNA is configured by the LNA_gain field,
R9_DB(20:21), and can be set by either the user or the AGC
logic.

IF Filter Settings/Calibration

Out-of-band interference is rejected by means of a fourth-order
Butterworth polyphase IF filter centered around a frequency of
200 kHz. The bandwidth of the IF filter can be programmed
between 100 kHz and 200 kHz by means of Control Bits
R1_DB(22:23), and should be chosen as a compromise between
interference rejection, attenuation of the desired signal, and the
AFC pull-in range.

To compensate for manufacturing tolerances, the IF filter
should be calibrated once after power-up. The IF filter
calibration logic requires that the IF filter divider in Bits
R6_DB(20:28) be set dependent on the crystal frequency. Once
initiated by setting Bit R6_DB19, the calibration is performed
automatically without any user intervention. The calibration
time is 200 µs, during which the ADF7020 should not be
accessed. It is important not to initiate the calibration cycle
before the crystal oscillator has fully settled. If the AGC loop is
disabled, the gain of IF filter can be set to three levels using the
filter_gain field, R9_DB(20:21). The filter gain is adjusted
automatically, if the AGC loop is enabled.

The signal in the image channel of the low IF mixer, located at a
frequency of 400 kHz below the desired channel, is rejected due
to the image rejection of the polyphase filter. The image
rejection performance of the IF filter is subject to manufactur­ing tolerances, and, to some extent, temperature drift. To
improve the image rejection, a calibration procedure can be
performed as outlined in the Image Rejection Calibration
section.

Mixer Linearity
(R6_DB18)

Sensitivity
(DR = 9.6 kbps,
f

= 10 kHz)

DEV

Rx Current
Consumption
(mA)

Input IP3 (dBm)

Rev. PrH | Page 16 of 40

Preliminary Technical Data ADF7020

RSSI/AGC SECTION

The RSSI is implemented as a successive compression log amp
following the base-band channel filtering. The log amp achieves
±3 dB log linearity. It also doubles as a limiter to convert the
signal-to-digital levels for the FSK demodulator. The RSSI itself
is used for amplitude shift keying (ASK) demodulation. In ASK
mode, extra digital filtering is performed on the RSSI value.
Offset correction is achieved using a switched capacitor integra­tor in feedback around the log amp. This uses the BB offset
clock divide. The RSSI level is converted for user readback and
digitally controlled AGC by an 80-level (7-bit) flash ADC. This
level can be converted to input power in dBm.

OFFSET

CORRECTION

FSK

1

IFWR IFWR IFWR IFWR

R

Figure 15. RSSI Block Diagram

LATCHAAA

CLK

RSSI Thresholds

When the RSSI is above AGC_HIGH_THRESHOLD, the gain is
reduced. When the RSSI is below AGC_LOW_THRESHOLD,
the gain is increased. A delay (AGC_DELAY) is programmed to
allow for settling of the loop. The user programs the two
threshold values (recommended defaults, 27 and 76) and the
delay (default, 10). The default AGC setup values should be
adequate for most applications. The threshold values must be
chosen to be more than 30 apart for the AGC to operate
correctly.

Offset Correction Clock

In Register 3, the user should set the BB offset clock divide bits
R3_DB(4:5) to give an offset clock between 1 MHz and 2 MHz,
where:

BBOS _CLK [Hz] = XTAL/(BBOS_CLK_DIVIDE)

BBOS_CLK_DIVIDE can be set to 4, 8, or 16.

AGC Information

In Register 9, the user should select automatic gain control by
selecting auto in R9_DB18 and auto in R9_DB19. The user
should then program AGC low threshold R9_DB(4:10) and
AGC high threshold R9_DB(11:17). The recommended/default
values for the low and high thresholds are 30 and 70, respec­tively. In the AGC2 register the user should program the AGC
delay to be long enough to allow the loop to settle. The
recommended value is 10.

DEMOD

ADC

RSSI
ASK
DEMOD

01975-PrG-015

RSSI Formula (Converting to dBm)

Input_Power [dBm] = −110 dBm + (Readback_Code +

Gain_Mode_Correction ) × 0.5

where:

Readback_Code is given by Bits RV7 to RV1 in the readback
register (see Readback Format section).

Gain_Mode_Correction is given by the values in Table 6.

LNA gain and filter gain (LG2/LG1, FG2/FG1) are also obtained
from the readback register.

Table 6. Gain Mode Correction Table

LNA Gain
(LG2, LG1)

Filter Gain
(FG2, FG1) Gain Mode Correction

H (10) H (10) 0
M (01) H (10) 11
M (01) M (01) 19 + 11 = 30
M (01) L (00) 19 + 19 + 11 = 49
L (00) L (00) 19 + 19 + 19 + 11 = 68

An additional factor should be introduced to account for losses
in the front-end matching network/antenna.

FSK DEMODULATORS ON THE ADF7020

The two FSK demodulators on the ADF7020 are

• FSK correlator/demodulator

• Linear demodulator

Select these using the demod select bits, R4_DB(4:5).

FSK CORRELATOR/DEMODULATOR

The quadrature outputs of the IF filter are first limited and then
fed to a pair of digital frequency correlators that perform band­pass filtering of the binary FSK frequencies at (IF + F
(IF − F

). Data is recovered by comparing the output levels

DEV

from each of the two correlators. The performance of this
frequency discriminator approximates that of a matched filter
detector, which is known to provide optimum detection in the
presence of AWGN.

SLICERFREQUENCY CORRELATOR

IF – F

DEV

IF

DB(14)

IF + F

DEV

POST

DEMOD FILTER

0

I

LIMITERS

Q

DB(4:13)

Figure 16. FSK Correlator/Demodulator Block Diagram

DEV

DATA

DB(8:15)

) and

Rx DATA

Rx CLK

SYNCHRONIZER

01975-PrG-016

Rev. PrH | Page 17 of 40

ADF7020 Preliminary Technical Data

Postdemodulator Filter

A second-order, digital low-pass filter removes excess noise
from the demodulated bit stream at the output of the
discriminator. The bandwidth of this postdemodulator filter is
programmable and must be optimized for the user’s data rate. If
the bandwidth is set too narrow, performance is degraded due
to intersymbol interference (ISI). If the bandwidth is set too
wide, excess noise degrades the receiver’s performance.
Typically, the 3 dB bandwidth of this filter is set at
approximately 0.75 times the user’s data rate, using Bits
R4_DB(6:15).

Bit Slicer

The received data is recovered by threshold detecting the output
of the postdemodulator low-pass filter. In the correlator/
demodulator, the binary output signal levels of the frequency
discriminator are always centered on zero. Therefore, the slicer
threshold level can be fixed at zero and the demodulator
performance is independent of the run-length constraints of the
transmit data bit stream. This results in robust data recovery,
which does not suffer from the classic baseline wander
problems that exist in the more traditional FSK demodulators.

Frequency errors are removed by an internal AFC loop that
measures the average IF frequency at the limiter output and
applies a frequency correction value to the fractional-N
synthesizer. This loop should be activated when the frequency
errors are greater than approximately 40% of the transmit
frequency deviation (see the AFC Section).

Data Synchronizer

An oversampled digital PLL is used to resynchronize the
received bit stream to a local clock. The oversampled clock rate
of the PLL (CDR_CLK) must be set at 32 times the data rate.
See the notes for the Register 3—Receiver Clock Register
section for a definition of how to program. The clock recovery
PLL can accommodate frequency errors of up to ±2%.

FSK Correlator Register Settings

To enable the FSK correlator/demodulator, Bits R4_DB(5:4)
should be set to [01]. To achieve best performance, the
bandwidth of the FSK correlator must be optimized for the
specific deviation frequency that is used by the FSK transmitter.

The discriminator BW is controlled in Register 6 by
R6_DB(4:13) and is defined as

3

)10800/()_(_

××= KCLKDEMODBWtorDiscrimina

where:

DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.
K = Round(200e3/FSK Deviation)

To optimize the coefficients of the FSK correlator, two
additional bits, R6_DB14 and R6_DB29, must be assigned. The
value of these bits depends on whether K (as defined above) is
odd or even. These bits are assigned according to Table 7 and
Tabl e 8 .

Table 7. When K Is Even

K K/2 R6_DB14 R6_DB29

Even Even 0 0
Even Odd 0 1

Table 8. When K Is Odd

K (K + 1)/2 R6_DB14 R6_DB29

Odd Even 1 0
Odd Odd 1 1

Postdemodulator Bandwidth Register Settings

The 3 dB bandwidth of the postdemodulator filter is controlled
by Bits R4_ DB(6:15) and is given by

where F

10

BWSettingDemodPost

__

is the target 3 dB bandwidth in Hz of the

CUTOFF

=

F

22

×π×

CUTOFF

CLKDEMOD

_

postdemodulator filter. This should typically be set to 0.75 times
the data rate (DR).

Some sample settings for the FSK correlator/demodulator are

DEMOD_CLK = 5 MHz
DR = 9.6 kbps

= 20 kHz

F

DEV

Therefore,

= 0.75 × 9.6 × 103 Hz

F

CUTOFF

Post_Demod_BW = 2

11

π 7.2 × 103 Hz/(5 MHz)

Post_Demod_BW = Round(9.26) = 9

and

K = Round(200 kHz)/20 kHz) = 10

3

Discriminator_BW = (5 MHz × 10)/(800 × 10

) = 62.5 =

63 (rounded to nearest integer)

Table 9.

Setting Name Register Address Value

Post_Demod_BW R4_DB(6:15) 0x09
Discriminator BW R6_DB(4:13) 0x3F
Dot Product R6_DB14 0
Rx Data Invert R6_DB29 0

Rev. PrH | Page 18 of 40

Preliminary Technical Data ADF7020

LINEAR FSK DEMODULATOR

A block diagram of the linear FSK demodulator is shown in
Figure 17.

ENVELOPE

DETECTOR

×π×

F

CUTOFF

_

SLICER

FREQUENCY
READBACK
AND
AFC LOOP

CLKDEMOD

Rx DATA

01975-PrG-017

MUX 1

ADC RSSI OUTPUT

LEVEL

I

LIMITER
Q

LINEAR DISCRIMINATOR

Figure 17. Block Diagram of Frequency Measurement System and

IF

FREQUENCY

ASK.OOK/Linear FSK Demodulator

7

FILTER

AVERAGING

DB(6:15)

This method of frequency demodulation is useful when very
short preamble length is required and the system protocol
cannot support the overhead of the settling time of the internal
feedback AFC loop settling.

A digital frequency discriminator provides an output signal that
is linearly proportional to the frequency of the limiter outputs.
The discriminator output is then filtered and averaged using a
combined averaging filter and envelope detector. The demodu­lated FSK data is recovered by threshold-detecting the output of
the averaging filter, as shown in Figure 17. In this mode, the
slicer output shown in Figure 17 is routed to the data synchro­nizer PLL for clock synchronization. To enable the linear FSK
demodulator, set Bits R4_DB(4:5) to [00].

The 3 dB bandwidth of the postdemodulation filter is set in the
same way as the FSK correlator/demodulator, which is set in
R4_DB(6:15) and is defined as

10

22

=

SettingBWDemodPost

___

where:

is the target 3 dB bandwidth in Hz of the

F

CUTOFF

postdemodulator filter.
DEMOD_CLK is as defined in the Register 3—Receiver Clock
Register section, Note 2.

ASK/OOK Operation

ASK/OOK demodulation is activated by setting Bits
R4_DB(4:5) to [10].

Digital filtering and envelope detecting the digitized RSSI input
via MUX 1, as shown in Figure 17, perform ASK/OOK
demodulation. The bandwidth of the digital filter must be
optimized to remove any excess noise without causing ISI in the
received ASK/OOK signal.

The 3 dB bandwidth of this filter is typically set at approxi­mately 0.75 times the user data rate and is assigned by R4
_DB(6:15) as

Post_Demod_BW_Setting =

where F

is the target 3 dB bandwidth in Hz of the

CUTOFF

10

DEMOD_CLK

×π× 22

F

CUTOFF

postdemodulator filter.

AFC SECTION

The ADF7020 supports a real-time AFC loop, which is used to
remove frequency errors that can arise due to mismatches
between the transmit and receive crystals. This uses the
frequency discriminator block, as described in the Linear FSK
Demodulator section (see Figure 17). The discriminator output
is filtered and averaged to remove the FSK frequency
modulation using a combined averaging filter and envelope
detector. In FSK mode, the output of the envelope detector
provides an estimate of the average IF frequency.

Two methods of AFC, external and internal, are supported on
the ADF7020 (in FSK mode only).

External AFC

The user reads back the frequency information through the
ADF7020 serial port and applies a frequency correction value to
the fractional-N synthesizer’s N divider.

The frequency information is obtained by reading the 16-bit
signed AFC_readback, as described in the Readback Format
section, and applying the following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2

Note that while the AFC_READBACK value is a signed number,
under normal operating conditions it is positive. In the absence
of frequency errors, the FREQ_RB value is equal to the IF
frequency of 200 kHz.

Internal AFC

The ADF7020 supports a real-time internal automatic
frequency control loop. In this mode, an internal control loop
automatically monitors the frequency error and adjusts the
synthesizer N divider using an internal PI control loop.

The internal AFC control loop parameters are controlled in
Register 11. The internal AFC loop is activated by setting
R11_DB20 to 1. A scaling coefficient must also be entered,
based on the crystal frequency in use. This is set up in
R11_DB(4:19) and should be calculated using

AFC_Scaling_Coefficient = (500 × 2

24

)/XTAL

Therefore, using a 10 MHz XTAL yields an AFC scaling
coefficient of 839.

15

Rev. PrH | Page 19 of 40

ADF7020 Preliminary Technical Data

Maximum AFC Range

The maximum AFC frequency range is ±100 kHz. This is set by
the maximum IF filter bandwidth of 200 kHz. Using the
minimum IF filter bandwidth of 100 kHz, the AFC range is
±50 kHz.

When AFC errors have been removed using either the internal
or external AFC, further improvement in the receiver’s sensi­tivity can be obtained by reducing the IF filter bandwidth using
Bits R1_DB(22:23).

AUTOMATIC SYNC WORD RECOGNITION

The ADF7020 also supports automatic detection of the sync or
ID fields. To activate this mode, the sync (or ID) word must be
preprogrammed into the ADF7020. In receive mode, this
preprogrammed word is compared to the received bit stream
and, when a valid match is identified, the external pin
INT/LOCK is asserted by the ADF7020.

This feature can be used to alert the microprocessor that a valid
channel has been detected. It relaxes the computational
requirements of the microprocessor and reduces the overall
power consumption. The INT/LOCK is automatically de­asserted again after nine data clock cycles.

The automatic sync/ID word detection feature is enabled by
selecting demod mode 2 or 3 in the demodulator setup register.
Do this by setting R4_DB(25:23) = [010] or [011]. Bits
R5_DB(4:5) are used to set the length of the sync/ID word,
which can be either 12, 16, 20, or 24 bits long. The transmitter
must transmit the MSB of the sync byte first and the LSB last to
ensure proper alignment in the receiver sync byte detection
hardware.

For systems using FEC, an error tolerance parameter can also be
programmed that accepts a valid match when up to three bits of
the word are incorrect. The error tolerance value is assigned in
R5_DB(6:7).

Rev. PrH | Page 20 of 40

Preliminary Technical Data ADF7020

A

A

APPLICATIONS SECTION

LNA/PA MATCHING

The ADF7020 exhibits optimum performance in terms of
sensitivity, transmit power, and current consumption only if its
RF input and output ports are properly matched to the antenna
impedance. For cost-sensitive applications, the ADF7020 is
equipped with an internal Rx/Tx switch, which facilitates the
use of a simple combined passive PA/LNA matching network.
Alternatively, an external Rx/Tx switch such as the Analog
Devices ADG919 can be used, which yields a slightly improved
receiver sensitivity and lower transmitter power consumption.

External Rx/Tx Switch

Figure 18 shows a configuration using an external Rx/Tx switch.
This configuration allows an independent optimization of the
matching and filter network in the transmit and receive path,
and is, therefore, more flexible and less difficult to design than
the configuration using the internal Rx/Tx switch. The PA is
biased through inductor L1, while C1 blocks dc current. Both
elements, L1 and C1, also form the matching network, which
transforms the source impedance into the optimum PA load
impedance, Z

NTENN

Rx/Tx – SELECT

Z

_PA depends on various factors such as the required output

OPT

power, the frequency range, the supply voltage range, and the
temperature range. Selecting an appropriate Z
minimize the Tx current consumption in the application. This
datasheet contains a number of Z
tive conditions. Under certain conditions, however, it is
recommended to obtain a suitable Z
load-pull measurement.

Due to the differential LNA input, the LNA matching network
must be designed to provide both a single-ended to differential
conversion and a complex conjugate impedance match. The
network with the lowest component count that can satisfy these
requirements is the configuration shown in Figure 18, which
consists of two capacitors and one inductor. A first-order
implementation of the matching network can be obtained by
understanding the arrangement as two L-type matching

_PA.

OPT

V

BAT

OPTIONAL

LPF

OPTIONAL

BPF

(SAW)

ADG919

Figure 18. ADF7020 with External Rx/Tx Switch

L1

Z
Z

IN

C

A

L

ZIN_RFIN

C

B

_PA values for representa-

OPT

OPT

PA_OUT

_PA

OPT

_RFIN

RFIN

A

RFINB

ADF7020

OPT

_PA value by means of a

PA

LNA

_PA helps to

01975-PrG-018

networks in a back-to-back configuration. Due to the
asymmetry of the network with respect to ground, a compro­mise between the input reflection coefficient and the maximum
differential signal swing at the LNA input must be established.
The use of appropriate CAD software is strongly recommended
for this optimization.

Depending on the antenna configuration, the user might need a
harmonic filter at the PA output to satisfy the spurious emission
requirement of the applicable government regulations. The
harmonic filter can be implemented in various ways, such as a
discrete LC-filter. Dielectric low-pass filter components such as
the LFL18924MTC1A052 (for operation in the 915 MHz band),
or LFL18869MTC2A160 (for operation in the 868 MHz band),
both by Murata Mfg. Co., Ltd., represent an attractive alternative
to discrete designs. The immunity of the ADF7020 to strong
out-of-band interference can be improved by adding a band­pass filter in the Rx path. Apart from discrete designs, SAW or
dielectric filter components such as the
SAFCH869MAM0T00B0S, SAFCH915MAL0N00B0S,
DCFB2869MLEJAA-TT1, or DCFB3915MLDJAA-TT1, all by
Murata Mfg. Co., Ltd., are well suited for this purpose.

Internal Rx/Tx Switch

Figure 19 shows the ADF7020 in a configuration where the
internal Rx/Tx switch is used with a combined LNA/PA
matching network. Depending on the application, the slight
performance degradation caused by the internal Rx/Tx switch
might be acceptable, allowing the user to take advantage of the
cost-saving potential of this solution. The design of the
combined matching network must compensate for the
reactance presented by the networks in the Tx and the Rx paths,
taking the state of the Rx/Tx switch into consideration.

V

BAT

L1

ANTENNA

C1

OPTIONAL

BPF OR LPF

Figure 19. ADF7020 with Internal Rx/Tx Switch

Z
ZIN_RFIN

C

A

L

A

ZIN_RFIN

C

B

OPT

_PA

PA_OUT

RFIN

RFINB

ADF7020

PA

LNA

01975-PrG-019

The procedure typically requires several iterations until an
acceptable compromise has been reached. The successful
implementation of a combined LNA/PA matching network for
the ADF7020 is critically dependent on the availability of an

Rev. PrH | Page 21 of 40

ADF7020 Preliminary Technical Data

accurate electrical model for the PC board. In this context, the
use of a suitable CAD package is strongly recommended. To
avoid this effort, the reference design provided for the ADF7020
RF module can be used.

As with the external Rx/Tx switch, an additional LPF or BPF
might be required to suppress harmonics in the transmit
spectrum or to improve the resilience of the receiver against
out-of-band interferers.

TRANSMIT PROTOCOL AND CODING CONSIDERATIONS

PREAMBLE

A dc-free preamble pattern is recommended for FSK/ASK/
OOK demodulation. The recommended preamble pattern is a
dc-free pattern such as a 10101010… pattern. Preamble patterns
with longer run-length constraints such as 11001100…. can also
be used. However, this results in a longer synchronization time
of the received bit stream in the receiver.

Manchester coding can be used for the entire transmit protocol.
However, the remaining fields that follow the preamble header
do not have to use dc-free coding. For these fields, the ADF7020
can accommodate coding schemes with a run-length of up to
6 bits without any performance degradation.

If longer run-length coding must be supported, the ADF7020
has several other features that can be activated. These involve a
range of programmable options that allow the envelope detector
output to be frozen after preamble acquisition.

SYNC

WORDIDFIELD DATA FIELD CRC

Figure 20. Typical Format of a Transmit Protocol

01975-PrG-042

IMAGE REJECTION CALIBRATION

The image channel in this receiver, with an IF at 200 kHz, is at

−200 kHz or +400 kHz below the desired signal. The polyphase
filter rejects this image with an asymmetric frequency response.
The image rejection performance of the receiver is dependent
on how well matched in amplitude the I and Q signals are, and
how perfect the quadrature is between them, that is, how close
to 90° apart they are. The uncalibrated image rejection perform­ance is approximately 30 dB. However, it is possible to improve
on this performance by adjusting the I/Q phase/gain adjust bits
in Register 10, resulting in an image rejection of approximately
45 dB.

Bits R10_DB(24:27) adjust the relative phase of the signal
and Bits R10_DB(16:20) adjust the relative amplitude (see
Figure 20).

POLYPHASE

LNA MIXERS

GAIN PHASE

LO QLO I

Figure 20. Phase/Gain Adjustment on ADF7020

FILTER

01975-PrG-020

DEVICE PROGRAMMING AFTER INITIAL
POWER-UP

Basic mode is the minimum number of write sequences to
power up the device. Enhanced mode uses the additional
features of the ADF7020 to tailor the part to a particular
application such as setting up a sync byte sequence or doing
automatic frequency control.

The sample setting is for the following setup:

Rev. PrH | Page 22 of 40

FRF = 915 MHz, FSK, DR = 9.868 kbps, ICP = 1.44 mA

= 50 kHz, XTAL = 10 MHz, Correlator/Demodulator

F

DEV

Preliminary Technical Data ADF7020

REGISTER WRITE

WRITE TO R0

WRITE TO R1

WRITE TO R2

REGISTER WRITE

WRITE TO R0

WRITE TO R1

WRITE TO R3

PRIMARY

FUNCTION

PROGRAM

FREQUENCY

SET UP

OSCILLATOR

AND IF FILTER

SET UP
MODULATION
PARAMETERS

Figure 21. Basic Mode—Tx

PRIMARY

FUNCTION

PROGRAM

FREQUENCY

SET UP

OSCILLATOR

AND IF FILTER

SET UP

Rx CLOCKS

EXAMPLE

SETTING

0x72DC 0000

0x86 9011

0x8022 6012

EXAMPLE

SETTING

0x7ADB D710

0x86 9011

0x64 2053

01975-PrG-021

REGISTER WRITE

WRITE TO R0

WRITE TO R1

WRITE TO R3

PRIMARY

FUNCTION

PROGRAM

FREQUENCY

SET UP

OSCILLATOR

AND IF FILTER

SET UP

Rx CLOCKS

EXAMPLE

SETTING

0x0000

0x0000

0x0000

WRITE TO R4

WRITE TO R5

WRITE TO R6

WRITE TO R9

SET UP

DEMOD

SET UP
SYNC BYTE
SEQUENCE

SET UP

Rx MODE

SET UP AGC

PARAMETERS AND

LNA/GAIN FILTER

0x0000

0x0000

0x0000

0x0000

WRITE TO R4

WRITE TO R6

SET UP
DEMOD

SET UP

Rx MODE

Figure 22. Basic Mode—Rx

0x0194

0x2C82 0326

01975-PrG-022

WRITE TO R10

WRITE TO R11

Figure 23. Enhanced Mode—Rx

SET UP I/Q

GAIN/PHASE

ADJUST

SET UP AFC

PARAMETERS

0x0000

0x0000

01975-PrG-023

REGISTER WRITE

WRITE TO R0

PRIMARY

FUNCTION

CHANGE FREQUENCY

AND CHANGE MODE

TO Rx

Figure 24. Change Mode from Tx to Rx

EXAMPLE

SETTING

0x0000

01975-PrG-024

Rev. PrH | Page 23 of 40

ADF7020 Preliminary Technical Data

SERIAL INTERFACE

The serial interface allows the user to program the eleven 32-bit
registers using a 3-wire interface (SCLK, SDATA, and SLE). It
consists of a level shifter, 32-bit shift register and eleven latches.
Signals should be CMOS compatible. The serial interface is
powered by the regulator, and, therefore, is inactive when CE is
low.

Data is clocked into the register, MSB first, on the rising edge of
each clock (SCLK). Data is transferred to one of eleven latches
on the rising edge of SLE. The destination latch is determined
by the value of the four control bits (C4 to C1). These are the
bottom four LSBs, DB3 to DB0, as shown in the timing diagram
in Figure 2. Data can also be read back on the SREAD pin.

READBACK FORMAT

The readback operation is initiated by writing a valid control
word to the readback register and setting the readback-enable
bit (R7_DB8 = 1). The readback can begin after the control
word has been latched with the SLE signal. SLE must be kept
high while the data is being read out. Each active edge at the
SCLK pin clocks the readback word out successively at the
SREAD pin, as shown in Figure 25, starting with the MSB first.
The data appearing at the first clock cycle following the latch
operation must be ignored.

AFC Readback

The AFC readback is valid only during the reception of FSK
signals with either the linear or correlator demodulator active.
The AFC readback value is formatted as a signed 16-bit integer
comprised of Bits RV1 to RV16, and is scaled according to the
following formula:

FREQ_RB [Hz] = (AFC_READBACK × DEMOD_CLK)/2

In the absence of frequency errors, the FREQ_RB value is equal
to the IF frequency of 200 kHz. Note that, for the AFC readback
to yield a valid result, the down-converted input signal must not
fall outside the bandwidth of the analogue IF filter. At low-input
signal levels, the variation in the readback value can be
improved by averaging.

15

RSSI Readback

The RSSI readback operation yields valid results in Rx mode
with ASK or FSK signals. The format of the readback word is
shown in Figure 25. It is comprised of the RSSI level informa­tion (Bits RV1 to RV7), the current filter gain (FG1, FG2), and
the current LNA gain (LG1, LG2) setting. The filter and LNA
gain are coded in accordance with the definitions in Register 9.
With the reception of ASK modulated signals, averaging of the
measured RSSI values improves accuracy. The input power can
be calculated from the RSSI readback value as outlined in the
RSSI/AGC Section.

Battery Voltage ADCIN/Temperature Sensor Readback

The battery voltage is measured at Pin VDD4. The readback
information is contained in Bits RV1 to RV7. This also applies
for the readback of the voltage at the ADCIN pin and the
temperature sensor. From the readback information, the battery
or ADCIN voltage can be determined using

V

= (Battery_Voltage_Readback)/21.1

BATTERY

V

= (ADCIN_Voltage_Readback)/42.1

ADCIN

Silicon Revision Readback

The silicon revision readback word is valid without setting any
other registers, especially directly after power-up. The silicon
revision word is coded with four quartets in BCD format. The
product code (PC) is coded with two quartets extending from
Bits RV9 to RV16. The revision code (RV) is coded with two
quartets extending from Bits RV1 to RV8. The product code
should read back as PC = #20h. The current revision code
should read as RC = #30h.

Filter Calibration Readback

The filter calibration readback word is contained in Bits RV1 to
RV8, and is for diagnostic purposes only. Using the automatic
filter calibration function, accessible through Register 6, is
recommended.

READBACK MODE

AFC READBACK

RSSI READBACK

BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK

SILICON REVISION

FILTER CAL READBACK

DB15

RV16

X

X

RV16

0

DB14

RV15

X

X

RV15

0

DB13

RV14

X

X

RV14

0

READBACK VALUE

DB12

DB11

DB10

DB9

RV13

RV12

RV11

RV10

X

X

LG2

LG1

X

X

X

X

RV13

RV12

RV11

RV10

0

0

0

0

Figure 25. Readback Value Table

Rev. PrH | Page 24 of 40

DB8

RV9

FG2

X

RV9

0

DB7

RV8

FG1

X

RV8

RV8

DB6

RV7

RV7

RV7

RV7

RV7

DB5

RV6

RV6

RV6

RV6

RV6

DB4

RV5

RV5

RV5

RV5

RV5

DB3

RV4

RV4

RV4

RV4

RV4

DB2

RV3

RV3

RV3

RV3

RV3

DB1

RV2

RV2

RV2

RV2

RV2

DB0

RV1

RV1

RV1

RV1

RV1

01975-PrG-025

Preliminary Technical Data ADF7020

REGISTER 0—N REGISTER

DB15

DB14

M11

M12

N COUNTER
DIVIDE RATIO

.
.
.

15-BIT FRACTIONAL-N8-BIT INTEGER-N

DB9

DB10

M7

M13
0

0
0
.
.
.
1
1
1
1

M6

DB8

M5

...
...

...
...
...
...
...
...
...
...
...

DB12

M9

M15
0

0
0
.
.
.
1
1
1
1

DB11

M8

M14
0

0
0
.
.
.
1
1
1
1

DB13

M10

MUXOUT

DB31

M3

M3 M2 M1 MUXOUT
0 REGULATOR READY (DEFAULT)

0
0 N DIVIDER OUTPUT
0 DIGITAL LOCK DETECT
1 ANALOG LOCK DETECT
1 THREE-STATE
1 PLL TEST MODES
1

PLL

Tx/Rx

ENABLE

DB27

DB28

DB29

DB30

M1

M2

0
0
1
1
0
0
1
1

TR1

PLE1

TR1
0 TRANSMIT

PLE1 PLL ENABLE
0 PLL OFF

1 PLL ON

0

R

1
0
1
0
1
0
1 Σ-∆ TEST MODES

D

IVI

DB22

DB23

DB24

DB26

DB25

N5

N8

N7

TRANSMIT/
RECEIVE

RECEIVE1

D

R

E

U

O

P

T

N8 N7 N6 N5 N4 N3 N2 N1
031

032
.
.
.
1 253

1 254

1

N4

N6

U

T

0

0

0

1

.

.

.

.

.

.

1

1

1

1

1

1

DB16

DB20

DB21

N2

N3

1

1

0

0

.

.

.

.

.

.

1

1

1

1

1

1

DB17

DB19

DB18

N1

M13

M15

M14

1

1
0
.
.
.
0

1

1

1
0
.
.
.
1

0

1 255

0
.
.
.
1

1

1

Figure 26.

Notes:

1. The Tx/Rx bit (R0_DB27) configures the part in Tx or Rx mode and also controls the state of the internal Tx/Rx switch.

DB7

M4

M3
1

1
1
.
.
.
1
1
1
1

DB6

M3

M2
0

0
1
.
.
.
0
0
1
1

DB5

M2

DB4

M1

M1
0

1
0
.
.
.
0
1
0
1

ADDRESS

BITS

DB2

DB3

C3 (0)

C4 (0)

FRACTIONAL
DIVIDE RATIO

4
5
6
.
.
.
32764
32765
32766
32767

DB1

C2 (0)

DB0

C1 (0)

01975-PrG-026

2.

XTAL

F

OUT

(

R

Integer-N

+×=

-NFractional

.

)

15

2

Rev. PrH | Page 25 of 40

ADF7020 Preliminary Technical Data

REGISTER 1—OSCILLATOR/FILTER REGISTER

CLOCKOUT

DIVIDE

XOSC

ENABLE

DB11

DB12

X1

CL4

X1 XTAL OSC
0 OFF
1ON

VCO Band
MHz

R COUNTER

XTAL

DOUBLER

DB9

DB8

CL1

CL2

D1
0 DISABLE
1

0
0
0
.
.
.
1

DB7

D1

XTAL
DOUBLER

ENABLED

0
0
1
.
.
.
1

DB10

CL3

CL4 CL3 CL2 CL1
0
0
0
.
.
.
1

DB6

DB5

R3

R2

R3 R2 R1
0

0

0

1

.

.

.

.

.

.

1

1

0
1
0
.
.
.
1

DB16

VB1

DB15

DD2

I

CP

3.6kΩ

CP

(MA)

CURRENT

DB14

DD1

VCO BAND

DB13

V1

V1

0 866–940
1 433–470

ADJUST

DB20

VA1

0
1
.
1

VCO BIAS

DB17

DB19

DB18

VB3

VB4

VB2

VCO BIAS

CURRENT
1
0
.
1

CP2
0 0 0.3
0 1 0.9
1 0 1.5
1 1 2.1

CP1
RSET

VCO

IF FILTER BW

DB21

DB22

DB23

DB24

DB26

DB27

DB28

DB29

DB30

DB31

DB25

VA2 VA1
0 880–950

0 870–940
1 860–930
1

IR2 IR1
0 100kHz

0 150kHz
1 200kHz
1

FILTER
BANDWIDTH

0
1
0
1 NOT USED

IR2

IR1

VA2

FREQUENCY
OF OPERATION

0
1
0
1 850–920

VB4 VB3 VB2 VB1
0 0.5mA

0

0 1mA

0

.

.

1

1 8mA

ADDRESS

DB4

DB3

R1

C4 (0)

RF R COUNTER
DIVIDE RATIO

1

1

2

0

.

.

.

.

.

.

7

1

CLK

OUT

DIVIDE RATIO
OFF

2
4
.
.
.

30

BITS

DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (1)

01975-PrG-027

Figure 27.

Notes:

1. Set the VCO adjust bits (R1_DB(20:21) to 0 for normal operation.

2.

XTAL

(

+×=

F

OUT

Integer-N

R

-NFractional

.

)

15

2

Rev. PrH | Page 26 of 40

Preliminary Technical Data ADF7020

REGISTER 2—TRANSMIT MODULATION REGISTER (ASK/OOK MODE)

PA BIAS

DB31

PA2

PA2
0

1
0
1

PA1
0

0
1
1

DB30

PA1

INDEX

TxDATA

INVERT

COUNTER

DB28

DB29

IC2

DI1

IC2XIC1XMC3XMC2XMC1

DI1
0

TxDATA

1

TxDATA

PA BIAS
5µA

7µA
9µA
11µA

GFSK MOD

CONTROL

DB27

IC1

DB26

MC3

DB25

MC2

DB24

MC1

MODULATION PARAMETER POWER AMPLIFIER

DB16

DB15

DB20

DB19

DB21

DB22

DB23

D9

D8

D7

X

POWER AMPLIFIER OUTPUT LOW LEVEL

D6

D5

X

X

0

X

0

0

0

0

0

.

.

.

.

.

1

1

DB18

D4

D5

D6

.

D2

D1

.

X
.
.
.
.
.
.
1

X

X

X

0

0

0

1

1

0

.

.

.

.

1

1

DB17

D3

OOK MODE
PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm

DB14

P6

D1

D2

DB13

P5

DB11

DB12

DB10

P2

P3

P4

POWER AMPLIFIER OUTPUT HIGH LEVEL

P6

.

0

.

0

.

0

.

0

.

.

.

.

.

1

1

Figure 28.

Note:

1. See the Transmitter section for a description of how the PA bias affects power amplifier level. Default level is 9 µA.

MODULATION

SCHEME

DB9

DB8

S3

P1

S3
0

0
1
0
1

.

P2

.

X

.

0

.

0

.

1

.

.

.

.

1

1

DB7

S2

S2
0

0
0
1
1

MUTE PA

UNTIL LOCK

DB6

DB5

S1

MP1

PE1
0

1

MUTE PA UNTIL
LOCK DETECT HIGH

MP1

OFF

0

ON

1

MODULATION SCHEME

S1

FSK

0

GFSK

1

ASK

0

OOK

1

G - OOK

1

P1
X

PA OFF

0

–16.0dBm

1

–16 + 0.45dBm

0

–16 + 0.90dBm

.

.

.

.

1

13dBm

ADDRESS

PA

BITS

ENABLE

DB4

DB2

DB3

PE1

C3 (0)

C4 (0)

POWER AMPLIFIER
OFF

ON

DB1

C2 (1)

DB0

C1 (0)

01975-PrG-028

Rev. PrH | Page 27 of 40

ADF7020 Preliminary Technical Data

REGISTER 2—TRANSMIT MODULATION REGISTER (FSK MODE)

PA BIAS

PA2
0

0
1
1

Notes:

1.

STEP

.

GFSK MOD

CONTROL

INDEX

TxDATA

INVERT

COUNTER

DB24

DB26

DB27

DB28

DB29

DB30

DB31

IC2

DI1

PA2

PA1

IC2XIC1XMC3XMC2XMC1

DI1
0

TxDATA

1

TxDATA

PA BIAS

PA1

5µA

0

7µA

1

9µA

0

11µA

1

IC1

MC3

DB25

MC2

MC1

X

MODULATION PARAMETER POWER AMPLIFIER

DB16

DB15

DB21

DB22

DB23

D9

D8

D7

FOR FSK MODE,

....

D9

....

0

....

0

....

0

....

0

....

.

....

1

DB20

D6

D3
0

0
0
0
.
1

DB17

DB19

DB18

D4

D5

D3

F DEVIATION

D1

D2

PLL MODE

0

0
0
1
1
.
1

1× F

1

0

2× F

1

3× F

.

.

1

511 × F

DB14

DB13

P5

P6

D1

D2

STEP
STEP
STEP

STEP

DB11

DB12

P3

P4

POWER AMPLIFIER OUTPUT LEVEL

P6
0

0
0
0
.
.
1

DB10

P2

.
.

.
.
.
.
.
1

MODULATION

SCHEME

DB9

DB8

S3

P1

S3
0

0
0
0
1

P2

.

X

.

0

.

0

.

1

.

.

.

.

.

1

1

DB7

DB6

S2

S1

MP1
0

1

S1

S2

0

0

1

0

0

1

1

1

1

1

P1
X

0
1
0
.
.
1

MUTE PA

UNTIL LOCK

DB5

MP1

PE1
0

1

MUTE PA UNTIL
LOCK DETECT HIGH

OFF
ON

MODULATION SCHEME
FSK

GFSK
ASK
OOK
G - OOK

PA OFF
–16.0dBm
–16 + 0.45dBm
–16 + 0.90dBm
.
.
13dBm

ADDRESS

PA

BITS

ENABLE

DB4

DB2

DB3

PE1

C3 (0)

C4 (0)

POWER AMPLIFIER
OFF

ON

DB1

C2 (1)

DB0

C1 (0)

01975-PrG-029

Figure 29.

14

2/PFDF

=

PA Bias default = 9 µA.

2.

Rev. PrH | Page 28 of 40

Preliminary Technical Data ADF7020

REGISTER 2—TRANSMIT MODULATION REGISTER (GFSK/GOOK MODE)

GFSK MOD

PA BIAS

DB31

PA2

PA2
0

1
0
1

MC3
0

0
.
1

PA1
0

0
1
1

DB30

PA1

TxDATA

INVERT

DB29

DI1

DI1
0

1

PA BIAS
5µA

7µA
9µA
11µA

IC2
0

0
1
1

MC2
0

0
.
1

TxDATA
TxDATA

CONTROL

INDEX

COUNTER

DB26

DB27

DB28

IC1

IC2

MC3

INDEX_COUNTER

IC1

16

0

32

1

64

0

128

1

GFSK_MOD_CONTROL

MC1

0

0

1

1

.

.

7

1

DB25

MC2

DB24

MC1

DB23

D9

D8

D9

0

0

1

0

0

1

1

1

Notes:

1. GFSK_DEVIATION = (2

GFSK_MOD_CONTROL

× PFD)/212.

2. DR = PFD/(INDEX_COUNTER × DIVIDER_FACTOR).

3. PA Bias default = 9 µA.

MODULATION PARAMETER POWER AMPLIFIER

DB20

DB21

DB22

D8

D6

D7

...

D7

...

0

...

0

...

0

...

0

...

.

...

1

GAUSSIAN – OOK
MODE

BLEED/BUFFER OFF
OUTPUT BUFFER ON
BLEED CURRENT ON
BLEED/BUFFER ON

DB16

DB15

DB17

DB19

DB18

D2

D4

D5

D3

D2

D3

0

0

0

0

1

0

1

0

.

.

1

1

DB14

P6

D1

DIVIDER_FACTOR

D1

INVALID

0

1

1

2

0

3

1

.

.

127

1

DB11

DB13

DB12

P3

P4

P5

POWER AMPLIFIER OUTPUT LEVEL

P6
0

0
0
0
.
.
1

Figure 30.

DB10

P2

.
.

.
.
.
.
.
1

MODULATION

SCHEME

DB9

DB8

S3

P1

S3
0

0
1
0
1

.
.

.
.
.
.
.
1

DB7

S2

S2
0

0
0
1
1

P2
X

0
0
1
.
.
1

PA

ENABLE

MUTE PA

UNTIL LOCK

DB6

DB5

DB4

S1

PE1

MP1

PE1
0

1

MUTE PA UNTIL
LOCK DETECT HIGH

MP1

OFF

0

ON

1

S1

MODULATION SCHEME

0

FSK

1

GFSK

0

ASK

1

OOK

1

G - OOK

P1
X

PA OFF

0

–16.0dBm

1

–16 + 0.45dBm

0

–16 + 0.90dBm

.

.

.

.

1

13dBm

ADDRESS

BITS

DB1

DB2

DB3

C2 (1)

C3 (0)

C4 (0)

POWER AMPLIFIER
OFF

ON

DB0

C1 (0)

01975-PrG-030

Rev. PrH | Page 29 of 40

ADF7020 Preliminary Technical Data

REGISTER 3—RECEIVER CLOCK REGISTER

SEQUENCER CLOCK DIVIDE CDR CLOCK DIVIDE

DB16

DB15

DB28

DB29

DB30

DB31

DB25

IR2

IR1

SK8

SK8
0

0
.
1
1

SK7

SK5

SK6

SK7
0

0
.
1
1

SK3

...
...

0

...

0

...

.

...

1

...

1

DB20

DB21

DB22

DB23

DB24

DB26

DB27

DB17

DB19

DB18

SK3

SK4

SK2

SK2

SK1

0

1

1

0

.

.

1

0

1

1

FS8
0

0
.
1
1

DB14

FS8

FS7

SK1

SEQ_CLK_DIVIDE
1

2
.
254
255

FS7

...

0

...

0

...

.

...

1

...

1

...

DB13

FS6

FS3
0

0
.
1
1

DB12

FS5

DB11

FS4

FS2
0

1
.
1
1

DB10

FS3

FS1
1

0
.
0
1

Figure 31.

Notes:

1. Baseband offset clock frequency (BBOS_CLK) must be greater than 1 MHz and less than 2 MHz, where:

DB9

DB8

DB7

FS1

FS2

OK2

OK2
0

0
1
1

CDR_CLK_DIVIDE
1

2
.
254
255

DEMOD

BB OFFSET

CLOCK DIVIDE

DB6

DB5

BK2

OK1

BK2

BK1

0

0

0

1

1

x

OK1

DEMOD_CLK_DIVIDE

0

4

1

1

0

2

1

3

ADDRESS

BITS

CLOCK DIVIDE

DB4

DB2

DB3

BK1

C3(0)

C4(0)

BBOS_CLK_DIVIDE
4

8
16

DB1

C2(1)

DB0

C1(1)

01975-PrG-031

CLKBBOS___ =

XTAL

DIVIDECLKBBOS

2. The demodulator clock (DEMOD_CLK) must be < 12 MHz for FSK and < 6 MHz for ASK, where:

CLKDEMOD___ =

XTAL

DIVIDECLKDEMOD

3. Data/clock recovery frequency (CDR_CLK) should be within 2% of (32 × data rate), where:

CLKDEMOD

CLKCDR

_ =

_

__

DIVIDECLKCDR

Note that this might affect your choice of XTAL, depending on the desired data rate.

4. The sequencer clock (SEQ_CLK) supplies the clock to the digital receive block. It should be close to 100 kHz for FSK and close to 40 kHz for ASK:

CLKSEQ___ =

XTAL

DIVIDECLKSEQ

Rev. PrH | Page 30 of 40

Preliminary Technical Data ADF7020

REGISTER 4—DEMODULATOR SETUP REGISTER

SELECT

DB4

DS1

ADDRESS

BITS

DB2

DB3

C3(1)

C4(0)

DB1

C2(0)

DB0

C1(0)

01975-PrG-032

DB29

DB30

DB31

DEMOD MODE
0

1
2
3
4
5

DEMODULATOR LOCK SETTING POSTDEMODULATOR BW

DEMOD LOCK/

SYNC WORD MATCH

DB9

DB8

DW4

DS2
0

0
1
1

DW3

DB7

DW2

DS1
0

1
0
1

DB16

DB15

DL1

DB14

DW9

DW10

INT/LOCK PIN
–

–
OUTPUT
OUTPUT
INPUT
–

DB28

LM2
0

0
0
0
1
1

LM1
0

0
1
1
0
1

DB25

DL5

DL6

DL8

LM2

DL8
0

1
0
1
X
DL8

MODE5 ONLY

DL8
0

0
0
.
1
1

DL7

LM1

DEMOD LOCK/SYNC WORD MATCH
SERIAL PORT CONTROL – FREE RUNNING

SERIAL PORT CONTROL – LOCK THRESHOLD
SYNC WORD DETECT – FREE RUNNING
SYNC WORD DETECT – LOCK THRESHOLD
INTERRUPT/LOCK PIN LOCKS THRESHOLD
DEMOD LOCKED AFTER DL8–DL1 BITS

DL7
0

0
0
.
1
1

DL3

...
...

...
...
...
...
...

DL2

0
0
0
.
1
1

DL1

0

0

0

1

1

0

.

.

1

0

1

1

DB20

DB21

DB22

DB23

DB24

DB26

DB27

DB17

DB19

DB18

DL3

DL4

DL2

LOCK_THRESHOLD_TIMEOUT
0

1
2
.
254
255

DB13

DW8

DB12

DW7

DB11

DW6

DB10

DW5

DEMOD

DB6

DB5

DS2

DW1

DEMODULATOR
TYPE

LINEAR DEMODULATOR
CORRELATOR/DEMODULATOR
ASK/OOK
INVALID

Figure 32.

Notes :

1. The cutoff frequency of the postdemodulator filter should typically be 0.75 times the data rate.

2. Demodulator modes 1, 3, 4, and 5 are modes that can be activated to allow the ADF7020 to demodulate data-encoding schemes that have run-length constraints

greater than 7.

11

π F

3. Post_Demod_BW = 2

/DEMOD_CLK.

CUTOFF

4. For Mode 5, the timeout delay to lock threshold = (LOCK_THRESHOLD_SETTING)/SEQ_CLK, where SEQ_CLK is defined in the Register 3—Receiver Clock Register

section.

Rev. PrH | Page 31 of 40

ADF7020 Preliminary Technical Data

REGISTER 5—SYNC BYTE REGISTER

CONTROL

DB4

PL1

BITS

DB2

DB3

C3(1)

C4(0)

SYNC BYTE
LENGTH

12 BITS
16 BITS
20 BITS
24 BITS

DB1

C2(0)

DB0

C1(1)

01975-PrG-033

SYNC BYTE SEQUENCE

MATCHING

DB9

DB8

MT2
0

0
1
1

DB7

MT2

MT1
0

1
0
1

DB16

DB15

DB28

DB29

DB30

DB31

DB25

DB20

DB21

DB22

DB23

DB24

DB26

DB27

DB17

DB19

DB18

DB14

DB11

DB13

DB12

DB10

TOLERANCE

DB6

MT1

PL2
0

0
1
1

LENGTH

SYNC BYTE

DB5

PL2

PL1
0

1
0
1

MATCHING
TOLERANCE

0 ERRORS
1 ERROR
2 ERRORS
3 ERRORS

Figure 33.

Notes:

1. Sync byte detect is enabled by programming Bits R4_DB(25:23) to [010] or [011].

2. This register allows a 28-bit sync byte sequence to be stored internally. If the sync byte detect mode is selected, then the INT/LOCK pin goes high when the sync

byte has been detected in Rx mode. Once the sync word detect signal has gone high, it goes low again after nine data bits.

3. The transmitter must Tx the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.

Rev. PrH | Page 32 of 40

Preliminary Technical Data ADF7020

REGISTER 6—CORRELATOR/DEMODULATOR REGISTER

RESET

CDR

RESET

Rx

DB31

DEMOD

RESET

LNA

CAL

INVERT

RxDATA

DB21

DB22

DB23

DB24

DB26

DB27

DB28

DB29

DB30

RI1

FC9

RxDATA
INVERT

RI1

RxDATA

0

RxDATA

1

FC9

.

0

.

0

.

.

.

.

.

.

.

.

.

1

.

FC8

FC6
0

0
.
.
.
.
1

FC7

FC5
0

0
.
.
.
.
1

DB25

FC6

ML1
0

1

FC4

FC3

FC5

FILTER CAL

CA1

NO CAL

0

CALIBRATE

1

MIXER LINEARITY
DEFAULT

HIGH

FC3

FC4

0

0

0

0

.

.

.

.

.

.

.

.

1

1

FC2
0

1
.
.
.
.
1

FC2

FC1
1

0
.
.
.
.
1

MIXER

IF FILTER

LINEARITY

DB19

CA1

DB17

DB18

LI2

ML1

800µA (DEFAULT)

DB20

FC1

LI20LI10LNA BIAS

FILTER CLOCK
DIVIDE RATIO

1
2
.
.
.
.
511

CURRENT

DB16

LI1

DOT

PRODUCT

LNA MODE

DB15

DB14

LG1

DP1

DP1
0

1

LG1
0

1

DB13

TD10

DISCRIMINATOR BWIF FILTER DIVIDER

DB9

DB11

DB12

DB10

TD6

TD7

TD8

TD9

DOT PRODUCT
CROSS PRODUCT

DOT PRODUCT

LNA MODE
DEFAULT

REDUCED GAIN

DB8

TD5

DB7

TD4

DB6

TD3

DB5

TD2

DB4

TD1

Figure 34.

Notes:

1. See the FSK Correlator/Demodulator section for an example of how to determine register settings.

2. Nonadherence to correlator programming guidelines results in poorer sensitivity.

3. The filter clock is used to calibrate the IF filter. The filter clock divide ratio should be adjusted so that the frequency is 50 kHz. The formula is

XTAL/FILTER_CLOCK_DIVIDE.

4. The filter should be calibrated only when the crystal oscillator is settled. The filter calibration is initiated every time Bit R6_DB19 is set high.

3

5. Discriminator_BW = (DEMOD_CLK × K)/(800 × 10

). See the FSK Correlator/Demodulator section.

ADDRESS

BITS

DB2

DB3

C3(1)

C4(0)

DB1

C2(1)

DB0

C1(0)

01975-PrG-034

Rev. PrH | Page 33 of 40

ADF7020 Preliminary Technical Data

REGISTER 7—READBACK SETUP REGISTER

RB3
0

1

READBACK
DISABLED

ENABLED

READBACK

DB8

RB3

RB2
0

0
1
1

SELECT

DB7

DB6 DB5 DB4 DB3 DB2

RB1

READBACK MODE

0

AFC WORD

1

ADC OUTPUT

0

FILTER CAL

1

SILICON REV

ADC

MODE

CONTROL

BITS

DB1 DB0

C2(1) C1(1)

AD2
0

0
1
1

C3(1)C4(0)

ADC MODE

AD1

MEASURE RSSI

0

BATTERY VOLTAGE

1

TEMP SENSOR

0

TO EXTERNAL PIN

1

01975-PrG-035

AD1AD2RB1RB2

Figure 35.

Notes:

1. Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, the temperature sensor, and the voltage at the external pin is not

available in Rx mode, if the ASK demodulator is active or if AGC is enabled.

2. Readback of the ADC value is valid in Tx mode only if the log amp/RSSI has not been disabled through the power-down bits R8_DB10. The log amp/RSSI section is

active per default upon enabling Tx mode.

3. Readback of the AFC word is valid in Rx mode only if either the linear demodulator or the correlator/demodulator is active.

4. See the Readback Format section for more information.

Rev. PrH | Page 34 of 40

Preliminary Technical Data ADF7020

REGISTER 8—POWER-DOWN TEST REGISTER

CONTROL

C3(0)C4(1)

PLE1
(FROM REG 0)

0
0
0
0
1

BITS

DB1 DB0

C2(0) C1(0)

PD2
0

0
1
1
X

PA ENABLE

DB15 DB14 DB13 DB12 DB11

PD7

PA (Rx MODE)

PD9

PA OFF

0

PA ON

1

Tx/Rx SWITCH

PD4

DEFAULT (ON)

0

OFF

1

LR2

LR1

RSSI MODE

X

0
1

RSSI OFF
RSSI ON

X

Rx MODE

INTERNAL Tx/Rx

PD6

DEMOD ENABLE

0

DEMOD OFF

1

DEMOD ON

SWITCH ENABLE

LR2SW1

LOG AMP/

RSSI

DB10 DB9

LR1 PD6

DEMOD

PD5

0

1

ENABLE

ADC

ENABLE

DB7

DB8

PD5

ADC ENABLE
ADC OFF

ADC ON

VCO

FILTER

ENABLE

ENABLE

LNA/MIXER

DB6 DB5 DB4 DB3 DB2

PD4

FILTER ENABLE

0

FILTER OFF

1

FILTER ON

SYNTH

ENABLE

PD1PD2PD3PD4

PD3

LNA/MIXER ENABLE

0

LNA/MIXER OFF

1

LNA/MIXER ON

ENABLE

Figure 36.

Notes:

1. For a combined LNA/PA matching network, Bit R8_DB12 should always be set to 0. This is the power-up default condition.

2. It is not necessary to write to this register under normal operating conditions.

PD1
0

1
0
1
X

LOOP
CONDITION

VCO/PLL OFF
PLL ON
VCO ON
PLL/VCO ON
PLL/VCO ON

01975-PrG-036

Rev. PrH | Page 35 of 40

ADF7020 Preliminary Technical Data

REGISTER 9—AGC REGISTER

DB23

FG2

LG2
0

0
1
1

DB22

FG1

LNA

GAIN

DB21

LG2

LG1
0

1
0
1

GAIN

CONTROL

DB20

DB19

LG1

GC1

GS1
0

1

GC1
0

1

LNA GAIN
3

10
30
INVALID

AGC HIGH THRESHOLD

AGC

SEARCH

DB16

DB17

DB18

GS1

GH6

GH7

AGC SEARCH

AUTO AGC

HOLD SETTING

GAIN CONTROL
AUTO

USER

DB15

GH5

GH7
0

0
0
0
.
.
.
1
1
1

DB14

GH4

DB13

GH3

GH6
0

0
0
0
.
.
.
0
0
0

GL7
0

0
0
0
.
.
.
1
1
1

DB12

GH2

GH5
0

0
0
0
.
.
.
0
0
1

AGC LOW THRESHOLD

DB9

DB11

DB10

GL6

GL7

GH1

GL6

GL5

0

0

0

0

0

0

0

0

.

.

.

.

.

.

1

1

1

1

1

1

GH3

GH4

0

0

0

0

0

0

1

0

.

.

.

.

.

.

1

1

1

1

0

0

GL4
0

0
0
0
.
.
.
1
1
1

GH2
0

1
1
0
.
.
.
1
1
0

DB8

GL5

GL3
0

0
0
1
.
.
.
1
1
1

FILTER

CURRENT

DB24

DB25

FI1

FILTER GAIN
8

24
72
INVALID

FILTER

GAIN

DIGITAL
TEST IQ

DB26

DB27

DB28

DB29

DB30

DB31

FI1

FILTER CURRENT

0

LOW

1

HIGH

FG2

FG1

0

0

0

1

1

0

1

1

Figure 37.

Notes :

1. Default AGC_LOW_THRESHOLD = 27, default AGC_HIGH_THRESHOLD = 76. See the RSSI/AGC Section for more details.

2. AGC high and low settings must be more than 30 apart to ensure correct operation.

3. LNA gain of 30 is available only if LNA mode, R6_DB15, is set to zero.

DB7

GL4

GH1
1

0
1
0
.
.
.
0
1
0

DB6

GL3

GL1

GL2

1

0

0

1

1

1

0

0

.

.

.

.

.

.

1

0

0

1

1

1

RSSI LEVEL
CODE

1
2
3
4
.
.
.
78
79
80

DB5

GL2

ADDRESS

BITS

DB4

DB3

GL1

C4(1)

AGC LOW
THRESHOLD

1
2
3
4
.
.
.
61
62
63

DB2

C3(0)

DB1

C2(0)

DB0

C1(1)

01975-PrG-037

Rev. PrH | Page 36 of 40

Preliminary Technical Data ADF7020

REGISTER 10—AGC 2 REGISTER

I/Q PHASE

I/Q

ADJUST

SELECT

DB24

DB26

DB27

DB28

DB29

DB30

DB31

SIQ2

SIQ2

SELECT IQ

0

PHASE TO I CHANNEL

1

PHASE TO Q CHANNEL

DB25

PH2

PH1

PH3

PH4

I/Q

SELECT

RESERVED

DB22

DB23

R1

SIQ1

SIQ2

SELECT IQ

0

GAIN TO I CHANNEL

1

GAIN TO Q CHANNEL

UP/DOWN

DB21

UD1

DB20

GC5

Note:

1. This register is not used under normal operating conditions.

REGISTER 11—AFC REGISTER

AFC ENABLE

DB20

DB21

DB22

DB23

DB24

DB26

DB27

DB28

DB29

DB30

DB31

DB25

AE1

DB19

GC4

DB19

M16

DB18

GC3

DB18

M15

DB16

DB17

GC1

GC2

Figure 38.

DB16

DB17

M13

M14

AGC DELAYI/Q GAIN ADJUST LEAK FACTOR

DB13

DH2

DB11

DB12

GL7

DH1

DEFAULT = 10

DB10

GL6

DB15

DB14

DH4

DH3

DEFAULT = 10 DEFAULT = 2

DB9

GL5

DB8

GL4

PEAK RESPONSE

DB7

PR4

AFC SCALING COEFFICIENT

DB9

DB8

M6

M5

DB7

M4

DB15

DB14

M11

M12

DB11

DB13

DB12

DB10

M7

M8

M9

M10

DB6

PR3

DB6

M3

DB5

PR2

DB5

M2

DB4

PR1

DB4

M1

ADDRESS

BITS

DB2

DB3

C3 (0)

C4 (1)

CONTROL

BITS

DB2

DB3

C3(0)

C4(0)

DB1

C2 (1)

DB1

C2(1)

DB0

C1 (0)

DB0

C1(0)

01975-PrG-038

INTERNAL
AFC

AE1

OFF

0

ON

1

Figure 39.

Notes:

1. See the Internal AFC section to program AFC scaling coefficient bits.

2. The AFC scaling coefficient bits can be programmed using the following formula:

AFC_Scaling_Coefficient = Round((500 × 2

24

)/XTAL)

01975-PrG-039

Rev. PrH | Page 37 of 40

ADF7020 Preliminary Technical Data

REGISTER 12—TEST REGISTER

ANALOG TEST

PRESCALER

DB31

PRE

P
0

1

MUX IMAGE FILTER ADJUST

DB29

DB30

PRESCALER
4/5 (DEFAULT)

8/9

FORCE

LD HIGH

SOURCE

OSC TEST

DB20

DB19

SF3

SF2

DB18

SF1

DB28

DB25

QT1

CS1

CAL SOURCE

0

INTERNAL

1

SERIAL IF BW CAL

SF6

SF5

CS1

SF4

DEFAULT = 32. INCREASE
NUMBER TO INCREASE BW
IF USER CAL ON

DB21

DB22

DB23

DB24

DB26

DB27

Using the Test DAC on the ADF7020 to Implement
Analog FM DEMOD and Measuring SNR

The test DAC allows the output of the postdemodulator filter
for both the linear and correlator/demodulators (Figure 16 and
Figure 17) to be viewed externally. It takes the 16-bit filter
output and converts it to a high frequency, single-bit output
using a second-order error feedback
can be viewed on the XCLK

OUT

Σ-∆ converter. The output

pin. This signal, when IF filtered

appropriately, can then be used to

• Monitor the signals at the FSK/ASK postdemodulator filter

output. This allows the demodulator output SNR to be
measured. Eye diagrams can also be constructed of the
received bit stream to measure the received signal quality.

•

Provide analog FM demodulation.

While the correlators and filters are clocked by DEMOD_CLK,
CDR_CLK clocks the test DAC. Note that, although the test
DAC functions in a regular user mode, the best performance is
achieved when the CDR_CLK is increased up to or above the
frequency of DEMOD_CLK. The CDR block does not function
when this condition exists.

DIGITAL

TEST MODES

DB16

DB15

DB17

Figure 40.

RESET

COUNTER

DB14

DB13

CR1
0

1

Σ-∆

TEST MODES

DB11

DB12

DB10

T7

T8

T9

COUNTER RESET
DEFAULT

RESET

PLL TEST MODES

DB9

DB8

T5

T6

DB7

T4

DB6

T3

DB5

T2

DB4

T1

ADDRESS

BITS

DB2

DB3

C3(1)

C4(1)

DB1

C2(0)

DB0

C1(0)

01975-PrG-043

Programming the test register, Register 12, enables the test DAC.
Both the linear and correlator/demodulator outputs can be
multiplexed into the DAC.

Register 13 allows a fixed offset term to be removed from the
signal (to remove the IF component in the ddt case). It also has
a signal gain term to allow the usage of the maximum dynamic
range of the DAC.

Setting Up the Test DAC

• Digital test modes = 7: enables the test DAC, with no offset

removal.

• Digital test modes = 10: enables the test DAC, with offset

removal.

The output of the active demodulator drives the DAC, that is, if
the FSK correlator/demodulator is selected, the correlator filter
output drives the DAC.

Rev. PrH | Page 38 of 40

Preliminary Technical Data ADF7020

REGISTER 13—OFFSET REMOVAL AND SIGNAL GAIN REGISTER

DB4

CONTROL

BITS

DB2

DB3

C3(1)

C4(1)

DB1

C2(0)

DB0

C1(1)

01975-PrG-044

PULSE

EXTENSIONTEST DAC GAIN TEST DAC OFFSET REMOVAL

DB9

DB16

DB15

DB28

DB29

DB30

DB31

DB25

PE4

PE3

0

0

0

0

0

0

.

.

.

.

.

.

1

1

DB20

DB21

DB22

DB23

DB24

DB26

DB27

DB17

DB19

DB18

PE2

PE1

0

0

0

1

1

0

.

.

.

.

.

.

1

1

DB14

DB13

PE2

PE3

PE4

PULSE EXTENSION
NORMAL PULSE WIDTH

2 × PULSE WIDTH
3 × PULSE WIDTH
.
.
.
16 × PULSE WIDTH

DB12

PE1

DB11

DB8

DB10

DB7

KPKI

DB6

DB5

Figure 41.

Note:

1. Because the linear demodulator’s output is proportional to frequency, it usually consists of an offset combined with a relatively low signal. The offset can be

removed, up to a maximum of 1.0 and gained to use the full dynamic range of the DAC:

DAC_input = (2^ Test_DAC_Gain) × (Signal − Test_DAC_Offset_Removal/4096)

Rev. PrH | Page 39 of 40

ADF7020 Preliminary Technical Data

OUTLINE DIMENSIONS

0.25 MIN

37

36

48

1

PIN 1
INDICATOR

0.25
MIN

1.50

1.45

1.40

SEATING
PLANE

TOP

VIEW

0.35

0.20

0.25

7.00

BSC SQ

0.05 MAX

0.02 NOM

COPLANARITY

0.05

0.50

BSC

0.55

0.50

0.45

BOTTOM

VIEW

25

5.50BSC

5.25

4.70 SQ

2.25

12

1324

Figure 42. 48-Lead Micro Lead Frame Chip Scale Package [MLFCSP]

(CP-48M)

7 mm × 7 mm Body

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF7020BCP −40°C to +85°C 48-Lead Micro Lead Frame Chip Scale Package [MLFCSP] CP-48M

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

PR01975–0–6/04(PrH)

Rev. PrH | Page 40 of 40