Analog Devices ADF7020 prh Datasheet

High Performance ISM Band

A

Preliminary Technical Data

FEATURES

Low power, low IF transceiver
Frequency bands:

433 MHz to 464 MHz
862 MHz to 928 MHz

Data rates supported:

0.3 kbps to 200 kbps, FSK

0.3 kbps to 64 kbps, ASK

2.3 V to 3.6 V power supply
Programmable output power:

−16 dBm to +13 dBm in 0.3 dBm steps

Receiver sensitivity:

−117.5 dBm at 1 kbps, FSK

−110.5 dBm at 9.6 kbps, FSK

−106.5 dBm at 9.6 kbps, ASK

Low power consumption:

19 mA in receive mode
22 mA in transmit mode (10 dBm output)

FSK/ASK Transceiver IC

ADF7020

On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
±1 ppm RF output frequency accuracy possible from

low cost 100 ppm crystal
Digital RSSI
Leakage current <1 µA in power-down mode
48-lead ultrasmall MLF package (chip scale)

APPLICATIONS

Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice

FUNCTIONAL BLOCK DIAGRAM

MUXOUTADCINRSET VREG(1:4)

RFINB

P

R

LNA

RFIN

OUT

BIAS LDO(1:4)

LNA

GAIN

DIVIDERS/

MUXING

ASK/OOK

MOD CONTROL

GAUSSIAN FILTER

IF FILTER

FSK MOD

CONTROL

VCO

VCOIN CPOUT

OFFSET

CORRECTION

RSSI

OFFSET

CORRECTION

GAUSSIAN

FILTER

CP

MODULATOR

N/N+1DIV P

PFD

TEMP

SENSOR

MUX

Σ-∆

DIV R

7-BIT ADC

Figure 1.

TEST MUX

DEMODULATOR

CONTROL

CONTROL

RING
OSC

OSC

FSK/ASK

AGC

AFC

CLK

DIV

SYNCHRONIZER

CONTROL

OUT

CLK

DATA

Tx/Rx

SERIAL

PORT

CE
RxCLK
Tx/Rx DATA
CLKOUT
INT/LOCK

SLE
SDATA IN
SDATA OUT
SCLK

01975-PrG-001

Rev. PrH

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Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF7020 Preliminary Technical Data

TABLE OF CONTENTS

General Description......................................................................... 3

Device Programming after Initial Power-Up ......................... 22

Specifications..................................................................................... 4

Timing Characteristics..................................................................... 7

Absolute Maximum Ratings............................................................ 8

ESD Caution.................................................................................. 8

Pin Configuration and Function Descriptions............................. 9

Frequency Synthesizer ................................................................... 11

Reference Input Section............................................................. 11

Choosing Channels for Best System Performance................. 13

Transmitter ...................................................................................... 14

Modulation Schemes.................................................................. 14

Receiver Section.............................................................................. 16

RF Front End............................................................................... 16

RSSI/AGC Section...................................................................... 17

FSK Demodulators on the ADF7020....................................... 17

FSK Correlator/Demodulator................................................... 17

Linear FSK Demodulator.......................................................... 19

AFC Section ................................................................................ 19

Automatic Sync Word Recognition.......................................... 20

Applications Section....................................................................... 21

LNA/PA Matching...................................................................... 21

Transmit Protocol and Coding Considerations ..................... 22

Image Rejection Calibration .....................................................22

Serial Interface................................................................................ 24

Readback Format........................................................................ 24

Register 0—N Register............................................................... 25

Register 1—Oscillator/Filter Register...................................... 26

Register 2—Transmit Modulation Register (ASK/OOK

........................................................................................... 27

Mode)

Register 2—Transmit Modulation Register (FSK Mode) ..... 28

Register 2—Transmit Modulation Register (GFSK/GOOK

........................................................................................... 29

Mode)

Register 3—Receiver Clock Register ....................................... 30

Register 4—Demodulator Setup Register............................... 31

Register 5—Sync Byte Register................................................. 32

Register 6—Correlator/Demodulator Register ...................... 33

Register 7—Readback Setup Register...................................... 34

Register 8—Power-Down Test Register .................................. 35

Register 9—AGC Register......................................................... 36

Register 10—AGC 2 Register.................................................... 37

Register 11—AFC Register ....................................................... 37

Register 12—Test Register......................................................... 38

Register 13—Offset Removal and Signal Gain Register ....... 39

Outline Dimensions....................................................................... 40

Ordering Guide .......................................................................... 40

REVISION HISTORY

Revision PrH: Preliminary Version

Rev. PrH | Page 2 of 40

Preliminary Technical Data ADF7020

GENERAL DESCRIPTION

The ADF7020 is a low power, highly integrated FSK/GFSK/
ASK/OOK/GASK transceiver designed for operation in the
license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It
is suitable for circuit applications that meet either the European
ETSI-300-220 or the North American FCC (Part 15) regulatory
standards. A complete transceiver can be built using a small
number of external discrete components, making the ADF7020
very suitable for price-sensitive and area-sensitive applications.

The transmit section contains a VCO and low noise
fractional-N PLL with output resolution of <1 ppm. The VCO
operates at twice the fundamental frequency to reduce spurious
emissions and frequency pulling problems.

The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.

A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application. The
receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.

An on-chip ADC provides readback of an integrated tempera­ture sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some
applications. The temperature sensor is accurate to ±5°C over
the full operating temperature range of −40°C to +85°C.

Rev. PrH | Page 3 of 40

ADF7020 Preliminary Technical Data

SPECIFICATIONS

VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T
Typical specifications are at V

= 3 V, TA = 25°C.

DD

All measurements are performed using the test circuit in Figure TBD using PN9 data sequence, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions

RF CHARACTERISTICS

Frequency Ranges 862 928 MHz

Frequency Ranges (Divide-by-2 Mode) 433 464 MHz

Phase Frequency Detector Frequency RF/256 20 MHz
TRANSMISSION PARAMETERS

Data Rate FSK/GFSK 0.3 200 kbps

Data Rate OOK/ASK 0.3 64

Frequency Shift Keying

GFSK/FSK Frequency Deviation

4.88 620 kHz PFD = 20 MHz
Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Adjacent Channel Power, GFSK TBD dBc

−50 dBc

Amplitude Shift Keying

ASK Modulation Depth 30 dB

OOK –PA Off Feedthrough −50 dBm
Transmit Power4 −20 +13 dBm FRF = 915 MHz, VDD = 3.0 V, TA = 25°C
TBD dBm FRF = 868 MHz, VDD = 3.0 V, TA = 25°C
TBD dBm FRF = 433 MHz, VDD = 3.0 V, TA = 25°C
Transmit Power Variation

Highest Power Setting TBD dBm FRF = 915 MHz, VDD = 3.6 V

13 dBm FRF = 915 MHz, VDD = 3.0 V
TBD dBm FRF = 915 MHz, VDD = 2.3 V

Transmit Power Flatness TBD dB From 902 MHz to 928 MHz
Programmable Step Size

−20 dBm to +13 dBm 0.3125 dB

Spurious Emissions during PLL Settling −57 dBm Mute PA until lock enabled (R2_DB5 =1 )

Integer Boundary −55 dBc 50 kHz loop BW

Reference −65 dBc
Harmonics

Second Harmonic −27 −18 dBc

Third Harmonic −21 −18 dBc

All Other Harmonics −35 dBc
VCO Frequency Pulling, OOK mod TBD kHz rms DR = 9.6 kbps
Optimum PA Load Impedance

5

TBD Ω FRF = 868 MHz
TBD Ω FRF = 433 MHz

RECEIVER PARAMETERS

FSK Input Sensitivity6 At BER = 1E − 3, FRF = 915 MHz

High Sensitivity Mode −117.5 dBm DR = 1 kbps, F

Low Current Mode −TBD dBm DR = 1 kbps, F

See notes at end of table.

to T

MIN

2, 3

, unless otherwise noted.

MAX

1

kbps

1 110 kHz PFD = 3.625 MHz

Channel spacing = 25 kHz, measured in
adjacent channel ± 8.5 kHz from center;
DR = 4.8 kbps, F

= 2.4 kHz,

DEV

FRF = 868 MHz

868.95 MHz ± 250 kHz, DR = 38.4 kbps,
= 19.2 kHz

F

DEV

TBD Ω FRF = 915 MHz

= 5 kHz

DEV

= 5 kHz

DEV

Rev. PrH | Page 4 of 40

Preliminary Technical Data ADF7020

Parameter Min Typ Max Unit Test Conditions

High Sensitivity Mode −110.5 dBm DR = 9.6 kbps, FDEV = 10 kHz
Low Current Mode −104 dBm DR = 9.6 kbps, FDEV = 10 kHz
High Sensitivity Mode −99 dBm DR = 200 kbps, FDEV = 50 kHz
Low Current Mode −TBD dBm DR = 200 kbps, FDEV = 50 kHz

OOK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz

High Sensitivity Mode −TBD dBm DR = 1 kbps
Low Current Mode −TBD dBm DR = 1 kbps
High Sensitivity Mode −106.5 dBm DR = 9.6 kbps

Low Current Mode −TBD dBm DR = 9.6 kbps
LNA and Mixer
Input IP3

Rx Spurious Emissions

−47 dBm >1 GHz at antenna input
AFC

Channel Filtering
Adjacent Channel Rejection

Second Adjacent Channel Rejection

Third Adjacent Channel Rejection

Image Channel Rejection 30 dB Uncalibrated

Co-channel Rejection −3 dB
Wide-Band Interference Rejection TBD dB

Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10
Input Impedance TBD Ω FRF = 915 MHz, RFIN, RFIN to GND
TBD Ω FRF = 868 MHz
TBD Ω FRF = 433 MHz
RSSI

PHASE LOCKED LOOP

VCO Gain 65 MHz/V

130 MHz/V

TBD MHz/V At 433MHz, VCO Adjust = 0
Phase Noise (In-Band) −92 dBc/Hz

Phase Noise (Out-of-Band) −110 dBc/Hz At 1 MHz offset
Residual FM TBD Hz From 300 Hz to 5 kHz

See notes at end of table.

7

Enhanced Linearity Mode 6.8 dBm Pin = −20 dBm, 2 CW interferers
Low Current Mode −3.2 dBm FRF = 915 MHz, f1 = FRF + 3 MHz
High Sensitivity Mode −35 dBm F2 = FRF + 6 MHz, maximum gain

8

−57 dBm <1 GHz at antenna input

Pull-In Range ±50 kHz IF_BW = 200 kHz
Response time TBD Bits
Accuracy 1 TBD kHz

27 dB

(Offset = ±1 × IF Filter BW Setting)

50 dB

(Offset = ±2 × IF Filter BW Setting)

TBD dB

(Offset = ±3 × IF Filter BW Setting)

(Image Channel = FRF − 400 kHz) TBD dB Calibrated

IF filter BW settings = 100 kHz, 150 kHz,
200 kHz

Desired signal 3 dB above the input
sensitivity level, CW interferer power
level increased until BER = 10

−3

, image

channel excluded

9

Swept from 100 MHz to 2 GHz, measured
as channel rejection

−3

Range at Input −100 to −36 dBm
Linearity ±3 dB
Absolute Accuracy TBD dB
Response Time 350 µs

Maximum input step change, AGC
included, RSSI ready for readback

902 MHz to 928 MHz band.,
VCO adjust = 0

860MHz to 870 MHz band,
VCO Adjust = 0

PA = 0 dBm, V

= 3.0 V, PFD = 10 MHz,

DD

FRF = 915 MHz, VCO BIAS = 4

Rev. PrH | Page 5 of 40

ADF7020 Preliminary Technical Data

Parameter Min Typ Max Unit Test Conditions

PLL Settling Time 40 µs

REFERENCE INPUT

Crystal Reference 3.625 24 MHz
External Oscillator 3.625 24 MHz
Load capacitance TBD pF

Input Level

CMOS
levels

TIMING INFORMATION

Chip Enabled to Regulator Ready TBD µs C
Crystal Oscillator Startup time 1 ms With 19.2 MHz XTAL
Tx to Rx Turnaround Time

LOGIC INPUTS

V

Input High Voltage 0.7 × V DD V

INH,

V

, Input Low Voltage 0.2 × V

INL

I

Input Current ±1 µA

INH/IINL,

350 µs +
(5 × T

)

BIT

V

DD

CIN, Input Capacitance 10 pF
Control Clock Input 50 MHz

LOGIC OUTPUTS

VOH,Output High Voltage

DV

DD

V I

−

0.4
VOL, Output Low Voltage 0.4 V IOL = 500 µA
CLK

Rise/Fall 5 ns

OUT

CLK

Load 10 pF

OUT

TEMPERATURE RANGE—TA −40 +85 °C
POWER SUPPLIES

Voltage Supply

AV
DV

DD

DD

2.3 3.6 V

AV

DD

AV

DD

Transmit Current Consumption

−20 dBm TBD mA

−10 dBm 12 mA VCO_BIAS_SETTING = 3
0 dBm 15 mA
10 dBm 22 mA

Receive Current Consumption

Low Current Mode 19 TBD mA
High Sensitivity Mode 21 TBD mA

Power-Down Mode

Low Power Sleep Mode

0.1 1 µA

1

Higher data rates are achievable depending on local regulations.

2

For definition of frequency deviation, see the R section. egister 2—Transmit Modulation Register (FSK Mode)

3

For definition of GFSK frequency deviation, see the R section. egister 2—Transmit Modulation Register (GFSK/GOOK Mode)

4

Measured as maximum unmodulated power. Output power varies with both supply and temperature.

5

For matching details, see the LN section. A/PA Matching

6

See Table 5 for description of different receiver modes.

7

See Table 5 for description of different receiver modes.

8

Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.

9

See the section. Image Rejection Calibration

Measured for a 10 MHz frequency step to
within 5 ppm accuracy,
PFD = 20 MHz, LBW = TBD

See the Reference Input Section

= 100 nF

REG

Time to synchronized data, includes AGC
settling

= 500 µA

OH

FRF = 915 MHz, V

= 3.0 V, PA is matched

DD

in to 50 Ω

Rev. PrH | Page 6 of 40

Preliminary Technical Data ADF7020

A

TIMING CHARACTERISTICS

VDD = 3 V ± 10%; VGND = 0 V, TA = 25°C, unless otherwise noted.
Guaranteed by design, but not production tested.

Table 2.

Parameter Limit at T

t

1

<10 ns SDATA to SCLK Setup Time

t2 <10 ns SDATA to SCLK Hold Time

t3 <25 ns SCLK High Duration

t4 <25 ns SCLK Low Duration

t5 <10 ns SCLK to SLE Setup Time

t6 <20 ns SLE Pulse Width

t

7

t

8

t

9

t

10

<TBD ns SLE to SCLK Setup Time, Readback

<TBD ns SCLK to SREAD Data Valid, Readback

<TBD ns SREAD Hold Time after SCLK, Readback

<TBD ns SCLK to SLE Disable Time, Readback

MIN

to T

MAX

Unit Test Conditions/Comments

SCLK

SDAT

SLE

t

1

DB31 (MSB) DB30 DB2

t

1

SCLK

SDATA

REG7 DB0

(CONTROL BIT C1)

SLE

t

3

t

2

t

2

t

3

t

4

DB1

(CONTROL BIT C2)

Figure 2. Serial Interface Timing Diagram

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

01975-PrG-002

t

10

SREAD

t

X RV16 RV15 RV2 RV1

t

8

9

Figure 3. Readback Timing Diagram

01975-PrG-003

Rev. PrH | Page 7 of 40

ADF7020 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 125°C
MLF θJA Thermal Impedance
Lead Temperature Soldering

Vapor Phase (60 s) 235°C
Infrared (15 s) 240°C

1

−0.3 V to +5 V

TBD°C/W

1

GND = CPGND = RFGND = DGND = AGND = 0 V.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high-performance RF integrated circuit with an
ESD rating of <2 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

Rev. PrH | Page 8 of 40

Preliminary Technical Data ADF7020

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

CVCO

GND1

GND

VCO GND

GND

VDD

CPOUT

VREG3

VDD3

OSC1

OSC2

MUXOUT

VCOIN

VREG1

VDD1
RFOUT
RFGND

RFIN

RFINB

R

LNA

VDD4

RSET

VREG4

GND4

4847464544434241403938

PIN 1

1

INDICATOR

2
3
4
5
6
7
8
9

10

11

12

ADF7020

TOP VIEW

(Not to Scale)

37

36

CLKOUT

35

DATA CLK

34

DATA I/O
INT/LOCK

33

VDD2

32

VREG2

31

ADCIN

30

GND2

29

SCLK

28

SREAD

27

SDATA

26

SLE

25

1314151617181920212223

MIX_I

MIX_I

MIX_Q

GND4

FILT_I

FILT_I

MIX_Q

FILT_Q

GND4

FILT_Q

24

CE

TEST_A

01975-PrG-004

Figure 4. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 VCOIN

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.

2 VREG1

Regulator Voltage for PA Block. A 100 nF capacitor should be placed between this pin and ground for
regulator stability and noise rejection.

3 VDD1

Voltage Supply for PA Block. Decoupling capacitors (X7R or Tantalum) of 0.1 µF and 0.01 µF should be placed
as close as possible to this pin.

4 RFOUT

The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The output

should be impedance matched to the desired load using suitable components. See the Transmitter section.
5 RFGND Ground for Output Stage of Transmitter.
6 RFIN

LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA

input to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 R

External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.

LNA

9 VDD4 Voltage supply for LNA/MIXER block. This pin should be decoupled to ground with a 0.01 µF capacitor.
10 RSET External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5% tolerance.
11 VREG4

Regulator Voltage for LNA/MIXER block. A 100 nF capacitor should be placed between this pin and GND for

regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER block.
13–18 MIX/FILT

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.
19, 22 GND4 Ground for LNA/MIXER block.
20, 21, 23 FILT/TEST_A

Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left

unconnected.
24 CE

Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when CE

is low, and the part must be reprogrammed once CE is brought high.
25 SLE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches. A latch is selected using the control bits.
26 SDATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high

impedance CMOS input.
27 SREAD

Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The SCLK

input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
28 SCLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.

Rev. PrH | Page 9 of 40

ADF7020 Preliminary Technical Data

Pin No. Mnemonic Function

29 GND2 Ground for Digital Section.
30 ADCIN

31 VREG2

32 VDD2

33 INT/LOCK

34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin and normal CMOS levels apply.
35 DATA CLK

36 CLKOUT

37 MUXOUT

38 OSC2

39 OSC1 The reference crystal should be connected between this pin and OSC2.
40 VDD3

41 VREG3

42 CPOUT

43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
44–47 GND Grounds for VCO Block.
48 CVCO A 22 nF capacitor should be placed between this pin and VREG1 to reduce VCO noise.

Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 to

1.9 V. Readback is made using the SREAD pin.
Regulator Voltage for Digital Block. A 100 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.
Voltage Supply for Digital Block. A decoupling capacitor (X7R or Tantalum) of 0.01 µF should be placed as

close as possible to this pin.
Bidirectional Pin. In output mode (INTerrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has found

a match for the preamble sequence.
In input mode (lock mode), the microcontroller can be used to lock the demodulator threshold when a valid

preamble has been detected. Once the threshold is locked, NRZ data can be reliably received. In this mode, a
demod lock can be asserted with minimum delay.

In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data.

In GFSK transmit mode, the pin outputs an accurate clock to latch the data from the microcontroller into the
transmit section at the exact required data rate. See the Gaussian Frequency Shift Keying (GFSK) section.

A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to
drive several other CMOS inputs such as a microcontroller clock. The output has a 50:50 mark-space ratio.

This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
regulator.

The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.

Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a

0.01 µF capacitor.
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF capacitor should be placed between this pin

and ground for regulator stability and noise rejection.
Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The

integrated current changes the control voltage on the input to the VCO.

Rev. PrH | Page 10 of 40

Preliminary Technical Data ADF7020

A

T

FREQUENCY SYNTHESIZER

REFERENCE INPUT SECTION

The on-board crystal oscillator circuitry (Figure 5) can use an
inexpensive quartz crystal as the PLL reference. The oscillator
circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC Section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.

R Counter

The 3-bit R counter divides the reference input frequency by an
integer from 1 to 7. The divided-down signal is presented as the
reference clock to the phase frequency detector (PFD). The
divide ratio is set in Register 1. Maximizing the PFD frequency
reduces the N value. This reduces the noise multiplied at a rate
of 20 log(N) to the output, as well as reducing occurrences of
spurious components. The R Register defaults to R = 1 on
power-up:

PFD [Hz] = XTAL/R

MUXOUT and Lock Detect

OSC1

Figure 5. Oscillator Circuit on the ADF7020

OSC2

CP1CP2

01975-PrG-005

Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. Track capacitance
values vary from 2 pF to 5 pF, depending on board layout.
Where possible, choose capacitors that have a very low
temperature coefficient to ensure stable frequency operation
over all conditions.

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 5, and supplies a divided­down 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB(8:11). On power-up, the CLKOUT defaults to
divide-by-8.

DV

DD

CLK

OUT

ENABLE BIT

OSC1

DIVIDER

1 TO 15

÷2

Figure 6. CLK

OUT

Stage

CLK

OUT

01975-PrG-006

To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at F

CLK

.

The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB(29:31).

Regulator Ready

REGULATOR READY is the default setting on MUXOUT after
the transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is
powered from the regulator, the regulator must be at its nominal
voltage before the ADF7020 can be programmed. The status of
the regulator can be monitored at MUXOUT. When the
REGULATOR READY signal on MUXOUT is high,
programming of the ADF7020 can begin.

DV

DD

REGULATOR READY

DIGITAL LOCK DETECT

NALOG LOCK DETEC

R COUNTER OUTPUT
N COUNTER OUTPUT

PLL TEST MODES

Σ-∆ TEST MODES

MUX CONTROL

Figure 7. MUXOUT Circuit

DGND

MUXOUT

01975-PrG-007

Digital Lock Detect

Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.

Rev. PrH | Page 11 of 40

ADF7020 Preliminary Technical Data

Analog Lock Detect

This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low-going pulses.

Voltage Regulators

The ADF7020 contains four regulators to supply stable voltages
to the part. The nominal regulator voltage is 2.3 V. Each
regulator should have a 100 nF capacitor connected between
VREG and GND. When CE is high, the regulators and other
associated circuitry are powered on, drawing a total supply
current of 2 mA. Bringing the chip-enable pin low disables the
regulators, reduces the supply current to less than 1 µA, and
erases all values held in the registers. The serial interface
operates off a regulator supply; therefore, to write to the part,
the user must have CE high and the regulator voltage must be
stabilized. Regulator status (VREG4) can be monitored using
the regulator ready signal from MUXOUT.

Loop Filter

For GFSK, it is recommended that an LBW of 2.0 to 2.5 times
the data rate be used to ensure that sufficient samples are taken
of the input data while filtering system noise. The free design
tool ADIsimPLL can be used to design loop filters for the
ADF7020.

N Counter

The feedback divider in the ADF7020 PLL consists of an 8-bit
integer counter and a 14-bit Σ-∆ fractional-N divider. The
integer counter is the standard pulse-swallow type common in
PLLs. This sets the minimum integer divide value to 31. The
fractional divide value gives very fine resolution at the output,
where the output frequency of the PLL is calculated as

F

REFERENCE IN

OUT

=

4R

XTAL

R

CHARGE

PFD/

PUMP

× (Integer-N +

-NFractional

)

14

2

VCO

The loop filter integrates the current pulses from the charge
pump to form a voltage that tunes the output of the VCO to the
desired frequency. It also attenuates spurious levels generated by
the PLL. A typical loop filter design is shown in Figure 8.

CHARGE

PUMP OUT

Figure 8. Typical Loop Filter Configuration

VCO

01975-PrG-008

In FSK, the loop should be designed so that the loop bandwidth
(LBW) is approximately five times the data rate. Widening the
LBW excessively reduces the time spent jumping between
frequencies, but can cause insufficient spurious attenuation.

For ASK systems, a wider LBW is recommended. The sudden
large transition between two power levels might result in VCO
pulling and can cause a wider output spectrum than is desired.
By widening the LBW to more than 10 times the data rate, the
amount of VCO pulling is reduced, because the loop settles
quickly back to the correct frequency. The wider LBW might
restrict the output power and data rate of ASK-based systems
compared with FSK-based systems.

Narrow-loop bandwidths can result in the loop taking long
periods of time to attain lock. Careful design of the loop filter is
critical to obtaining accurate FSK/GFSK modulation.

4N

THIRD-ORDER

Σ-∆ MODULATOR

INTEGER-NFRACTIONAL-N

Figure 9. Fractional-N PLL

01975-PrG-009

The combination of the integer-N (maximum = 255) and the
fractional-N (maximum = 16383/16384) give a maximum N
divider of 255 + 1. Therefore, the minimum usable PFD is

PDF

[Hz] = Maximum Required Output Frequency/(255 + 1)

MIN

For example, when operating in the European 868 MHz to
870 MHz band, PFD

equals 3.4 MHz.

MIN

Voltage Controlled Oscillator (VCO)

To minimize spurious emissions, the on-chip VCO operates
from 1732 MHz to 1856 MHz. The VCO signal is then divided
by 2 to give the required frequency for the transmitter and the
required LO frequency for the receiver.

The VCO should be recentered, depending on the required
frequency of operation, by programming the VCO adjust bits
R1_DB(20:21).

The VCO is enabled as part of the PLL by the PLL-enable bit,
R0_DB28.

A further frequency divide-by-2 is included to allow operation
in the lower 433 MHz and 460 MHz bands. To enable operation
in the these bands, R1_DB13 should be set to 1. The VCO needs
an external 22 nF between the VCO and the regulator to reduce
internal noise.

Rev. PrH | Page 12 of 40