FSK/ASK Transceiver IC
Data Sheet
ADF7020
Rev. D
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Tx/Rx
CONTROL
AGC
CONTROL
FSK/ASK
DEMODULATOR
DATA
SYNCHRONIZER
RSSI
7-BIT ADC
GAIN
DIV R
SERIAL
PORT
RFOUT
OFFSET
CORRECTION
OFFSET
CORRECTION
LNA
VCO
PFD
CP
AFC
CONTROL
OSC1
OSC2
DIVIDERS/
MUXING
N/N + 1DIV P
MUX
TEMP
SENSOR
OSC
CLK
DIV
CLKOUT
TEST MUX
VCOIN CPOUT
LDO(1:4)
MUXOUTADCINRSET CREG[1:4]
R
LNA
RFIN
RFINB
SLE
SDATA
CE
DATA CLK
SREAD
SCLK
INT/LOCK
DATA I/O
FSK MOD
CONTROL
GAUSSIAN
FILTER
Σ-Δ
MODULATOR
05351-001
IF FILTER
ADF7020
FEATURES
Low power, low IF transceiver
Frequency bands
431 MHz to 478 MHz
862 MHz to 956 MHz
Data rates supported
0.15 kbps to 200 kbps, FSK
0.15 kbps to 64 kbps, ASK
2.3 V to 3.6 V power supply
Programmable output power
−16 dBm to +13 dBm in 0.3 dBm steps
Receiver sensitivity
−119 dBm at 1 kbps, FSK
−112 dBm at 9.6 kbps, FSK
−106.5 dBm at 9.6 kbps, ASK
Low power consumption
19 mA in receive mode
26.8 mA in transmit mode (10 dBm output)
−3 dBm IIP3 in high linearity mode
High Performance, ISM Band,
On-chip VCO and fractional-N PLL
On-chip 7-bit ADC and temperature sensor
Fully automatic frequency control loop (AFC) compensates
for ±25 ppm crystal at 862 MHz to 956 MHz or±50 ppm at
431 MHz to 478 MHz
Digital RSSI
Integrated Tx/Rx switch
Leakage current of <1 µA in power-down mode
APPLICAT ION S
Low cost wireless data transfer
Remote control/security systems
Wireless metering
Keyless entry
Home automation
Process and building control
Wireless voice
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
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ADF7020 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications ..................................................................................... 5
Timing Characteristics ..................................................................... 8
Timing Diagrams .......................................................................... 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 13
Frequency Synthesizer ................................................................... 15
Reference Input ........................................................................... 15
Choosing Channels for Best System Performance ................. 17
Trans mitter ...................................................................................... 18
RF Output Stage .......................................................................... 18
Modulation Schemes .................................................................. 18
Receiver ............................................................................................ 20
RF Front End ............................................................................... 20
RSSI/AGC .................................................................................... 21
FSK Demodulators on the ADF7020 ....................................... 21
FSK Correlator/Demodulator ................................................... 21
Linear FSK Demodulator .......................................................... 23
AFC .............................................................................................. 23
Automatic Sync Word Recognition ......................................... 24
Applications Information .............................................................. 25
LNA/PA Matching ...................................................................... 25
Image Rejection Calibration ..................................................... 26
Transmit Protocol and Coding Considerations ..................... 27
Device Programming after Initial Power-Up ......................... 27
Interfacing to Microcontroller/DSP ........................................ 27
Power Consumption and battery lifetime calculations ......... 28
Serial Interface ................................................................................ 31
Readback Format ........................................................................ 31
Registers ........................................................................................... 32
Register 0—N Register ............................................................... 32
Register 1—Oscillator/Filter Register ...................................... 33
Register 2—Transmit Modulation Register (ASK/OOK
Mode) ........................................................................................... 34
Register 2—Transmit Modulation Register (FSK Mode) ..... 35
Register 2—Transmit Modulation Register (GFSK/GOOK
Mode) ........................................................................................... 36
Register 3—Receiver Clock Register ....................................... 37
Register 4—Demodulator Setup Register ............................... 38
Register 5—Sync Byte Register ................................................. 39
Register 6—Correlator/Demodulator Register ...................... 40
Register 7—Readback Setup Register ...................................... 41
Register 8—Power-Down Test Register .................................. 42
Register 9—AGC Register ......................................................... 43
Register 10—AGC 2 Register .................................................... 44
Register 11—AFC Register ....................................................... 44
Register 12—Test Register ......................................................... 45
Register 13—Offset Removal and Signal Gain Register ....... 46
Outline Dimensions ....................................................................... 47
Ordering Guide .......................................................................... 47
Rev. D | Page 2 of 48
Data Sheet ADF7020
REVISION HISTORY
8/12—Rev. C to Rev. D
Added EPAD Notation ................................................................... 11
Changed CP-48-3 Package to CP-48-5 Package .......................... 47
Updated Outline Dimensions ........................................................ 47
Changes to Ordering Guide ........................................................... 47
5/11—Rev. B to Rev. C
Added Exposed Pad Notation to Outline Dimensions .............. 47
Changes to Ordering Guide ........................................................... 47
8/07—Rev. A to Rev. B
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 8
Changes to Reference Input Section ............................................. 15
Changes to N Counter Section ...................................................... 16
Changes to Choosing Channels for Best Performance Section 17
Changes to Table 5 .......................................................................... 20
Changes to FSK Correlator Register Settings Section ................ 22
Added Image Rejection Calibration Section ............................... 26
Added Figure 41 .............................................................................. 30
Changes to Readback Format Section .......................................... 31
Changes to Register 9—AGC Register Comments Section ....... 43
Added Register 12—Test Register Comments Section .............. 45
4/06—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Table 1 ............................................................................ 5
Changes to Figure 24 ...................................................................... 17
Changes to the Setting Up the ADF7020 for GFSK Section ..... 19
Changes to Table 6 .......................................................................... 21
Changes to Table 9 .......................................................................... 23
Changes to External AFC Section................................................. 23
Deleted Maximum AFC Range Section ....................................... 23
Added AFC Performance Section ................................................. 24
Changes to Internal Rx/Tx Switch Section .................................. 25
Changes to Figure 32 ...................................................................... 25
Changes to Transmit Protocol and Coding Considerations
Section .............................................................................................. 26
Added Text Relating to Figure 37 ................................................. 27
Changes to Figure 41 ...................................................................... 31
Changes to Register 1—Oscillator/Filter Register
Comments ........................................................................................ 31
Changes to Figure 42 ...................................................................... 32
Changes to Register 2—Transmit Modulation Register
(FSK Mode) Comments ................................................................. 33
Changes to Figure 44 ...................................................................... 34
Changes to Register 2—Transmit Modulation Register
(GFSK/GOOK Mode) Comments ................................................ 34
Changes to Register 4—Demodulator Setup Register
Comments ........................................................................................ 36
Changes to Figure 51 ...................................................................... 41
Changes to Figure 53 ...................................................................... 42
Changes to Ordering Guide ........................................................... 45
6/05—Revision 0: Initial Version
Rev. D | Page 3 of 48
ADF7020 Data Sheet
GENERAL DESCRIPTION
The ADF7020 is a low power, highly integrated FSK/ASK/OOK
transceiver designed for operation in the license-free ISM bands
at 433 MHz, 868 MHz, and 915 MHz, as well as the proposed
Japanese RFID band at 950 MHz. A Gaussian data filter option
is available to allow either GFSK or G-ASK modulation, which
provides a more spectrally efficient modulation. In addition to
these modulation options, the ADF7020 can also be used to
perform both MSK and GMSK modulation, where MSK is a
special case of FSK with a modulation index of 0.5. The modulation index is calculated as twice the deviation divided by the
data rate. MSK is spectrally equivalent to O-QPSK modulation
with half-sinusoidal Tx baseband shaping, so the ADF7020 can
also support this modulation option by setting up the device in
MSK mode.
This device is suitable for circuit applications that meet the
European ETSI-300-220, the North American FCC (Part 15),
or the Chinese Short Range Device regulatory standards. A
complete transceiver can be built using a small number of
external discrete components, making the ADF7020 very
suitable for price-sensitive and area-sensitive applications.
The transmitter block on the ADF7020 contains a VCO and
low noise fractional-N PLL with an output resolution of
<1 ppm. This frequency agile PLL allows the ADF7020 to be
used in frequency-hopping spread spectrum (FHSS) systems.
The VCO operates at twice the fundamental frequency to
reduce spurious emissions and frequency-pulling problems.
The transmitter output power is programmable in 0.3 dB steps
from −16 dBm to +13 dBm. The transceiver RF frequency,
channel spacing, and modulation are programmable using a
simple 3-wire interface. The device operates with a power
supply range of 2.3 V to 3.6 V and can be powered down when
not in use.
A low IF architecture is used in the receiver (200 kHz),
minimizing power consumption and the external component
count and avoiding interference problems at low frequencies.
The ADF7020 supports a wide variety of programmable
features, including Rx linearity, sensitivity, and IF bandwidth,
allowing the user to trade off receiver sensitivity and selectivity
against current consumption, depending on the application.
The receiver also features a patent-pending automatic frequency
control (AFC) loop, allowing the PLL to track out the frequency
error in the incoming signal.
An on-chip ADC provides readback of an integrated temperature sensor, an external analog input, the battery voltage, or the
RSSI signal, which provides savings on an ADC in some applications. The temperature sensor is accurate to ±10°C over the
full operating temperature range of −40°C to +85°C. This
accuracy can be improved by doing a 1-point calibration at
room temperature and storing the result in memory.
Rev. D | Page 4 of 48
Data Sheet ADF7020
Frequency Ranges (Direct Output)
862 870
MHz
VCO adjust = 0, VCO bias = 10
Frequency Ranges (Divide-by-2 Mode)
431 440
MHz
VCO adjust = 0, VCO bias = 10
OOK/ASK
0.15 641
kbps
GFSK/FSK Frequency Deviation
2, 3
1 110
kHz
PFD = 3.625 MHz
ASK Modulation Depth
30
dB
Third Harmonic
−21 dBc
54 + j94
Ω FRF = 433 MHz
Sensitivity at 1 kbps
−119.2
dBm
FDEV = 5 kHz, high sensitivity mode7
SPECIFICATIONS
VDD = 2.3 V to 3.6 V, GND = 0 V, TA = T
All measurements are performed using the EVAL-ADF7020DBZx using the PN9 data sequence, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
RF CHARACTERISTICS
902 928 MHz VCO adjust = 3, VCO bias = 10
928 956 MHz VCO adjust = 3, VCO bias = 12, VDD = 2.7 V to 3.6 V
440 478 MHz VCO adjust = 3, VCO bias = 12
Phase Frequency Detector Frequency RF/256 24 MHz
TRANSMISSION PARAMETERS
Data Rate
FSK/GFSK 0.15 200 kbps
OOK/ASK 0.3 100 kbaud Using Manchester encoding
Frequency Shift Keying
4.88 620 kHz PFD = 20 MHz
Deviation Frequency Resolution 100 Hz PFD = 3.625 MHz
Gaussian Filter BT 0.5
Amplitude Shift Keying
MIN
to T
, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C.
MAX
PA Off Feedthrough in OOK Mode −50 dBm
Transmit Power4 −20 +13 dBm VDD = 3.0 V, TA = 25°C
Transmit Power Variation vs.
Temperature
Transmit Power Variation vs. VDD ±1 dB From 2.3 V to 3.6 V at 915 MHz, TA = 25°C
Transmit Power Flatness ±1 dB From 902 MHz to 928 MHz, 3 V, TA = 25°C
Programmable Step Size
−20 dBm to +13 dBm 0.3125 dB
Integer Boundary −55 dBc 50 kHz loop BW
Reference −65 dBc
Harmonics
VCO Frequency Pulling, OOK Mode 30 kHz rms DR = 9.6 kbps
Optimum PA Load Impedance5 39 + j61 Ω FRF = 915 MHz
48 + j54 Ω FRF = 868 MHz
RECEIVER PARAMETERS
FSK/GFSK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz,
OOK Input Sensitivity At BER = 1E − 3, FRF = 915 MHz
Second Harmonic −27 dBc Unfiltered conductive
All Other Harmonics −35 dBc
Sensitivity at 9.6 kbps −112.8 dBm FDEV = 10 kHz, high sensitivity mode
Sensitivity at 200 kbps −100 dBm FDEV = 50 kHz, high sensitivity mode
Sensitivity at 1 kbps −116 dBm High sensitivity mode
Sensitivity at 9.6 kbps −106.5 dBm High sensitivity mode
±1 dB From −40°C to +85°C
LNA and PA matched separately
6
Rev. D | Page 5 of 48
ADF7020 Data Sheet
High Sensitivity Mode
−24 dBm
F2 = FRF + 6 MHz, maximum gain
AFC
(Offset = ±3 × IF Filter BW Setting)
Image Channel Rejection
30 dB
Image at FRF = 400 kHz
Wideband Interference Rejection
70 dB
Swept from 100 MHz to 2 GHz, measured as channel
LNA Input Impedance
24 − j60
Ω FRF = 915 MHz, RFIN to GND
65 MHz/V
433 MHz, VCO adjust = 0
Parameter Min Typ Max Unit Test Conditions
LNA and Mixer, Input IP37
Enhanced Linearity Mode −3 dBm Pin = −20 dBm, 2 CW interferers
Low Current Mode −5 dBm FRF = 915 MHz, F1 = FRF + 3 MHz
Rx Spurious Emissions8 −57 dBm <1 GHz at antenna input
−47 dBm >1 GHz at antenna input
Pull-In Range at 868 MHz/915 MHz ±50 kHz IF_BW = 200 kHz
Pull-In Range at 433 MHz ±25 kHz IF_BW = 200 kHz
Response Time 48 Bits Modulation index = 0.875
Accuracy 1 kHz
CHANNEL FILTERING Desired signal 3 dB above the input sensitivity level,
Adjacent Channel Rejection
(Offset = ±1 × IF Filter BW Setting)
Second Adjacent Channel Rejection
(Offset = ±2 × IF Filter BW Setting)
Third Adjacent Channel Rejection
(Uncalibrated)
Image Channel Rejection (Calibrated) 50 dB Image at FRF = 400 kHz
CO-CHANNEL REJECTION −2 dB
CW interferer power level increased until BER = 10
image channel excluded
27 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
50 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
55 dB IF filter BW settings = 100 kHz, 150 kHz, 200 kHz
−3
,
rejection
BLOCKING Desired signal 3 dB above the input sensitivity level,
±1 MHz 60 dB
±5 MHz 68 dB
±10 MHz 65 dB
±10 MHz (High Linearity Mode) 72 dB
Saturation (Maximum Input Level) 12 dBm FSK mode, BER = 10−3
26 − j63 Ω FRF = 868 MHz
71 − j128 Ω FRF = 433 MHz
RSSI
Range at Input −110 to
−24
Linearity ±2 dB
Absolute Accuracy ±3 dB
Response Time 150 µs
PHASE-LOCKED LOOP
VCO Gain 65 MHz/V 902 MHz to 928 MHz band,
130 MHz/V 860 MHz to 870 MHz band, VCO adjust = 0
Phase Noise (In-Band) −89 dBc/Hz PA = 0 dBm, VDD = 3.0 V, PFD = 10 MHz,
Phase Noise (Out-of-Band) −110 dBc/Hz 1 MHz offset
Residual FM 128 Hz From 200 Hz to 20 kHz, FRF = 868 MHz
PLL Settling 40 µs Measured for a 10 MHz frequency step to within
dBm
CW interferer power level increased until BER = 10
See the
RSSI/AGC section
VCO adjust = 0, VCO_BIAS_SETTING = 10
FRF = 915 MHz, VCO_BIAS_SETTING = 10
5 ppm accuracy, PFD = 20 MHz, LBW = 50 kHz
−2
Rev. D | Page 6 of 48
Data Sheet ADF7020
Chip Enabled to Regulator Ready
10 µs
C
REG
= 100 nF
INH/IINL
OUT
VDD
2.3 3.6 V All VDD pins must be tied together
Low Power Sleep Mode
0.1 1 µA
Parameter Min Typ Max Unit Test Conditions
REFERENCE INPUT
Crystal Reference 3.625 24 MHz
External Oscillator 3.625 24 MHz
Load Capacitance 33 pF See crystal manufacturer’s specification sheet
Crystal Start-Up Time 2.1 ms 11.0592 MHz crystal, using 33 pF load capacitors
1.0 ms Using 16 pF load capacitors
Input Level CMOS levels
ADC PARAMETERS
INL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
DNL ±1 LSB From 2.3 V to 3.6 V, TA = 25°C
TIMING INFORMATION
See the
Reference Input section
Chip Enabled to RSSI Ready 3.0 ms
Tx to Rx Turnaround Time 150 µs +
(5 × T
BIT
Time to synchronized data out, includes AGC settling;
)
See
Tab le 11 for more details
see the
AGC Information and Timing section
LOGIC INPUTS
Input High Voltage, V
0.7 ×
INH
V
VDD
Input Low Voltage, V
0.2 ×
INL
V
VDD
Input Current, I
±1 µA
Input Capacitance, CIN 10 pF
Control Clock Input 50 MHz
LOGIC OUTPUTS
Output High Voltage, VOH DVDD −
V IOH = 500 µA
0.4
Output Low Voltage, VOL 0.4 V IOL = 500 µA
CLK
Rise/Fall 5 ns
CLK
Load 10 pF
OUT
TEMPERATURE RANGE, TA −40 +85 °C
POWER SUPPLIES
Voltage Supply
Transmit Current Consumption FRF = 915 MHz, VDD = 3.0 V,
PA is matched to 50 Ω
−20 dBm 14.8 mA Combined PA and LNA matching network as on
−10 dBm 15.9 mA
0 dBm 19.1 mA
EVAL-ADF7020DBZx boards
VCO_BIAS_SETTING = 12
10 dBm 28.5 mA
10 dBm 26.8 mA PA matched separately with external antenna
switch, VCO_BIAS_SETTING = 12
Receive Current Consumption
Low Current Mode 19 mA
High Sensitivity Mode 21 mA
Power-Down Mode
1
Higher data rates are achievable, depending on local regulations.
2
For the definition of frequency deviation, see the Register 2—Transmit Modulation Register (FSK Mode) section.
3
For the definition of GFSK frequency deviation, see the Register 2—Transmit Modulation Register (GFSK/GOOK Mode) section.
4
Measured as maximum unmodulated power. Output power varies with both supply and temperature.
5
For matching details, see the LNA/PA Matching section and the AN-764 Application Note.
6
Sensitivity for combined matching network case is typically 2 dB less than separate matching networks.
7
See Table 5 for a description of different receiver modes.
8
Follow the matching and layout guidelines to achieve the relevant FCC/ETSI specifications.
Rev. D | Page 7 of 48
ADF7020 Data Sheet
TIMING CHARACTERISTICS
VDD = 3 V ± 10%, VGND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design, not production tested.
Table 2.
Parameter Limit at T
t
>10 ns SDATA to SCLK setup time
1
t2 >10 ns SDATA to SCLK hold time
t3 >25 ns SCLK high duration
t4 >25 ns SCLK low duration
t
>10 ns SCLK to SLE setup time
5
t
>20 ns SLE pulse width
6
t
<25 ns SCLK to SREAD data valid, readback
8
t
<25 ns SREAD hold time after SCLK, readback
9
t
>10 ns SCLK to SLE disable time, readback
10
TIMING DIAGRAMS
SCLK
MIN
to T
Unit Test Conditions/Comments
MAX
t
3
t
4
SDATA
SLE
t
1
DB31 (MSB) DB30 DB2
t
2
Figure 2. Serial Interface Timing Diagram
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
5
t
6
05351-002
SCLK
SDATA
SLE
SREAD
t
1
R7_DB0
(CONTROL BIT C1)
t
2
t
3
X RV16 RV15 RV2 RV1
t
t
8
9
Figure 3. Readback Timing Diagram
t
10
05351-003
Rev. D | Page 8 of 48
Data Sheet ADF7020
A
A
±1 × DATA RATE/32 1/DATA RATE
RxCLK
RxDAT
DATA
05351-004
Figure 4. RxData/RxCLK Timing Diagram
1/DATA RATE
TxCLK
TxDAT
NOTES
1. TxCLK ONLY AVAILABL E IN GFSK MODE.
SAMPLEFETCH
DATA
5351-005
Figure 5. TxData/TxCLK Timing Diagram
Rev. D | Page 9 of 48
ADF7020 Data Sheet
Maximum Junction Temperature
150°C
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND1 −0.3 V to +5 V
Analog I/O Voltage to GND −0.3 V to AVDD + 0.3 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
MLF θJA Thermal Impedance 26°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1
GND = GND1 = RFGND = GND4 = VCO GND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and is ESD sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
Rev. D | Page 10 of 48
Data Sheet ADF7020
K
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CVCO
GND1
GND
VCO GND
GND
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
48
47
43
42
46
45
41
44
MUXOUT
40
39
38
37
24
CE
CLKOUT
36
DATA CL
35
DATA I/O
34
INT/LOCK
33
VDD2
32
CREG2
31
ADCIN
30
GND2
29
SCLK
28
SREAD
27
SDATA
26
SLE
25
5351-006
VCOIN
1
2
CREG1
3
VDD1
4
RFOUT
5
RFGND
6
RFIN
7
RFINB
R
8
LNA
9
VDD4
10
RSET
11
CREG4
12
GND4
NOTES
1. EXPOSED PAD MUST BE CONNECTED TO GROUND.
13
14
MIX_I
MIX_I
ADF7020
TOP VIEW
(Not to Scale)
15
16
17
18
FILT_I
FILT_I
MIX_Q
MIX_Q
19
20
21
22
23
GND4
GND4
FILT_Q
FILT_Q
TEST_A
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 VCOIN
The tuning voltage on this pin determines the output frequency of the voltage-controlled oscillator (VCO).
The higher the tuning voltage, the higher the output frequency.
2 CREG1
Regulator Voltage for PA Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between this
pin and ground for regulator stability and noise rejection.
3 VDD1
Voltage Supply for PA Block. Decoupling capacitors of 0.1 μF and 10 pF should be placed as close as
possible to this pin. All VDD pins should be tied together.
4 RFOUT
The modulated signal is available at this pin. Output power levels are from −20 dBm to +13 dBm. The
output should be impedance matched to the desired load using suitable components. See the Transmitter
section.
5 RFGND Ground for Output Stage of Transmitter. All GND pins should be tied together.
6 RFIN
LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA
input to ensure maximum power transfer. See the LNA/PA Matching section.
7 RFINB Complementary LNA Input. See the LNA/PA Matching section.
8 R
External bias resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance.
LNA
9 VDD4 Voltage Supply for LNA/MIXER Block. This pin should be decoupled to ground with a 10 nF capacitor.
10 RSET
External Resistor to Set Charge Pump Current and Some Internal Bias Currents. Use 3.6 kΩ with 5%
tolerance.
11 CREG4
Regulator Voltage for LNA/MIXER Block. A 100 nF capacitor should be placed between this pin and GND
for regulator stability and noise rejection.
12 GND4 Ground for LNA/MIXER Block.
13 to 18
MIX_I, MIX_I
MIX_Q, MIX_Q
FILT_I, FILT_I
,
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
,
19, 22 GND4 Ground for LNA/MIXER Block.
20, 21, 23
FILT_Q, FILT_Q
TEST_A
24 CE
,
Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left
unconnected.
Chip Enable. Bringing CE low puts the ADF7020 into complete power-down. Register values are lost when
CE is low, and the part must be reprogrammed once CE is brought high.
25 SLE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the fourteen latches. A latch is selected using the control bits.
26 SDATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This pin is a high
impedance CMOS input.
Rev. D | Page 11 of 48
ADF7020 Data Sheet
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
29
GND2
Ground for Digital Section.
frequency. Other signals include Regulator_Ready, which is an indicator of the status of the serial interface
Regulator Voltage for Charge Pump and PLL Dividers. A 100 nF in parallel with a 5.1 pF capacitor should be
48
CVCO
A 22 nF capacitor should be placed between this pin and CREG1 to reduce VCO noise.
Pin No. Mnemonic Description
27 SREAD Serial Data Output. This pin is used to feed readback data from the ADF7020 to the microcontroller. The
SCLK input is used to clock each readback bit (AFC, ADC readback) from the SREAD pin.
28 SCLK
the 24-bit shift register on the CLK rising edge. This pin is a digital CMOS input.
30 ADCIN Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V
to 1.9 V. Readback is made using the SREAD pin.
31 CREG2 Regulator Voltage for Digital Block. A 100 nF in parallel with a 5.1 pF capacitor should be placed between
this pin and ground for regulator stability and noise rejection.
32 VDD2 Voltage Supply for Digital Block. A decoupling capacitor of 10 nF should be placed as close as possible to
this pin.
33 INT/LOCK Bidirectional Pin. In output mode (interrupt mode), the ADF7020 asserts the INT/ LOCK pin when it has
found a match for the preamble sequence. In input mode (lock mode), the microcontroller can be used to
lock the demodulator threshold when a valid preamble has been detected. Once the threshold is locked,
NRZ data can be reliably received. In this mode, a demodulation lock can be asserted with minimum delay.
34 DATA I/O Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply.
35 DATA C LK In receive mode, the pin outputs the synchronized data clock. The positive clock edge is matched to the
center of the received data. In GFSK transmit mode, the pin outputs an accurate clock to latch the data
from the microcontroller into the transmit section at the exact required data rate. See the Gaussian
Frequency Shift Keying (GFSK) section.
36 CLKOUT A Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be
used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-
space ratio.
37 MUXOUT This pin provides the Lock_Detect signal, which is used to determine if the PLL is locked to the correct
regulator.
38 OSC2 The reference crystal should be connected between this pin and OSC1. A TCXO reference can be used by
driving this pin with CMOS levels and disabling the crystal oscillator.
39 OSC1 The reference crystal should be connected between this pin and OSC2.
40 VDD3 Voltage Supply for the Charge Pump and PLL Dividers. This pin should be decoupled to ground with a
0.01 µF capacitor.
41 CREG3
placed between this pin and ground for regulator stability and noise rejection.
42 CPOUT Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The
integrated current changes the control voltage on the input to the VCO.
43 VDD Voltage Supply for VCO Tank Circuit. This pin should be decoupled to ground with a 0.01 µF capacitor.
44 to 47 GND, GND1,
VCO GND
EP Exposed Pad. The exposed pad must be connected to ground.
Grounds for VCO Block.
Rev. D | Page 12 of 48
Data Sheet ADF7020
05351-007
10MHz
10.0000kHz
–87.80dBc/Hz
CARRIER POW E R –0.28dBm ATTEN 0.00dB MKR1
REF –70.00dBc/Hz
10.00
dB/DIV
1kHz FREQUENCY OFFSET
1
05351-008
FREQUENCY (MHz)
913.38913.28 913.30 913.32 913.36
SIGNAL LEVEL (dBm)
10
20
30
40
50
60
70
PRBS PN9
DR = 7.1kbps
FDEV = 4.88kHz
RBW = 300kHz
FSK
GFSK
05351-009
IF FREQ (kHz)
600–400 –300 –200
–100 0 100 200 300 400 500
550–350 –250 –150 –50 50 150 250 350 450
ATTENUATION LEVEL (dB)
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
200kHz FILTER BW
150kHz FILTER BW
100kHz FILTER BW
05351-010
STOP 10. 000GHz
SWEEP 16. 52ms ( 601pts)
MKR4 3.482GHz
SWEEP 16. 52ms ( 601pts)
START 100MHz
RES BW 3MHz
REF 10dBm
PEAK
log
10dB/DIV
VBW 3MHz
ATTEN 20dB
1
3
4
REF LEVEL
10.00dBm
05351-011
STOP 5. 000GHz
SWEEP 5. 627s ( 601pts)
Δ Mkr1 1.834GHz
–62.57dB
START 800MHz
#RES BW 30kHz
REF 15dBm ATTEN 30dB
VBW 30kHz
NORM
log
10dB/DIV
LgAv
W1 S2
S3 FC
AA
£(f):
FTun
Swp
1R
1
MARKER
Δ
1.834000000GHz
–62.57dB
05351-012
FREQUENCY (MHz)
900.80899.60 900.00899.80 900.20 900.40 900.60
SIGNAL LEVEL (dBm)
10
0
–10
–20
–30
–40
–50
OOK
GOOK
ASK
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Phase Noise Response at 868.3 MHz, VDD = 3.0 V, ICP = 1.5 mA
Figure 8. Output Spectrum in FSK and GFSK Modulation
Figure 10. Harmonic Response, RF
Matched to 50 Ω, No Filter
OUT
Figure 11. Harmonic Response, Murata Dielectric Filter
Rev. D | Page 13 of 48
Figure 9. IF Filter Response
Figure 12. Output Spectrum in ASK, OOK, and GOOK Modes, DR = 10 kbps
ADF7020 Data Sheet
05351-013
PA SETTING
1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61
PA OUTPUT POWER
20
10
15
0
5
–10
–5
–20
–15
–25
11µA
9µA
5µA
7µA
05351-014
FREQUENCY OF INTERFERER (MHz)
1100
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950
1000
1050
LEVEL OF REJECTION (dB)
80
70
60
50
40
30
20
10
0
–10
05351-015
20–120 –100 –80 –60 –40 –20 0
20
–20
–60
0
–40
–80
–100
–120
ACTUAL INPUT LEVEL
RSSI READBACK LE V E L
RF INPUT ( dB)
RSSI LEVEL (dB)
05351-016
RF INPUT LEVEL (dBm)
–114
–113
–112
–111
–110
–109
–108
–107
–106
–124
–123
–122
–121
–120
–119
–118
–117
–116
–115
0
–1
–2
–3
–5
–4
–6
–7
–8
3.6V, –40°C
2.4V, +85°C
3.0V, +25° C
DATA RATE = 1kbps FSK
IF BW = 100kHz
DEMOD BW = 0. 77kHz
BER
05351-017
RF INPUT LEVEL (dBm)
–90
–122
–121
–120
–119
–118
–117
–116
–115
–114
–113
–112
–111
–110
–109
–108
–107
–106
–105
–104
–103
–102
–101
–100
–99
–98
–97
–96
–95
–94
–93
–92
–91
BER
0
–1
–2
–4
–5
–3
–6
–7
–8
9.760k
DATA RATE
200.8k
DATA RATE
1.002k
DATA RATE
05351-018
FREQUENCY E RROR (kHz)
110
–110
–90
–70
–50
–30
–10
10
30
50
70
90
100
–100
–80
–60
–40
–20
0
20
40
60
80
SENSITIVITY (dBm)
–60
–70
–75
–65
–80
–85
–90
–95
–100
–105
–110
LINEAR AFC OFF
LINEAR AFC ON
CORRELATOR
AFC OFF
CORRELATOR
AFC ON
Figure 13. PA Output Power vs. Setting
Figure 16. BER vs. VDD and Temperature
Figure 14. Wideband Interference Rejection; Wanted Signal (880 MHz)
at 3 dB above Sensitivity Point
Interferer = FM Jammer (9.76 kbps, 10 kHz Deviation)
Figure 15. Digital RSSI Readback Linearity
Figure 17. BER vs. Data Rate (Combined Matching Network)
Separate LNA and PA Matching Paths Typically
Improve Performance by 2 dB
Figure 18. Sensitivity vs. Frequency Error with AFC On/Off
Rev. D | Page 14 of 48
Data Sheet ADF7020
OSC1
CP1CP2
OSC2
05351-019
PCB
L
C
CP2CP
C +
+
=
1
1
1
1
DV
DD
CLKOUT
ENABLE BIT
CLKOUTOSC1
DIVIDER
1 TO 15
05351-020
÷2
REGULATOR READY
DIGITAL LOCK DETECT
ANALOG L OCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
PLL TEST MODES
Σ-Δ TEST MODES
MUX CONTROL
DGND
DV
DD
MUXOUT
05351-021
FREQUENCY SYNTHESIZER
REFERENCE INPUT
The on-board crystal oscillator circuitry (see Figure 19) can use
an inexpensive quartz crystal as the PLL reference. The oscillator circuit is enabled by setting R1_DB12 high. It is enabled by
default on power-up and is disabled by bringing CE low. Errors
in the crystal can be corrected using the automatic frequency
control (see the AFC section) feature or by adjusting the
fractional-N value (see the N Counter section). A single-ended
reference (TCXO, CXO) can also be used. The CMOS levels
should be applied to OSC2 with R1_DB12 set low.
Figure 19. Oscillator Circuit on the ADF7020
Two parallel resonant capacitors are required for oscillation at
the correct frequency; their values are dependent on the crystal
specification. They should be chosen so that the series value of
capacitance added to the PCB track capacitance adds up to the
load capacitance of the crystal, usually 20 pF. PCB track
capacitance values might vary from 2 pF to 5 pF, depending on
board layout. Thus, CP1 and CP2 can be calculated using:
R Counter
The 3-bit R counter divides the reference input frequency by an
integer ranging from 1 to 7. The divided-down signal is
presented as the reference clock to the phase frequency detector
(PFD). The divide ratio is set in Register 1. Maximizing the
PFD frequency reduces the N value. Every doubling of the PFD
gives a 3 dB benefit in phase noise, as well as reducing
occurrences of spurious components. The R register defaults to
R = 1 on power-up.
PFD [Hz] = XTAL/R
MUXOUT and Lock Detect
The MUXOUT pin allows the user to access various digital
points in the ADF7020. The state of MUXOUT is controlled by
Bits R0_DB[29:31].
Regulator Ready
Regulator ready is the default setting on MUXOUT after the
transceiver has been powered up. The power-up time of the
regulator is typically 50 µs. Because the serial interface is
powered from the regulator, the regulator must be at its
nominal voltage before the ADF7020 can be programmed. The
status of the regulator can be monitored at MUXOUT. When
the regulator ready signal on MUXOUT is high, programming
of the ADF7020 can begin.
Where possible, choose capacitors that have a low temperature
coefficient to ensure stable frequency operation over all
conditions.
CLKOUT Divider and Buffer
The CLKOUT circuit takes the reference clock signal from the
oscillator section, shown in Figure 19, and supplies a divideddown 50:50 mark-space signal to the CLKOUT pin. An even
divide from 2 to 30 is available. This divide number is set in
R1_DB[8:11]. On power-up, the CLKOUT defaults to
divide-by-8.
To disable CLKOUT, set the divide number to 0. The output
buffer can drive up to a 20 pF load with a 10% rise time at
4.8 MHz. Faster edges can result in some spurious feedthrough
to the output. A small series resistor (50 Ω) can be used to slow
the clock edges to reduce these spurs at f
Rev. D | Page 15 of 48
Figure 20. CLKOUT Stage
CLK
Figure 21. MUXOUT Circuit
Digital Lock Detect
Digital lock detect is active high. The lock detect circuit is
located at the PFD. When the phase error on five consecutive
cycles is less than 15 ns, lock detect is set high. Lock detect
remains high until 25 ns phase error is detected at the PFD.
Because no external components are needed for digital lock
detect, it is more widely used than analog lock detect.
Analog Lock Detect
This N-channel open-drain lock detect should be operated with
an external pull-up resistor of 10 kΩ nominal. When a lock has
been detected, this output is high with narrow low going pulses.
.
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