Analog Devices ADF7012 Datasheet

Multichannel ISM Band

FEATURES

Single-chip, low power UHF transmitter
75 MHz to 1 GHz frequency operation
Multichannel operation using Frac-N PLL

2.3 V to 3.6 V operation
On-board regulator—stable performance
Programmable output power:

−16 dBm to +14 dBm, 0.4 dB steps

Data rates: dc to 179.2 kbps
Low current consumption:

868 MHz, 10 dBm, 21 mA
433 MHz, 10 dBm, 17 mA

315 MHz, 0 dBm, 10 mA
Programmable low battery voltage indicator
24-lead TSSOP

APPLICATIONS

Low cost wireless data transfer
Security systems
RF remote controls
Wireless metering
Secure keyless entry

FSK/GFSK/OOK/GOOK/ASK Transmitter

ADF7012

GENERAL DESCRIPTION

The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK
UHF transmitter designed for short range devices (SRDs). The
output power, output channels, deviation frequency, and mod­ulation type are programmable by using four, 32-bit registers.

The fractional-N PLL and VCO with external inductor enable
the user to select any frequency in the 75 MHz to 1 GHz band.
The fast lock times of the fractional-N PLL make the ADF7012
suitable in fast frequency hopping systems. The fine frequency
deviations available and PLL phase noise performance facilitates
narrow-band operation.

There are five selectable modulation schemes: binary frequency
shift keying (FSK), Gaussian frequency shift keying (GFSK),
binary on-off keying (OOK), Gaussian on-off keying (GOOK),
and amplitude shift keying (ASK). In the compensation register,
the output can be moved in <1 ppm steps so that indirect com­pensation for frequency error in the crystal reference can be
made.

A simple 3-wire interface controls the registers. In power-down,
the part has a typical quiescent current of <0.1 μA.

FUNCTIONAL BLOCK DIAGRAM

CLK

CPVDDCP

CENTER

OUT

PFD/

CHARGE

PUMP

+FRACTIONAL N

OSC1 OSC2 L1 L2 C

÷CLK

SERIAL

INTERFACE

CE

÷R

FREQUENCY

COMPENSATION

FREQUENCY

DV

DD

D

GND

OOK\ASK

TxCLK

TxDATA

LE

DATA

CLK

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

FSK\GFSK

GND

Σ-∆

A

GND

Figure 1.

C

PRINTED

INDUCTOR

VCO

PLL LOCK

DETECT

BATTERY
MONITOR

REG

OOK\ASK

PA

REGULATOR

MUXOUT

LDO

VCO

RF

OUT

RF GND

C

REG

MUXOUT

R

SET

V

DD

04617-0-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF7012

TABLE OF CONTENTS

Specifications..................................................................................... 3

GOOK Modulation.................................................................... 15

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transis t o r Count ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

315 MHz ........................................................................................ 8

433 MHz ........................................................................................ 9

868 MHz ......................................................................................10

915 MHz ......................................................................................11

Circuit Description......................................................................... 12

PLL Operation ............................................................................ 12

Crystal Oscillator........................................................................ 12

Crystal Compensation Register................................................ 12

Clock Out Circuit....................................................................... 12

Output Divider ........................................................................... 16

MUXOUT Modes....................................................................... 16

Theory of Operation ...................................................................... 17

Choosing the External Inductor Value.................................... 17

Choosing the Crystal/PFD Value............................................. 17

Tips on Designing the Loop Filter ........................................... 17

PA Mat c h ing................................................................................ 18

Transmit Protocol and Coding Considerations ..................... 18

Application Examples.................................................................... 19

315 MHz Operation................................................................... 20

433 MHz Operation................................................................... 21

868 MHz Operation................................................................... 22

915 MHz Operation................................................................... 23

Register Descriptions..................................................................... 24

R Register..................................................................................... 24

Loop Filter ................................................................................... 13

Volt a ge- C ont r o ll e d Os cil lato r (VCO ) ..................................... 13

Volt a ge R e gu l ator s ...................................................................... 13

FSK Modulation..........................................................................13

GFSK Modulation ...................................................................... 14

Power Amplifier.......................................................................... 14

REVISION HISTORY

10/04—Revision 0: Initial Version

N-Counter Latch ........................................................................ 25

Modulation Register .................................................................. 26

Function Register ....................................................................... 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

ADF7012

SPECIFICATIONS

DVDD = 2.3 V – 3.6 V; AGND = DGND = 0 V; TA = T

Table 1.

Parameter B Version Unit Conditions/Comments

RF OUTPUT CHARACTERISTICS

Operating Frequency 75/1000 MHz min/max

Phase Frequency Detector FRF/128 Hz min

MODULATION PARAMETERS

Data Rate FSK/GFSK 179.2 kbps Using 1 MHz loop bandwidth
Data Rate ASK/OOK 64 Kbps

Deviation FSK/GFSK PFD/2

511 × PFD/214Hz max For example, 10 MHz PFD – deviation max = ± 311.7 kHz

GFSK BT 0.5 typ
ASK Modulation Depth 25 dB max
OOK Feedthrough (PA Off) −40 dBm typ FRF = Fvco

−80 dBm typ FRF = Fvco/2
POWER AMPLIFIER PARAMETERS

Max Power Setting, DVDD = 3.6 V 14 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.0 V 13.5 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 2.3 V 12.5 dBm FRF = 915 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.6 V 14.5 dBm FRF = 433 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 3.0 V 14 dBm FRF = 433 MHz, PA is matched into 50 Ω
Max Power Setting, DVDD = 2.3 V 13 dBm FRF = 433 MHz, PA is matched into 50 Ω
PA Programmability 0.4 dB typ PA output = −20 dBm to +13 dBm

POWER SUPPLIES

DVDD 2.3/3.6 V min/V max
Current Comsumption

315 MHz, 0 dBm/5 dBm 8/14 mA typ DVDD = 3.0 V, PA is matched into 50 Ω, IVCO = min
433 MHz, 0 dBm/10 dBm 10/18 mA typ
868 MHz, 0 dBm/10 dBm/14 dBm 14/21/32 mA typ

915 MHz, 0 dBm/10 dBm/14 dBm
VCO Current Consumption 1/8 mA min/max VCO current consumption is programmable
Crystal Oscillator Current Consumption 190 µA typ
Regulator Current Consumption 280 µA typ
Power-Down Current 0.1/1 µA typ/max

REFERENCE INPUT

Crystal Reference Frequency 3.4/26 MHz min/max

Single-Ended Reference Frequency 3.4/26 MHz min/max
Crystal Power-On Time 3.4 MHz/26 MHz 1.8/2.2 ms typ CE to Clock Enable Valid
Single-Ended Input Level CMOS Levels

16/24/35 mA typ

to T

MIN

14

, unless otherwise noted. Operating temperature range is −40°C to +85°C.

MAX

VCO range adjustable using external inductor;
divide-by-2, -4, -8 options may be required

Based on US FCC 15.247 specfications for ACP; higher
data rates are achievable depending on local regulations

Hz min For example, 10 MHz PFD – deviation min = ± 610 Hz

Refer to the LOGIC INPUTS parameter. Applied to OSC 2 –
oscillator circuit disabled.

Rev. 0 | Page 3 of 28

ADF7012

Parameter B Version Unit Conditions/Comments

PHASE-LOCKED LOOP PARAMETERS

VCO Gain

315MHz 22 MHz/V typ VCO divide-by-2 active
433MHz 24 MHz/V typ VCO divide-by-2 active

868MHz 80 MHz/V typ

915MHz 88 MHz/V typ
VCO Tuning Range 0.3/2.0 V min/max
Spurious (IVCO Min/Max) −65/−70 dBc I

Charge Pump Current

Setting [00] 0.3 mA typ Refering to DB[7:6] in Function Register

Setting [01] 0.9 mA typ Refering to DB[7:6] in Function Register

Setting [10] 1.5 mA typ Refering to DB[7:6] in Function Register

Setting [11] 2.1 mA typ Refering to DB[7:6] in Function Register
Phase Noise (In band)

1

315MHz −85 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, I

433MHz −83 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, I

868MHz −80 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, I

915MHz −80 dBc/Hz typ PFD = 10 MHz, 5 kHz offset, I
Phase Noise (Out of Band)1

315MHz −103 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, I

433MHz −104 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, I

868MHz −115 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, I

915MHz −114 dBc/Hz typ PFD = 10 MHz, 1 MHz offset, I
Harmonic Content (Second)

2

−20 dBc typ FRF = F
Harmonic Content (Third)2 −30 dBc typ

Harmonic Content (Others)2 −27 dBc typ
Harmonic Content (Second)2 −24 dBc typ FRF = F
Harmonic Content (Third)2 −14 dBc typ

Harmonic Content (Others)2 −19 dBc typ

LOGIC INPUTS

Input High Voltage,V

Input Low Voltage, V
Input Current, I

INH/IINL

Input Capacitance, C

INH

INL

IN

0.7 × DV

0.2 × DV

DD

DD

V min

V max

±1 µA max

4.0 pF max

LOGIC OUTPUTS

Output High Voltage, V

OH

DVDD − 0.4 V min CMOS output chosen

Output High Current, IOH, 500 µA max
Output Low Voltage, V

OL

0.4 V max IOL = 500 µA

is programmable

VCO

VCO

/N (where N = 2, 4, 8)

VCO

= 2 mA

VCO

= 2 mA

VCO

= 3 mA

VCO

= 3 mA

VCO

VCO

VCO

VCO

VCO

= 2 mA
= 2 mA

= 3 mA
= 3 mA

1

Measurements made with N

2

Measurements made without harmonic filter.

FRAC

= 2048.

Rev. 0 | Page 4 of 28

ADF7012

K

TIMING CHARACTERISTICS

DVDD = 3 V ± 10%; AGND = DGND = 0 V; TA = T

Table 2.

Parameter Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE setup time
t2 10 ns min Data-to-clock setup time
t3 10 ns min Data-to-clock hold time
t4 25 ns min Clock high duration
t5 25 ns min Clock low duration
t6 10 ns min Clock –to-LE setup time
t7 20 ns min LE pulse width

MIN

to T

, unless otherwise noted.

MAX

CLOC

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

t

4

3

t

5

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

04617-0-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF7012

ABSOLUTE MAXIMUM RATINGS

T

= 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

DVDD to GND
(GND = AGND = DGND = 0 V)

Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Operating Temperature Range

Maximum Junction Temperature 150°C

TSSOP θJA Thermal Impedance 150.4°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

−0.3 V to +3.9 V

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of 1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

TRANSISTOR COUNT

35819 (CMOS)

Rev. 0 | Page 6 of 28

ADF7012

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DV

1

DD

2

C

REG1

3

CP

OUT

4

TxDATA

TxCLK

5

DGND

OSC1
OSC2

OUT

CLK

DATA

ADF7012

6

TOP VIEW

(Not to Scale)

7
8

9
10
11
12

MUXOUT

CLK

Figure 3.

Table 4. Pin Functional Descriptions

Pin No. Mnemonic Description

1 DV

DD

Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog
ground plane should be placed as close as possible to this pin.

2 C

REG1

A 2.2 µF capacitor should be added at C

REG

improves regulator power-on time, but may cause higher spurious noise.

3 CP

OUT

Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated

current changes the control voltage on the input to the VCO.
4 TxDATA Digital Data to Be Transmitted is inputted on this pin.
5 TxCLK

GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the

ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on

the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit.
6 MUXOUT

Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors

battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator.
7 DGND Ground for Digital Section.
8 OSC1 The reference crystal should be connected between this pin and OSC2.
9 OSC2

The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving

this pin with CMOS levels, and powering down the crystal oscillator bit in software.
10 CLK

OUT

A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive

several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio.
11 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high

impedance CMOS input.
13 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.
14 CE

Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are

lost when CE is low and the part must be reprogrammed once CE is brought high.
15 L1

Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the

value of the inductor to be connected between L1 and L2.
16 L2 Connected to external printed or discrete inductor.
17 C

VCO

A 220 nF capacitor should be tied between the C

This capacitor is necessary to ensure stable VCO operation.
18 VCO

19 RF
20 RF

IN

GND

OUT

The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The

higher the tuning voltage, the higher the output frequency.

Ground for Output Stage of Transmitter.

The modulated signal is available at this pin. Output power levels are from –16 dBm to +12 dBm. The output

should be impedance matched using suitable components to the desired load. See the PA Matching section.
21 DV

DD

Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between

2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin.
22 AGND Ground Pin for the RF Analog Circuitry.
23 R
24 C

SET

REG2

External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default.
Add a 470 nF capacitor at C

to reduce regulator noise and improve stability. A reduced capacitor improves

REG

regulator power-on time and phase noise, but may have stability issues over the supply and temperature.

24

C

REG2

R

23

SET

AGND

22

TSSOP

21

DV

DD

RF

20

OUT

RF

19

GND

VCO

18

IN

C

17

VCO

16

L2

15

L1
CE

14

LE

13

04617-0-003

to reduce regulator noise and improve stability. A reduced capacitor

VCO

and C

pins. This line should run underneath the ADF7012.

REG2

Rev. 0 | Page 7 of 28

ADF7012

TYPICAL PERFORMANCE CHARACTERISTICS

315 MHZ

–60

–70

–80

–90

–100

dBc (Hz)

–110

–120

–130

–140

1.0k 10.0k 100.0k 1.0M 10.0M
PHASE NOISE (Hz)

Figure 4. Phase Noise Response—DV

IVCO = 2.0 mA, F

REF LVL
5dBm

5

0
–10
–20
–30

–40

–50

–60
–70

–80
–90

–95

CENTER 315MHz 50kHz/ SPAN 500kHz

= 315 MHz, PFD = 3.6864 MHZ, PA Bias = 5.5 mA

OUT

0.45dBm

315.05060120MHz

Figure 5. FSK Modulation, Power = 0 dBm, Data Rate = 1 kbps,

F

= ±50 kHz

DEVIATION

REF LVL
5dBm

5

0
–10
–20
–30

–40

D1 –41.5dBm

D2 –49dBm

–50

–60
–70

–80

1 [T1] 0.31dBm

–90
–95

CENTER 315MHz 40MHz/

0.31dBm

315.40080160MHz

315.40080160MHz

Figure 6. Spurious Components—Meets FCC Specs

= NORMAL
FREQUENCY = 9.08 kHz
LEVEL = –84.47dBc/Hz

= 3.0 V, ICP = 0.86 mA

DD

RBW

5kHz

VBW

5kHz

SWT

500ms

21

RBW

500kHz

VBW

500kHz

SWT

5ms

1

30dB

RF ATT

dBm

UNIT

30dB

RF ATT

dBm

UNIT

SPAN 400MHz

04617-0-004

A

1MA

04617-0-005

A

1MA

04617-0-006

REF LVL
5dBm

5

1

0
–10
–20
–30

–40

–50

–60
–70

–80
–90

–95

3

4

2

1 [T1] 0.27dBm
2 [T1]

0.27dBm

308.61723447MHz

308.61723447MHz
–35.43dBm

631.26252505MHz

Figure 7. Harmonic Response, RF

REF LVL
5dBm

5

1

0
–10
–20
–30

–40

–50

–60
–70

–80
–90

–95

3

2

4

1 [T1] 0.18dBm

308.61723447MHz

2 [T1]

631.26252505MHz

CENTER 3.5MHz 700MHz/

0.18dBm

308.61723447MHz

–50.53dBm

RBW

1MHz

VBW

1MHz

SWT

17.5ms

3 [T1]

939.87975952MHz

4 [T1]

1.26252505GHz

Matched to 50 Ω, No Filter

OUT

RBW

1MHz

VBW

1MHz

SWT

17.5ms

3 [T1]

939.87975952MHz

4 [T1]

1.26252505GHz

RF ATT
UNIT

D1 –41.5dBm

–11.48dBm
–34.11dBm

RF ATT
UNIT

D1 –41.5dBm

–42.93dBm
–55.48dBm

SPAN 7GHz

30dB

dBm

1MA

30dB

dBm

Figure 8. Harmonic Response, Fifth-Order Butterworth Filter

REF LVL
5dBm

5

0
–10
–20
–30

–40

–50

–60

1 [T1] –3.49dBm

–70

3 [T1]

–80

2 [T1]

–90
–95

20.33dBm

26.55310621kHz

2 3

315.00012525MHz
–20.33dB

26.55310621kHz
–20.85dB

–27.55511022kHz

RBW
VBW
SWT

1

5kHz
5kHz

500ms

RF ATT
UNIT

dBm

30dB

Figure 9. OOK Modulation, Power = 0 dBm, Data Rate = 10 kbps

A

04617-0-007

A

SGL

1MA

04617-0-008

A

1MA

04617-0-009

Rev. 0 | Page 8 of 28

ADF7012

433 MHZ

40dB

2 1.00V/ 1.50ms 720mv500µs TRIG'D 1

1 2.00V/

2

CLKOUT

1

CE

Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms

–40

–60

–80

–100

–120

dBc (Hz)

–140

–160

–180

–200

1.0k 10.0k 100.0k 1.0M 10.0M
PHASE NOISE (Hz)

Figure 11. Phase Noise Response—ICP = 2.0 mA, I

RF

= 433.92 MHz, PFD = 4 MHz, PA Bias = 5.5 mA

OUT

REF LVL
15dBm

15
10

0
–10
–20

–30

D1 –36dBm

–40

–50
–60

–70
–80

–85

START 433.05MHz 174kHz/ STOP 434.79kHz

5.60dBm

433.91158317MHz

= NORMAL
FREQUENCY = 393.38 kHz
LEVEL = –102.34dBc/Hz

RBW

10kHz

VBW

300kHz

SWT

44ms

1

VCO

RF ATT
UNIT

= 2.0 mA,

40dB

dBm

04617-0-010

A

1MA

04617-0-012

04617-0-011

REF LVL
15dBm

15
10

0
–10
–20

–30

D1 –36dBm

–40

–50
–60

–70
–80

–85

CENTER 433.9500601MHz 3.2MHz/ SPAN 32MHz

10.01dBm

433.91158317MHz

RBW
VBW
SWT

1

Figure 13. Spurious Components—Meets ETSI Specs

REF LVL
15dBm

15

1

10

0
–10
–20

–30

–40

–50
–60

–70
–80

–85

2

1 [T1] 10.10dBm
2 [T1]

CENTER 3.5GHz 700MHz/ SPAN 7GHz

10.10dBm

434.86973948MHz

3

4

434.86973948MHz
–15.25dBm

869.73947896MHz

Figure 14. Harmonic Response, RF

REF LVL
15dBm

15

1

10

0
–10
–20

–30

–40

–50
–60

–70
–80

–85

2

3

1 [T1] 9.51dBm

434.86973948MHz

2 [T1]

869.73947896MHz

CENTER 3.5GHz 700MHz/ SPAN 7GHz

9.51dBm

434.86973948MHz

4

–33.75dBm

RBW
VBW
SWT

3 [T1]
4 [T1]

Matched to 50 Ω, No Filter

OUT

RBW
VBW
SWT

3 [T1]
4 [T1]

30kHz
30kHz

90ms

1MHz
1MHz

17.5ms

D1 –30dBm
D1 –36dBm

1.30460922GHz
–17.57dBm

1.73947896GHz

1MHz
1MHz

17.5ms

D1 –30dBm
D1 –36dBm

–43.60dBm

1.30460922GHz
–43.44dBm

1.73947896GHz

RF ATT
UNIT

RF ATT
UNIT

–5.12dBm

RF ATT
UNIT

dBm

A

1MA

04617-0-013

40dB

dBm

A

1MA

04617-0-014

40dB

dBm

A

SGL

1MA

04617-0-015

Figure 12. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, F

= ±19.28 kHz

DEVIATION

Rev. 0 | Page 9 of 28

Figure 15. Harmonic Response, Fifth-Order Butterworth Filter