ANALOG DEVICES ADF4360-9 Service Manual

A

V

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Clock Generator PLL with Integrated VCO

FEATURES

Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Software power-down mode

APPLICATIONS

System clock generation
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

DD

ADF4360-9

REF

CLK

DATA

IN

LE

14-BIT R

COUNTER

24-BIT DATA

REGISTER

13-BIT B

COUNTER

N = B

24-BIT

FUNCTION

LATCH

ADF4360-9

GENERAL DESCRIPTION

The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.

An additional divider stage allows division of the VCO signal.
The CM
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.

Control of all the on-chip registers is through a simple 3-wire
in
from 3.0 V to 3.6 V and can be powered down when not in use.

DV

DD

OS level output is equivalent to the VCO signal divided

terface. The device operates with a power supply ranging

R

SET

LD

LOCK

DETECT

PHASE

COMPARATOR

VCO

CORE

MUTE

CHARGE

PUMP

OUTPUT

STAGE

CP

V

V

L1
L2
C
C

RF

RF

VCO

TUNE

C

N

OUT

OUT

A

B

AGND DGND CPGND

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

DIVIDE-BY-A

(2 TO 31)

DIVIDE-BY-2

MULTIPLEXER

DIVOUT

07139-001

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADF4360-9

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transi s t o r Cou n t ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

N Counter.................................................................................... 10

R Counter ....................................................................................10

PFD and Charge Pump.............................................................. 10

Lock Detect .................................................................................10

Input Shift Register .................................................................... 10

VCO ............................................................................................. 11

Output Stage................................................................................ 12

DIVOUT Stage............................................................................ 12

Latch Structure ........................................................................... 13

Power-Up..................................................................................... 17

Control Latch.............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Choosing the Correct Inductance Value................................. 20

Encode Clock for ADC.............................................................. 20

GSM Test Clock.......................................................................... 21

Interfacing ................................................................................... 22

PCB Design Guidelines for Chip Scale Package .................... 22

Output Matching........................................................................ 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

3/08—Rev. 0 to Rev. A

Changes to Table 1 ........................................................................... 3

Changes to Figure 23...................................................................... 14

Changes to Output Matching Section.......................................... 23

1/08—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4360-9

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SPECIFICATIONS

AVDD = DVDD = V

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

VCO

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/MHz max

REFIN Input Sensitivity 0.7/AV
0 to AV

V p-p min/V p-p max AC-coupled

DD

V max CMOS-compatible

DD

For f < 10 MHz, use a dc-coupled, CMOS-compatible

e wave, slew rate > 21 V/μs

squar

REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±60 μA max

PHASE DETECTOR

Phase Detector Frequency

2

8 MHz max

CHARGE PUMP

ICP Sink/Source

3

With R

= 4.7 kΩ

SET

High Value 2.5 mA typ
Low Value 0.312 mA typ
R

Range 2.7/10 kΩ min/kΩ max

SET

ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. V

CP

1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V

ICP vs. Temperature 2 % typ VCP = 2.0 V

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INH/IINL

Input Capacitance, C

INH

0.6 V max

INL

IN

1.5 V min

±1 μA max

3.0 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output High Current, I
Output Low Voltage, V

OH

OH

OL

DVDD − 0.4 V min CMOS output chosen
500 μA max

0.4 V max IOL = 500 μA

POWER SUPPLIES

AV

DD

DV

DD

V

VCO

4

AI

DD

4

DI

DD

4, 5

I

VCO

4

I

RFOUT

Low Power Sleep Mode

RF OUTPUT CHARACTERISTICS

4

5

Maximum VCO Output Frequency 400 MHz

3.0/3.6 V min/V max
AV
AV

DD

DD

5 mA typ

2.5 mA typ

12.0 mA typ I

CORE

= 5 mA

3.5 to 11.0 mA typ RF output stage is programmable
7 μA typ

= 5 mA; depending on L1 and L2; see the

I

CORE

Choosing the Correct Inductance Value section
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 90/108 MHz min/MHz max

VCO Frequency Range 1.2 Ratio f
VCO Sensitivity 2 MHz/V typ

Lock Time

6

400 μs typ To within 10 Hz of final frequency

L1, L2 = 270 nH; see the Choosing the Correct

ductance Value section for other frequency values

In

MAX/fMIN

L1, L2 = 270 nH; see the Choosing the Correct

ductance Value section for other sensitivity values

In

1

Rev. A | Page 3 of 24

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Parameter B Version Unit Conditions/Comments

Frequency Pushing (Open Loop) 0.24 MHz/V typ
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load
Harmonic Content (Second) −16 dBc typ
Harmonic Content (Third) −21 dBc typ
Output Power

Output Power

Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/V max

VCO NOISE CHARACTERISTICS

VCO Phase Noise Performance

−117 dBc/Hz typ @ 100 kHz offset from carrier

−139 dBc/Hz typ @ 1 MHz offset from carrier

−140 dBc/Hz typ @ 3 MHz offset from carrier

−147 dBc/Hz typ @ 10 MHz offset from carrier

Normalized In-Band Phase Noise
In-Band Phase Noise
RMS Integrated Jitter
Spurious Signals Due to PFD Frequency

DIVOUT CHARACTERISTICS

Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)

DIVOUT = 180 MHz 1.4 ps rms A = 2, A output selected
DIVOUT = 95 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 80 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 52 MHz 1.4 ps rms

DIVOUT = 45 MHz 1.4 ps rms A = 4, A/2 output selected
DIVOUT = 10 MHz 1.6 ps rms

DIVOUT Duty Cycle

A Output 1/A × 100 % typ Divide-by-A selected
A/2 Output 50 % typ Divide-by-A/2 selected

1

Operating temperature range is −40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.

6

Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7

For more detail on using tuned loads, see the Output Matching section.

8

Using 50 Ω resistors to V

9

The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.

10

The phase noise is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer.

11

f

= 10 MHz; f

REFIN

VCO and subtracting 20logN (where N is the N divider value) and 10logf

12

The jitter is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the

synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. f
noted.

13

The spurious signals are measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides

the REF

IN

5, 7

−9/0 dBm typ

Using tuned load, programmable in 3 dB steps;
see Figure 35

5, 8

−14/−9 dBm typ

Using 50 Ω resistors to V

, programmable in

VCO

3 dB steps; see Figure 33

9,10

10, 11

10, 11

12

12

−91 dBc/Hz typ @ 10 kHz offset from carrier

−218 dBc/Hz typ

−110 dBc/Hz typ @ 1 kHz offset from carrier

1.4 ps typ Measured at RF

13

−75 dBc typ

OUT

A

VCO frequency = 320 MHz to 380 MHz

A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MH

z)

A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MH

= 3.3 V.

VCO

into a 50 Ω load.

VCO

= 1 MHz; N = 360; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the

PFD

for the synthesizer; f

= 10 MHz @ 0 dBm. f

REFIN

= 10 MHz; f

REFIN

. PN

= PN

PFD

SYNTH

= 1 MHz; N = 360; loop BW = 40 kHz.

PFD

− 10logf

TOT

= 10 MHz; f

REFIN

PFD

− 20logN.

z)

= 1 MHz; N = 360; loop BW = 40 kHz, unless otherwise

PFD

Rev. A | Page 4 of 24

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TIMING CHARACTERISTICS

AVDD = DVDD = V

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

1

Table 2.

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

1

Refer to the Power-Up section for the recommended power-up procedure for this device.

20 ns min LE setup time
10 ns min DATA to CLK setup time
10 ns min DATA to CLK hold time
25 ns min CLK high duration
25 ns min CLK low duration
10 ns min CLK to LE setup time
20 ns min LE pulse width

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t

4

CLK

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

3

t

5

DB1

(CONTROL BIT C2)

to T

MIN

(CONTROL BIT C1)

, unless otherwise noted.

MAX

DB0 (LSB)

t

7

t

1

LE

t

6

07139-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4360-9

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND
AVDD to DV
V

to GND −0.3 V to +3.9 V

VCO

V

to AV

VCO

Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance

Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

GND = CPGND = AGND = DGND = 0 V.

1

DD

DD

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an

D rating of <1 kV, and it is ESD sensitive. Proper precautions

ES
should be taken for handling and assembly.

TRANSISTOR COUNT

The transistor count is 12,543 (CMOS) and 700 (bipolar).

ESD CAUTION

Rev. A | Page 6 of 24

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

AGND

DV

LD

CP

DIVOUT

LE

20

19

22

21

23

24

PIN 1
INDICATOR

1CPGND
2AV

DD

ADF4360-9

3AGND

A

4RF
5RF
6V

TOP VIEW

(Not to Scale)

9

7

8

L1

TUNE

V

AGND

OUT
OUT

B

VCO

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AV

DD

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF

5 RF

6 V

VCO

OUT

OUT

A

B

VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a

description of the v

arious output stages.

VCO Complementary Output. The output level is pr

atching section for a description of the various output stages.

M

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. V
7 V

TUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

output voltage.
9 L1

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output fr

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output fr

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 C
13 R

C

SET

Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the

synthesizer. The nominal voltage potential at the R

14 C

= 11.75/R

I

CPmax

For example, R

N

Internal Compensation Node. This pin must be decoupled to V

SET

= 4.7 kΩ and I

SET

CPmax

= 2.5 mA.

15 DGND Digital Ground.
16 REF

IN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK

Serial Clock Input. This serial clock is used to clock in the ser

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA

Serial Data Input. The serial da

ta is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.
19 LE

Load Enable, CMOS Input. When LE goes high, the data stor

four latches, and the relevant latch is selected using the control bits.
20 DIVOUT

This output allows the user to select VCO frequenc

Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21 DV

DD

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV
23 LD Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24 CP

Charge Pump Output. When enabled, this provides ±I

internal VCO.

18 DATA
17 CLK
16 REF

IN

15 DG ND
14 C

N

13 R

SET

11

10

12

C

L2

C

AGND

07139-003

must have the same value as DVDD.

DD

ogrammable from 0 dBm to −9 dBm. See the Output

must have the same value as AVDD.

VCO

pin is 0.6 V. The relationship between ICP and R

SET

with a 10 μF capacitor.

VCO

ial data to the registers. The data is latched into the

ed in the shift registers is loaded into one of the

y divided by A or VCO frequency divided by 2A.

must have the same value as AVDD.

DD

to the external loop filter, which in turn drives the

CP

equency. L1 and

equency. L1 and

is

SET

Rev. A | Page 7 of 24

ADF4360-9

–

–

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–

–

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TYPICAL PERFORMANCE CHARACTERISTICS

20

–40

–60

–80

–100

–120

PHASE NOISE (dBc/Hz)

–140

–160

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH

07139-004

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A/2 Selected, A = 2

07139-007

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1k 10M

FREQUENCY OF FSET (Hz)

07139-005

Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth,

R

MS Jitter = 1.4 ps

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

07139-006

Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A Selected, A = 2

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A/2 Selected, A = 2

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M

FREQUENCY OF FSET (Hz)

Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz,

PFD F

requency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps,

Divide-by-A/2 Selected, A = 3

07139-008

07139-009

Rev. A | Page 8 of 24