Datasheet ADF4360-9 Datasheet (ANALOG DEVICES)

A

V

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Clock Generator PLL with Integrated VCO

FEATURES

Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Software power-down mode

APPLICATIONS

System clock generation
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

DD

ADF4360-9

REF

CLK

DATA

IN

LE

14-BIT R

COUNTER

24-BIT DATA

REGISTER

13-BIT B

COUNTER

N = B

24-BIT

FUNCTION

LATCH

ADF4360-9

GENERAL DESCRIPTION

The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.

An additional divider stage allows division of the VCO signal.
The CM
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.

Control of all the on-chip registers is through a simple 3-wire
in
from 3.0 V to 3.6 V and can be powered down when not in use.

DV

DD

OS level output is equivalent to the VCO signal divided

terface. The device operates with a power supply ranging

R

SET

LD

LOCK

DETECT

PHASE

COMPARATOR

VCO

CORE

MUTE

CHARGE

PUMP

OUTPUT

STAGE

CP

V

V

L1
L2
C
C

RF

RF

VCO

TUNE

C

N

OUT

OUT

A

B

AGND DGND CPGND

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

DIVIDE-BY-A

(2 TO 31)

DIVIDE-BY-2

MULTIPLEXER

DIVOUT

07139-001

Figure 1.

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Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

ADF4360-9

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transi s t o r Cou n t ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

N Counter.................................................................................... 10

R Counter ....................................................................................10

PFD and Charge Pump.............................................................. 10

Lock Detect .................................................................................10

Input Shift Register .................................................................... 10

VCO ............................................................................................. 11

Output Stage................................................................................ 12

DIVOUT Stage............................................................................ 12

Latch Structure ........................................................................... 13

Power-Up..................................................................................... 17

Control Latch.............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Choosing the Correct Inductance Value................................. 20

Encode Clock for ADC.............................................................. 20

GSM Test Clock.......................................................................... 21

Interfacing ................................................................................... 22

PCB Design Guidelines for Chip Scale Package .................... 22

Output Matching........................................................................ 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

3/08—Rev. 0 to Rev. A

Changes to Table 1 ........................................................................... 3

Changes to Figure 23...................................................................... 14

Changes to Output Matching Section.......................................... 23

1/08—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4360-9

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SPECIFICATIONS

AVDD = DVDD = V

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

VCO

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/MHz max

REFIN Input Sensitivity 0.7/AV
0 to AV

V p-p min/V p-p max AC-coupled

DD

V max CMOS-compatible

DD

For f < 10 MHz, use a dc-coupled, CMOS-compatible

e wave, slew rate > 21 V/μs

squar

REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±60 μA max

PHASE DETECTOR

Phase Detector Frequency

2

8 MHz max

CHARGE PUMP

ICP Sink/Source

3

With R

= 4.7 kΩ

SET

High Value 2.5 mA typ
Low Value 0.312 mA typ
R

Range 2.7/10 kΩ min/kΩ max

SET

ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. V

CP

1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V

ICP vs. Temperature 2 % typ VCP = 2.0 V

LOGIC INPUTS

Input High Voltage, V
Input Low Voltage, V
Input Current, I

INH/IINL

Input Capacitance, C

INH

0.6 V max

INL

IN

1.5 V min

±1 μA max

3.0 pF max

LOGIC OUTPUTS

Output High Voltage, V
Output High Current, I
Output Low Voltage, V

OH

OH

OL

DVDD − 0.4 V min CMOS output chosen
500 μA max

0.4 V max IOL = 500 μA

POWER SUPPLIES

AV

DD

DV

DD

V

VCO

4

AI

DD

4

DI

DD

4, 5

I

VCO

4

I

RFOUT

Low Power Sleep Mode

RF OUTPUT CHARACTERISTICS

4

5

Maximum VCO Output Frequency 400 MHz

3.0/3.6 V min/V max
AV
AV

DD

DD

5 mA typ

2.5 mA typ

12.0 mA typ I

CORE

= 5 mA

3.5 to 11.0 mA typ RF output stage is programmable
7 μA typ

= 5 mA; depending on L1 and L2; see the

I

CORE

Choosing the Correct Inductance Value section
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 90/108 MHz min/MHz max

VCO Frequency Range 1.2 Ratio f
VCO Sensitivity 2 MHz/V typ

Lock Time

6

400 μs typ To within 10 Hz of final frequency

L1, L2 = 270 nH; see the Choosing the Correct

ductance Value section for other frequency values

In

MAX/fMIN

L1, L2 = 270 nH; see the Choosing the Correct

ductance Value section for other sensitivity values

In

1

Rev. A | Page 3 of 24

ADF4360-9

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Parameter B Version Unit Conditions/Comments

Frequency Pushing (Open Loop) 0.24 MHz/V typ
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load
Harmonic Content (Second) −16 dBc typ
Harmonic Content (Third) −21 dBc typ
Output Power

Output Power

Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/V max

VCO NOISE CHARACTERISTICS

VCO Phase Noise Performance

−117 dBc/Hz typ @ 100 kHz offset from carrier

−139 dBc/Hz typ @ 1 MHz offset from carrier

−140 dBc/Hz typ @ 3 MHz offset from carrier

−147 dBc/Hz typ @ 10 MHz offset from carrier

Normalized In-Band Phase Noise
In-Band Phase Noise
RMS Integrated Jitter
Spurious Signals Due to PFD Frequency

DIVOUT CHARACTERISTICS

Integrated Jitter Performance
(Integrated from 100 Hz to 1 GHz)

DIVOUT = 180 MHz 1.4 ps rms A = 2, A output selected
DIVOUT = 95 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 80 MHz 1.4 ps rms A = 2, A/2 output selected
DIVOUT = 52 MHz 1.4 ps rms

DIVOUT = 45 MHz 1.4 ps rms A = 4, A/2 output selected
DIVOUT = 10 MHz 1.6 ps rms

DIVOUT Duty Cycle

A Output 1/A × 100 % typ Divide-by-A selected
A/2 Output 50 % typ Divide-by-A/2 selected

1

Operating temperature range is −40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.

6

Jumping from 90 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7

For more detail on using tuned loads, see the Output Matching section.

8

Using 50 Ω resistors to V

9

The noise of the VCO is measured in open-loop conditions. L1, L2 = 56 nH.

10

The phase noise is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer.

11

f

= 10 MHz; f

REFIN

VCO and subtracting 20logN (where N is the N divider value) and 10logf

12

The jitter is measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. A low noise TCXO provides the REFIN for the

synthesizer, and the jitter is measured over the instrument’s jitter measurement bandwidth. f
noted.

13

The spurious signals are measured with the EVAL-ADF4360-9EBZ1 evaluation board and the Agilent E5052A signal source analyzer. The spectrum analyzer provides

the REF

IN

5, 7

−9/0 dBm typ

Using tuned load, programmable in 3 dB steps;
see Figure 35

5, 8

−14/−9 dBm typ

Using 50 Ω resistors to V

, programmable in

VCO

3 dB steps; see Figure 33

9,10

10, 11

10, 11

12

12

−91 dBc/Hz typ @ 10 kHz offset from carrier

−218 dBc/Hz typ

−110 dBc/Hz typ @ 1 kHz offset from carrier

1.4 ps typ Measured at RF

13

−75 dBc typ

OUT

A

VCO frequency = 320 MHz to 380 MHz

A = 3, A/2 output selected (VCO = 312 MHz,
PFD = 1.6 MH

z)

A = 18, A/2 output selected (VCO = 360 MHz,
PFD = 1.6 MH

= 3.3 V.

VCO

into a 50 Ω load.

VCO

= 1 MHz; N = 360; loop B/W = 40 kHz. The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the

PFD

for the synthesizer; f

= 10 MHz @ 0 dBm. f

REFIN

= 10 MHz; f

REFIN

. PN

= PN

PFD

SYNTH

= 1 MHz; N = 360; loop BW = 40 kHz.

PFD

− 10logf

TOT

= 10 MHz; f

REFIN

PFD

− 20logN.

z)

= 1 MHz; N = 360; loop BW = 40 kHz, unless otherwise

PFD

Rev. A | Page 4 of 24

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TIMING CHARACTERISTICS

AVDD = DVDD = V

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

1

Table 2.

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

1

Refer to the Power-Up section for the recommended power-up procedure for this device.

20 ns min LE setup time
10 ns min DATA to CLK setup time
10 ns min DATA to CLK hold time
25 ns min CLK high duration
25 ns min CLK low duration
10 ns min CLK to LE setup time
20 ns min LE pulse width

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t

4

CLK

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

3

t

5

DB1

(CONTROL BIT C2)

to T

MIN

(CONTROL BIT C1)

, unless otherwise noted.

MAX

DB0 (LSB)

t

7

t

1

LE

t

6

07139-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4360-9

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND
AVDD to DV
V

to GND −0.3 V to +3.9 V

VCO

V

to AV

VCO

Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance

Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

GND = CPGND = AGND = DGND = 0 V.

1

DD

DD

−0.3 V to +3.9 V

−0.3 V to +0.3 V

−0.3 V to +0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an

D rating of <1 kV, and it is ESD sensitive. Proper precautions

ES
should be taken for handling and assembly.

TRANSISTOR COUNT

The transistor count is 12,543 (CMOS) and 700 (bipolar).

ESD CAUTION

Rev. A | Page 6 of 24

ADF4360-9

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

AGND

DV

LD

CP

DIVOUT

LE

20

19

22

21

23

24

PIN 1
INDICATOR

1CPGND
2AV

DD

ADF4360-9

3AGND

A

4RF
5RF
6V

TOP VIEW

(Not to Scale)

9

7

8

L1

TUNE

V

AGND

OUT
OUT

B

VCO

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AV

DD

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF

5 RF

6 V

VCO

OUT

OUT

A

B

VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a

description of the v

arious output stages.

VCO Complementary Output. The output level is pr

atching section for a description of the various output stages.

M

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. V
7 V

TUNE

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

output voltage.
9 L1

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output fr

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2

An external inductor to AGND should be connected to this pin to set the ADF4360-9 output fr

L2 need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 C
13 R

C

SET

Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the

synthesizer. The nominal voltage potential at the R

14 C

= 11.75/R

I

CPmax

For example, R

N

Internal Compensation Node. This pin must be decoupled to V

SET

= 4.7 kΩ and I

SET

CPmax

= 2.5 mA.

15 DGND Digital Ground.
16 REF

IN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK

Serial Clock Input. This serial clock is used to clock in the ser

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA

Serial Data Input. The serial da

ta is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.
19 LE

Load Enable, CMOS Input. When LE goes high, the data stor

four latches, and the relevant latch is selected using the control bits.
20 DIVOUT

This output allows the user to select VCO frequenc

Alternatively, the scaled RF, or the scaled reference frequency, can be accessed externally through this output.
21 DV

DD

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV
23 LD Lock Detect. The output on this pin is logic high to indicate that the part is in lock. Logic low indicates loss of lock.
24 CP

Charge Pump Output. When enabled, this provides ±I

internal VCO.

18 DATA
17 CLK
16 REF

IN

15 DG ND
14 C

N

13 R

SET

11

10

12

C

L2

C

AGND

07139-003

must have the same value as DVDD.

DD

ogrammable from 0 dBm to −9 dBm. See the Output

must have the same value as AVDD.

VCO

pin is 0.6 V. The relationship between ICP and R

SET

with a 10 μF capacitor.

VCO

ial data to the registers. The data is latched into the

ed in the shift registers is loaded into one of the

y divided by A or VCO frequency divided by 2A.

must have the same value as AVDD.

DD

to the external loop filter, which in turn drives the

CP

equency. L1 and

equency. L1 and

is

SET

Rev. A | Page 7 of 24

ADF4360-9

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TYPICAL PERFORMANCE CHARACTERISTICS

20

–40

–60

–80

–100

–120

PHASE NOISE (dBc/Hz)

–140

–160

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 4. Open-Loop VCO Phase Noise at 218 MHz, L1, L2 = 56 nH

07139-004

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 7. DIVOUT Phase Noise, 95 MHz, VCO = 380 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A/2 Selected, A = 2

07139-007

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1k 10M

FREQUENCY OF FSET (Hz)

07139-005

Figure 5. VCO Phase Noise, 360 MHz, 1 MHz PFD, 40 kHz Loop Bandwidth,

R

MS Jitter = 1.4 ps

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

07139-006

Figure 6. DIVOUT Phase Noise, 180 MHz, VCO = 360 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A Selected, A = 2

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

Figure 8. DIVOUT Phase Noise, 80 MHz, VCO = 320 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.3 ps,

Divide-by-A/2 Selected, A = 2

60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

100 1k 10k 100k 1M

FREQUENCY OF FSET (Hz)

Figure 9. DIVOUT Phase Noise, 52 MHz, VCO = 312 MHz,

PFD F

requency = 1.6 MHz, Loop Bandwidth = 40 kHz, Jitter = 1.4 ps,

Divide-by-A/2 Selected, A = 3

07139-008

07139-009

Rev. A | Page 8 of 24

ADF4360-9

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60

–70

–80

–90

–100

–110

–120

–130

PHASE NOISE (dBc/Hz)

–140

–150

–160

1k100 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

Figure 10. DIVOUT Phase Noise, 45 MHz, VCO = 360 MHz,

PFD F

requency = 1.6 MHz, Loop Bandwidth = 60 kHz, Jitter = 1.4 ps,

Divide-by-A/2 Selected, A = 2

100

+25°C

–110

–120

–40°C
+85°C

07139-010

CH1 500mV M 2.00ns1A CH1 20mV

Figure 13. DIVOUT 90 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,

= 4, Duty Cycle = ~25%

A

C1 FREQUENCY: 90MHz
C1 + DUTY: 28.98%
C1 PEAK TO PEAK: 1.55V

07139-013

–130

–140

PHASE NOISE (dBc/Hz)

–150

–160

1k 10k 100k 1M 10M

FREQUENCY OF FSET (Hz)

07139-011

Figure 11. DIVOUT Phase Noise over Temperature, 52 MHz, VCO = 312 MHz,

PFD F

requency = 1 MHz, Loop Bandwidth = 60 kHz,

Divide-by-A/2 Selected, A = 3

C1 FREQUENCY: 180MHz
C1 + DUTY: 45.32%

1

CH1 500mV M 2.00ns A CH1 20mV

07139-012

Figure 12. DIVOUT 180 MHz Waveform, VCO = 360 MHz,

Divide-by-A S

elected, A = 2, Duty Cycle = ~50%

1

C1 FREQUENCY: 36. 01MHz
C1 + DUTY: 13.13%
C1 PEAK TO PEAK 1. 28V

CH1 500mV M 5.00ns A CH1 920mV

07139-014

Figure 14. DIVOUT 36 MHz Waveform, VCO = 360 MHz, Divide-by-A Selected,

= 10, Duty Cycle = ~10%

A

1

C1 FREQUENCY: 36M Hz
C1 + DUTY: 49.41%

CH1 500mV M 12.5ns A CH1 920mV

07139-015

Figure 15. DIVOUT 36 MHz Waveform, VCO = 360 MHz,

Divide-by-A/2 S

elected, A = 5, Duty Cycle = ~50%

Rev. A | Page 9 of 24

ADF4360-9

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CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches, and SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
power-down.

POWER-DOWN

CONTROL

100kΩ

NC

SW1

SW2

SW3

NO

REF

IN

NC

Figure 16. Reference Input Stage

BUFFER

TO R COUNTER

N COUNTER

The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is
referred to as the B counter. It makes it possible to generate
output frequencies that are spaced only by the reference
frequency divided by R. The VCO frequency equation is

f

VCO

= B × f

REFIN

/R

where:

f

is the output frequency of the VCO.

VCO

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
f

is the external reference frequency oscillator.

REFIN

R COUNTER

The 14-bit R counter allows the input reference frequency
to be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N = B)
and produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The P

FD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function and
minimizes phase noise and reference spurs. Two bits in the R
counter latch, ABP2 and ABP1, control the width of the pulse
(see

Figure 25).

pin at

IN

07139-016

V

P

CHARGE

PUMP

HI

R DIVIDER

HI

N DIVIDER

R DIVIDER

N DIVIDER

CP OUTPUT

Figure 17. PFD Simplified Schematic and Timing (In Lock)

Q1D1

U1

CLR1

PROGRAMMABLE

ABP1 ABP2

CLR2

Q2D2

U2

UP

DELAY

DOWN

U3

CPGND

CP

LOCK DETECT

The LD pin outputs a lock detect signal. Digital lock detect is
active high. When lock detect precision (LDP) in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is <15 ns.

When LDP is set to 1, five consecutive cycles of <15 ns phase
er

ror are required to set the lock detect. It stays set high until a

phase error of >25 ns is detected on any subsequent PD cycle.

INPUT SHIFT REGISTER

The digital section of the ADF4360 family includes a 24-bit
input shift register, a 14-bit R counter, and an 18-bit N counter,
comprising a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in

Figure 2.

07139-017

Rev. A | Page 10 of 24

ADF4360-9

www.BDTIC.com/ADI

The truth table for these bits is shown in Tab le 5 . Figure 22
shows a summary of how the latches are programmed. Note
that the test modes latch is used for factory testing and should
not be programmed by the user.

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1

Data Latch

0 0 Control
0 1 R Counter
1 0 N Counter (B)
1 1 Test Modes

VCO

The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 18, to allow a wide frequency range

be covered without a large VCO sensitivity (K

to
poor phase noise and spurious performance.

The correct band is chosen automatically by the band select
log

ic at power-up or whenever the N counter latch is updated.
It is important that the correct write sequence be followed at
power-up. The correct write sequence is as follows:

1. R

Counter Latch

2. Co

ntrol Latch

3. N C

ounter Latch

During band selection, which takes five PFD cycles, the VCO
V

is disconnected from the output of the loop filter and

TUNE

connected to an internal reference voltage.

) and resultant

V

3.5

3.0

2.5

2.0

(V)

TUNE

V

1.5

1.0

0.5

0

80 85 90 10095 105 115110

Figure 18. V

TUNE

FREQUENCY ( MHz)

, ADF4360-9, L1 and L2 = 270 nH vs. Frequency

07139-019

The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by the BSC1 bit and the BSC2 bit in the R counter
latch. Where the required PFD frequency exceeds 1 MHz, the
divide ratio should be set to allow enough time for correct band
selection. For many applications, it is usually best to set this to 8.

After band selection, normal PLL action resumes. The value of
K

is determined by the value of the inductors used (see the

V

Choosing the Correct Inductance Value section). The ADF4360
fa

mily contains linearization circuitry to minimize any variation

of the product of I

and KV.

CP

The operating current in the VCO core is programmable in four

teps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by

s
the PC1 bit and the PC2 bit in the control latch.

It is strongly recommended that only the 5 mA setting be used.
H

owever, in applications requiring a low VCO frequency, the
high temperature coefficient of some inductors may lead to the
VCO tuning voltage varying as temperature changes. The 7.5 mA
VCO core power setting shows less tuning voltage variation over
temperature in these applications and can be used, provided that
240 Ω resistors are used in parallel with Pin 9 and Pin 10, instead of
the default 470 Ω.

Rev. A | Page 11 of 24

ADF4360-9

A

A

www.BDTIC.com/ADI

OUTPUT STAGE

The RF
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 19. To
a

llow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch.
Four current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −9 dBm, −6 dBm,

−3 dBm, and 0 dBm, respectively, using the correct shunt inductor
to V
outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).

Another feature of the ADF4360 family is that the supply

urrent to the RF output stage is shut down until the part

c
achieves lock, as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.

A and RF

OUT

and ac coupling into a 50 Ω load. Alternatively, both

DD

VCO

B pins of the ADF4360 family are

OUT

OUT

RF

OUT

RF

BUFFER

B

DV

DD

COUNTER/2 OUT PUT

A COUNTER OUTPUT

R COUNTER OUTPUT

N COUNTER OUTPUT

CONTROLMUX

Figure 20. DIVOUT Circuit

DIVOUT

DGND

The primary use of this pin is to derive the lower frequencies
from the VCO by programming various divider values to the
auxiliary A divider. Values ranging from 2 to 31 are possible.
The duty cycle of this output is 1/A times 100%, with the logic
high pulse width equal to the inverse of the VCO frequency.
That is,

Pulse Width [secon

ds] = 1/f

(Frequency [Hz])

VCO

See Figure 21 for a graphical description. By selecting the

e-by-2 function, this divided down frequency can in turn

divid
be divided by 2 again. This provides a 50% duty cycle in contrast to
the A counter output, which may be more suitable for some
applications (see

f

VCO

Figure 21).

07139-018

07139-020

Figure 19. RF Output Stage

DIVOUT STAGE

The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of DIVOUT
is controlled by D3, D2, and D1 in the control latch. The full
truth table is shown in

ection in block diagram form.

s

Figure 23. Figure 20 shows the DIVOUT

f

/A (A = 4)

VCO

f

/2A (A = 4)

VCO

07139-021

Figure 21. DIVOUT Wa

veforms

Rev. A | Page 12 of 24

ADF4360-9

www.BDTIC.com/ADI

LATCH STRUCTURE

Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.

CONTROL L ATCH

RESERVED

RESERVED

RESERVED

CURRENT

DOWN 2

POWER-

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

PD2RSVRSV

CP GAIN

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CPGRSVRSV

BAND

SELECT

CLOCK

RESERVED

DB21

DB22DB23

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BSC2RSVRSV

SETTING 2

DOWN 1

POWER-

LOCK

PULSE WIDTH

DETECT

PRECISION

BACKLASH

BIT

TEST MODE

ANTI-

CURRENT

SETTING 1

13-BIT B COUNTER

OUTPUT

POWER

LEVEL

N COUNTER LAT CH

R COUNTER LAT CH

LD

MUTE-TILL-

CP

STATE

PHASE

THREE-

CP GAIN

14-BIT REFERENCE COUNTER

DETECTOR

DIVOUT

CONTROL

POLARIT Y

5-BIT DIVO UT

RESERVED

COUNTER

RESET

CORE

POWER

LEVEL

PC1PC2CRD1D2PDPCPCP GMTLDPL1PL2CPI1CPI2CPI3CPI 4CP I5CPI6PD1 D3

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTROL

BITS

C2 (0) C1 (0)

CONTROL

BITS

C2 (1) C1 (0)

CONTROL

BITS

C2 (0) C1 (1)

07139-034

Figure 22. Latch Structure

Rev. A | Page 13 of 24

ADF4360-9

www.BDTIC.com/ADI

RESERVED

I

CP

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

(mA)

–9dBm
–6dBm
–3dBm
0dBm

OUTPUT

POWER

LEVEL

LD

CP GAIN

MUTE-TILL-

CP
0
1

CP GAIN

CPG

0

CURRENT SETTING 1
CURRENT SETTING 2

1

MUTE-TIL -LOCK DET ECT

MTLD
0

DISABLED
ENABLED

1

USING 5 0Ω TO V

–19dBm
–15dBm
–12dBm
–9dBm

CP

STATE

PHASE

THREE-

PDP
0
1

CHARGE PUMP
OUTPUT

NORMAL
THREE-STATE

VCO

CURRENT

DOWN 2

POWER-

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

PD2RSVRSV

SETTING 2

DOWN 1

POWER-

CPI6 CPI 5 CPI4
CPI3 CPI 2 CPI1 4.7kΩ

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

PL2 PL1 OUTPUT POWER LEVEL

0
0
1
1

CURRENT

SETTING 1

0
1
0
1
0
1
0
1

CURRENT USING TUNED LOAD

0

3.5mA

1

5.0mA

0

7.5mA

1

11.0mA

DIVOUT

CONTROL

POLARITY

DETECTOR

PHASE DETECTOR
POLARITY

NEGATIVE
POSITIVE

D3 D2 D1
000
001

010
011

100
101
110
111

RESET

COUNTER

PC2

PC1

0

0

0

1

1

0

11

COUNTER
OPERATIO N

CR
0

NORMAL

1

R, A, B COUNTERS
HELD IN RESET

CORE

POWER

LEVEL

MUXOUT
DV
DIGITAL LOCK DETE CT
(ACTIVE HIG H)
N DIVIDER OUTPUT
DV
R DIVIDER OUTPUT
A CNTR/2 O UT
A CNTR OUT
DGND

CONTRO L

BITS

C2 (0) C1 (0)

PC1PC2CRD1D2PDPCPCPGMTL DPL1PL2CPI1CPI2CPI 3CPI4CPI5CPI 6PD1 D3

CORE PO WER LE VEL

2.5mA
5mA (RECOMMENDED)

7.5mA
10mA

DD

DD

CE PIN PD2 PD1 MODE
0 X X ASYNCHRONO US POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRO NOUS POWE R-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN

THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BIT S.

07139-022

Figure 23. Control Latch

Rev. A | Page 14 of 24

ADF4360-9

www.BDTIC.com/ADI

CONTRO L

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

BITS

C2 (1) C1 (0)

RESERVED

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CPGRSVRSV

THIS BIT IS NOT
USED BY THE
DEVICE AND IS A
DON'T CARE BIT.

RESERVED

5-BIT DIVOUT13-BIT B COUNT ER

B12

B13

0

0

0

0

0

0

0

0

.

.

.

.

.

.

1

1

1

1

1

1

1

1

CP GAIN OPERATION

0 CHARGE PUMP CURRENT SETTING 1

1 CHARGE PUMP CURRENT SETTING 2

THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BIT S.

IS PERMANENTLY USED

IS PERMANENTLY USED

B11
0
0
0
0
.
.
.
1
1
1
1

............

............

............

............

............

............

............

............

............

............

............

A5

A4

............

0

0
0
0
0
.
.
.
1
1
1
1

B COUNTER DIVIDE RATIO

B1

B2

B3

0

0

0

0

1

0

1

1

.

.

.

.

.

.

0

1

0

1

1

1

1

1

0
1
0
1
.
.
.
0
1
0
1

NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190
8191

............

0

............

0

............

0

............

.

............

.

............

.

............

1

............

1

............

1

............

1

A2
0
0
1
1
.
.
.
0
0
1
1

OUTPUT DIVI DE RATIO

A1

NOT ALLOWED

0

NOT ALLOWED

1

2

0

3

1

.

.

.

.

.

.

28

0

29

1

30

0

31

1

07139-023

Figure 24. N Counter Latch

Rev. A | Page 15 of 24

ADF4360-9

www.BDTIC.com/ADI

RESERVED

RESERVED

BAND

SELECT

CLOCK

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB 11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

BSC2RSVRSV

BIT

TEST

MODE

LOCK

DETECT

PRECISION

ANTI-

BACKLASH

PULSE
WIDTH

14-BIT REFE RENCE COUNTER

R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTRO L

BITS

C2 (0) C1 (1)

TEST MODE
BIT SHOULD
BE SET TO 0

THESE BITS ARE
NOT USED BY
THE DEVICE
AND ARE DON'T
CARE BITS.

BSC2 BSC1 BAND SELECT CLOCK DIVI DER
001
01 2
104
118

FOR NORMAL

OPERATION.

LDP LO CK DETECT PRE CISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1 FIVE CONSE CUTIVE CYCL ES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LO CK DETECT I S SET.

15ns MUST OCCUR BEFORE LO CK DETECT I S SET.

R14 R13 R12 R3 R2 R1 DIVIDE RATIO

00 0
00 0
00 0

.. .
.. .

11 1
11 1
11 1

ABP2 ABP1 ANTI BACKLASH PULSE W IDTH
00 3.0ns
01 1.3ns
10 6.0ns
11 3.0ns

Figure 25. R Counter Latch

.......... 000 0

.......... 0 1 0 2

.......... 0 1 1 3

.......... 1 0 0 4

.......... ... .

.......... . . . .

.......... . . . .

.......... 111 1

.......... 1 0 1 16381

.......... 1 1 0 16382

.......... 1 1 1 16383

01 1

.. .

0 0 16380

07139-024

Rev. A | Page 16 of 24

ADF4360-9

www.BDTIC.com/ADI

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-9 after
power-up is as follows:

1. R

Counter Latch

2. Co

ntrol Latch

3. N C

Initial Power-Up

Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-9 during initial power-up to settle.

ounter Latch

, DVDD, and V

DD

pins. On

VCO

During initial power-up, a write to the control latch powers up

he part, and the bias currents of the VCO begin to settle. If

t
these currents have not settled to within 10% of their steady­state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-9 may not achieve lock. If the
recommended interval is inserted, and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.

The duration of this interval is affected by the value of the
ca

pacitor on the C

pin (Pin 14). This capacitor is used to

N

reduce the close-in noise of the ADF4360-9 VCO. The
recommended value of this capacitor is 10 μF. Using this
value requires an interval of ≥15 ms between the latching in
of the control latch bits and latching in of the N counter latch
bits. If a shorter delay is required, the capacitor can be reduced.
A slight phase noise penalty is incurred by this change, which is
further explained in

Tabl e 6.

Table 6. C

CN Valu e

Capacitance vs. Interval and Phase Noise

N

Recommended Interval Between
C

ontrol Latch and N Counter Latch

Open-Loop Phase Noise @ 10 kHz Offset

L1 and L2 = 18.0 nH L1 and L2 = 110.0 nH L1 and L2 = 560.0 nH

10 μF ≥15 ms −100 dBc/Hz −97 dBc/Hz −99 dBc/Hz
440 nF ≥600 μs −99 dBc/Hz −96 dBc/Hz −98 dBc/Hz

POWER-UP

CLK

DATA

R COUNTER

LATCH DATA

LE

CONTROL

LATCH DATA

Figure 26. Power-Up Timing

N COUNTER

LATCH DATA

REQUIRED INTERVAL

CONTROL LATCH WRITE TO

N COUNTER LATCH WRIT E

07139-033

Rev. A | Page 17 of 24

ADF4360-9

www.BDTIC.com/ADI

Software Power-Up/Power-Down

If the part is powered down via the software (using the control
latch) and powered up again without any change to the N counter
latch during power-down, the part locks at the correct frequency
because the part is already in the correct frequency band. The
lock time depends on the value of capacitance on the C
which is <15 ms for 10 μF capacitance. The smaller capacitance
of 440 nF on this pin enables lock times of <600 μs.

The N counter value cannot be changed while the part is in

ower-down because the part may not lock to the correct

p
frequency on power-up. If it is updated, the correct program­ming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and
N counter latch, as described in the

Initial Power-Up section.

pin,

N

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Figure 23
shows the input data format for programming the control latch.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power­down modes.

In the programmed asynchronous power-down, the device
p

owers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded in PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When a power-down is activated (either
synchronous or asynchronous mode), the following events occur:

ll active dc current paths are removed.

• A

• The R

• The cha

• The dig

• The RF

• T

, N, and timeout counters are forced to their load

state conditions.

rge pump is forced into three-state mode.

ital lock detect circuitry is reset.

outputs are debiased to a high impedance state.

he reference input buffer circuitry is disabled.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1. CPI6, CPI5, and CPI4 determine Current
Setting 2 (see the truth table in

Figure 23).

Output Power Level

Bit PL1 and Bit PL2 set the output power level of the VCO (see
the truth table in Figure 23).

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360 family is the mute­till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.

Charge Pump Three-State

This bit (DB9) puts the charge pump into three-state mode
when programmed to a 1. For normal operation, it should be
set to 0.

Phase Detector Polarity

The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.

DIVOUT Control

The on-chip multiplexer is controlled by D3, D2, and D1 (see
the truth table in Figure 23).

Counter Reset

DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The
recommended setting is 5 mA. The 7.5 mA setting is
permissible in some applications (see the truth table in Figure 23).

• The i

nput register remains active and capable of loading

and latching data.

Rev. A | Page 18 of 24

ADF4360-9

www.BDTIC.com/ADI

N COUNTER LATCH

Figure 24 shows the input data format for programming the
N counter latch.

5-Bit Divider

A5 to A1 program the output divider. The divide range is 2 (00010)
to 31 (11111). If unused, this divider should be set to 0. The output
or the output divided by 2 is available at the DIVOUT pin.

Reserved Bits

DB23, DB22, and DB7 are spare bits and are designated as
reserved. They should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3
(00 … 0011) to 8191 (11 … 111).

Overall Divide Range

The overall VCO feedback divide range is defined by B.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the
control latch. The bit always reflects the latest value written to it,
whether this is through the control latch or the N counter latch.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.
Figure 25 shows the input data format for programming the

unter latch.

R co

R Counter

R1 to R14 set the counter divide ratio. The divide range is
1 (00 … 001) to 16,383 (111 … 111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with <15 ns phase error for entering the locked
state. With LDP at 1, five cycles are taken; with LDP at 0, three
cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.

Band Select Clock

These bits (DB20 and DB21) set a divider for the band select
logic clock input. The output of the R counter is, by default, the
value used to clock the band select logic; if this value is too high
(>1 MHz), a divider can be switched on to divide the R counter
output to a smaller value (see
r

ecommended.

Reserved Bits

DB23 to DB22 are spare bits that are designated as reserved.
They should be programmed to 0.

Figure 25). A value of 8 is

Rev. A | Page 19 of 24

ADF4360-9

www.BDTIC.com/ADI

APPLICATIONS

CHOOSING THE CORRECT INDUCTANCE VALUE

The ADF4360-9 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 27 shows a graph of both minimum
a

nd maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.

The lowest center frequency of oscillation possible is approximately
65 MH

z, which is achieved using 560 nH inductors. This

relationship can be expressed by

=

O

where:

f

is the center frequency.

O

L

is the external inductance.

EXT

450

400

350

300

250

200

150

FREQUENCY (MHz)

100

50

0

0 100 200 300 400 600500

Figure 27. Output Center Frequency vs. External Inductor Value

The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 28 shows a graph of the tuning sensitivity (in MHz/V)
vs. t

he inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the previous equation; that is, because the
inductance increased, the change in capacitance from the
varactor has less of an effect on the frequency.

1

()

nH0.9pF9.32π

INDUCTANCE (nH)

Lf+

EXT

07139-025

12

10

8

6

4

SENSITIVITY (MHz/V)

2

0

0 100 200 300 400 600500

Figure 28. Tuning Sensitivity vs. Inductance

INDUCTANCE (nH)

07139-026

ENCODE CLOCK FOR ADC

Analog-to-digital converters (ADCs) require a sampling clock
for their operation. Generally, this is provided by TCXO or VCXOs,
which can be large and expensive. The frequency range is usually
quite limited. An alternative solution is the ADF4360-9, which can
be used to generate a CMOS clock signal suitable for use in all
but the most demanding converter applications.

Figure 29 shows an ADF4360-9 with a VCO frequency of 320 MHz
a

nd a DIVOUT frequency of 80 MHz. Because a 50% duty cycle
is preferred by most sampling clock circuitry, the A/2 mode is
selected. Therefore, A is programmed to 2, giving an overall
divide value of 4. The AD9215-80 is a 10-bit, 80 MSPS ADC

hat requires an encode clock jitter of 6 ps or less. The ADF4360-9

t
takes a 10 MHz TCXO frequency and divides this to 1 MHz;
therefore, R = 10 is programmed and N = 320 is programmed
to achieve a VCO frequency of 320 MHz. The resultant 80 MHz
CMOS signal has a jitter of <1.5 ps, which is more than adequate
for the application.

SPI

TCXO

ADF4360-9

10MHz

470Ω

21nH

80MHz

21nH

470Ω

PC

USB

Rev. A | Page 20 of 24

SIGNAL

GENERATOR

LPF

Figure 29. The ADF4360-9 Used as an Encode Clock for an ADC

A

IN

ENCODE

CLOCK

AD9215-80

HC-ADC-

EVALA-SC

07139-036

ADF4360-9

K

www.BDTIC.com/ADI

GSM TEST CLOCK

Figure 30 shows the ADF4360-9 used to generate three different
frequencies at DIVOUT. The frequencies required are 45 MHz,
80 MHz, and 95 MHz. This is achieved by generating 360 MHz,
320 MHz, and 380 MHz and programming the correct A divider
ratio. Because a 50% duty cycle is required, the A/2 DIVOUT
mode is selected. This means that A values of 4, 2, and 2 are
selected, respectively, for each of the output frequencies
previously mentioned.

The low-pass filter was designed using ADIsimPLL™ for a
cha

nnel spacing of 1 MHz and an open-loop bandwidth of
40 kHz. Larger PFD frequencies can be used to reduce in-band
noise and, therefore, rms jitter. However, for the purposes of
this example, 1 MHz is used. The measured rms jitter from this
circuit at each frequency is less than 1.5 ps.

V

VCO

V

VDD

Two 21 nH inductors are required for the specified frequency

ange. The reference frequency is from a 20 MHz TCXO from

r
Fox; therefore, an R value of 20 is programmed. Taking into
account the high PFD frequency and its effect on the band
select logic, the band select clock divider is enabled. In this case,
a value of 8 is chosen. A very simple shunt resistor and dc-blocking
capacitor complete the RF output stage. Because these outputs
are not used, they are terminated in 50 Ω resistors. This is
recommended for circuit stability. Leaving the RF outputs
open is not recommended.

The CMOS level output frequency is available at DIVOUT. If
t

he frequency has to drive a low impedance load, a buffer is

recommended.

LOC

DETECT

FOX

801BE-160

20MHz

1nF

SPI-COMPATIBLE SERIAL BUS

10µF

6

V

VCO

14

C

N

1nF1nF

16

REF

51Ω

4.7kΩ

IN

17

CLK

18

DATA

19

LE

12

C

C

13

R

SET

CPGND AGND DGND L1 L2

1 3 8

AVDDDV

ADF4360-9

23212

V

TUNE

DIVOUT

RF

OUT

RF

OUT

CP

7

24

20

V

VCO

51Ω

A

4

5

B

150pF

51Ω

12kΩ

2.2nF

5.6kΩ

100pF

100pF

56pF

51Ω

51Ω

07139-027

LD

DD

9

1011 22 15

21nH

470Ω

21nH470Ω

Figure 30.GSM Test Clock

Rev. A | Page 21 of 24

ADF4360-9

www.BDTIC.com/ADI

INTERFACING

The ADF4360 family has a simple SPI-compatible serial interface
for writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits that are clocked into
the appropriate register on each rising edge of CLK are transferred
to the appropriate latch. See Figure 2 for the timing diagram

Tabl e 5 for the latch truth table.

nd

a

The maximum allowable serial clock rate is 20 MHz. This
m

eans that the maximum update rate possible is 833 kHz, or
one update every 1.2 μs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.

ADuC812 Interface

Figure 31 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Because the ADuC812 is based
o

n an 8051 core, this interface can be used with any 8051-based
microcontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. After the
third byte is written, the LE input should be brought high to
complete the transfer.

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 31. ADuC812 to ADF4360-x Interface

I/O port lines on the ADuC812 are used to detect lock (MUXOUT
configured as lock detect and polled by the port input). When
operating in the described mode, the maximum SCLOCK rate
of the ADuC812 is 4 MHz. This means that the maximum rate
at which the output frequency can be changed is 166 kHz.

SCLK

SDATA

LE

ADF4360-x

CE

MUXOUT
(LOCK DETECT)

07139-028

ADSP-21xx Interface

Figure 32 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated.

SCLOCK

MOSI

TFS

ADSP-21xx

I/O PORTS

Figure 32. ADSP-21xx to ADF4360-x Interface

SCLK

SDATA

LE

ADF4360-x

CE

MUXOUT
(LOCK DETECT )

07139-029

Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the autobuffered mode, and write to
the transmit register of the DSP. This last operation initiates the
autobuffer transfer.

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24-2) are rectangular.
The PCB pad for these should be 0.1 mm longer than the
package lead length and 0.05 mm wider than the package lead
width. The lead should be centered on the pad to ensure that
the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The t

hermal pad on the PCB should be at least as large as this

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the
pad pattern to ensure that shorting is avoided.

Thermal vias can be used on the PCB thermal pad to improve
th

ermal performance of the package. If vias are used, they should
be incorporated into the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 ounce of copper to plug the via.

The user should connect the printed circuit thermal pad to AGND.
Thi

s is internally connected to AGND.

Rev. A | Page 22 of 24

ADF4360-9

C

V

V

www.BDTIC.com/ADI

OUTPUT MATCHING

There are a number of ways to match the VCO output of the
ADF4360-9 for optimum operation; the most basic is to use a
51 Ω resistor to V
in series, as shown in Figure 33. Because the resistor is not

requency dependent, this provides a good broadband match.

f
The output power in the circuit in Figure 33 typically gives

−9 dBm o

utput power into a 50 Ω load.

A better solution is to use a shunt inductor (acting as an RF
choke) to V
output power.

Experiments have shown that the circuit shown in Figure 34

rovides an excellent match to 50 Ω over the operating range of

p
the ADF4360-9. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-9 using the
recommended shunt inductor, followed by a 100 pF dc-blocking
capacitor.

. A dc bypass capacitor of 100 pF is connected

VCO

VCO

51Ω

L

100pF

100pF

50Ω

50Ω

07139-030

07139-031

RF

OUT

Figure 33. Simple Output Stage

. This gives a better match and, therefore, more

VCO

VCO

RF

OUT

Figure 34. Optimum Output Stage

The recommended value of this inductor changes with the VCO
center frequency. Figure 35 shows a graph of the optimum

uctor value vs. center frequency.

ind

300

250

200

150

TANCE (nH)

INDU

100

50

0

0 100 200 300 500400

Figure 35. Optimum Shunt Inductor vs. Center Frequency

CENTER FREQ UENCY (MHz)

07139-032

Both complementary architectures can be examined using the
EVAL-ADF4360-9EBZ1 evaluation board. If the user does not
need the differential outputs available on the ADF4360-9, the
user should either terminate the unused output with the same
circuitry as much as possible or combine both outputs using a
balun. Alternatively, instead of the LC balun, both outputs can
be combined using a 180° rat-race coupler.

If the user is only using DIVOUT and does not use the RF
outputs, it is still necessary to terminate both RF output pins
with a shunt inductor/resistor to V

and also a dc bypass

VCO

capacitor and a 50 Ω load. The circuit in Figure 33 is probably

e simplest and most cost-effective solution. It is important

th
that the load on each pin be balanced because an unbalanced
load is likely to cause stability problems. Terminations should
be identical as much as possible.

Rev. A | Page 23 of 24

ADF4360-9

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

Figure 36. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

mm × 4 mm Body, Very Thin Quad

4

(CP-24-2)

Dimensions shown in millimeters

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

ORDERING GUIDE

Model Temperature Range Package Description Frequency Range Package Option

ADF4360-9BCPZ
ADF4360-9BCPZRL
ADF4360-9BCPZRL7
EVAL-ADF4360-9EBZ1

1

Z = RoHS Compliant Part.

1

1

1

1

−40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2

−40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2

−40°C to +85°C 24-Lead LFCSP_VQ 65 MHz to 400 MHz CP-24-2
Evaluation Board

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07139-0-3/08(A)

Rev. A | Page 24 of 24