ANALOG DEVICES ADF4360-8 Service Manual

Integrated Synthesizer and VCO

FEATURES

Output frequency range: 65 MHz to 400 MHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility Integer-N synthesizer Programmable output power level 3-wire serial interface Digital lock detect Hardware and software power-down mode

APPLICATIONS

System clock generation Test equipment Wireless LANs CATV equipment

ADF4360-8

REF

CLK

DATA

14-BIT R

COUNTER

24-BIT

DATA REGISTER

GENERAL DESCRIPTION

The ADF4360-8 is an integrated integer-N synthesizer and voltage-controlled oscillator (VCO). The ADF4360-8 center frequency is set by external inductors. This allows a frequency range of between 65 MHz to 400 MHz.

Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from

3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

24-BIT

FUNCTION

LATCH

SET

LOCK

DETECT

PHASE

COMPARATOR

MULTIPLEXER

CHARGE

PUMP

MUTE

ADF4360-8

MUXOUT

VCO

13-BIT B

COUNTER

N = B

AGND DGND CPGND

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

TUNE

L1 L2 C

VCO

CORE

OUTPUT

STAGE

OUT

04763-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADF4360-8

TABLE OF CONTENTS

Specifications..................................................................................... 3

Output Stage................................................................................ 12

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

N Counter.................................................................................... 10

R Counter ....................................................................................10

PFD and Charge Pump.............................................................. 10

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 11

VCO.............................................................................................. 11

Latch Structure ........................................................................... 13

Power-Up..................................................................................... 17

Control Latch.............................................................................. 19

N Counter Latch......................................................................... 20

R Counter Latch ......................................................................... 20

Applications..................................................................................... 21

Choosing the Correct Inductance Value................................. 21

Fixed Frequency LO................................................................... 21

Interfacing ................................................................................... 22

PCB Design Guidelines for Chip Scale Package........................... 22

Output Matching........................................................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

01/05 — Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Figure 20...................................................................... 12

Added Power-Up Section .............................................................. 17

Deleted Power-Up Section ............................................................ 22

Updated Outline Dimensions....................................................... 24

Changes to Ordering Guide.......................................................... 24

10/04—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4360-8

SPECIFICATIONS1

AVDD = DVDD = V

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/max

REFIN Input Sensitivity 0.7/AVDD V p-p min/max AC-coupled 0 to AVDD V max CMOS-compatible REFIN Input Capacitance 5.0 pF max REFIN Input Current ±60 µA max

PHASE DETECTOR

Phase Detector Frequency2 8 MHz max

CHARGE PUMP

ICP Sink/Source3 With R

High Value 2.5 mA typ Low Value 0.312 mA typ R

Range 2.7/10 kΩ

SET

ICP Three-State Leakage Current 0.2 nA typ Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V ICP vs. Temperature 2 % typ VCP = 2.0 V

LOGIC INPUTS

, Input High Voltage 1.5 V min

INH

, Input Low Voltage 0.6 V max

INL

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 3.0 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min CMOS output chosen IOH, Output High Current 500 µA max VOL, Output Low Voltage 0.4 V max IOL = 500 µA

POWER SUPPLIES

AVDD 3.0/3.6 V min/V max DVDD AVDD V

AVDD

VCO

5 mA typ

2.5 mA typ

4, 5

VCO

3.5 to 11.0 mA typ RF output stage is programmable

RFOUT

Low Power Sleep Mode4 7 µA typ

RF OUTPUT CHARACTERISTICS5

Maximum VCO Output Frequency 400 MHz

Minimum VCO Output Frequency 65 MHz VCO Output Frequency 88/108 MHz min/max

VCO Frequency Range 1.2 Ratio F VCO Sensitivity 2 MHz/V typ

Lock Time6 400 µs typ To within 10 Hz of final frequency Frequency Pushing (Open Loop) 0.24 MHz/V typ Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load Harmonic Content (Second) −16 dBc typ

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

VCO

12.0 mA typ I

MIN

to T

, unless otherwise noted.

MAX

For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 21 V/µs.

= 4.7 kΩ

SET

= 5 mA

CORE

= 5 mA. Depending on L. See the

CORE

Choosing the Correct Inductance Value section.

L1, L2 = 270 nH. See the Choosing the Correct Inductance Value section for other frequency values.

/ F

MIN

MAX

L1, L2 = 270 nH. See the Choosing the Correct Inductance Value section for other sensitivity values.

Rev. A | Page 3 of 24

ADF4360-8

Parameter B Version Unit Conditions/Comments

Harmonic Content (Third) −21 dBc typ

Output Power

Output Power Variation ±3 dB typ

VCO Tuning Range 1.25/2.5 V min/max NOISE CHARACTERISTICS5

VCO Phase Noise Performance9 −120 dBc/Hz typ @ 100 kHz offset from carrier

−139 dBc/Hz typ @ 800 kHz offset from carrier

−140 dBc/Hz typ @ 3 MHz offset from carrier

−142 dBc/Hz typ @ 10 MHz offset from carrier

Synthesizer Phase Noise Floor10 −160 dBc/Hz typ @ 200 kHz PFD frequency

−150 dBc/Hz typ @ 1 MHz PFD frequency

−142 dBc/Hz typ @ 8 MHz PFD frequency

Phase Noise Figure of Merit10 −215 dBc/Hz typ

In-Band Phase Noise

RMS Integrated Phase Error13 0.09 Degrees typ 100 Hz to 100 kHz

Spurious Signals due to PFD

Frequency

Level of Unlocked Signal with

MTLD Enabled

Operating temperature range is –40°C to +85°C.

Guaranteed by design. Sample tested to ensure compliance.

ICP is internally modified to maintain constant loop gain over the frequency range.

TA = 25°C; AVDD = DVDD = V

Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.

Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

For more detail on using tuned loads, see the Output Matching section.

Using 50 Ω resistors to V

The noise of the VCO is measured in open-loop conditions.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The

phase noise figure of merit subtracts 10 log (PFD frequency).

The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the

synthesizer; offset frequency = 1 kHz.

= 10 MHz; f

REFIN 13

= 10 MHz; f

REFIN 14

The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN

for the synthesizer; f

5, 7

5, 8

−14/−9 dBm typ Using 50 Ω resistors to V

11, 12

−102 dBc/Hz typ @ 1 kHz offset from carrier

12, 14

−9/0 dBm typ Using tuned load, programmable in 3 dB steps; see Table 7

−75 dBc typ

−70 dBm typ

= 3.3 V.

VCO

, into a 50 Ω load.

VCO

= 200 kHz; N = 1000; loop B/W = 10 kHz.

PFD

= 1 MHz; N = 120; loop B/W = 100 kHz.

PFD

= 10 MHz @ 0 dBm.

REFOUT

, programmable in 3 dB steps; see Table 7

VCO

Rev. A | Page 4 of 24

ADF4360-8

TIMING CHARACTERISTICS1

AVDD = DVDD = V

Table 2.

Parameter Limit at T

t1 20 ns min LE setup time t2 10 ns min DATA to CLOCK setup time t3 10 ns min DATA to CLOCK hold time t4 25 ns min CLOCK high duration t5 25 ns min CLOCK low duration t6 10 ns min CLOCK to LE setup time t7 20 ns min LE pulse width

Refer to the Power-Up section for the recommended power-up procedure for this device.

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

to T

MIN

(B Version) Unit Test Conditions/Comments

MAX

MIN

to T

, unless other wise noted.

MAX

CLOC

DATA

DB23 (MSB) DB22 DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

04763-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4360-8

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V AVDD to DVDD −0.3 V to +0.3 V V

to GND −0.3 V to +3.9 V

VCO

to AVDD −0.3 V to +0.3 V

VCO

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V REFIN to GND −0.3 V to VDD + 0.3 V Operating Temperature Range −40°C to + 85°C

Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C CSP θJA Thermal Impedance

Paddle Soldered 50°C/W

Paddle Not Soldered 88°C/W Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <1 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT

12543 (CMOS) and 700 (Bipolar)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 6 of 24

ADF4360-8

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1 IDENTIFIER

ADF4360-8

TOP VIEW

(Not to Scale)

8L19

AGND

MUXOU

20LE19

AGND

DATA CLK

REF

DGND

SET

04763-003

CPGND

AGND

OUT

VCO

CP24CE23AGND22DV

1 2

5 6

TUNE

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump. 2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be

placed as close as possible to this pin. AV

must have the same value as DVDD.

3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO. 4 RF

OUT

VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a description of the various output stages.

5 RF

B VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching

OUT

section for a description of the various output stages.

6 V

7 V

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should

VCO

be placed as close as possible to this pin. V

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

TUNE

must have the same value as AVDD.

VCO

output voltage.

9 L1 An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2

need to be the same value. A 470 Ω resistor should be added in parallel to AGND.

10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2

need to be the same value. A 470 Ω resistor should be added in parallel to AGND. 12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor. 13 R

14 CN Internal Compensation Node. This pin must be decoupled to V

Connecting a resistor between this pin and CP

SET

The nominal voltage potential at the R

where R

CPmax

SET

75.11

SET

= 4.7 kΩ, I

= 2.5 mA.

CPmax

SET

sets the maximum charge pump output current for the synthesizer.

GND

pin is 0.6 V. The relationship between ICP and R

with a 10 µF capacitor.

VCO

SET

15 DGND Digital Ground. 16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit

shift register on the CLK rising edge. This input is a high impedance CMOS input. 18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high

impedance CMOS input. 19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, and the relevant latch is selected using the control bits. 20 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally. 21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. DV

must have the same value as AVDD.

23 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

Taking the pin high powers up the device depending on the status of the power-down bits. 24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the internal VCO.

Rev. A | Page 7 of 24

ADF4360-8

TYPICAL PERFORMANCE CHARACTERISTICS

–40 –50

–60 –70 –80

–90 –100 –110

OUTPUT POWER (dB)

–120 –130 –140 –150

100 1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

Figure 4. Open-Loop VCO Phase Noise, L1, L2 = 560 nH

–70

–75

–80

–85

–90

–95 –100 –105 –110 –115 –120 –125

OUTPUT POWER (dB)

–130 –135 –140 –145 –150

100 1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

Figure 5. VCO Phase Noise, 65 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth

04763-004

04763-005

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80 –90

–1.1MHz –0.55MHz 65MHz 0.55MHz 1.1MHz

REFERENCE

LEVEL = –2.5dBm

VDD= 3.3V,V

=2.5mA

PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 4.2SECONDS AVERAGES= 20

VCO

=3.3V

–84dBc

Figure 7. Reference Spurs at 65 MHz

(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)

–40 –50

–60 –70 –80

–90 –100 –110

OUTPUT POWER (dB)

–120 –130 –140 –150

100 1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

Figure 8. Open-Loop VCO Phase Noise, L1, L2 = 110 nH

04763-007

04763-008

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80 –90

REFERENCE

LEVEL = –2.5dBm

–2kHz –1kHz 65MHz 1kHz 2kHz

VDD = 3.3V, V ICP = 2.5mA PFD FREQUENCY = 1MHz LOOP BANDWIDTH = 100kHz RES. BANDWIDTH = 30Hz VIDEO BANDWIDTH = 30Hz SWEEP = 1.9SECONDS AVERAGES = 20

= 3.3V

VCO

–107.4dBc/Hz

Figure 6. Close-In Phase Noise at 65 MHz (1 MHz Channel Spacing)

04763-006

Rev. A | Page 8 of 24

–70

–75

–80

–85

–90

–95 –100 –105 –110 –115 –120 –125

OUTPUT POWER (dB)

–130 –135 –140 –145 –150

100 1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

04763-009

Figure 9. VCO Phase Noise, 160 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth

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