Integrated Synthesizer and VCO
FEATURES
Output frequency range: 65 MHz to 400 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Hardware and software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
ADF4360-8
REF
CLK
DATA
IN
LE
14-BIT R
COUNTER
24-BIT
DATA REGISTER
GENERAL DESCRIPTION
The ADF4360-8 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). The ADF4360-8 center
frequency is set by external inductors. This allows a frequency
range of between 65 MHz to 400 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
AV
24-BIT
FUNCTION
LATCH
DV
DD
DD
R
SET
LOCK
DETECT
PHASE
COMPARATOR
CE
MULTIPLEXER
CHARGE
PUMP
MUTE
ADF4360-8
MUXOUT
CP
V
VCO
13-BIT B
COUNTER
N = B
AGND DGND CPGND
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Figure 1.
V
TUNE
L1
L2
C
C
C
N
A
RF
VCO
CORE
OUTPUT
STAGE
OUT
RF
B
OUT
04763-001
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
ADF4360-8
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Stage................................................................................ 12
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Circuit Description......................................................................... 10
Reference Input Section............................................................. 10
N Counter.................................................................................... 10
R Counter ....................................................................................10
PFD and Charge Pump.............................................................. 10
MUXOUT and Lock Detect...................................................... 10
Input Shift Register..................................................................... 11
VCO.............................................................................................. 11
Latch Structure ........................................................................... 13
Power-Up..................................................................................... 17
Control Latch.............................................................................. 19
N Counter Latch......................................................................... 20
R Counter Latch ......................................................................... 20
Applications..................................................................................... 21
Choosing the Correct Inductance Value................................. 21
Fixed Frequency LO................................................................... 21
Interfacing ................................................................................... 22
PCB Design Guidelines for Chip Scale Package........................... 22
Output Matching........................................................................ 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
01/05 — Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Figure 20...................................................................... 12
Added Power-Up Section .............................................................. 17
Deleted Power-Up Section ............................................................ 22
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
10/04—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADF4360-8
SPECIFICATIONS1
AVDD = DVDD = V
Table 1.
Parameter B Version Unit Conditions/Comments
REFIN CHARACTERISTICS
REFIN Input Frequency 10/250 MHz min/max
REFIN Input Sensitivity 0.7/AVDD V p-p min/max AC-coupled
0 to AVDD V max CMOS-compatible
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±60 µA max
PHASE DETECTOR
Phase Detector Frequency2 8 MHz max
CHARGE PUMP
ICP Sink/Source3 With R
High Value 2.5 mA typ
Low Value 0.312 mA typ
R
Range 2.7/10 kΩ
SET
ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % typ VCP = 2.0 V
LOGIC INPUTS
V
, Input High Voltage 1.5 V min
INH
V
, Input Low Voltage 0.6 V max
INL
I
, Input Current ±1 µA max
INH/IINL
CIN, Input Capacitance 3.0 pF max
LOGIC OUTPUTS
VOH, Output High Voltage DVDD – 0.4 V min CMOS output chosen
IOH, Output High Current 500 µA max
VOL, Output Low Voltage 0.4 V max IOL = 500 µA
POWER SUPPLIES
AVDD 3.0/3.6 V min/V max
DVDD AVDD
V
AVDD
VCO
4
AI
5 mA typ
DD
4
DI
2.5 mA typ
DD
4, 5
I
VCO
4
I
3.5 to 11.0 mA typ RF output stage is programmable
RFOUT
Low Power Sleep Mode4 7 µA typ
RF OUTPUT CHARACTERISTICS5
Maximum VCO Output Frequency 400 MHz
Minimum VCO Output Frequency 65 MHz
VCO Output Frequency 88/108 MHz min/max
VCO Frequency Range 1.2 Ratio F
VCO Sensitivity 2 MHz/V typ
Lock Time6 400 µs typ To within 10 Hz of final frequency
Frequency Pushing (Open Loop) 0.24 MHz/V typ
Frequency Pulling (Open Loop) 10 Hz typ Into 2.00 VSWR load
Harmonic Content (Second) −16 dBc typ
= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T
VCO
12.0 mA typ I
MIN
to T
, unless otherwise noted.
MAX
For f < 10 MHz, use a dc-coupled CMOS-compatible square wave,
slew rate > 21 V/µs.
= 4.7 kΩ
SET
= 5 mA
CORE
= 5 mA. Depending on L. See the
I
CORE
Choosing the Correct Inductance Value section.
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other frequency values.
/ F
MIN
MAX
L1, L2 = 270 nH. See the Choosing the Correct Inductance Value
section for other sensitivity values.
Rev. A | Page 3 of 24
ADF4360-8
Parameter B Version Unit Conditions/Comments
Harmonic Content (Third) −21 dBc typ
Output Power
Output Power
Output Power Variation ±3 dB typ
VCO Tuning Range 1.25/2.5 V min/max
NOISE CHARACTERISTICS5
VCO Phase Noise Performance9 −120 dBc/Hz typ @ 100 kHz offset from carrier
−139 dBc/Hz typ @ 800 kHz offset from carrier
−140 dBc/Hz typ @ 3 MHz offset from carrier
−142 dBc/Hz typ @ 10 MHz offset from carrier
Synthesizer Phase Noise Floor10 −160 dBc/Hz typ @ 200 kHz PFD frequency
−150 dBc/Hz typ @ 1 MHz PFD frequency
−142 dBc/Hz typ @ 8 MHz PFD frequency
Phase Noise Figure of Merit10 −215 dBc/Hz typ
In-Band Phase Noise
RMS Integrated Phase Error13 0.09 Degrees typ 100 Hz to 100 kHz
Spurious Signals due to PFD
Frequency
Level of Unlocked Signal with
MTLD Enabled
1
Operating temperature range is –40°C to +85°C.
2
Guaranteed by design. Sample tested to ensure compliance.
3
ICP is internally modified to maintain constant loop gain over the frequency range.
4
TA = 25°C; AVDD = DVDD = V
5
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
6
Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
7
For more detail on using tuned loads, see the Output Matching section.
8
Using 50 Ω resistors to V
9
The noise of the VCO is measured in open-loop conditions.
10
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
phase noise figure of merit subtracts 10 log (PFD frequency).
11
The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the
synthesizer; offset frequency = 1 kHz.
12
f
= 10 MHz; f
REFIN
13
f
= 10 MHz; f
REFIN
14
The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN
for the synthesizer; f
5, 7
5, 8
−14/−9 dBm typ Using 50 Ω resistors to V
11, 12
−102 dBc/Hz typ @ 1 kHz offset from carrier
12, 14
−9/0 dBm typ Using tuned load, programmable in 3 dB steps; see Table 7
−75 dBc typ
−70 dBm typ
= 3.3 V.
VCO
, into a 50 Ω load.
VCO
= 200 kHz; N = 1000; loop B/W = 10 kHz.
PFD
= 1 MHz; N = 120; loop B/W = 100 kHz.
PFD
= 10 MHz @ 0 dBm.
REFOUT
, programmable in 3 dB steps; see Table 7
VCO
Rev. A | Page 4 of 24
ADF4360-8
K
TIMING CHARACTERISTICS1
AVDD = DVDD = V
Table 2.
Parameter Limit at T
t1 20 ns min LE setup time
t2 10 ns min DATA to CLOCK setup time
t3 10 ns min DATA to CLOCK hold time
t4 25 ns min CLOCK high duration
t5 25 ns min CLOCK low duration
t6 10 ns min CLOCK to LE setup time
t7 20 ns min LE pulse width
1
Refer to the Power-Up section for the recommended power-up procedure for this device.
= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T
VCO
to T
MIN
(B Version) Unit Test Conditions/Comments
MAX
MIN
to T
, unless other wise noted.
MAX
CLOC
DATA
t
2
DB23 (MSB) DB22 DB2
LE
t
1
LE
t
t
4
3
t
5
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
6
t
7
04763-002
Figure 2. Timing Diagram
Rev. A | Page 5 of 24
ADF4360-8
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
V
to GND −0.3 V to +3.9 V
VCO
V
to AVDD −0.3 V to +0.3 V
VCO
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance
Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1
GND = AGND = DGND = 0 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <1 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
12543 (CMOS) and 700 (Bipolar)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Rev. A | Page 6 of 24
ADF4360-8
T
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DD
21
PIN 1
IDENTIFIER
ADF4360-8
TOP VIEW
(Not to Scale)
8L19
10
L2
AGND
MUXOU
20LE19
11
AGND
18
DATA
CLK
17
REF
16
IN
DGND
15
C
14
N
R
13
SET
12
C
C
04763-003
CPGND
AV
AGND
RF
OUT
RF
OUT
V
VCO
CP24CE23AGND22DV
1
2
DD
3
A
4
B
5
6
7
TUNE
V
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be
placed as close as possible to this pin. AV
must have the same value as DVDD.
DD
3, 8, 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF
OUT
A
VCO Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching section for a
description of the various output stages.
5 RF
B VCO Complementary Output. The output level is programmable from 0 dBm to −9 dBm. See the Output Matching
OUT
section for a description of the various output stages.
6 V
7 V
Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should
VCO
be placed as close as possible to this pin. V
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP
TUNE
must have the same value as AVDD.
VCO
output voltage.
9 L1 An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2
need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
10 L2 An external inductor to AGND should be connected to this pin to set the ADF4360-8 output frequency. L1 and L2
need to be the same value. A 470 Ω resistor should be added in parallel to AGND.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R
14 CN Internal Compensation Node. This pin must be decoupled to V
Connecting a resistor between this pin and CP
SET
The nominal voltage potential at the R
I
where R
CPmax
SET
75.11
=
R
SET
= 4.7 kΩ, I
= 2.5 mA.
CPmax
SET
sets the maximum charge pump output current for the synthesizer.
GND
pin is 0.6 V. The relationship between ICP and R
with a 10 µF capacitor.
VCO
is
SET
15 DGND Digital Ground.
16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit
shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high
impedance CMOS input.
19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, and the relevant latch is selected using the control bits.
20 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
must have the same value as AVDD.
DD
23 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the internal VCO.
Rev. A | Page 7 of 24
ADF4360-8
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–50
–60
–70
–80
–90
–100
–110
OUTPUT POWER (dB)
–120
–130
–140
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 4. Open-Loop VCO Phase Noise, L1, L2 = 560 nH
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
OUTPUT POWER (dB)
–130
–135
–140
–145
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 5. VCO Phase Noise, 65 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
04763-004
04763-005
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
–1.1MHz –0.55MHz 65MHz 0.55MHz 1.1MHz
REFERENCE
LEVEL = –2.5dBm
VDD= 3.3V,V
=2.5mA
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES= 20
VCO
=3.3V
–84dBc
Figure 7. Reference Spurs at 65 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
–40
–50
–60
–70
–80
–90
–100
–110
OUTPUT POWER (dB)
–120
–130
–140
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 8. Open-Loop VCO Phase Noise, L1, L2 = 110 nH
04763-007
04763-008
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
REFERENCE
LEVEL = –2.5dBm
–2kHz –1kHz 65MHz 1kHz 2kHz
VDD = 3.3V, V
ICP = 2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
= 3.3V
VCO
–107.4dBc/Hz
Figure 6. Close-In Phase Noise at 65 MHz (1 MHz Channel Spacing)
04763-006
Rev. A | Page 8 of 24
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
OUTPUT POWER (dB)
–130
–135
–140
–145
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
04763-009
Figure 9. VCO Phase Noise, 160 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
ADF4360-8
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
REFERENCE
LEVEL = 1dBm
–2kHz –1kHz 160MHz 1kHz 2kHz
VDD = 3.3V, V
= 2.5mA
I
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
= 3.3V
VCO
–109.4dBc/Hz
Figure 10. Close-In Phase Noise at 160 MHz (1 MHz Channel Spacing)
04763-010
–70
–75
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
OUTPUT POWER (dB)
–130
–135
–140
–145
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
04763-013
Figure 13. VCO Phase Noise, 400 MHz, 1 MHz PFD, 100 kHz Loop Bandwidth
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
–1.1MHz –0.55MHz 160MHz 0.55MHz 1.1MHz
REFERENCE
LEVEL = 1dBm
VDD= 3.3V,V
I
=2.5mA
CP
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES= 20
VCO
=3.3V
–76dBc
Figure 11. Reference Spurs at 160 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
–40
–50
–60
–70
–80
–90
–100
–110
OUTPUT POWER (dB)
–120
–130
–140
–150
100 1k 10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 12. Open-Loop VCO Phase Noise, L1, L2 = 18 nH
04763-011
04763-012
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
REFERENCE
LEVEL = 0dBm
–2kHz –1kHz 400MHz 1kHz 2kHz
VDD = 3.3V, V
ICP = 2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 20
= 3.3V
VCO
–103.4dBc/Hz
Figure 14. Close-In Phase Noise at 400 MHz (1 MHz Channel Spacing)
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER (dB)
–80
–90
–1.1MHz –0.55MHz 400MHz 0.55MHz 1.1MHz
REFERENCE
LEVEL = 0dBm
VDD= 3.3V,V
ICP=2.5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 4.2SECONDS
AVERAGES= 20
VCO
=3.3V
–77dBc
Figure 15. Reference Spurs at 400 MHz
(1 MHz Channel Spacing, 100 kHz Loop Bandwidth)
04763-014
04763-015
Rev. A | Page 9 of 24
ADF4360-8
C
T
T
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
POWER-DOWN
CONTROL
100kΩ
NC
REF
SW1
SW2
SW3
NO
IN
NC
BUFFER
TO R COUNTER
Figure 16. Reference Input Stage
N COUNTER
The CMOS N counter allows a wide division ratio in the PLL
feedback counter. The counters are specified to work when the
VCO output is 400 MHz or less. To avoid confusion, this is referred to as the B counter. It makes it possible to generate output
frequencies that are spaced only by the reference frequency
divided by
R. The VCO frequency equation is
RfBf
/×=
VCO
REFIN
where:
f
is the output frequency of the VCO.
VCO
is the preset divide ratio of the binary 13-bit counter (3 to 8191).
B
f
is the external reference frequency oscillator.
REFIN
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PFD AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter
(
N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 17 is a simplified schematic. The PFD includes a programmable delay element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function, and minimizes phase noise and reference spurs. Two
bits in the R counter latch, ABP2 and ABP1, control the width of
the pulse (see Table 9).
pin
IN
04763-016
V
P
CHARGE
PUMP
HI
R DIVIDER
HI
N DIVIDER
R DIVIDER
N DIVIDER
P OUTPU
Q1D1
U1
CLR1
PROGRAMMABLE
ABP1 ABP2
CLR2
Q2D2
U2
UP
DELAY
DOWN
U3
CPGND
CP
Figure 17. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 18 shows
the MUXOUT section in block diagram form.
DV
DD
DIGITAL LOCK DETEC
R COUNTER OUTPUT
N COUNTER OUTPUT
CONTROLMUX
Figure 18. MUXOUT Circuit
MUXOUT
DGND
04763-017
04763-018
Rev. A | Page 10 of 24
ADF4360-8
Lock Detect
MUXOUT can be programmed for one type of lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase error
on three consecutive phase detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.
INPUT SHIFT REGISTER
The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs, DB1 and DB0,
are shown in Figure 2.
The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.
Table 5. C2 and C1 Truth Table
Control Bits
C2 C1
Data Latch
0 0 Control Latch
0 1 R Counter
1 0 N Counter (B)
1 1 Test Modes Latch
VCO
The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 19, to allow a wide frequency range to
be covered without a large VCO sensitivity (K
poor phase noise and spurious performance.
) and resultant
V
The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is
R counter latch
1.
Control latch
2.
N counter latch
3.
During band s elect, which takes five PFD cycles, the VCO V
TUNE
is disconnected from the output of the loop filter and connected
to an internal reference voltage.
3.5
3.0
2.5
2.0
(V)
TUNE
V
1.5
1.0
0.5
0
80 85 90 10095 105 115110
Figure 19. Frequency vs. V
FREQUENCY (MHz)
, ADF4360-8, L1 and L2 = 270 nH
TUNE
04763-019
The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8,
and is controlled by the BSC1 bit and the BSC2 bit in the R
counter latch. Where the required PFD frequency exceeds
1 MHz, the divide ratio should be set to allow enough time for
correct band selection.
After band selection, normal PLL action resumes. The value of
K
is determined by the value of inductors used (see the
V
Choosing the Correct Inductance Value section). The ADF4360
family contains linearization circuitry to minimize any variation
of the product of I
and KV.
CP
The operating current in the VCO core is programmable in four
steps: 2.5 mA, 5 mA, 7.5 mA, and 10 mA. This is controlled by
the PC1 bit and the PC2 bit in the control latch.
Rev. A | Page 11 of 24
ADF4360-8
OUTPUT STAGE
The RF
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in Figure 20. To allow
the user to optimize the power dissipation vs. the output power
requirements, the tail current of the differential pair is programmable via Bits PL1 and PL2 in the control latch. Four current levels may be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA. These
levels give output power levels of −9 dBm, −6 dBm, −3 dBm,
and 0 dBm, respectively, using the correct shunt inductor to V
and ac coupling into a 50 Ω load. Alternatively, both outputs can
be combined in a 1 + 1:1 transformer or a 180° microstrip coupler (see the Output Matching section).
A and RF
OUT
B pins of the ADF4360 family are
OUT
DD
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
DD
.
Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock, as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.
RF
ARF
OUT
OUT
B
VCO
BUFFER
Figure 20. Output Stage ADF4360-8
04763-020
Rev. A | Page 12 of 24
ADF4360-8
LATCH STRUCTURE
Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed.
Table 6. Latch Structure
CONTROL LATCH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RSVRSV
RESERVED
CURRENT
DOWN 1
POWER-
SETTING2
DOWN 2
POWER-
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
PD2RSVRSV
CURRENT
SETTING1
OUTPUT
POWER
LEVEL
MUTE-TIL-
LD
CP
CP GAIN
STATE
THREE-
PHASE
DETECTOR
POLARITY
MUXOUT
CONTROL
POWER
LEVEL
RESET
COUNTER
CORE
PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3
N COUNTER LATCH
13-BIT B COUNTER
CP GAIN
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
CPG
RESERVED
RSVRSVRSVRSVRSVB1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
R COUNTER LATCH
LOCK
DETECT
ANTI-
BACKLASH
PULSE
WIDTH
PRECISION
14-BIT REFERENCE COUNTER
R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
BAND
SELECT
CLOCK
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
BSC2RSVRSV
TEST
BIT
MODE
CONTROL
BITS
C2 (0) C1 (0)
CONTROL
BITS
C2 (1) C1 (0)
CONTROL
BITS
C2 (0) C1 (1)
04763-021
Rev. A | Page 13 of 24
ADF4360-8
Table 7. Control Latch
RESERVED
RESERVED
CURRENT
SETTING 2
DOWN 2
DOWN 1
POWER-
POWER-
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
CURRENT
SETTING 1
OUTPUT
POWER
LEVEL
MUTE-TIL-
LD
CP GAIN
CP
THREE-
STATE
PHASE
DETECTOR
MUXOUT
CONTROL
POLARITY
PD2RSVRSV
I
CPI6 CPI5 CPI4
CPI3 CPI2 CPI1 4.7kΩ
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
PL2 PL1 OUTPUT POWER LEVEL
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
CP
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
CURRENT (USING TUNED LOAD)
3.5mA
5.0mA
7.5mA
11.0mA
(mA)
–9dBm
–6dBm
–3dBm
0dBm
CPG
0
1
MUTE-TIL-LOCK DETECT
MTLD
0
DISABLED
ENABLED
1
(USING 50Ω TO V
–19dBm
–15dBm
–12dBm
–9dBm
CP
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
PHASE DETECTOR
PDP
POLARITY
0
NEGATIVE
POSITIVE
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
)
VCO
CR
0
1
M3 M2 M1
001
010
011
100
101
110
111
CORE
POWER
LEVEL
RESET
COUNTER
PC2
PC1
0
0
0
1
10
11
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
MUXOUT
THREE-STATE OUTPUT000
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
R DIVIDER OUTPUT
NOT USED
NOT USED
DGND
PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3
DD
CONTROL
BITS
C2 (0) C1 (0)
CORE POWER LEVEL
2.5mA
5mA
7.5mA
10mA
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN
04763-022
Rev. A | Page 14 of 24
ADF4360-8
Table 8. N Counter Latch
RESERVED
RESERVED
13-BIT B COUNTER
RESERVED
CP GAIN
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
CPGRSVRSV
B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO
000
000
000
.. .
.. .
111
111
111
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
CP GAIN OPERATION
00
10
.......... 000 0
.......... 0 0 1 NOT ALLOWED
.......... 0 1 0 NOT ALLOWED
.......... 1 1 1 3
.......... ... .
.......... . . . .
.......... . . . .
.......... 111 1
.......... 1 0 1 8189
.......... 1 1 0 8190
.......... 1 1 1 8191
CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED
0 0 NOT ALLOWED
.. .
0 0 8188
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
RSVRSVRSVRSVRSVB1B2B3B4B5B6B7B8B9B10B11B12B13 RSV
CONTROL
BITS
C2 (1) C1 (0)
THESE BITS ARE
NOT USED BY THE
DEVICE AND ARE
DON'T CARE BITS.
N = B; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N × F
), AT THE OUTPUT, N
REF
IS (P2–P).
MIN
04763-023
Rev. A | Page 15 of 24
ADF4360-8
Table 9. R Counter Latch
RESERVED
RESERVED
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
LOCK
DETECT
ANTI-
BACKLASH
PULSE
WIDTH
PRECISION
14-BIT REFERENCE COUNTER
BAND
SELECT
CLOCK
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DB21DB22DB23
TEST
MODE
BIT
BSC2RSVRSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns
LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
R14 R13 R12 R3 R2 R1 DIVIDE RATIO
000
000
000
...
...
111
111
111
.......... 0000
.......... 0 1 0 2
.......... 0 1 1 3
.......... 1 0 0 4
.......... ....
.......... . . . .
.......... . . . .
.......... 1111
.......... 1 0 1 16381
.......... 1 1 0 16382
.......... 1 1 1 16383
01 1
.. .
0 0 16380
CONTROL
BITS
C2 (0) C1 (1)R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6
BSC2 BSC1 BAND SELECT CLOCK DIVIDER
001
012
104
118
04763-024
Rev. A | Page 16 of 24
ADF4360-8
POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-8 after
power-up is
1.
R counter latch
Control latch
2.
N counter latch
3.
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-8 during initial power-up to settle.
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
Table 10. CN Capacitance vs. Interval and Phase Noise
Recommended Interval
Between Control Latch
CN Value
and N Counter Latch
10 µF ≥15 ms −100 dBc/Hz −97 dBc/Hz −99 dBc/Hz
440 nF ≥ 600 µs −99 dBc/Hz −96 dBc/Hz −98 dBc/Hz
, DVDD, V
DD
and CE pins. On
VCO,
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 18.0 nH)
these currents have not settled to within 10% of their steadystate value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-8 may not achieve lock. If the recommended interval is inserted, and the N counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
pin (Pin 14). This capacitor is used to
N
reduce the close-in noise of the ADF4360-8 VCO. The
recommended value of this capacitor is 10 µF. Using this value
requires an interval of ≥15 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, the capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is further
explained in Table 10.
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 110.0 nH)
Open-Loop Phase Noise
@ 10 kHz Offset
(L1 and L2 = 560.0 nH)
POWER-UP
CLOCK
DATA
R COUNTER
LATCH DATA
LE
Figure 21. ADF4360-8 Power-Up Timing
CONTROL
LATCH DATA
N COUNTER
LATCH DATA
REQUIRED INTERVAL
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
04763-033
Rev. A | Page 17 of 24
ADF4360-8
Hardware Power-Up/Power-Down
If the part is powered down via the hardware (using the CE pin)
and powered up again without any change to the N counter
register during power-down, the part locks at the correct frequency, because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C
pin, which is <15 ms for 10 µF capacitance. The smaller
N
capacitance of 440 nF on this pin enables lock times of <600 µs.
Software Power-Up/Power-Down
If the part is powered down via the software (using the control
latch) and powered up again without any change to the N
counter latch during power-down, the part locks at the correct
frequency, because the part is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C
pin, which is <15 ms for 10 µF capacitance. The smaller
N
capacitance of 440 nF on this pin enables lock times of <600 µs.
The N counter value cannot be changed while the part is in
power-down, since the part may not lock to the correct
frequency on power-up. If it is updated, the correct programming sequence for the part after power-up is the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
The N counter value cannot be changed while the part is in
power-down, because the part may not lock to the correct
frequency on power-up. If it is updated, the correct programming sequence for the part after power-up is to the R counter
latch, followed by the control latch, and finally the N counter
latch, with the required interval between the control latch and N
counter latch, as described in the Initial Power-Up section.
Rev. A | Page 18 of 24
ADF4360-8
CONTROL LATCH
With (C2, C1) = (0,0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.
Charge Pump Currents
CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1.
Power-Down
DB21 (PD2) and DB20 (PD1) provide programmable powerdown modes.
In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1,
with the condition that PD2 has been loaded with a 0. In the
programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing a
1 into Bit PD1 (on the condition that a 1 has also been loaded to
PD2), the device goes into power-down on the second rising
edge of the R counter output, after LE goes high. When the CE
pin is low, the device is immediately disabled, regardless of the
state of PD1 or PD2.
When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:
• All active dc current paths are removed.
• The R, N, and timeout counters are forced to their load
state conditions.
• The charge pump is forced into three-state mode.
• The digital lock detect circuitry is reset.
• The RF outputs are de-biased to a high impedance state.
• The reference input buffer circuitry is disabled.
• The input register remains active and capable of loading
and latching data.
CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7
.
Output Power Level
Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7
.
Mute-Till-Lock Detect
DB11 of the control latch in the ADF4360 family is the MuteTill-Lock Detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.
CP Gain
DB10 of the control latch in the ADF4360 family is the Charge
Pump Gain bit. When it is programmed to 1, Current Setting 2
is used. When programmed to 0, Current Setting 1 is used.
Charge Pump Three-State
This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.
Phase Detector Polarity
The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active non-inverting filter. It can also be set to 0, which
is required if an active inverting loop filter is used.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in Table 7
.
Counter Reset
DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.
Core Power Level
PC1 and PC2 set the power level in the VCO core. The recommended setting is 5 mA. See the truth table in Table 7.
Rev. A | Page 19 of 24
ADF4360-8
N COUNTER LATCH
Tabl e 8 shows the input data format for programming the
N counter latch.
Reserved Bits
DB2 to DB7 are spare bits and have been designated as
reserved. They should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00...0011) to 8191 (11...111).
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Tabl e 9
shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is
1 (00...001) to 16383 (111...111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Overall Divide Range
The overall VCO feedback divide range is defined by B.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When it is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is used.
This bit can also be programmed through DB10 of the control
latch. The bit always reflects the latest value written to it, whether
this is through the control latch or the N counter latch.
Lock Detect Precision
DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs, as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be
programmed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input.
The output of the R counter is, by default, the value used to
clock the band select logic; if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits that have been designated as
reserved. They should be programmed to 0.
Rev. A | Page 20 of 24
ADF4360-8
APPLICATIONS
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-8 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 22 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
The lowest center frequency of oscillation possible is approximately 65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
=
O
1
()
nH0.9pF9.32π
where FO is the center frequency and L
tance.
450
400
350
300
250
200
150
FREQUENCY (MHz)
100
50
0
0 100 200 300 400 600500
INDUCTANCE (nH)
Figure 22. Output Center Frequency vs. External Inductor Value
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 23 shows a graph of the tuning sensitivity (in MHz/V) vs.
the inductance (nH). It can be seen that as the inductance increases, the sensitivity decreases. This relationship can be derived from the equation above; that is, since the inductance has
increased, the change in capacitance from the varactor has less
of an effect on the frequency.
LF+
EXT
is the external induc-
EXT
04763-025
12
10
8
6
4
SENSITIVITY (MHz/V)
2
0
0 100 200 300 400 600500
INDUCTANCE (nH)
04763-026
Figure 23. Tuning Sensitivity (in MHz/V) vs. Inductance (nH)
FIXED FREQUENCY LO
Figure 24 shows the ADF4360-8 used as a fixed frequency LO at
200 MHz. The low-pass filter was designed using ADIsimPLL
for a channel spacing of 2 MHz and an open-loop bandwidth of
100 kHz. The maximum PFD frequency of the ADF4360-8 is
8 MHz. Since using a larger PFD frequency allows the use of a
smaller N, the in-band phase noise is reduced to as low as possible, −109 dBc/Hz. The typical rms phase noise (100 Hz to
100 kHz) of the LO in this configuration is 0.09°. The reference
frequency is from a 16MHz TCXO from Fox; thus, an R value of
2 is programmed. Taking into account the high PFD frequency
and its effect on the band select logic, the band select clock
divider is enabled. In this case, a value of 8 is chosen. A very
simple shunt inductor and dc-blocking capacitor complete the RF
output stage.
LOCK
V
DETECT
VDD
2023221
V
7
TUNE
24
CP
RF
A
4
OUT
5
RF
B
OUT
9
1011 22 15
68nH
470Ω
68nH470Ω
47pF
6.8kΩ
V
VCO
56nH 56nH
15kΩ
680pF
22nF
100pF
100pF
FOX
801BE-160
16MHz
SPI-COMPATIBLE SERIAL BUS
1nF
10µF
V
VCO
6
DVDDAVDDCE MUXOUT
V
VCO
14
C
N
1nF1nF
16
REF
IN
51Ω
17
CLK
18
DATA
19
LE
12
C
C
13
R
4.7kΩ
SET
CPGND AGND DGND L1 L2
1 3 8
Figure 24. Fixed Frequency LO
ADF4360-8
04763-027
Rev. A | Page 21 of 24
ADF4360-8
INTERFACING
The ADF4360 family has a simple SPI®-compatible serial interface for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz, or
one update every 1.2 µs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 25 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontrollers. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. After the
third byte has been written, the LE input should be brought
high to complete the transfer.
ADSP-2181 Interface
Figure 26 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.
SCLOCK
MOSI
TFS
ADSP-21xx
I/O PORTS
Figure 26. ADSP-21xx to ADF4360-x Interface
SCLK
SDATA
LE
ADF4360-x
CE
MUXOUT
(LOCK DETECT)
04763-029
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.
SCLOCK
MOSI
ADuC812
I/O PORTS
Figure 25. ADuC812 to ADF4360-x Interface
SCLK
SDATA
LE
ADF4360-x
CE
MUXOUT
(LOCK DETECT)
04763-028
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the
output frequency can be changed is 166 kHz.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that shorting is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias
are used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
Rev. A | Page 22 of 24
ADF4360-8
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-8 for optimum operation; the most basic is to use a
50 Ω resistor to V
connected in series, as shown in Figure 27. Because the resistor
is not frequency dependent, this provides a good broadband
match. The output power in the circuit below typically gives
−9 dBm output power into a 50 Ω load.
. A dc bypass capacitor of 100 pF is
VCO
V
VCO
The recommended value of this inductor changes with the VCO
center frequency. A graph of the optimum inductor value vs.
frequency is shown in Figure 29.
300
250
200
150
51Ω
RF
OUT
100pF
50Ω
04763-030
Figure 27. Simple ADF4360-8 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to V
This gives a better match and, therefore, more
VCO.
output power.
Experiments have shown that the circuit shown in Figure 28
provides an excellent match to 50 Ω over the operating range of
the ADF4360-8. This gives approximately 0 dBm output power
across the specific frequency range of the ADF4360-8 using the
recommended shunt inductor, followed by a 100 pF dc blocking
capacitor.
V
VCO
L
RF
OUT
100pF
50Ω
04763-031
Figure 28. Optimum ADF4360-8 Output Stage
INDUCTANCE (nH)
100
50
0
0 100 200 300 5000400
CENTRE FREQUENCY (MHz)
04763-032
Figure 29. Optimum ADF4360-8 Shunt Inductor
Both complementary architectures can be examined using the
EVAL-ADF4360-8EB1 evaluation board. If the user does not
need the differential outputs available on the ADF4360-8, the
user should either terminate the unused output or combine
both outputs using a balun. Alternatively, instead of the LC
balun, both outputs may be combined using a 180° rat-race
coupler.
Rev. A | Page 23 of 24
ADF4360-8
OUTLINE DIMENSIONS
0.60 MAX
19
18
EXPOSED
(BOTTOMVIEW)
13
12
PA D
24
6
7
1
2.50 REF
PIN 1
INDICATOR
*
2.45
2.30 SQ
2.15
0.23 MIN
PIN 1
INDICATOR
1.00
0.85
0.80
SEATING
PLANE
12° MAX
4.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
*
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
0.30
0.23
0.18
3.75
BSC SQ
0.20 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.08
Figure 30. 24-Lead Lead Frame Chip Scale Package [VQ_LFCSP]
4 x 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Frequency Range Package Option
ADF4360-8BCP −40°C to +85°C 65 MHz to 400 MHz CP-24-1
ADF4360-8BCPRL −40°C to +85°C 65 MHz to 400 MHz CP-24-1
ADF4360-8BCPRL7 −40°C to +85°C 65 MHz to 400 MHz CP-24-1
ADF4360-8BCPZ1 −40°C to +85°C 65 MHz to 400 MHz CP-24-1
ADF4360-8BCPZRL1 −40°C to +85°C 65 MHz to 400 MHz CP-24-1
ADF4360-8BCPZRL71 −40°C to +85°C 65 MHz to 400 MHz CP-24-1
EVAL-ADF4360-8EB1 Evaluation Board
1
Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04763–0–1/05(A)
Rev. A | Page 24 of 24
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