Datasheet ADF4360-2 Datasheet (ANALOG DEVICES)

Integrated Synthesizer and VCO

FEATURES

Output frequency range: 1850 MHz to 2170 MHz
Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DD

ADF4360-2

REF

CLK

DATA

IN

LE

14-BIT R

COUNTER

24-BIT

DATA REGISTER

24-BIT

FUNCTION

LATCH

DV

DD

ADF4360-2

GENERAL DESCRIPTION

The ADF4360-2 is a fully integrated integer-N synthesizer
and voltage-controlled oscillator (VCO). The ADF4360-2 is
designed for a center frequency of 2000 MHz. In addition, a
divide-by-2 option is available, whereby the user gets an RF
output of between 925 MHz and 1085 MHz.

Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.

CE

R

SET

MUXOUT

CP

V

VCO

V

TUNE

C

C

C

N

LOCK

DETECT

PHASE

COMPARATOR

MULTIPLEXER

CHARGE

PUMP

MUTE

INTEGER

REGISTER

13-BIT B

COUNTER

PRESCALER

P/P+1

N = (BP + A)

LOAD
LOAD

5-BIT A

COUNTER

AGND DGND CPGND

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

RF

A

OUT

RF

OUT

04436-001

B

MULTIPLEXER

DIVSEL = 1

DIVSEL = 2

VCO

CORE

OUTPUT

STAGE

÷2

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADF4360-2

TABLE OF CONTENTS

Features .............................................................................................. 1

MUXOUT and Lock Detect...................................................... 10

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transi s t o r Cou n t ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

Input Shift Register .................................................................... 10

VCO ............................................................................................. 10

Output Stage................................................................................ 11

Latch Structure ........................................................................... 12

Power-Up..................................................................................... 16

Control Latch.............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Direct Conversion Modulator .................................................. 20

Fixed Frequency LO................................................................... 21

Interfacing ................................................................................... 21

PCB Design Guidelines for Chip Scale Package........................... 22

Output Matching........................................................................ 22

Outline Dimensions ....................................................................... 23

R Counter ...................................................................................... 9

PFD and Charge Pump................................................................ 9

REVISION HISTORY

4/06—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Features and General Description ............................. 1

Changes to Table 1............................................................................ 3

Changes to VCO Section............................................................... 11

Changes to Control Latch Section................................................ 18

Changes to Direct Conversion Modulator Section.................... 20

Changes to Ordering Guide.......................................................... 23

Ordering Guide .......................................................................... 23

12/04—Rev. 0 to Rev. A

Updated Format.................................................................. Universal

Changes to Specifications.................................................................3

Changes to Timing Characteristics.................................................5

Changes to Power-Up Section ...................................................... 16

Added Table 10 ............................................................................... 16

Added Figure 16 ............................................................................. 16

Changes to Ordering Guide.......................................................... 23

Updated Outline Dimensions....................................................... 23

1/04—Revision 0: Initial Version

Rev. B | Page 2 of 24

ADF4360-2

SPECIFICATIONS

AVDD = DVDD = V

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/max

REFIN Input Sensitivity 0.7/AV
0 to AVDD V max CMOS-compatible
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency2 8 MHz max

CHARGE PUMP

ICP Sink/Source3 With R

High Value 2.5 mA typ
Low Value 0.312 mA typ
R

Range 2.7/10 kΩ

SET

ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % typ VCP = 2.0 V

LOGIC INPUTS

V

, Input High Voltage 1.5 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 μA max

INH/IINL

CIN, Input Capacitance 3.0 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD − 0.4 V min CMOS output chosen
IOH, Output High Current 500 μA max
VOL, Output Low Voltage 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 3.0/3.6 V min/V max
DVDD AV
V

AV

VCO

4

AI

DD

4

DI

DD

4, 5

I

VCO

4, 5

I

VCO

4

I

RFOUT

Low Power Sleep Mode

VCO

1

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

DD

DD

DD

10 mA typ

2.5 mA typ

24.0 mA typ I

29.0 mA typ I

3.5 to 11.0 mA typ RF output stage is programmable

4

7 μA typ

MIN

to T

, unless otherwise noted.

MAX

For f < 10 MHz, use a CMOS-compatible
square wave, slew rate > 21 V/μs

V p-p min/max AC-coupled

= 4.7 kΩ

SET

= 15 mA

CORE

= 20 mA

CORE

Rev. B | Page 3 of 24

ADF4360-2

Parameter B Version Unit Conditions/Comments

RF OUTPUT CHARACTERISTICS

VCO Output Frequency 1850/2170 MHz min/max I
I
VCO Sensitivity 57 MHz/V typ
Lock Time

6

Frequency Pushing (Open Loop) 6 MHz/V typ
Frequency Pulling (Open Loop) 15 kHz typ Into 2.00 VSWR load
Harmonic Content (Second) −19 dBc typ
Harmonic Content (Third) −37 dBc typ
Output Power

5, 7

Output Power Variation ±3 dB typ For tuned loads, see the Output Matching section
VCO Tuning Range 1.25/2.7 V min/max

NOISE CHARACTERISTICS

VCO Phase-Noise Performance

−133 dBc/Hz typ @ 1 MHz offset from carrier

−141 dBc/Hz typ @ 3 MHz offset from carrier

−147 dBc/Hz typ @ 10 MHz offset from carrier
Synthesizer Phase-Noise Floor9 −172 dBc/Hz typ @ 25 kHz PFD frequency

−163 dBc/Hz typ @ 200 kHz PFD frequency

−147 dBc/Hz typ @ 8 MHz PFD frequency
In-Band Phase Noise
RMS Integrated Phase Error12 0.64 Degrees typ 100 Hz to 100 kHz
Spurious Signals due to PFD Frequency
Level of Unlocked Signal with MTLD Enabled −42 dBm typ

1

Operating temperature range is −40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

For RF > 2 GHz, these characteristics are guaranteed only for VCO core power = 15 mA. For frequencies < 2 GHz, these characteristics are guaranteed only for VCO core

power = 20 mA.

6

Jumping from 2.0 GHz to 2.17 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7

Using 50 Ω resistors to V

8

The noise of the VCO is measured in open-loop conditions.

9

The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the

synthesizer; offset frequency = 1 kHz.

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for

the synthesizer; f

VCO

= 200 kHz; N = 10000; Loop B/W = 10 kHz.

PFD

= 1 MHz; N = 2000; Loop B/W = 25 kHz.

PFD

= 10 MHz @ 0 dBm.

REFOUT

5

400 μs typ To within 10 Hz of final frequency

−13/−6 dBm typ Programmable in 3 dB steps (see Tabl e 7)

5

8

10, 11

11, 13

= 3.3 V; P = 32.

VCO

into a 50 Ω load. For tuned loads, see the Output Matching section.

−110 dBc/Hz typ @ 100 kHz offset from carrier

−83 dBc/Hz typ @ 1 kHz offset from carrier

−70 dBc typ

= 20 mA, RF < 2 GHz

CORE

= 15 mA, RF > 2 GHz

CORE

Rev. B | Page 4 of 24

ADF4360-2

K

TIMING CHARACTERISTICS

AVDD = DVDD = V

Table 2.

Parameter Limit at T

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

1

See the Power-Up section for the recommended power-up procedure for this device.

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

to T

MIN

1

to T

MIN

(B Version) Unit Test Conditions/Comments

MAX

, unless otherwise noted.

MAX

CLOC

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

t

4

3

t

5

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

04436-002

Figure 2. Timing Diagram

Rev. B | Page 5 of 24

ADF4360-2

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND
AVDD to DVDD −0.3 V to +0.3 V
V

to GND −0.3 V to +3.9 V

VCO

V

to AVDD −0.3 V to +0.3 V

VCO

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature

Maximum Junction Temperature 150°C

CSP θJA Thermal Impedance

Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

GND = AGND = DGND = 0 V.

1

−0.3 V to +3.9 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those included in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

This device is a high performance RF integrated circuit with an

ESD rating of <1 kV; it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

TRANSISTOR COUNT

12,543 (CMOS) and 700 (Bipolar).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 6 of 24

ADF4360-2

T

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

21

PIN 1
IDENTIFIER

ADF4360-2

TOP VIEW

(Not to Scale)

AGND8AGND9AGND10AGND

MUXOU

20LE19

11

18

DATA

CLK

17

REF

16

IN

DGND

15

C

14

N

R

13

SET

12

C

C

04436-003

CPGND

AV

AGND

RF

OUT

RF

OUT

V

VCO

CP24CE23AGND22DV

1

2

DD

3

A

4

B

5

6

7

TUNE

V

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Descriptions

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV

must have the same value as DVDD.

DD

3, 8 to 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF

OUT

A

VCO Output. The output level is programmable from −6 dBm to −13 dBm. See the

Output Matching section

for a description of the various output stages.

5 RF

OUT

B

VCO Complementary Output. The output level is programmable from −6 dBm to −13 dBm. See the
Output Matching section for a description of the various output stages.

6 V

7 V

VCO

TUNE

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V

must have the same value as AVDD.

VCO

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

output voltage.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R

14 C

SET

N

Connecting a resistor between this pin and CP

synthesizer. The nominal voltage potential at the R

CPmax

where R

=

= 4.7 kΩ, I

SET

R

SET

= 2.5 mA.

CPmax

7511I.

Internal Compensation Node. This pin must be decoupled to V

sets the maximum charge pump output current for the

GND

pin is 0.6 V. The relationship between ICP and R

SET

with a 10 μF capacitor.

VCO

15 DGND Digital Ground.
16 REFIN

Reference Input. This is a CMOS input with a nominal threshold of V

100 kΩ. See
17 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

Figure 10. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

/2 and a dc equivalent input resistance of

DD

the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.
19 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches, and the relevant latch is selected using the control bits.
20 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.
21 DVDD

23 CE

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

must have the same value as AVDD.

DD

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP

Charge Pump Output. When enabled, this provides ± I

to the external loop filter, which in turn drives the

CP

internal VCO.

SET

is

Rev. B | Page 7 of 24

ADF4360-2

TYPICAL PERFORMANCE CHARACTERISTICS

0
–10

–20
–30
–40
–50

–60
–70
–80
–90

–100
–110
–120

OUTPUT POWER (dB)

–130
–140

–150
–160
–170

1k 10M1M100k10k

1

2

FREQUENCY OFFSET (Hz)

3

4

04436-004

Figure 4. Open-Loop VCO Phase Noise

–70

–75

–80

–85
–90

–95

–100

–105

–110
–115
–120

–125

OUTPUT POWER (dB)

–130
–135

–140

–145
–150

100 10M1M100k10k1k

FREQUENCY OFFSET (Hz)

04436-005

Figure 5. VCO Phase Noise, 2000 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth

–70

–75

–80

–85
–90

–95

–100

–105

–110
–115
–120

–125

OUTPUT POWER (dB)

–130
–135

–140

–145
–150

100 10M1M100k10k1k

FREQUENCY OFFSET (Hz)

04436-006

Figure 6. VCO Phase Noise, 1000 MHz,

Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth

0

VDD = 3V, V

–10

I

= 2.5mA

CP

PFD FREQUENCY = 200kHz

–20

LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 30Hz

–30

VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9SECONDS
AVERAGES = 10

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–2kHz –1kHz 2000MHz 1kHz 2kHz

VCO

= 3V

–84.0dBc/Hz

04436-007

Figure 7. Close-In Phase Noise at 2000 MHz (200 kHz Channel Spacing)

0

VDD = 3V, V

–10

I

= 2.5mA

CP

PFD FREQUENCY = 200kHz

–20

LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 3kHz

–30

VIDEO BANDWIDTH = 3kHz
SWEEP = 140ms
AVERAGES = 100

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–200kHz –100kHz 2000MHz 100kHz 200kHz

VCO

= 3V

–79.5dBc

04436-008

Figure 8. Reference Spurs at 2000 MHz

(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)

0

VDD = 3V, V

–10

I

= 2.5mA

CP

PFD FREQUENCY = 1MHz

–20

LOOP BANDWIDTH = 25kHz
RES. BANDWIDTH = 30kHz

–30

VIDEO BANDWIDTH = 30kHz
SWEEP = 50ms
AVERAGES = 100

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–1MHz –0.5MHz 2000MHz 0.5MHz 1MHz

VCO

= 3V

–83.8dBc/Hz

04436-009

Figure 9. Reference Spurs at 2000 MHz

(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)

Rev. B | Page 8 of 24

ADF4360-2

C

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

FROM VCO

N = BP + A

PRESCALER

MODULUS
CONTROL

P/P+1

13-BIT B

COUNTER

LOAD

LOAD

5-BIT A

COUNTER

TO PFD

100kΩ

NC

REF

SW1

SW2

SW3

NO

IN

NC

BUFFER

TO R COUNTER

04436-010

Figure 10. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the VCO and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, or 32/33 and is based on a synchronous 4/5 core. There is
a minimum divide ratio possible for fully contiguous output
frequencies; this minimum is determined by P, the prescaler
value, and is given by (P

2

− P).

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feedback
counter. The counters are specified to work when the prescaler
output is 300 MHz or less. Thus, with a VCO frequency of

2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9
is not valid.

N DIVIDER

04436-011

Figure 11. A and B Counters

R COUNTER

The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them.
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see

Tabl e 9).

U1

CLR1

UP

Q1D1

HI

R DIVIDER

Figure 12 is a simplified

V

P

CHARGE

PUMP

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
VCO frequency equation is

= [(P × B) + A] × f

f

VCO

REFIN

/R

where:

is the output frequency of the VCO.

f

VCO

P is the preset modulus of the dual-modulus prescaler (8/9,

HI

N DIVIDER

R DIVIDER

PROGRAMMABLE

ABP1 ABP2

CLR2

Q2D2

U2

DELAY

DOWN

U3

CPGND

CP

16/17, and so on).

B is the preset divide ratio of the binary 13-bit counter (3 to 8,191).

A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).

f

is the external reference frequency oscillator.

REFIN

Rev. B | Page 9 of 24

N DIVIDER

P OUTPUT

Figure 12. PFD Simplified Schematic and Timing (In Lock)

04436-012

ADF4360-2

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in
the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle.

The N-channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When a lock is detected, the output is high with narrow low­going pulses.

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

Tabl e 7. Figure 13 shows

DV

DD

CONTROLMUX

MUXOUT

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1 Data Latch

0 0 Control Latch
0 1 R Counter
1 0 N Counter (A and B)
1 1 Test Mode Latch

VCO

The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in
to be covered without a large VCO sensitivity (K
poor phase noise and spurious performance.

The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is

1. R counter latch

2. Control latch

3. N counter latch

During band select, which takes five PFD cycles, the VCO V
is disconnected from the output of the loop filter and is
connected to an internal reference voltage.

3.5

3.0

2.5

Figure 14, to allow a wide frequency range

) and resultant

V

TUNE

DGND

Figure 13. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. The two LSBs are DB1 and
DB0, as shown in

The truth table for these bits is shown in
a summary of how the latches are programmed. Note that the
test mode latch is used for factory testing and should not be
programmed by the user.

Figure 2.

Tabl e 5. Ta b le 6 shows

Rev. B | Page 10 of 24

04436-013

2.0

1.5

VOLTAGE (V)

1.0

0.5

0
1600 23002000 2100 2200190018001700

Figure 14. Frequency vs. V

FREQUENCY (MHz)

, ADF4360-2

TUNE

04436-014

The R counter output is used as the clock for the band select
logic and should not exceed 1 MHz. A programmable divider is
provided at the R counter input to allow division by 1, 2, 4, or 8
and is controlled by Bit BSC1 and Bit BSC2 in the R counter latch.
Where the required PFD frequency exceeds 1 MHz, the divide ratio
should be set to allow enough time for correct band selection.

After band selection, normal PLL action resumes. The nominal
value of K

is 57 MHz/V, or 28 MHz/V if divide-by-2 operation

V

is selected (by programming DIV2 [DB22] high in the N
counter latch). The ADF4360 family contains linearization
circuitry to minimize any variation of the product of I

and KV.

CP

ADF4360-2

The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bit PC1 and Bit PC2 in the control latch. For VCO frequencies
above 2 GHz, only the 15 mA core current should be used, and
for frequencies below 2 GHz, only 20 mA core current should
be used.

OUTPUT STAGE

The RF
connected to the collectors of an NPN differential pair driven
by buffered outputs of the VCO, as shown in
allow the user to optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable via Bit PL1 and Bit PL2 in the control latch. Four
current levels can be set: 3.5 mA, 5 mA, 7.5 mA, and 11 mA.
These levels give output power levels of −13 dBm, −11 dBm,

−8 dBm, and −6 dBm, respectively, using a 50 Ω resistor to V
and ac coupling into a 50 Ω load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the

A and RF

OUT

B pins of the ADF4360 family are

OUT

Output Matching section).

Figure 15. To

DD

If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V

DD

.

Another feature of the ADF4360 family is that the supply
current to the RF output stage is shut down until the part
achieves lock as measured by the digital lock detect circuitry.
This is enabled by the mute-till-lock detect (MTLD) bit in the
control latch.

VCO

BUFFER/

DIVIDE-BY-2

Figure 15. Output Stage ADF4360-2

RF

OUT

ARF

OUT

B

04436-015

Rev. B | Page 11 of 24

ADF4360-2

LATCH STRUCTURE

Tabl e 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determines which latch is programmed.

Table 6. Latch Structure

CONTROL LATCH

PRESCALER

VALUE

2 SELECT

DIVIDE-BY-

DIVSEL

RESERVED

POWER-

DB21DB22DB23

PD2P1P2

BY-2

DIVIDE-

DB21DB22DB23

CPGDIV2

BAND

SELECT

CLOCK

RESERVED

DB21DB22DB23

BSC2RSVRSV

CURRENT

DOWN 1

POWER-

SETTING 2

DOWN 2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CURRENT
SETTING 1

OUTPUT

POWER

LEVEL

LD

CP GAIN

MUTE-TILL-

CP

STATE

THREE-

PHASE

DETECTOR

POLARITY

MUXOUT

CONTROL

CORE

POWER

LEVEL

RESET

COUNTER

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

C2 (0) C1 (0)

N COUNTER LATCH

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

CONTROL

C2 (1) C1 (0)

13-BIT B COUNTER

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RESERVED

5-BIT A COUNTER

R COUNTER LATCH

ANTI-

BACKLASH

BIT

TEST

MODE

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LOCK

DETECT

PULSE

WIDTH

PRECISION

14-BIT REFERENCE COUNTER

R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTROL

C2 (0) C1 (1)

BITS

BITS

BITS

04436-016

Rev. B | Page 12 of 24

ADF4360-2

Table 7. Control Latch

PRESCALER

VAL UE

CURRENT

POWER-

SETTING 2

DOWN 1

DOWN 2

POWER-

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB1 0 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CURRENT

SETTING 1

OUTPUT

POWER

LEVEL

LD

MUTE-TILL-

CP

STATE

PHASE

THREE-

CP GAIN

MUXOUT

CONTROL

POLARITY

DETECTOR

PD2P1P2

(mA)

CPI6 CPI5 CPI4

CPI3 CPI2 CPI1 4.7kΩ

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

PL2 PL1 OUTPUT POWER LEVEL

0

0

0

1

1

0

1

1

I

CP

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

CURRENT POW ER INTO 50Ω (USING 50Ω TO V

3.5mA

5.0mA

7.5mA

11.0 mA

–13dBm
–11dBm
–8dBm
–6dBm

CPG
0
1

MUTE-TILL-LOCK DETECT

MTLD
0

DISABLED
ENABLED

1

CP
0
1

CP GAIN
CURRENT SE TTING 1
CURRENT SE TTING 2

PHASE DET ECTOR

PDP

POLARITY

0

NEGATIVE
POSITIVE

1

CHARGE PUM P
OUTPUT
NORMAL
THREE-STATE

)

VCC

CR

0
1

M3 M2 M1

001

010
011

100
101

110
111

CORE

POWER

LEVEL

RESET

COUNTER

PC2

PC1

0

0

0

1
10
11

COUNTER
OPERATION

NORMAL
R, A, B CO UNTERS
HELD IN RESE T

OUTPUT
THREE-STATE OUTPUT000
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV

R DIVIDER OUTPUT
N-CHANNE L OPEN-DRAI N
LOCK DETECT
SERIAL DATA OUTPUT
DGND

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CORE POW ER LEVEL
5mA
10mA
15mA
20mA

DD

CONTROL

BITS

C2 (0) C1 (0)

CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS P OWER-DO WN
1X0NORMAL OPERATION
101ASYNCHRONOUSPOWER-DOWN
1 1 1 SYNCHRONOUS POWE R-DOWN

P2 P1 PRESCALER VALUE
008/9
01 16/17
1032/33
1132/33

04436-017

Rev. B | Page 13 of 24

ADF4360-2

Table 8. N Counter Latch

DIVIDE-BY-

DIVSEL

BY-2

DIVIDE-

2 SELECT

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB2 3

13-BIT B COUNTER

RESERVED

5-BIT A COUNTER

CPGDIV2

THIS BIT IS NOT USED
BY THE DEVICE AND
IS A DON'T CARE BIT.

A5 A4 .......... A2 A1

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 28

1 1 .......... 0 1 29

1 1 .......... 1 0 30

1 1 .......... 1 1 31

B13 B12 B11 B3 B2 B1 B COUNTER DIVI DE RATIO

00 0
00 0
00 0

.. .
.. .

11 1
11 1
11 1

.......... 000 0

.......... 0 0 1 NOT ALLOWED

.......... 0 1 0 NOT ALLOWED

.......... 1 1 1 3

.......... ... .

.......... . . . .

.......... . . . .

.......... 111 1

.......... 1 0 1 8189

.......... 1 1 0 8190

.......... 1 1 1 8191

00 NOTALLOWED

.. .

0 0 8188

CONTROL

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

A COUNTER
DIVIDE RATIO

BITS

DIVSEL
0
1

F4 (FUNCT ION LATCH)
FASTLOCK ENABLE

DIVIDE-BY-2

DIV2
0

FUNDAMENTAL OUTPUT
DIVIDE-BY-2

1

DIVIDE- BY-2 SELECT (PRESCAL ER INPUT)

FUNDAMEN TAL OUTPUT SELECTED
DIVIDE- BY-2 SELECTED

CP GAIN OPERATION

00

10

CHARGE PUM P CURRENT S ETTING 1
IS PERMAN ENTLY USED

CHARGE PUM P CURRENT S ETTING 2
IS PERMAN ENTLY USED

Rev. B | Page 14 of 24

N = BP + A; P IS PRESCAL ER VALUE SET I N THE CONT ROL LATCH.
B MUST BE G REATER THAN OR EQ UAL TO A. FOR CONT INUOUSLY
ADJACENT VALUES OF (N × F

), AT THE OUTPUT, N

REF

IS (P2–P).

MIN

04436-018

ADF4360-2

Table 9. R Counter Latch

RESERVED

RESERVED

THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.

LOCK

DETECT

ANTI-

BACKLASH

PULSE
WIDTH

PRECISION

14-BIT REFERENCE COUNTER

BAND

SELECT

CLOCK

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

TEST

BIT

MODE

BSC2RSVRSV

TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns

LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

R14 R13 R12 R3 R2 R1 DIVIDE RATIO

00 0
00 0
00 0

.. .
.. .

11 1
11 1
11 1

.......... 000 0

.......... 0 1 1 2

.......... 0 1 0 3

.......... 1 0 1 4

.......... ... .

.......... . . . .

.......... . . . .

.......... 111 1

.......... 1 0 1 16381

.......... 1 1 0 16382

.......... 1 1 1 16383

00 1

.. .

0 0 16380

CONTROL

BITS

C2 (0) C1 (1)R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

BSC2 BSC1 BAND SELECT CLOCK DIVIDER
001
01 2
104
118

04436-019

Rev. B | Page 15 of 24

ADF4360-2

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-2 after
power-up is as:

1. R counter latch

2. Control latch

3. N counter latch

Initial Power-Up

Initial power-up refers to programming the part after the
application of voltage to the AV

, DVDD, V

DD

initial power-up, an interval is required between programming
the control latch and programming the N counter latch.

, and CE pins. On

VCO

This interval is necessary to allow the transient behavior of the
ADF4360-2 during initial power-up to have settled. During
initial power-up, a write to the control latch powers up the part
and the bias currents of the VCO begin to settle. If these
currents have not settled to within 10% of their steady-state
value, and if the N counter latch is then programmed, the VCO
may not be able to oscillate at the desired frequency, which does
not allow the band select logic to choose the correct frequency
band and the ADF4360-2 may not achieve lock. If the
recommended interval is inserted and the N counter latch is
programmed, the band select logic can choose the correct
frequency band, and the part locks to the correct frequency.

The duration of this interval is affected by the value of the
capacitor on the C

pin (Pin 14). This capacitor is used to

N

reduce the close-in noise of the ADF4360-2 VCO. The
recommended value of this capacitor is 10 μF. Using this value
requires an interval of ≥ 5 ms between the latching in of the
control latch bits and the latching in of the N counter latch bits.
If a shorter delay is required, this capacitor can be reduced. A
slight phase noise penalty is incurred by this change, which is
explained further in

Tabl e 10 .

Table 10. C

Capacitance vs. Interval and Phase Noise

N

CN Value Recommended Interval Between Control Latch and N Counter Latch Open-Loop Phase Noise @ 10 kHz Offset

10 μF ≥ 5 ms −86 dBc
440 nF ≥ 600 μs −85 dBc

POWER-UP

CLOCK

DATA

R COUNTER

LATCH DATA

LE

Figure 16. ADF4360-2 Power-Up Timing

CONTROL

LATCH DATA

N COUNTER

LATCH DATA

REQUIRED INTERVAL

CONTROL LATCH WRITE TO

N COUNTER LATCH WRITE

04436-020

Rev. B | Page 16 of 24

ADF4360-2

Hardware Power-Up/Power-Down

If the ADF4360-2 is powered down via the hardware (using the
CE pin) and powered up again without any change to the N
counter register during power-down, the part locks at the
correct frequency because it is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C

pin, which is <5 ms for 10 μF capacitance. The smaller

N

capacitance of 440 nF on this pin enables lock times of <600 μs.

Software Power-Up/Power-Down

If the ADF4360-2 is powered down via the software (using the
control latch) and powered up again without any change to the
N counter latch during power-down, the part locks at the
correct frequency because it is already in the correct frequency
band. The lock time depends on the value of capacitance on the
C

pin, which is <5 ms for 10 μF capacitance. The smaller

N

capacitance of 440 nF on this pin enables lock times of <600 μs.

The N counter value cannot be changed while it is in power­down because it may not lock to the correct frequency on
power-up. If it is updated, the correct programming sequence
for the part after power-up is to the R counter latch, followed by
the control latch, and finally the N counter latch, with the
required interval between the control latch and N counter latch,
as described in the

Initial Power-Up section.

The N counter value cannot be changed while the part is in
power-down because it may not lock to the correct frequency
on power-up. If it is updated, the correct programming
sequence for the parts after power-up is to the R counter latch,
followed by the control latch, and finally the N counter latch,
with the required interval between the control latch and N
counter latch, as described in the

Initial Power-Up section.

Rev. B | Page 17 of 24

ADF4360-2

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Tabl e 7
shows the input data format for programming the control latch.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1.

Prescaler Value

In the ADF4360 family, P2 and P1 in the control latch set the
prescaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power­down modes.

In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 is loaded with a 0. In the programmed
synchronous power-down, the device power-down is gated by
the charge pump to prevent unwanted frequency jumps. Once
the power-down is enabled by writing a 1 into Bit PD1 (on the
condition that a 1 is also loaded to PD2), the device goes into
power-down on the second rising edge of the R counter output,
after LE goes high. When the CE pin is low, the device is
immediately disabled regardless of the state of PD1 or PD2.

When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF outputs are debiased to a high impedance state.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in

Tabl e 7.

Output Power Level

Bit PL1 and Bit PL2 set the output power level of the VCO. See
the truth table in

Tabl e 7.

Mute-Till-Lock Detect (LD)

DB11 of the control latch in the ADF4360 family is the mute­till-lock detect bit. This function, when enabled, ensures that
the RF outputs are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360 family is the charge
pump gain bit. When it is programmed to 1, Current Setting 2
is used. When it is programmed to 0, Current Setting 1 is used.

Charge Pump (CP) Three-State

This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active noninverting filter. It can also be set to 0, which is
required if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1.
See the truth table in

Table 7 .

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading and

latching data.

Rev. B | Page 18 of 24

Counter Reset

DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The
recommended setting is 15 mA for frequencies above 2 GHz
and 20 mA for frequencies below 2 GHz. No other settings are
valid. See the truth table in

Tabl e 7.

ADF4360-2

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.
Tabl e 8 shows the input data format for programming the
N counter latch.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.
Tabl e 9 shows the input data format for programming the
R counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is
0 (00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit that is reserved. It should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is
the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When this bit is programmed to 1,
Current Setting 2 is used. When programmed to 0, Current
Setting 1 is used. This bit can also be programmed through DB10
of the control latch. The bit always reflects the latest value written to
it, whether through the control latch or the N counter latch.

Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For
example, using the output divide-by-2 feature and a PFD
frequency of 200 kHz, the user needs a value of N = 10,000 to
generate 1000 MHz. With the divide-by-2 select bit high, the
user can keep N = 5,000.

R Counter

R1 to R14 set the counter divide ratio. The divide range is

1 (00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.

Test Mode Bit (TMB)

DB19 is the test mode bit and should be set to 0. With TMB = 0,
the contents of the test mode latch are ignored and normal
operation occurs as determined by the contents of the control
latch, R counter latch, and N counter latch. Note that test modes
are for factory testing only and should not be programmed by
the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic. If this value is too high (>1 MHz), a divider
can be switched on to divide the R counter output to a smaller
value (see

Table 9).

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be
programmed to 0.

Rev. B | Page 19 of 24

ADF4360-2

APPLICATIONS

DIRECT CONVERSION MODULATOR

Direct conversion architectures are increasingly being used to
implement base station transmitters.

Figure 17 shows how ADI

parts can be used to implement such a system.

The circuit block diagram shows the
used with the
as the

AD8349. The use of dual integrated DACs, such

AD9761 with its specified ±0.02 dB and ±0.004 dB gain

AD9761 TxDAC® being

and offset matching characteristics, ensures minimum error
contribution (over temperature) from this portion of the signal
chain.

The local oscillator is implemented using the ADF4360-2. The
low-pass filter was designed using ADIsimPLL™ for a channel
spacing of 100 kHz and an open-loop bandwidth of 10 kHz.
The frequency range of the ADF4360-2 (1.85 GHz to 2.17 GHz)
makes it ideally suited for the implementation of a W-CDMA
transceiver.

The LO ports of the
from the complementary RF
ADF4360-2. This gives better performance than a single-ended
LO driver and eliminates the often necessary use of a balun to
convert from a single-ended LO input to the more desirable
differential LO inputs for the
noise (100 Hz to 100 kHz) of the LO in this configuration is 2.1°.

AD8349 accepts LO drive levels from −10 dBm to 0 dBm.

The
The optimum LO power can be software programmed on the
ADF4360-2, which allows levels from −13 dBm to −6 dBm from
each output.

The RF output is designed to drive a 50 Ω load but must be ac­coupled, as shown in
in quadrature by 2 V p-p signals, the resulting output power
from the modulator is approximately 2 dBm.

AD8349 can be driven differentially

A and RF

OUT

B outputs of the

OUT

AD8349. The typical rms phase

Figure 17. If the I and Q inputs are driven

MODULATED
DIGITAL
DATA

FREF

IN

1nF

10µF

4.7kΩ

REFIO

AD9761

TxDAC

FSADJ

2kΩ

V

VCO

6

DVDDAVDDCE MUXOUT

V

VCO

14

C

1nF1nF

51Ω

N

16

REF

IN

17

CLK

18

DATA

19

LE

12

C

C

13

R

SET

CPGND AGND DGND

1 3 8 9 10 11 22 15

ADF4360-2

V

DD

IOUTA

IOUTB

QOUTA

QOUTB

LOCK

DETECT

2023221

LOW-PASS

FILTER

LOW-PASS

FILTER

IBBP

V

7

TUNE

24

CP

V

RF

A

4

OUT

5

RF

B

OUT

13kΩ

6.8nF

470pF 220pF

6.8kΩ

VCO

47nH 47nH

1.8pF

1.8pF

3.6nH

3.6nH

IBBN

QBBP

QBBN

LOIP

LOIN

VPS1

PHASE

SPLITTER

AD8349

VPS2

TO

RF PA

04436-021

100pF

SPI-COMPATIBLE SERIAL BUS

Figure 17. Direct Conversion Modulator

Rev. B | Page 20 of 24

ADF4360-2

FIXED FREQUENCY LO

Figure 18 shows the ADF4360-2 used as a fixed frequency LO at

2.0 GHz. The low-pass filter was designed using ADIsimPLL
for a channel spacing of 8 MHz and an open-loop bandwidth of
40 kHz. The maximum PFD frequency of the ADF4360-2 is
8 MHz. Because using a larger PFD frequency allows the use of a
smaller N, the in-band phase noise is reduced to as low as
possible, –99 dBc/Hz. The 40 kHz bandwidth is chosen to be just
greater than the point at which the open-loop phase noise of the
VCO is –99 dBc/Hz, thus giving the best possible integrated
noise. The typical rms phase noise (100 Hz to 100 kHz) of the LO
in this configuration is 0.3°. The reference frequency is from a
16 MHz TCXO from Fox; thus, an R value of 2 is programmed.
Taking into account the high PFD frequency and its effect on the
band select logic, the band select clock divider is enabled. In this
case, a value of 8 is chosen. A very simple pull-up resistor and dc
blocking capacitor complete the RF output stage.

LOCK

V

DETECT

VDD

2023221

V

7

TUNE

24

CP

A

4

RF

OUT

5

B

RF

OUT

3.3nF

V

VCO

51Ω

18.0nF

560Ω

51Ω

100pF

100pF

FOX

801BE-160

16MHz

SPI-COMPATIBLE SERIAL BUS

1nF

10µF

V

VCO

6

DVDDAVDDCE MUXOUT

V

VCO

14

C

N

1nF1nF

16

REF

IN

51Ω

17

CLK

18

DATA

19

LE

12

C

C

13

R

4.7kΩ

SET

CPGND AGND DGND

1 3 8 9 10 11 22 15

Figure 18. Fixed Frequency LO

ADF4360-2

INTERFACING

The ADF4360 family has a simple SPI®-compatible serial
interface for writing to the device. CLK, DATA, and LE control
the data transfer. When LE goes high, the 24 bits that are
clocked into the appropriate register on each rising edge of CLK
are transferred to the appropriate latch. See
timing diagram and

Tabl e 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz or
one update every 1.2 μs. This is certainly more than adequate
for systems that have typical lock times in hundreds of
microseconds.

Figure 2 for the

04436-022

ADuC812 Interface

Figure 19 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Because the ADuC812 is based
on an 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three
8-bit bytes from the MicroConverter to the device. When the
third byte is written, the LE input should be brought high to
complete the transfer.

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 19. ADuC812 to ADF4360-x Interface

SCLK

SDATA

LE

ADF4360-x

CE

MUXOUT
(LOCK DE TECT )

04436-023

I/O port lines on the ADuC812 are also used to control power
down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the
output frequency can be changed is 166 kHz.

ADSP-21xx Interface

Figure 20 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated.

SCLOCK

MOSI

ADSP-21xx

TFS

I/O PORTS

Figure 20. ADSP-21xx to ADF4360-x Interface

SCLK

SDATA

LE

ADF4360-x

CE

MUXOUT
(LOCK DE TECT )

04436-024

Set up the word length for 8 bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the 8-bit bytes, enable the autobuffered mode, and write to
the transmit register of the DSP. This last operation initiates the
autobuffer transfer.

Rev. B | Page 21 of 24

ADF4360-2

V

V

V

04436-026

Figure 22

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that
shorting is avoided.

Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.

Experiments have shown that the circuit shown in
provides an excellent match to 50 Ω over the operating range of
the ADF4360-2. This gives approximately −3 dBm output
power across the frequency range of the ADF4360-2. Both
single-ended architectures can be examined using the
EVAL-ADF4360-2EB1 evaluation board.

VCO

47nH

3.6nH

RF

OUT

Figure 22. Optimum ADF4360-2 Output Stage

1.8pF

50Ω

If the user does not need the differential outputs available on
the ADF4360-2, the user can either terminate the unused
output or combine both outputs using a balun. The circuit in
Figure 23 shows how best to combine the outputs.

VCO

The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.

OUTPUT MATCHING

There are a number of ways to match the output of the
ADF4360-2 for optimum operation; the most basic is to use a
50 Ω resistor to V
connected in series, as shown in
is not frequency dependent, this provides a good broadband
match. The output power in this circuit typically gives −6 dBm
output power into a 50 Ω load.

A better solution is to use a shunt inductor (acting as an RF
choke) to V

VCO.

output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB
additional rejection of the second harmonic. The shunt
inductor needs to be a relatively high value (>40 nH).

. A dc bypass capacitor of 100 pF is

VCO

Figure 21. Because the resistor

VCO

51Ω

RF

OUT

Figure 21. Simple ADF4360-2 Output Stage

100pF

50Ω

04436-025

This gives a better match and, therefore, more

2.2nH

A

RF

OUT

RF

OUT

Figure 23. Balun for Combining ADF4360-2 RF Outputs

2.2nH

B

3.6nH

1.8pF

3.6nH

1.8pF

47nH

10pF

50Ω

04436-027

The circuit in Figure 23 is a lumped-lattice-type LC balun. It is
designed for a center frequency of 2.0 GHz and outputs 2.0 dBm at
this frequency. The series 2.2 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by −90°, thus
combining the two. The action of the 3.6 nH inductor and the

1.8 pF capacitor accomplishes this. The 47 nH is used to
provide an RF choke to feed the supply voltage, and the 10 pF
capacitor provides the necessary dc block. To ensure good RF
performance, the circuits in

Figure 22 and Figure 23 are
implemented with Coilcraft 0402/0603 inductors and AVX 0402
thin-film capacitors.

Alternatively, instead of the LC balun shown in

Figure 23, both

outputs can be combined using a 180° rat-race coupler.

Rev. B | Page 22 of 24

ADF4360-2

OUTLINE DIMENSIONS

0.60 MAX

19

18

EXPOSED

(BOTTOMVIEW)

13

12

PA D

24

6

7

1

2.50 REF

PIN 1
INDICATOR

*

2.45

2.30 SQ

2.15

0.23 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

*

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50

BSC

0.50

0.40

0.30

0.08

Figure 24. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4mm Body, Very Thin Quad (CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Frequency Range Package Description Package Option

ADF4360-2BCP −40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2
ADF4360-2BCPRL −40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2
ADF4360-2BCPRL7 −40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2
ADF4360-2BCPZ
ADF4360-2BCPZRL
ADF4360-2BCPZRL7
EVAL-ADF4360-2EB1 Evaluation Board

1

Z = Pb-free model.

1

−40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2

1

−40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2

1

−40°C to +85°C 1850 MHz to 2170 MHz 24-Lead LFCSP_VQ CP-24-2

Rev. B | Page 23 of 24

ADF4360-2

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04436–0–4/06(B)

T

Rev. B | Page 24 of 24

TTT