ANALOG DEVICES ADF4360-0 Service Manual

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Integrated Synthesizer and VCO

FEATURES

Output frequency range: 2400 MHz to 2725 MHz
Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

ADF4360-0

REF

CLK

DATA

IN

LE

14-BIT R

COUNTER

24-BIT

DATA REGISTER

AV

DD

24-BIT

FUNCTION

LATCH

DV

ADF4360-0

GENERAL DESCRIPTION

The ADF4360-0 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-0 is designed
for a center frequency of 2600 MHz. In addition, a divide-by-2
option is available, whereby the user gets an RF output of be­tween 1200 MHz and 1360 MHz.

Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from

3.0 V to 3.6 V and can be powered down when not in use.

CE

PHASE

R

SET

MULTIPLEXER

CHARGE

PUMP

MUTE

MUXOUT

CP

V

VCO

V

TUNE

C

C

C

N

DD

LOCK

DETECT

COMPARATOR

INTEGER

REGISTER

13-BIT B

COUNTER

PRESCALER

P/P+1

N = (BP + A)

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

LOAD
LOAD

5-BIT A

COUNTER

AGND DGND CPGND

MULTIPLEXER

Figure 1.

RF

A

OUT

RF

OUT

04644-0-001

B

DIVSEL = 1

DIVSEL = 2

VCO

CORE

OUTPUT

STAGE

÷2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADF4360-0

TABLE OF CONTENTS

Specifications..................................................................................... 3

VCO ............................................................................................. 10

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transis t o r Cou nt ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

PFD and Charge Pump................................................................ 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

Output Stage................................................................................ 11

Latch Structure ........................................................................... 12

Control Latch.............................................................................. 16

N Counter Latch......................................................................... 17

R Counter Latch ......................................................................... 17

Applications..................................................................................... 18

Fixed Frequency LO ................................................................... 18

Power-Up..................................................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for Chip Scale Package........................... 19

Output Matching........................................................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADF4360-0

SPECIFICATIONS

AVDD = DVDD = V

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/max

REFIN Input Sensitivity 0.7/AV
0 to AVDD V max CMOS compatible.
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±100 µA max

PHASE DETECTOR

Phase Detector Frequency2 8 MHz max

CHARGE PUMP

ICP Sink/Source3 With R

High Value 2.5 mA typ
Low Value 0.312 mA typ
R

Range 2.7/10 kΩ

SET

ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V.
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V.
ICP vs. Temperature 2 % typ VCP = 2.0 V.

LOGIC INPUTS

V

, Input High Voltage 1.5 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 3.0 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min CMOS output chosen.
IOH, Output High Current 500 µA max
VOL, Output Low Voltage 0.4 V max IOL = 500 µA.

POWER SUPPLIES

AVDD 3.0/3.6 V min/V max
DVDD AV
V

AV

VCO

4

AI

DD

4

DI

DD

, 5

4

I

VCO

4

I

RFOUT

Low Power Sleep Mode4 7 µA typ

RF OUTPUT CHARACTERISTICS5

VCO Output Frequency 2400/2725 MHz min/max I
VCO Sensitivity 56 MHz/V typ
Lock Time
Frequency Pushing (Open Loop) 1 MHz/V typ
Frequency Pulling (Open Loop) 15 kHz typ Into 2.00 VSWR load.
Harmonic Content (Second) −30 dBc typ
Harmonic Content (Third) −39 dBc typ
Output Power
Output Power Variation ±3 dB typ For tuned loads, see Output Matching section.
VCO Tuning Range 1.25/2.50 V min/max
VCO Tuning Port Leakage Current 0.2 nA typ

VCO

6

5, 7

1

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

DD

DD

DD

10 mA typ

2.5 mA typ

19.0 mA typ I

3.5 to 11.0 mA typ RF output stage is programmable.

250 µs typ To within 10 Hz of final frequency.

−13/−6.5 dBm typ Programmable in 3 dB steps. See Table 7.

MIN

to T

, unless otherwise noted.

MAX

For f < 10 MHz, use dc-coupled
CMOS compatible square wave, slew rate > 21 V/µs.

V p-p min/max AC-coupled.

= 4.7 kΩ.

SET

= 10 mA.

CORE

= 15 mA.

CORE

Rev. 0 | Page 3 of 20

ADF4360-0

Parameter B Version Unit Conditions/Comments

NOISE CHARACTERISTICS5

VCO Phase Noise Performance

−133 dBc/Hz typ @ 1 MHz offset from carrier.

−140 dBc/Hz typ @ 3 MHz offset from carrier.

−145 dBc/Hz typ @ 10 MHz offset from carrier.
Synthesizer Phase Noise Floor

−163 dBc/Hz typ @ 200 kHz PFD frequency.

−147 dBc/Hz typ @ 8 MHz PFD frequency.
In-Band Phase Noise

10, 11

RMS Integrated Phase Error12 1.4 Degrees typ 100 Hz to 100 kHz.
Spurious Signals due to PFD Frequency
Level of Unlocked Signal with MTLD Enabled −45 dBm typ

1

Operating temperature range is: –40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

These characteristics are guaranteed for VCO core power = 10 mA.

6

Jumping from 2.4 GHz to 2.725 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7

Using 50 Ω resistors to V

8

The noise of the VCO is measured in open-loop conditions.

9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer; offset frequency = 1 kHz.

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer; f

VCO

, into a 50 Ω load. For tuned loads, see Output Matching.

VCO

= 200 kHz; N = 2600; Loop B/W = 10 kHz.

PFD

= 1 MHz; N = 2600; Loop B/W = 25 kHz.

PFD

= 10 MHz @ 0 dBm.

REFOUT

8

9

= 3.3 V; P = 32.

11, 13

−111 dBc/Hz typ @ 100 kHz offset from carrier.

−172 dBc/Hz typ @ 25 kHz PFD frequency.

−80 dBc/Hz typ @ 1 kHz offset from carrier.

−75 dBc typ

Rev. 0 | Page 4 of 20

ADF4360-0

TIMING CHARACTERISTICS

AVDD = DVDD = V

Table 2.

Parameter Limit at T

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

to T

MIN

CLOCK

(B Version) Unit Test Conditions/Comments

MAX

t

t

4

5

MIN

to T

, unless other wise noted.

MAX

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

04414-0-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 20

ADF4360-0

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND
AVDD to DVDD −0.3 V to +0.3 V
V

to GND −0.3 V to +3.9 V

VCO

V

to AVDD −0.3 V to +0.3 V

VCO

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance

Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

−0.3 V to +3.9 V

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat­ing only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi­mum rating conditions for extended periods may affect device
reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

TRANSISTOR COUNT

12543 (CMOS) and 700 (Bipolar)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20