Datasheet ADF4360-0 Datasheet (ANALOG DEVICES)

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Integrated Synthesizer and VCO

FEATURES

Output frequency range: 2400 MHz to 2725 MHz
Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment

FUNCTIONAL BLOCK DIAGRAM

ADF4360-0

REF

CLK

DATA

IN

LE

14-BIT R

COUNTER

24-BIT

DATA REGISTER

AV

DD

24-BIT

FUNCTION

LATCH

DV

ADF4360-0

GENERAL DESCRIPTION

The ADF4360-0 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-0 is designed
for a center frequency of 2600 MHz. In addition, a divide-by-2
option is available, whereby the user gets an RF output of be­tween 1200 MHz and 1360 MHz.

Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from

3.0 V to 3.6 V and can be powered down when not in use.

CE

PHASE

R

SET

MULTIPLEXER

CHARGE

PUMP

MUTE

MUXOUT

CP

V

VCO

V

TUNE

C

C

C

N

DD

LOCK

DETECT

COMPARATOR

INTEGER

REGISTER

13-BIT B

COUNTER

PRESCALER

P/P+1

N = (BP + A)

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

LOAD
LOAD

5-BIT A

COUNTER

AGND DGND CPGND

MULTIPLEXER

Figure 1.

RF

A

OUT

RF

OUT

04644-0-001

B

DIVSEL = 1

DIVSEL = 2

VCO

CORE

OUTPUT

STAGE

÷2

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADF4360-0

TABLE OF CONTENTS

Specifications..................................................................................... 3

VCO ............................................................................................. 10

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transis t o r Cou nt ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

PFD and Charge Pump................................................................ 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

Output Stage................................................................................ 11

Latch Structure ........................................................................... 12

Control Latch.............................................................................. 16

N Counter Latch......................................................................... 17

R Counter Latch ......................................................................... 17

Applications..................................................................................... 18

Fixed Frequency LO ................................................................... 18

Power-Up..................................................................................... 18

Interfacing ................................................................................... 18

PCB Design Guidelines for Chip Scale Package........................... 19

Output Matching........................................................................ 19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

REVISION HISTORY

7/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20

ADF4360-0

SPECIFICATIONS

AVDD = DVDD = V

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/max

REFIN Input Sensitivity 0.7/AV
0 to AVDD V max CMOS compatible.
REFIN Input Capacitance 5.0 pF max
REFIN Input Current ±100 µA max

PHASE DETECTOR

Phase Detector Frequency2 8 MHz max

CHARGE PUMP

ICP Sink/Source3 With R

High Value 2.5 mA typ
Low Value 0.312 mA typ
R

Range 2.7/10 kΩ

SET

ICP Three-State Leakage Current 0.2 nA typ
Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V.
ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V.
ICP vs. Temperature 2 % typ VCP = 2.0 V.

LOGIC INPUTS

V

, Input High Voltage 1.5 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 3.0 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min CMOS output chosen.
IOH, Output High Current 500 µA max
VOL, Output Low Voltage 0.4 V max IOL = 500 µA.

POWER SUPPLIES

AVDD 3.0/3.6 V min/V max
DVDD AV
V

AV

VCO

4

AI

DD

4

DI

DD

, 5

4

I

VCO

4

I

RFOUT

Low Power Sleep Mode4 7 µA typ

RF OUTPUT CHARACTERISTICS5

VCO Output Frequency 2400/2725 MHz min/max I
VCO Sensitivity 56 MHz/V typ
Lock Time
Frequency Pushing (Open Loop) 1 MHz/V typ
Frequency Pulling (Open Loop) 15 kHz typ Into 2.00 VSWR load.
Harmonic Content (Second) −30 dBc typ
Harmonic Content (Third) −39 dBc typ
Output Power
Output Power Variation ±3 dB typ For tuned loads, see Output Matching section.
VCO Tuning Range 1.25/2.50 V min/max
VCO Tuning Port Leakage Current 0.2 nA typ

VCO

6

5, 7

1

= 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

DD

DD

DD

10 mA typ

2.5 mA typ

19.0 mA typ I

3.5 to 11.0 mA typ RF output stage is programmable.

250 µs typ To within 10 Hz of final frequency.

−13/−6.5 dBm typ Programmable in 3 dB steps. See Table 7.

MIN

to T

, unless otherwise noted.

MAX

For f < 10 MHz, use dc-coupled
CMOS compatible square wave, slew rate > 21 V/µs.

V p-p min/max AC-coupled.

= 4.7 kΩ.

SET

= 10 mA.

CORE

= 15 mA.

CORE

Rev. 0 | Page 3 of 20

ADF4360-0

Parameter B Version Unit Conditions/Comments

NOISE CHARACTERISTICS5

VCO Phase Noise Performance

−133 dBc/Hz typ @ 1 MHz offset from carrier.

−140 dBc/Hz typ @ 3 MHz offset from carrier.

−145 dBc/Hz typ @ 10 MHz offset from carrier.
Synthesizer Phase Noise Floor

−163 dBc/Hz typ @ 200 kHz PFD frequency.

−147 dBc/Hz typ @ 8 MHz PFD frequency.
In-Band Phase Noise

10, 11

RMS Integrated Phase Error12 1.4 Degrees typ 100 Hz to 100 kHz.
Spurious Signals due to PFD Frequency
Level of Unlocked Signal with MTLD Enabled −45 dBm typ

1

Operating temperature range is: –40°C to +85°C.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

These characteristics are guaranteed for VCO core power = 10 mA.

6

Jumping from 2.4 GHz to 2.725 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7

Using 50 Ω resistors to V

8

The noise of the VCO is measured in open-loop conditions.

9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer; offset frequency = 1 kHz.

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer; f

VCO

, into a 50 Ω load. For tuned loads, see Output Matching.

VCO

= 200 kHz; N = 2600; Loop B/W = 10 kHz.

PFD

= 1 MHz; N = 2600; Loop B/W = 25 kHz.

PFD

= 10 MHz @ 0 dBm.

REFOUT

8

9

= 3.3 V; P = 32.

11, 13

−111 dBc/Hz typ @ 100 kHz offset from carrier.

−172 dBc/Hz typ @ 25 kHz PFD frequency.

−80 dBc/Hz typ @ 1 kHz offset from carrier.

−75 dBc typ

Rev. 0 | Page 4 of 20

ADF4360-0

TIMING CHARACTERISTICS

AVDD = DVDD = V

Table 2.

Parameter Limit at T

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

= 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

to T

MIN

CLOCK

(B Version) Unit Test Conditions/Comments

MAX

t

t

4

5

MIN

to T

, unless other wise noted.

MAX

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

04414-0-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 20

ADF4360-0

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND
AVDD to DVDD −0.3 V to +0.3 V
V

to GND −0.3 V to +3.9 V

VCO

V

to AVDD −0.3 V to +0.3 V

VCO

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to + 85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
CSP θJA Thermal Impedance

Paddle Soldered 50°C/W
Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

−0.3 V to +3.9 V

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rat­ing only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maxi­mum rating conditions for extended periods may affect device
reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <1 kV and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

TRANSISTOR COUNT

12543 (CMOS) and 700 (Bipolar)

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 20

ADF4360-0

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DD

21

PIN 1
IDENTIFIER

ADF4360-0

TOP VIEW

(Not to Scale)

AGND8AGND9AGND10AGND

MUXOUT20LE

11

19

DATA

18

CLK

17
16

REF

IN

15

DGND

14

C

N

13

R

SET

12

C

C

04644-0-002

CPGND

AV

AGND

RF

OUT

RF

OUT

V

VCO

CP24CE23AGND22DV

1
2

DD

3
4

A
B

5
6

7

TUNE

V

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2 AVDD

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV

must have the same value as DVDD.

DD

3, 8 to 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.
4 RF

OUT

A

VCO Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output Matching section
for a description of the various output stages.

5 RF

OUT

B

VCO Complementary Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output
Matching section for a description of the various output stages.

6 V

7 V

VCO

TUNE

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. V

must have the same value as AVDD.

VCO

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

output voltage.
12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.
13 R

14 C

SET

N

Connecting a resistor between this pin and CP

synthesizer. The nominal voltage potential at the R

I

Where R

CPmax

SET

75.11

=

R

SET

= 4.7 kΩ, I

CPmax

= 2.5 mA.

Internal Compensation Node. This pin must be decoupled to V

sets the maximum charge pump output current for the

GND

pin is 0.6 V. The relationship between ICP and R

SET

with a 10 µF capacitor.

VCO

15 DGND Digital Ground.
16 REFIN

Reference Input. This is a CMOS input with a nominal threshold of V

/2 and a dc equivalent input resistance of

DD

100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
17 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
18 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.
19 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the

four latches, and the relevant latch is selected using the control bits.
20 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be

accessed externally.
21 DVDD

23 CE

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DV

must have the same value as AVDD.

DD

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

Taking the pin high powers up the device depending on the status of the power-down bits.
24 CP

Charge Pump Output. When enabled, this provides ± I

internal VCO.

to the external loop filter, which in turn, drives the

CP

is

SET

Rev. 0 | Page 7 of 20

ADF4360-0

TYPICAL PERFORMANCE CHARACTERISTICS

0
–10
–20
–30
–40
–50
–60
–70
–80
–90

–100
–110
–120

OUTPUT POWER (dB)

–130
–140
–150
–160
–170

1k 10M1M100k10k

–70
–75
–80
–85
–90

–95
–100
–105
–110
–115
–120
–125

OUTPUT POWER (dB)

–130
–135
–140
–145
–150

100 10M1M100k10k1000

Figure 5. VCO Phase Noise, 2600 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth

–70

–75

–80

–85

–90

–95
–100
–105
–110
–115
–120
–125

OUTPUT POWER (dB)

–130
–135
–140
–145
–150

100 10M1M100k10k1000

Divide-by-2 Enabled 200 kHz PFD, 10 kHz Loop Bandwidth

1

2

FREQUENCY OFFSET (Hz)

Figure 4. Open-Loop VCO Phase Noise

FREQUENCY OFFSET (Hz)

FREQUENCY OFFSET (Hz)

Figure 6. VCO Phase Noise, 1300 MHz,

3

4

04414-0-004

04644-0-007

04644-0-008

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80
–90

–2kHz –1kHz 2600MHz 1kHz 2kHz

REFERENCE

LEVEL = –3.5dBm

VDD = 3.3V, V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 30Hz
VIDEO BANDWIDTH = 30Hz
SWEEP = 1.9 SECONDS
AVERAGES = 20

= 3.3V

VCO

–80.4dBc/Hz

Figure 7. Close-In Phase Noise at 2600 MHz (200 kHz Channel Spacing)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80
–90

–0.25MHz –0.1MHz 2600MHz 0.1MHz 0.25MHz

REFERENCE

LEVEL = –6dBm

VDD = 3.3V, V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 10kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
AVERAGES = 20

VCO

–77dBc

= 3.3V

Figure 8. Reference Spurs at 2600 MHz

(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)

0

VDD = 3V, V

–10

= 2.5mA

I

CP

PFD FREQUENCY = 1MHz

–20

LOOP BANDWIDTH = 25kHz
RES. BANDWIDTH = 10kHz

–30

VIDEO BANDWIDTH = 10kHz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–40

–50

–60

–70

OUTPUT POWER (dB)

–80
–90

–1MHz –0.5MHz 2250MHz 0.5MHz 1MHz

VCO

= 3V

–86dBc/Hz

Figure 9. Reference Spurs at 2600 MHz

(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)

04644-0-009

04644-0-010

04644-0-011

Rev. 0 | Page 8 of 20

ADF4360-0

C

T

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

100kΩ

NC

REF

SW1

SW2

SW3

NO

IN

NC

BUFFER

TO R COUNTER

04414-0-010

Figure 10. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio,

N, to be realized (N =

BP + A). The dual-modulus prescaler, operating at CML levels,

takes the clock from the VCO and divides it down to a manage­able frequency for the CMOS A and B counters. The prescaler is
programmable. It can be set in software to 8/9, 16/17, or 32/33
and is based on a synchronous 4/5 core. There is a minimum
divide ratio possible for fully contiguous output frequencies;
this minimum is determined by P, the prescaler value, and is
given by (

2

P

− P).

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide range division ratio in the PLL feed­back counter. The counters are specified to work when the pre­scaler output is 300 MHz or less. Thus, with a VCO frequency of

2.5 GHz, a prescaler value of 16/17 is valid, but a value of 8/9 is
not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by
VCO frequency equation is

RfABPf

VCO

()

REFIN

/×]+×[=

where:

R. The

FROM VCO

R COUNTER

The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 12 is a simplified
schematic. The PFD includes a programmable delay element
that controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
R counter latch, ABP2 and ABP1, control the width of the pulse
(see Table 9).

HI

R DIVIDER

HI

N DIVIDER

N = BP + A

PRESCALER

P/P+1

MODULUS
CONTROL

N DIVIDER

Figure 11. A and B Counters

UP

Q1D1

U1

CLR1

PROGRAMMABLE

DELAY

ABP1 ABP2

CLR2

DOWN

Q2D2

U2

13-BIT B

COUNTER

LOAD

LOAD

5-BIT A

COUNTER

U3

V

P

CPGND

TO PFD

04414-0-011

CHARGE

PUMP

CP

f

is the output frequency of the VCO.

VCO

R DIVIDER

P is the preset modulus of the dual-modulus prescaler (8/9,

N DIVIDER

P OUTPU

Figure 12. PFD Simplified Schematic and Timing (In Lock)

04414-0-012

16/17, and so on).

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).
A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).
f

is the external reference frequency oscillator.

REFIN

Rev. 0 | Page 9 of 20

ADF4360-0

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4360 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. The full truth table is shown in Table 7. Figure 13 shows
the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital and analog. Digital lock detect is active high. When LDP
in the R counter latch is set to 0, digital lock detect is set high
when the phase error on three consecutive phase detector cycles
is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns
phase error are required to set the lock detect. It stays set high
until a phase error of greater than 25 ns is detected on any sub­sequent PD cycle.

The N-channel open-drain analog lock detect should be oper­ated with an external pull-up resistor of 10 kΩ nominal. When a
lock has been detected, this output is high with narrow low­going pulses.

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT
N COUNTER OUTPUT

SDOUT

Figure 13. MUXOUT Circuit

CONTROLMUX

INPUT SHIFT REGISTER

The ADF4360 family’s digital section includes a 24-bit input
shift register, a 14-bit R counter, and an 18-bit N counter,
comprised of a 5-bit A counter and a 13-bit B counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 5. Table 6 shows
a summary of how the latches are programmed. Note that the
test modes latch is used for factory testing and should not be
programmed by the user.

MUXOUT

DGND

04414-0-013

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1

0 0 Control Latch
0 1 R Counter
1 0 N Counter (A and B)
1 1 Test Modes Latch

VCO

The VCO core in the ADF4360 family uses eight overlapping
bands, as shown in Figure 14, to allow a wide frequency range to
be covered without a large VCO sensitivity (K
poor phase noise and spurious performance.

The correct band is chosen automatically by the band select
logic at power-up or whenever the N counter latch is updated. It
is important that the correct write sequence be followed at
power-up. This sequence is

1.

R counter latch
Control latch

2.

3.

N counter latch

During band s elect, which takes five PFD cycles, the VCO V
is disconnected from the output of the loop filter and connected
to an internal reference voltage.

2.5

2.3

2.1

1.9

1.7

1.5

1.3

VOLTAGE (V)

1.1

0.9

0.7

0.5
2200 2400 2600 2800 3000

Figure 14. Frequency vs. V

FREQUENCY (MHz)

TUNE

The R counter output is used as the clock for the band select logic
and should not exceed 1 MHz. A programmable divider is provided
at the R counter input to allow division by 1, 2, 4, or 8 and is con­trolled by Bits BSC1 and BSC2 in the R counter latch. Where the
required PFD frequency exceeds 1 MHz, the divide ratio should be
set to allow enough time for correct band selection.

After band select, normal PLL action resumes. The nominal
value of K

is 56 MHz/V or 28 MHz/V, if divide-by-2 operation

V

has been selected (by programming DIV2 (DB22) high in the N
counter latch). The ADF4360 family contains linearization cir­cuitry to minimize any variation of the product of I

) and resultant

V

, ADF4360-0

and KV.

CP

TUNE

04644-0-004

Rev. 0 | Page 10 of 20

ADF4360-0

The operating current in the VCO core is programmable in four
steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by
Bits PC1 and PC2 in the control latch.

OUTPUT STAGE

The RF
nected to the collectors of an NPN differential pair driven by
buffered outputs of the VCO, as shown in Figure 15. To allow
the user to optimize the power dissipation versus the output
power requirements, the tail current of the differential pair is
programmable via Bits PL1 and PL2 in the control latch. Four
current levels may be set: +3.5 mA, +5 mA, +7.5 mA, and
+11 mA. These levels give output power levels of −13 dBm,

−11 dBm, −8.5 dBm, and −6.5 dBm, respectively, using a 50 Ω
resistor to V
both outputs can be combined in a 1 + 1:1 transformer or a 180°
microstrip coupler (see the Output Matching section).

A and RF

OUT

and ac coupling into a 50 Ω load. Alternatively,

DD

B pins of the ADF4360 family are con-

OUT

If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V

DD

.

Another feature of the ADF4360 family is that the supply current
to the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by the
Mute-Till-Lock Detect (MTLD) bit in the control latch.

RF

VCO

BUFFER/

DIVIDE BY 2

Figure 15. Output Stage ADF4360-0

ARF

OUT

OUT

B

04414-0-015

Rev. 0 | Page 11 of 20

ADF4360-0

LATCH STRUCTURE

Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs decide which latch is programmed.

Table 6. Latch Structure

CONTROL LATCH

PRESCALER

VALUE

2 SELECT

DIVIDE-BY-

RESERVED

POWER-

DB21DB22DB23

PD2P1P2

BY-2

DIVIDE-

DB21DB22DB23

CPGDIV2DIVSEL

BAND

SELECT

CLOCK

RESERVED

DB21DB22DB23
BSC2RSVRSV

CURRENT

DOWN 1

POWER-

SETTING2

DOWN 2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CURRENT

SETTING1

OUTPUT
POWER

LEVEL

LD

CP GAIN

MUTE-TILL-

CP

STATE

THREE-

PHASE

DETECTOR

POLARITY

MUXOUT

CONTROL

CORE

POWER

LEVEL

RESET

COUNTER

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

C2 (0) C1 (0)

N COUNTER LATCH

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

CONTROL

C2 (1) C1 (0)

13-BIT B COUNTER

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

RESERVED

5-BIT A COUNTER

R COUNTER LATCH

ANTI-

BACKLASH

BIT

TEST

MODE

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

LOCK

DETECT

PULSE

WIDTH

PRECISION

14-BIT REFERENCE COUNTER

R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTROL

C2 (0) C1 (1)

BITS

BITS

BITS

04414-0-026

Rev. 0 | Page 12 of 20

ADF4360-0

Table 7. Control Latch

PRESCALER

VALUE

CURRENT

SETTING 2

DOWN 2

DOWN 1

POWER-

POWER-

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CURRENT

SETTING 1

OUTPUT

POWER

LEVEL

MUTE-TILL-

LD

CP

CP GAIN

STATE

THREE-

PHASE

MUXOUT

CONTROL

POLARITY

DETECTOR

PD2P1P2

I

CPI6 CPI5 CPI4
CPI3 CPI2 CPI1 4.7kΩ
0

0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

PL2 PL1 OUTPUT POWER LEVEL

0

0

1

0

0

1

1

1

CP

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

CURRENT POWER INTO 50Ω (USING 50Ω TO V

3.5mA

5.0mA

7.5mA

11.0mA

(mA)

–13dBm
–11dBm
–8.5dBm
–6.5dBm

CPG
0
1

MUTE-TILL-LOCK DETECT

MTLD
0

DISABLED
ENABLED

1

CP

0
1

CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2

PHASE DETECTOR
POLARITY

PDP
0

NEGATIVE
POSITIVE

1

CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE

)

VCC

CR
0

1

M3 M2 M1

001

010
011

100
101

110
111

CORE

POWER

LEVEL

RESET

COUNTER

PC2

PC1

0

0

0

1
10
11

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS
HELD IN RESET

OUTPUT
THREE-STATE OUTPUT000
DIGITAL LOCK DETECT

(ACTIVE HIGH)
N DIVIDER OUTPUT
DV

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

BITS

C2 (0) C1 (0)

CORE POWER LEVEL
5mA
10mA
15mA
20mA

CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
1 0 1 ASYNCHRONOUS POWER-DOWN
1 1 1 SYNCHRONOUS POWER-DOWN

P2 P1 PRESCALER VALUE
0 0 8/9
0 1 16/17
1 0 32/33
1 1 32/33

04436-0-013

Rev. 0 | Page 13 of 20

ADF4360-0

Table 8. N Counter Latch

2 SELECT

DIVIDE-BY-

DIVSEL

BY-2

DIVIDE-

DB21DB22DB23

CPGDIV2

CONTROL

CP GAIN

13-BIT B COUNTER

5-BIT A COUNTER

RESERVED

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

THIS BIT IS NOT USED
BY THE DEVICE AND
IS A DON'T CARE BIT.

A5 A4 .......... A2 A1

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 28

1 1 .......... 0 1 29

1 1 .......... 1 0 30

1 1 .......... 1 1 31

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

000
000
000

.. .
.. .

111
111
111

.......... 0000

.......... 0 0 1 NOT ALLOWED

.......... 0 1 0 NOT ALLOWED

.......... 1 1 1 3

.......... ... .

.......... . . . .

.......... . . . .

.......... 1111

.......... 1 0 1 8189

.......... 1 1 0 8190

.......... 1 1 1 8191

0 0 NOT ALLOWED

.. .

0 0 8188

A COUNTER
DIVIDE RATIO

BITS

DIVSEL
0
1

F4 (FUNCTION LATCH)
FASTLOCK ENABLE

DIVIDE-BY-2

DIV2
0

FUNDAMENTAL OUTPUT
DIVIDE-BY-2

1

DIVIDE-BY-2 SELECT (PRESCALER INPUT)
FUNDAMENTAL OUTPUT SELECTED

DIVIDE-BY-2 SELECTED

CP GAIN OPERATION
00

10

CHARGE PUMP CURRENT SETTING 1
IS PERMANENTLY USED

CHARGE PUMP CURRENT SETTING 2
IS PERMANENTLY USED

Rev. 0 | Page 14 of 20

N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N × F

), AT THE OUTPUT, N

REF

IS (P2–P).

MIN

04414-0-018

ADF4360-0

Table 9. R Counter Latch

RESERVED

RESERVED

THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.

LOCK

DETECT

ANTI-

BACKLASH

PULSE
WIDTH

PRECISION

14-BIT REFERENCE COUNTER

BAND

SELECT

CLOCK

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

TEST

BIT

MODE

BSC2RSVRSV

TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH
0 0 3.0ns
0 1 1.3ns
1 0 6.0ns
1 1 3.0ns

LDP LOCK DETECT PRECISION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

R14 R13 R12 R3 R2 R1 DIVIDE RATIO

000
000
000

...
...

111
111
111

.......... 000 0

.......... 0 1 1 2

.......... 0 1 0 3

.......... 1 0 1 4

.......... ....

.......... . . . .

.......... . . . .

.......... 111 1

.......... 1 0 1 16381

.......... 1 1 0 16382

.......... 1 1 1 16383

00 1

.. .

0 0 16380

CONTROL

BITS

C2 (0) C1 (1)R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

BSC2 BSC1 BAND SELECT CLOCK DIVIDER
001
012
104
118

04414-0-017

Rev. 0 | Page 15 of 20

ADF4360-0

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Table 7
shows the input data format for programming the control latch.

Prescaler Value

In the ADF4360 family, P2 and P1 in the control latch set the
prescaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power­down modes.

In the programmed asynchronous power-down, the device
powers down immediately after latching a 1 into Bit PD1, with
the condition that PD2 has been loaded with a 0. In the pro­grammed synchronous power-down, the device power-down is
gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a 1 into
Bit PD1 (on the condition that a 1 has also been loaded to PD2),
the device goes into power-down on the second rising edge of
the R counter output, after LE goes high. When the CE pin is
low, the device is immediately disabled regardless of the state of
PD1 or PD2.

When a power-down is activated (either synchronous or
asynchronous mode), the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF outputs are debiased to a high impedance state.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading and

latching data.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360 family determine
Current Setting 1.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the
truth table in Table 7.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the
truth table in Table 7.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360 family is the Mute-Till­Lock Detect bit. This function, when enabled, ensures that the RF
outputs are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360 family is the Charge
Pump Gain bit. When it is programmed to a 1, Current Setting 2
is used. When it is programmed to a 0, Current Setting 1 is used.

Charge Pump Three-State

This bit puts the charge pump into three-state mode when
programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

The PDP bit in the ADF4360 family sets the phase detector
polarity. The positive setting enabled by programming a 1 is
used when using the on-chip VCO with a passive loop filter or
with an active non-inverting filter. It can also be set to 0. This is
required, if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1. See
the truth table in Table 7.

Counter Reset

DB4 is the counter reset bit for the ADF4360 family. When this
is 1, the R counter and the A, B counters are reset. For normal
operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The recom­mended setting is 10 mA. See the truth table in Table 7.

Rev. 0 | Page 16 of 20

ADF4360-0

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.
Table 8 shows the input data format for programming the
N counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is 0
(00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit and has been designated as Reserved. It
should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is
the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When this is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is used.
This bit can also be programmed through DB10 of the control
latch. The bit always reflects the latest value written to it, whether
this is through the control latch or the N counter latch.

Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When it is set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For exam­ple, using the output divide-by-2 feature and a PFD frequency
of 200 kHz, the user needs a value of N = 13,000 to generate
1,500 MHz. With the divide-by-2 select bit high, the user may
keep N = 6,500.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.

R Counter

R1 to R14 set the counter divide ratio. The divide range is 1

(00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken; with LDP at 0,
three cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be pro­grammed by the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic, but, if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).

Reserved Bits

DB23 to DB22 are spare bits that have been designated as
Reserved. They should be programmed to 0.

Rev. 0 | Page 17 of 20

ADF4360-0

APPLICATIONS

FIXED FREQUENCY LO

Figure 16 shows the ADF4360-0 used as a fixed frequency LO at 2.6
GHz. The low-pass filter was designed using ADIsimPLL for a
channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz.
The maximum PFD frequency of the ADF4360-0 is 8 MHz. Since
using a larger PFD frequency allows users to use a smaller N, the
in-band phase noise is reduced to as low as possible, –100 dBc/Hz.
The 40 kHz bandwidth is chosen to be just greater than the point at
which the open-loop phase noise of the VCO is –100 dBc/Hz, thus
giving the best possible integrated noise. The typical rms phase
noise (100 Hz to 100 kHz) of the LO in this configuration is 0.35°.
The reference frequency is from a 16 MHz TCXO from Fox; thus,
an R value of 2 is programmed. Taking into account the high PFD
frequency and its effect on the band select logic, the band select
clock divider is enabled. In this case, a value of 8 is chosen. A very
simple pull-up resistor and dc blocking capacitor complete the RF
output stage.

V

VCO

6

DVDDAVDDCE MUXOUT

V

VCO

14

C

N

1nF1nF

16

REF

IN

51Ω

17

CLK

18

DATA

19

LE

12

C

13

R

CPGND AGND DGND

1

ADF4360-0

C

SET

3 8 9 10 11 22 15

FOX

801BE-160

16MHz

SPI COMPATIBLE SERIAL BUS

1nF

10µF

4.7kΩ

Figure 16. Fixed Frequency LO

POWER-UP

After power-up, the part needs three writes for normal opera­tion. The correct sequence is to the R counter latch, followed by
the control latch, and N counter latch.

INTERFACING

The ADF4360 family has a simple SPI® compatible serial inter­face for writing to the device. CLK, DATA, and LE control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the appropriate register on each rising edge of CLK
are transferred to the appropriate latch. See Figure 2 for the
timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible is 833 kHz or
one update every 1.2 µs. This is more than adequate for systems
that have typical lock times in hundreds of microseconds.

LOCK

V

DETECT

VDD

2023221

V

7

TUNE

24

CP

A

4

RF

OUT

5

B

RF

OUT

3kΩ

8.2nF

560pF 270pF

1.5kΩ

V

VCO

51Ω

51Ω

100pF

100pF

ADuC812 Interface

Figure 17 shows the interface between the ADF4360 family and
the ADuC812 MicroConverter®. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051 based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4360 family
needs a 24-bit word, which is accomplished by writing three 8­bit bytes from the MicroConverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 17. ADuC812 to ADF4360-x Interface

SCLK
SDATA

LE

ADF4360-x

CE
MUXOUT

(LOCK DETECT)

04437-0-014

I/O port lines on the ADuC812 are also used to control power­down (CE input) and detect lock (MUXOUT configured as lock
detect and polled by the port input). When operating in the
described mode, the maximum SCLOCK rate of the ADuC812
is 4 MHz. This means that the maximum rate at which the out­put frequency can be changed is 166 kHz.

ADSP-2181 Interface

Figure 18 shows the interface between the ADF4360 family and
the ADSP-21xx digital signal processor. The ADF4360 family
needs a 24-bit serial word for each latch write. The easiest way

04644-0-003

to accomplish this using the ADSP-21xx family is to use the
autobuffered transmit mode of operation with alternate fram­ing. This provides a means for transmitting an entire block of
serial data before an interrupt is generated.

SCLOCK

MOSI

TFS

ADSP-21xx

I/O PORTS

Figure 18. ADSP-21xx to ADF4360-x Interface

SCLK
SDATA

LE

ADF4360-x

CE
MUXOUT

(LOCK DETECT)

04437-0-015

Set up the word length for 8 bits and use three memory loca­tions for each 24-bit word. To program each 24-bit latch, store
the 8-bit bytes, enable the autobuffered mode, and write to the
transmit register of the DSP. This last operation initiates the
autobuffer transfer.

Rev. 0 | Page 18 of 20

ADF4360-0

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package lead length and 0.05 mm wider than
the package lead width. The lead should be centered on the pad
to ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short­ing is avoided.

Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and

0.33 mm, and the via barrel should be plated with 1 ounce of
copper to plug the via.

Experiments have shown that the circuit shown in Figure 20
provides an excellent match to 50 Ω over the operating range of
the ADF4360-0. This gives approximately −4 dBm output power
across the frequency range of the ADF4360-0. Both single­ended architectures can be examined using the EVAL­ADF4360-0EB1 evaluation board.

V

VCO

47nH

3.9nH

RF

OUT

Figure 20. Differential ADF4360-0 Output Stage

1.5pF

50Ω

04414-0-021

If the user does not need the differential outputs available on
the ADF4360-0, the user may either terminate the unused out­put or combine both outputs using a balun. The circuit in
Figure 21 shows how best to combine the outputs.

V

VCO

The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.

OUTPUT MATCHING

There are a number of ways to match the output of the
ADF4360-0 for optimum operation; the most basic is to use a
50 Ω resistor to V
nected in series, as shown in Figure 19. Because the resistor is
not frequency dependent, this provides a good broadband
match. The output power in the circuit below typically gives

−6.5 dBm output power into a 50 Ω load.

A better solution is to use a shunt inductor (acting as an RF
choke) to V

VCO.

therefore, more output power. Additionally, a series inductor is
added after the dc bypass capacitor to provide a resonant LC
circuit. This tunes the oscillator output and provides approxi­mately 10 dB additional rejection of the second harmonic. The
shunt inductor needs to be a relatively low value (<10 nH).

. A dc bypass capacitor of 100 pF is con-

VCO

V

VCO

51Ω

RF

OUT

Figure 19. Simple ADF4360-1 Output Stage

100pF

50Ω

04414-0-020

This gives a better match than a resistor and,

1nH

A

RF

OUT

RF

OUT

Figure 21. Balun for Combining ADF4360-0 RF Outputs

1nH

B

3.6nH

1.5pF

3.6nH

1.5pF

47nH

10pF

50Ω

04414-0-022

The circuit in Figure 21 is a lumped lattice type LC balun. It is
designed for a center frequency of 2.6 GHz and outputs −1 dBm
at this frequency. The series 1 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by −90°, thus
combining the two. The action of the 3.6 nH inductor and the

1.5 pF capacitor accomplishes this. The 12 nH is used to provide
an RF choke to feed the supply voltage, and the 10 pF capacitor
provides the necessary dc block. To ensure good RF perform­ance, the circuits in Figure 19 and Figure 21 are implemented
with Coilcraft 0402/0603 inductors and AVX 0402 thin-film
capacitors.

Alternatively, instead of the LC balun shown in Figure 21, both
outputs may be combined using a 180° rat-race coupler.

Rev. 0 | Page 19 of 20

ADF4360-0

OUTLINE DIMENSIONS

0.08

0.60 MAX

19

18

BOTTOM

13

12

VIEW

24

7

1

6

2.50 REF

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING
PLANE

12° MAX

4.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65TYP

COMPLIANT TOJEDEC STANDARDSMO-220-VGGD-2

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.60 MAX

0.05 MAX

0.02 NOM

0.50

BSC

0.50

0.40

0.30

COPLANARITY

Figure 22. 24-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Frequency Range Package Option

ADF4360-0BCP −40°C to +85°C 2400 MHz to 2725 MHz CP-24-1
ADF4360-0BCPRL −40°C to +85°C 2400 MHz to 2725 MHz CP-24-1
ADF4360-0BCPRL7 −40°C to +85°C 2400 MHz to 2725 MHz CP-24-1
EVAL-ADF4360-0EB1 Evaluation Board

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D04644–0–7/04(0)

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