ANALOG DEVICES ADF4351 Service Manual

Wideband Synthesizer

V

Data Sheet

FEATURES

Output frequency range: 35 MHz to 4400 MHz Fractional-N synthesizer and integer-N synthesizer Low phase noise VCO Programmable divide-by-1/-2/-4/-8/-16/-32/-64 output Typical jitter: 0.3 ps rms Typical EVM at 2.1 GHz: 0.4% Power supply: 3.0 V to 3.6 V Logic compatibility: 1.8 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level RF output mute function 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,

GSM, PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

with Integrated VCO

ADF4351

GENERAL DESCRIPTION

The ADF4351 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and external reference frequency.

The ADF4351 has an integrated voltage controlled oscillator (VCO) with a fundamental output frequency ranging from 2200 MHz to 4400 MHz. In addition, divide-by-1/-2/-4/-8/-16/-32/-64 circuits allow the user to generate RF output frequencies as low as 35 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable. An auxiliary RF output is also available, which can be powered down when not in use.

Control of all on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to

3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

SDV

REF

IN

CLK

DATA

LE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

×2

DOUBLER

DATA REGISTE R

N COUNTER

CE

INTEGER

VALUE

AGND

AV

DD

10-BIT R

COUNTER÷2DIVIDER

FUNCTION

FRACTION

VALUE

MODULUS

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

DGND CP

DV

LATCH

DD

GND

P

LOCK

DETECT

PHASE

COMPARATOR

R

SETVVCO

MULTIPLEXER

CHARGE

PUMP

VCO

CORE

÷1/2/4/8/16/

MULTIPLEXER

SD

32/64

GNDAGNDVCO

FAST LOCK

SWITCH

MULTIPLEXER

ADF4351

OUTPUT

STAGE

OUTPUT

STAGE

Figure 1.

MUXOUT

SW LD

CP

OUT

V

TUNE

V

REF

V

COM

TEMP

RF

OUT

RF

OUT

PDB

RF

OUT

RF

OUT

A+

A–

B+ B–

09800-001

ADF4351 Data Sheet

REVISION HISTORY

5/12—Revision 0: Initial Ve r si o n

Register 1 ..................................................................................... 18

Register 2 ..................................................................................... 18

Register 3 ..................................................................................... 19

Register 4 ..................................................................................... 20

Register 5 ..................................................................................... 20

Register Initialization Sequence ............................................... 20

RF Synthesizer—A Worked Example ...................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus ................................................ 21

Cycle Slip Reduction for Faster Lock Times ........................... 22

Spurious Optimization and Fast Lock ..................................... 22

Fast Lock Timer and Register Sequences ................................ 22

Fast Lock Example ..................................................................... 22

Fast Lock Loop Filter Topology ................................................ 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync ............................................................................... 24

Applications Information .............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing to the ADuC70xx and the ADSP-BF527 ............. 26

PCB Design Guidelines for a Chip Scale Package ................. 26

Output Matching ........................................................................ 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

Data Sheet ADF4351

REFIN CHARACTERISTICS

SET

Hig h Value

5

mA

SET

INH

INL

INH/IINL

LOGIC OUTPUTS

VCO

DD

VCO

2

RFOUT

2

SPECIFICATIONS

AVDD = DVDD = V temperature range is −40°C to +85°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

Input Frequency 10 250 MHz For f < 10 MHz, ensure slew rate > 21 V/µs

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/2; ac coupling ensures AVDD/2 bias

Input Capacitance 10 pF

Input Current ±60 µA

PHASE FREQUENCY DETECTOR (PFD)

Phase Detector Frequency 32 MHz Fractional-N

45 MHz Integer-N (band select enabled)

90 MHz Integer-N (band select disabled)

CHARGE PUMP

ICP Sink/Source1 R

Low Value 0.312 mA R

Range 3.9 10 kΩ Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ 2.5 V ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ 2.5 V ICP vs. Temperature 2 % VCP = 2.0 V

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, CIN 3.0 pF

= SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

VCO

1.5 V

0.6 V

±1 µA

MIN

to T

, unless otherwise noted. Operating

MAX

= 5.1 kΩ

Output High Voltage, VOH DVDD − 0.4 V CMOS output selected Output High Current, IOH 500 µA Output Low Voltage, VOL 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 3.0 3.6 V DVDD, V DIDD + AI

, SDVDD, VP AVDD These voltages must equal AVDD

2

21 27 mA Output Dividers 6 to 36 mA Each output divide-by-2 consumes 6 mA I

70 80 mA

I

21 26 mA RF output stage is programmable

Low Power Sleep Mode 7 10 µA

RF OUTPUT CHARACTERISTICS

VCO Output Frequency 2200 4400 MHz Fundamental VCO mode Minimum VCO Output Frequency

Using Dividers

34.375 MHz 2200 MHz fundamental output and divide-by-64 selected

VCO Sensitivity, KV 40 MHz/V Frequency Pushing (Open-Loop) 1 MHz/V Frequency Pulling (Open-Loop) 90 kHz Into 2.00 VSWR load Harmonic Content (Second) −19 dBc Fundamental VCO output

−20 dBc Divided VCO output Harmonic Content (Third) −13 dBc Fundamental VCO output

−10 dBc Divided VCO output

Rev. 0 | Page 3 of 28

ADF4351 Data Sheet

Maximum VCO Tuning Voltage

2.5 V

−134

dBc/Hz

1 MHz offset from 3.3 GHz carrier

−145

dBc/Hz

5 MHz offset from 4.4 GHz carrier

SYNTH

1_f

−116

dBc/Hz

ABP = 6 ns

Parameter Min Typ Max Unit Test Conditions/Comments

Minimum RF Output Power3 −4 dBm Programmable in 3 dB steps Maximum RF Output Power3 5 dBm Output Power Variation ±1 dB Minimum VCO Tuning Voltage 0.5 V

NOISE CHARACTERISTICS

VCO Phase Noise Performance VCO noise is measured in open-loop conditions

−89 dBc/Hz 10 kHz offset from 2.2 GHz carrier

−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier

−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier

−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier

−86 dBc/Hz 10 kHz offset from 3.3 GHz carrier

−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier

−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier

−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier

−110 dBc/Hz 100 kHz offset from 4.4 GHz carrier

−131 dBc/Hz 1 MHz offset from 4.4 GHz carrier

Normalized Phase Noise Floor

)4

(PN

PLL loop BW = 500 kHz

−220 dBc/Hz ABP = 6 ns

−221 dBc/Hz ABP = 3 ns Normalized 1/f Noise (PN

)5 10 kHz offset; normalized to 1 GHz

−118 dBc/Hz ABP = 3 ns In-Band Phase Noise −100 dBc/Hz 3 kHz from 2111.28 MHz carrier Integrated RMS Jitter6 0.27 ps Spurious Signals Due to PFD

−80 dBc

Frequency

Level of Signal with RF Mute Enabled −40 dBm

1

ICP is internally modified to maintain constant loop gain over the frequency range.

2

TA = 25°C; AVDD = DVDD = V

3

Using 50 Ω resistors to V

main output.

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log f

5

The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)

and at a frequency offset (f) is given by PN = PN

6

f

= 122.88 MHz; f

REFIN

measured with an EVAL-ADF4351EB1Z and the Rohde & Schwarz FSUP signal source analyzer.

PFD

= 3.3 V; prescaler = 8/9; f

VCO

, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the

VCO

. To calculate i n-band phase noise performance as seen at the VCO output, use the following formula: PN

+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

= 30.72 MHz; VCO frequency = 4222.56 MHz; RF

PFD

1_f

= 100 MHz; f

REFIN

= 25 MHz; fRF = 4.4 GHz.

PFD

= PN

SYNTH

= 2111.28 MHz; N = 137; loop BW = 60 kHz; ICP = 2.5 mA; low noise mode. The noise was

OUT

− 10 log(f

TOT

) − 20 log N.

PFD

Rev. 0 | Page 4 of 28

Data Sheet ADF4351

CLK

DATA

LE

DB31 (MSB) DB30

DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t

1

t

2

t

3

t

7

t

6

t

4

t

5

09800-002

TIMING CHARACTERISTICS

AVDD = DVDD = V otherwise noted.

Table 2.

Parameter Limit Unit Description

t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

Timing Diagram

= SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

MIN

to T

MAX

, unless

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF4351 Data Sheet

VCO

REFIN to GND1

−0.3 V to VDD + 0.3 V

32-Lead LFCSP (CP-32-2)

27.3

°C/W

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V AVDD to DVDD −0.3 V to +0.3 V V

to GND1 −0.3 V to +3.9 V

V

to AVDD −0.3 V to +0.3 V Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND1 −0.3 V to VDD + 0.3 V

Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C Reflow Soldering

Peak Temperature 260°C Time at Peak Temperature 40 sec

1

GND = AGND = DGND = CP

GND

= SD

GND

= A

GNDVCO

= 0 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <1.5 kV and is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT

The transistor count for the ADF4351 is 36,955 (CMOS) and 986 (bipolar).

THERMAL RESISTANCE

Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.

Table 4. Thermal Resistance

Package Type θJA Unit

ESD CAUTION

Rev. 0 | Page 6 of 28

Data Sheet ADF4351

1

CLK

2

DATA

3

LE

4

CE

5

SW

6 7

24

V

REF

23

V

COM

22 21 20 19 18 17

8

SDV

DD

ADF4351

TOP VIEW

(Not to S cale)

9

AGND

10

AV

DD

11

REF

IN

12

DGND13DV

DD

14

15

16

32

31

30

29

28

SD

GND

27

26

25

PIN 1 INDICATOR

V

P

CP

OUT

CP

GND

MUXOUT

R

SET

RF

OUT

A+

RF

OUT

B+

RF

OUT

B−

RF

OUT

A−

V

VCO

V

TUNE

A

GNDVCO

A

GNDVCO

TEM

P

PDB

RF

LD

A

GNDVCO

V

VCO

NOTES

1. THE LFCSP HAS AN EXPO S E D P AD THAT MUST BE CONNE CTED TO GND.

09800-003

impedance CMOS input.

2

DATA

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

TUNE

GND

OUT

DD

GNDVCO

VCO

20

V

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

3 LE Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is

selected by the three control bits. This input is a high impedance CMOS input.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

A logic high on this pin powers up the device, depending on the status of the power-down bits. 5 SW Fast Lock Switch. A connection should be made from the loop filter to this pin when using the fast lock mode. 6 VP Charge Pump Power Supply. VP must have the same value as AVDD. Place decoupling capacitors to the ground

plane as close to this pin as possible. 7 CP

8 CP

Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the

OUT

loop filter is connected to V

to drive the internal VCO.

Charge Pump Ground. This output is the ground return pin for CP 9 AGND Analog Ground. Ground return pin for AVDD. 10 AVDD Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog ground

11, 18, 21 A 12 RF

plane as close to this pin as possible. AV

VCO Analog Ground. Ground return pins for the VCO.

A+ VCO Output. The output level is programmable. The VCO fundamental output or a divided-down version is

OUT

must have the same value as DVDD.

available.

13 RF

A− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided-

OUT

down version is available.

14 RF

15 RF

16, 17 V

19 TEMP Temperature Compensation Output. Place decoupling capacitors to the ground plane as close to this pin as

B+ Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided-down

OUT

B− Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a

OUT

Power Supply for the VCO. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the analog

VCO

TUNE

version is available.

divided-down version is available.

ground plane as close to these pins as possible. V

possible.

output voltage.

Rev. 0 | Page 7 of 28

must have the same value as AVDD.

.

OUT

ADF4351 Data Sheet

CP

REF

29

REFIN

Reference Input. This CMOS input has a nominal threshold of AVDD/2 and a dc equivalent input resistance of

GND

Pin No. Mnemonic Description

22 R

23 V

24 V 25 LD Lock Detect Output Pin. A logic high output on this pin indicates PLL lock. A logic low output indicates loss

26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable. 27 DGND Digital Ground. Ground return pin for DVDD. 28 DVDD Digital Power Supply. DVDD must have the same value as AVDD. Place decoupling capacitors to the ground

30 MUXOUT Multiplexer Output. The multiplexer output allows the lock detect value, the N divider value, or the R counter

31 SD 32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. SDVDD must have the same value as AVDD. Place decoupling

EP Exposed Pad Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.

Connecting a resistor between this pin and ground sets the charge pump output current. The nominal voltage

SET

bias at the R

ICP = 25.5/R

pin is 0.55 V. The relationship between ICP and R

SET

is as follows:

SET

where:

R

= 5.1 kΩ.

SET

= 5 mA.

I

Internal Compensation Node. Biased at half the tuning range. Place decoupling capacitors to the ground plane

COM

as close to this pin as possible.

Reference Voltage. Place decoupling capacitors to the ground plane as close to this pin as possible.

of PLL lock.

plane as close to this pin as possible.

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

value to be accessed externally.

Digital Σ-Δ Modulator Ground. Ground return pin for the Σ-Δ modulator.

capacitors to the ground plane as close to this pin as possible.

Rev. 0 | Page 8 of 28

Data Sheet ADF4351

–160

–150

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–40

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

09800-104

–160

–150

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–40

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

09800-105

–160

–150

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–40

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

09800-106

–170

–160

–150

–140

–130

–120

–110

–100

–90

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64

09800-107

–170

–160

–150

–140

–130

–120

–110

–100

–90

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64

09800-108

–170

–160

–150

–140

–130

–120

–110

–100

–90

1k 10k 100k 1M 10M

PHASE NOISE (dBc/Hz)

FREQUENCY ( Hz )

DIV1 DIV2 DIV4 DIV8 DIV16 DIV32 DIV64

09800-109

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz

Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz

Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 2.2 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz

Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 3.3 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz

Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz

Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 4.4 GHz, PFD = 25 MHz, Loop Filter Bandwidth = 63 kHz

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADF4351 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

TRANSISTOR COUNT

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS