ANALOG DEVICES ADF 4350 BCPZ Datasheet

Wideband Synthesizer with Integrated VCO

ADF4350

Rev. B Document Feedback

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MUXOUT

CP

OUT

LD

SW

V

COM

TEMP

REF

IN

CLK

DATA

LE

AV

DD

SDV

DD

DV

DD

V

P

AGND

CE

DGND CP

GND

SD

GND

A

GNDVCO

R

SETVVCO

V

TUNE

V

REF

RF

OUT

A+

RF

OUT

A–

RF

OUT

B+

RF

OUT

B–

VCO

CORE

PHASE

COMPARATOR

FL

O

SWITCH

CHARGE

PUMP

OUTPUT

STAGE

OUTPUT

STAGE

PDB

RF

MULTIPLEXER

MULTIPLEXER

10-BIT R

COUNTER÷2DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

÷1/2/4/8/16

ADF4350

07325-001

Data Sheet

FEATURES

Output frequency range: 137.5 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16 output
Typical rms jitter: <0.4 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,

GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The ADF4350 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external loop filter and external reference
frequency.

The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.

Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

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Application Notes

• AN-0974: Multicarrier TD-SCMA Feasibility

Data Sheet

• ADF4350: Wideband Synthesizer with Integrated VCO
Data Sheet

User Guides

• UG-109: Evaluation Board User Guide for ADF4350

• UG-110: Evaluation User Guide for ADF4350

• UG-476: PLL Software Installation Guide

Software and Systems Requirements

• ADF4350 IIO Wideband Synthesizer Linux Driver

• AD9739A Native FMC Card / Xilinx Reference Designs

Tools and Simulations

• ADIsimPLL™

• ADIsimRF

• ADF4350 IBIS Model

Reference Designs

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• CN0144

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• CN0245

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Reference Materials

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• Analog Devices’ 4-GHz PLL Synthesizer Offers Leading
Phase Noise Performance

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Flexibility and Phase Noise Performance

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ADF4350 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 11

Reference Input Section ............................................................. 11

RF N Divider ............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship .................... 11

INT N MODE ............................................................................. 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump ............ 11

MUXOUT and LOCK Detect ................................................... 12

Input Shift Registers ................................................................... 12

Program Modes .......................................................................... 12

VCO.............................................................................................. 12

Output Stage ................................................................................ 13

Register Maps .................................................................................. 14

Register 0 ..................................................................................... 18

REVISION HISTORY

5/16—Rev. A to Rev. B

Changes to Figure 3 .......................................................................... 7

Changes to the ADuC7019 to ADuC7029 Family Interface

Section, Figure 35, and Figure 35 Caption .................................. 26

Updated Outline Dimensions ....................................................... 30

Changes to Ordering Guide .......................................................... 30

Rev. B | Page 2 of 34

Register 1 ..................................................................................... 18

Register 2 ..................................................................................... 18

Register 3 ..................................................................................... 20

Register 4 ..................................................................................... 20

Register 5 ..................................................................................... 20

Initialization Sequence .............................................................. 21

RF Synthesizer—A Worked Example ...................................... 21

Modulus ....................................................................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus ................................................ 21

Cycle Slip Reduction for Faster Lock Times ........................... 22

Spurious Optimization and Fast lock ...................................... 22

Fast-Lock Timer and Register Sequences ............................... 22

Fast Lock—An Example ............................................................ 22

Fast Lock—Loop Filter Topology ............................................. 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync ............................................................................... 24

Applications Information .............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for a Chip Scale Package ................. 26

Output Matching ........................................................................ 27

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

4/11—Rev. 0 to Rev. A

Changes to Typical rms Jitter in Features Section ......................... 1

Changes to Specifications ................................................................. 3

Changes Output Stage Section ...................................................... 13

Changes to Figure 29 ...................................................................... 17

Changes to Fast Lock—An Example Section ............................. 22

Changes to Direct Conversion Modulator Section and

Figure 34 ......................................................................................... 25

Changes to ADuC70xx Interface Section and ADSP-BF527

Interface Section ............................................................................. 26

Changes to Output Matching Section and Table 7 .................... 27

Added Table 8 ................................................................................. 28

Changes to Ordering Guide .......................................................... 29

11/08—Revision 0: Initial Version

Data Sheet ADF4350

CHARGE PUMP

Input High Voltage, V

1.5

V

POWER SUPPLIES

70

80

mA

Maximum VCO Output Frequency

4400

MHz

Harmonic Content (Third)

−13 dBc

Fundamental VCO output

SPECIFICATIONS

AVDD = DVDD = V
temperature range is −40°C to +85°C.

Table 1.

Parameter

REFIN CHARACTERISTICS

Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/µs
Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21
Input Capacitance 10 pF
Input Current ±60 µA

PHASE DETECTOR

Phase Detector Frequency2 32 MHz

= SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = T

VCO

B Version

to T

MIN

, unless otherwise noted. Operating

MAX

Unit Test Conditions/Comments Min Typ Max

ICP Sink/Source3 With R

= 5.1 kΩ

SET

High Value 5 mA
Low Value 0.312 mA
R

Range 2.7 10 kΩ

SET

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % VCP = 2.0 V

LOGIC INPUTS

INH

Input Low Voltage, V
Input Current, I

0.6 V

INL

±1 µA

INH/IINL

Input Capacitance, CIN 3.0 pF

LOGIC OUTPUTS

Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen
Output High Current, IOH 500 µA
Output Low Voltage, VOL 0.4 V IOL = 500 µA

AVDD 3.0 3.6 V
DVDD, V
DIDD + AI

, SD

VCO

, VP AVDD These voltages must equal AVDD

VDD

4

21 27 mA

DD

Output Dividers 6 to 24 mA Each output divide-by-2 consumes 6 mA

4

I

VCO

I

RFOUT

4

21 26 mA RF output stage is programmable

Low Power Sleep Mode 7 1000 µA

RF OUTPUT CHARACTERISTICS

Minimum VCO Output Frequency 2200 MHz Fundamental VCO mode
Minimum VCO Output Frequency

Using Dividers
VCO Sensitivity 33 MHz/V
Frequency Pushing (Open-Loop) 1 MHz/V
Frequency Pulling (Open-Loop) 90 kHz Into 2.00 VSWR load
Harmonic Content (Second) −19 dBc Fundamental VCO output

Harmonic Content (Second) −20 dBc Divided VCO output
Harmonic Content (Third) −10 dBc Divided VCO output
Minimum RF Output Power 5 −4 dBm Programmable in 3 dB steps
Maximum RF Output Power5 5 dBm
Output Power Variation ±1 dB
Minimum VCO Tuning Voltage 0.5 V
Maximum VCO Tuning Voltage 2.5 V

137.5 MHz 2200 MHz fundamental output and divide by 16 selected

Rev. B | Page 3 of 34

ADF4350 Data Sheet

−86 dBc/Hz

10 kHz offset from 3.3 GHz carrier

−110

dBc/Hz

100 kHz offset from 4.4 GHz carrier

B Version

Parameter

NOISE CHARACTERISTICS

VCO Phase-Noise Performance6 −89 dBc/Hz 10 kHz offset from 2.2 GHz carrier

−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier

−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier

−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier

−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier

−134 dBc/Hz 1 MHz offset from 3.3 GHz carrier

−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier

−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier

−132 dBc/Hz 1 MHz offset from 4.4 GHz carrier

−145 dBc/Hz 5 MHz offset from 4.4 GHz carrier
Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN

)8 −111 dBc/Hz 10 kHz offset; normalized to 1 GHz

1_f

)7 −220 dBc/Hz PLL Loop BW = 500 kHz

SYNTH

In-Band Phase Noise9 −97 dBc/Hz 3 kHz offset from 2113.5 MHz carrier
Integrated RMS Jitter10 0.5 ps
Spurious Signals Due to PFD Frequency −70 dBc
Level of Signal With RF Mute Enabled −40 dBm

1

AC coupling ensures AVDD/2 bias.

2

Guaranteed by design. Sample tested to ensure compliance.

3

ICP is internally modified to maintain constant loop gain over the frequency range.

4

TA = 25°C; AVDD = DVDD = V

5

Using 50 Ω resistors to V

main output.

6

The noise of the VCO is measured in open-loop conditions.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log F

8

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,

and at a frequency offset f is given by PN = P

9

f

= 100 MHz; f

REFIN

= 313 µA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.

I

CP

10

f

= 100 MHz; f

REFIN

PFD

PFD

PFD

= 3.3 V; prescaler = 8/9; f

VCO

, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the

VCO

. PN

= PN

SYNTH

= 25 MHz; offset frequency = 10 kHz; VCO frequency = 4227 MHz, output divide by two enabled. RF

− 10 log F

TOT

+ 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

1_f

= 25 MHz; VCO frequency = 4400 MHz, RF

REFIN

− 20 log N.

PFD

= 100 MHz; f

OUT

= 25 MHz; fRF = 4.4 GHz.

PFD

= 4400 MHz; N = 176; loop BW = 40 kHz, ICP = 313 µA; low noise mode. The noise was measured with

an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.

Unit Test Conditions/Comments Min Typ Max

= 2113.5 MHz; N = 169; loop BW = 40 kHz,

OUT

Rev. B | Page 4 of 34

Data Sheet ADF4350

TIMING CHARACTERISTICS

AVDD = DVDD = V
otherwise noted.

Table 2.

Parameter Limit (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

= SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = T

VCO

CLK

t

4

t

5

MIN

to T

MAX

, unless

DATA

DB31 (MSB) DB30

LE

t

1

LE

t

2

t

3

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

07325-002

Figure 2. Timing Diagram

Rev. B | Page 5 of 34

ADF4350 Data Sheet

REFIN to GND

−0.3 V to VDD + 0.3 V

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
V

to GND −0.3 V to +3.9 V

VCO

V

to AVDD −0.3 V to +0.3 V

VCO

Digital Input/Output Voltage to GND −0.3 V to VDD + 0.3 V
Analog Input/Output Voltage to GND −0.3 V to VDD + 0.3 V

Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

This device is a high-performance RF integrated circuit with an
ESD rating of <0.5 kV and is ESD sensitive. Proper precautions
must be taken for handling and assembly.

Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance 27.3°C/W

(Paddle-Soldered)

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 40 sec

1

GND = AGND = DGND = 0 V

TRANSISTOR COUNT

24202 (CMOS) and 918 (bipolar).

ESD CAUTION

Rev. B | Page 6 of 34

Data Sheet ADF4350

CLK

DATA

LE

CE

SW

V

P

CP

OUT

CP

GND

SDV

DD

REF

IN

DGND

DV

DD

SD

GND

MUXOUT

PDB

RF

LD

AGND

AV

DD

RF

OUT

A+

RF

OUT

B+

RF

OUT

B−

RF

OUT

A−

V

VCO

A

GNDVCO

V

REF

V

COM

R

SET

V

TUNE

A

GNDVCO

A

GNDVCO

TEM

P

V

VCO

07325-003

NOTES

1. THE LFCSP HAS AN EXPO S E D P ADDLE THAT
MUST BE CONNECTED TO G ND.

24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8

9

10111213141516

32313029282726

25

ADF4350

TOP VIEW

(Not to S cale)

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

5 SW Fast-Lock Switch. A connection must be made from the loop filter to this pin when using the fast-lock mode.
6 VP Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to

7 CP

8 CP
9 AGND Analog Ground. This is a ground return pin for AVDD.
10 AVDD Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are

11, 18, 21 A
12 RF
13 RF

14 RF

15 RF

16, 17 V

19 TEMP Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as

20 V

Charge Pump Output. When enabled, this provides ±I

OUT

Charge Pump Ground. This is the ground return pin for CP

GND

VCO Analog Ground. These are the ground return pins for the VCO.

GNDVCO

A+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.

OUT

A− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided

OUT

B+ Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down

OUT

B− Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a

OUT

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

VCO

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP

TUNE

Figure 3. Pin Configuration

impedance CMOS input.

impedance CMOS input.

that is selected by the three LSBs.

A logic high on this pin powers up the device depending on the status of the power-down bits.

be placed as close as possible to this pin.

to the external loop filter. The output of the loop filter is

connected to V

to drive the internal VCO.

TUNE

to be placed as close as possible to this pin. AV

CP

.

OUT

must have the same value as DVDD.

DD

down version is available.

version is available.

divided down version is available.

must be placed as close as possible to these pins. V

must have the same value as AVDD.

VCO

possible to this pin.

output voltage.

Rev. B | Page 7 of 34

OUT

ADF4350 Data Sheet

SET

CP

R

25.5

I =

where:

29

REFIN

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

Pin No. Mnemonic Description

22 R

23 V

24 V
25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.
26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27 DGND Digital Ground. Ground return path for DVDD.
28 DVDD Digital Power Supply. This pin must be the same voltage as AVDD. Decoupling capacitors to the ground plane

30 MUXOUT Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

31 SD
32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Must be the same voltage as AVDD. Decoupling capacitors to the

33 EP Exposed Pad.

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

SET

bias at the R

pin is 0.55 V. The relationship between ICP and R

SET

SET

is

R

= 5.1 kΩ

SET

ICP = 5 mA

Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane must

COM

be placed as close as possible to this pin.

Reference Voltage. Decoupling capacitors to the ground plane must be placed as close as possible to this pin.

REF

must be placed as close as possible to this pin.

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

frequency to be accessed externally.

Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.

GND

ground plane are to be placed as close as possible to this pin.

Rev. B | Page 8 of 34

Data Sheet ADF4350

–150
–160

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–40

1k

10k 100k

1M

10M

100M

07325-028

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

1k 10k 100k 1M 10M 100M

07325-029

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

–150
–160

–140

–120

–100

–80

–130

–110

–90

–70

–60

–50

–40

–140

–120

–100

–80

–130

–160

–150

–110

–90

–70

–60

–50

–40

1k 10k 100k

1M 10M 100M

07325-030

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

–170

–160

–150

–140

–130

–120

–110

–100

–90

–70

–80

1k

10k

100k 1M

10M 100M

07325-031

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

FUND
DIV2
DIV4
DIV8
DIV16

–170

–160

–150

–140

–130

–120

–110

–100

–90

–70

–80

PHASE NOISE (dBc/Hz)

FUND
DIV2
DIV4
DIV8
DIV16

1k 10k 100k 1M 10M 100M

07325-032

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

–170

–160

–150

–140

–130

–120

–110

–100

–90

–70

–80

FUND
DIV2
DIV4
DIV8
DIV16

1k 10k 100k 1M 10M 100M

07325-033

FREQUENCY (Hz )

PHASE NOISE (dBc/Hz)

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz

Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz

Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 2.2 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 3.3 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz

Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,

VCO = 4.4 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz

Rev. B | Page 9 of 34

ADF4350 Data Sheet

0

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-034

10M

0

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-035

10M

0

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-036

10M

0

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-037

10M

0

–20

–40

–60

–80

–100

–120

–140

–160

PHASE NOISE (dBc/Hz)

1k 10k

FREQUENCY (Hz)

100k 1M

07325-038

10M

2

.95

2.

96

2.97

2.98

2.

99

3.

00

3.01

3.

02

FREQUE

NC

Y (GHz)

CSR OFF
CSR ON

0 100 200

300

TIME (µs)

400 500 600

07325-039

Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band,

RF

= 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4

OUT

Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz.

Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band,

RF

= 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2

OUT

Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz.

Figure 13. Fractional-N Spur Performance. Low Noise Mode, RF

2.591 GHz, REF

= 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected;

IN

OUT

=

Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz.

Figure 14. Fractional-N Spur Performance. Low Spur Mode RF

2.591 GHz, REF

= 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected.

IN

OUT

=

Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz (Note That

Fractional Spurs Are Removed and Only the Integer Boundary Spur Remains

in Low Spur Mode).

Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band

RF

= 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2

OUT

Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz

Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with

Rev. B | Page 10 of 34

CSR On and Of f, PFD = 25 MHz, I

= 313 µA, L oop Filter Bandwidth = 20 kHz

CP