ANALOG DEVICES ADF4217L, ADF4218L, ADF4219L Service Manual

Dual Low Power

a

FEATURES Total IDD: 7.1 mA Bandwidth/RF 3.0 GHz

ADF4217L/ADF4218L, IF 1.1 GHz ADF4219L, IF 1.0 GHz

2.6 V to 3.3 V Power Supply

1.8 V Logic Compatibility Separate V Selectable Dual Modulus Prescaler Selectable Charge Pump Currents Charge Pump Current Matching of 1% 3-Wire Serial Interface Power-Down Mode

APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, WCDMA) Wireless LANs Communications Test Equipment Cable TV Tuners (CATV)

Allows Extended Tuning Voltage

P

Frequency Synthesizers

ADF4217L/ADF4218L/ADF4219L

GENERAL DESCRIPTION

The ADF4217L/ADF4218L/ADF4219L are low power dual frequency synthesizers that can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low noise digital PFD (phase frequency detector), a precision charge pump, programmable reference divider, programmable A and B counters, and a dual modulus prescaler (P/P + 1). The A and B counters, in conjunction with the dual modulus prescaler

(P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN quencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (voltage controlled oscillators).

Control of all the on-chip registers is via a simple 3-wire interface with 1.8 V compatibility. The devices operate with a power supply ranging from 2.6 V to 3.3 V and can be powered down when not in use.

fre-

a

REV. C

IF

IN

IF

IN

ADF4217L ADF4218L

ONLY

REF

CLOCK

DATA

LE

RF

IN

RF

IN

FUNCTIONAL BLOCK DIAGRAM

ADF4219L ONLY

N = BP + A

A

B

IN

A

B

FEATURES IN ( ) REFER TO ADF4219L NC = NO CONNECT

BUFFER

PRESCALER

22-BIT

DATA

REGISTER

N = BP + A

PRESCALER

IF

SDOUT

RF

NC

11(13)-BIT IF B COUNTER

6(5)-BIT IF

A COUNTER

14(15)-BIT IF R COUNTER

14(15)-BIT RF

R COUNTER

11(13)-BIT RF

B COUNTER

6(5)-BIT RF

A COUNTER

DGND

VP2VP1VDD2VDD1

PHASE

COMPARATOR

DETECT

PHASE

COMPARATOR

AGNDRFDGNDIFAGND

RF

IF

LOCK

RF

LOCK

ADF4217L/ ADF4218L/

ADF4219L

CHARGE

PUMP

OUTPUT

MUX

CHARGE

PUMP

IF

CP

IF

MUXOUT

CP

RF

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

ADF4217L/ADF4218L/ADF4219L–SPECIFICATIONS

(VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGND = DGND = 0 V; TA = T

MIN

to T

, unless otherwise noted.)

MAX

1

BChips

2

Parameter B Version1(T y p i c a l) U nit Test Conditions/Comments

RF CHARACTERISTICS Use a square wave for operation

below minimum frequency spec.

RF Input Frequency (RF

)

IN

ADF4217L, ADF4218L 0.15/3.0 0.15/3.0 GHz min/max –10 dBm minimum input signal ADF4217L, ADF4218L 0.15/2.5 0.15/2.5 GHz min/max –15 dBm minimum input signal ADF4219L 0.8/2.2 0.8/2.2 GHz min/max –20 dBm minimum input signal

RF Input Sensitivity

ADF4217L, ADF4218L –15/0 –15/0 dBm min/max ADF4219L –20/0 –20/0 dBm min/max

IF Input Frequency (IF

)

IN

ADF4217L/ADF4218L 0.045/1.1 0.045/1.1 GHz min/max –15 dBm minimum input signal ADF4219L P = 16/17 0.045/1.0 0.045/1.0 GHz min/max –10 dBm minimum input signal

ADF4219L P = 8/9 0.045/0.55 0.045/0.55 GHz min/max –10 dBm minimum input signal IF Input Sensitivity –15/0 –15/0 dBm min/max Maximum Allowable Prescaler

Output Frequency

3

188 188 MHz max

REFIN CHARACTERISTICS

Reference Input Frequency 10/110 10/110 MHz min/max For f < 10 MHz, use dc-coupled

square wave, (0 to V

DD

).

Reference Input Sensitivity 0.5 0.5 V p-p min AC-coupled. When dc-coupled,

DD

max.

0 to V REFIN Input Capacitance 10 10 pF max (CMOS compatible) REFIN Input Current ± 100 ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

4

56 56 MHz max

CHARGE PUMP

ICP Sink/Source

High Value 4 4 mA typ Low Value 1 1 mA typ Absolute Accuracy 1 1 % typ

Three-State Leakage Current 1 1 nA typ

I

CP

Sink and Source Current Matching 6 6 % max 0.5 V < V I

CP

vs. V

CP

55% max 0.5 V < VCP < VP – 0.5, 0.1% typ

< VP – 0.5, 1% typ

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 1.4 V min

INH

, Input Low Voltage 0.6 0.6 V max

V

INL

I C

, Input Current ± 1 ± 1 µA max

INH/IINL

, Input Capacitance 10 10 pF max

IN

Reference Input Current ±100 ± 100 µA max

LOGIC OUTPUTS

VOH, Output High Voltage VDD – 0.4 VDD – 0.4 V min IOH = 1 mA VOL, Output Low Voltage 0.4 0.4 V max IOL = 1 mA

POWER SUPPLIES

1 2.6/3.3 2.6/3.3 V min/V max

V

DD

V

2V

DD

1, VP2V

V

P

(RF + IF)

I

DD

(RF only) (IF only)

1 + IP2) 0.6 0.6 mA typ TA = 25°C

I

P (IP

5

1V

DD

1/5.5 V VDD1/5.5 V V min/V max

DD

1

10 10 mA max 7.1 mA typ 77mA 4.7 mA typ 55mA 3.4 mA typ

Low Power Sleep Mode 1 1 µA typ

–2–

REV. C

ADF4217L/ADF4218L/ADF4219L

BChips

2

Parameter B Version1(T y p i c a l) U nit Test Conditions/Comments

NOISE CHARACTERISTICS

RF Phase Noise Floor

IF Phase Noise Floor

Phase Noise Performance

9

RF

10

RF

11

IF

12

IF

Spurious Signals Measured at Offset of f

9

RF

10

RF

11

IF

12

IF

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The BChip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

4

Guaranteed by design. Sample tested to ensure compliance.

5

This includes relevant IP.

6

V

= 3 V; P = 16/32; IFIN/RFIN for ADF4218L, ADF4219L = 540 MHz/900 MHz.

DD

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

8

The phase noise is measured with the EVAL-ADF421xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer. (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

7

= 10 MHz @ 0 dBm.)

REFOUT

= 30 kHz; Offset frequency = 1 kHz; fRF = 1.95 GHz; N = 65000; Loop B/W = 3 kHz

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz

PFD

= 30 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 30000; Loop B/W = 3 kHz

PFD

= 200 kHz; Offset frequency = 1 kHz; fIF = 900 MHz; N = 4500; Loop B/W = 20 kHz

PFD

6

7

–171 –171 dBc/Hz typ @ 30 kHz PFD Frequency –163 –163 dBc/Hz typ @ 200 kHz PFD Frequency –167 –167 dBc/Hz typ @ 30 kHz PFD Frequency

8

–159 –159 dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output –75 –75 dBc/Hz typ 1.95 GHz Output; 30 kHz PFD –90 –90 dBc/Hz typ 900 MHz Output; 200 kHz PFD –77 –77 dBc/Hz typ 900 MHz Output; 30 kHz PFD –86 –86 dBc/Hz typ 900 MHz Output; 200 kHz PFD

/2f

PFD

–78/–85 –78/–85 dBc typ –80/–84 –80/–84 dBc typ –79/–86 –79/–86 dBc typ –80/–84 –80/–84 dBc typ

TIMING CHARACTERISTICS

VP2 ≤ 6.0 V ; AGND

RF1

= DGND

= AGND

RF1

(VDD1 = VDD2 = 3 V ⴞ 10%, 5 V ⴞ 10%; VDD1, VDD2 ≤ VP1,

= DGND

RF2

= 0 V; TA = T

RF2

MIN

to T

, unless otherwise noted.)

MAX

Limit at

to T

T

MIN

MAX

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

Guaranteed by design but not production tested.

10 ns min DATA to CLOCK Setup Time 10 ns min DATA to CLOCK Hold Time 25 ns min CLOCK High Duration 25 ns min CLOCK Low Duration 10 ns min CLOCK to LE Setup Time 50 ns min LE Pulsewidth

CLOCK

DATA

t

1

DB21 (MSB) DB20 DB2

LE

t

2

t

3

4

(CONTROL BIT C2)

DB1

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

REV. C

Figure 1. Timing Diagram

–3–

ADF4217L/ADF4218L/ADF4219L

ABSOLUTE MAXIMUM RATINGS

(

TA = 25°C, unless otherwise noted.)

VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.8 V

V

P

1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

V

P

Digital I/O Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

, RF1IN (A, B), IFIN (A, B)

REF

IN

to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

A to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV

RF

IN

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

1, 2

+ 0.3 V

P

TSSOP ␪ LGA ␪

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112°C/W

JA

Lead Temperature, Soldering

TSSOP, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . 215°C

TSSOP, Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . 220°C

LGA, Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . 240°C

LGA, Infrared (20 sec) . . . . . . . . . . . . . . . . . . . . . . . 240°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause

nent damage to the device. This is a stress rating only; functional operation device at these or any other conditions above those listed in the operational of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating of

< 2 kV and is ESD sensitive. Proper precautions should be taken for handling assembly.

3

GND = AGND = DGND = 0 V.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADF4217L/ADF4218L/ADF4219LBRU –40°C to +85°CThin Shrink Small Outline Package (TSSOP) RU-20 ADF4217L/ADF4218L/ADF4219LBCC –40°C to +85°CChip Array CASON (LGA) CC-24

*Contact the factory for chip availability.

sections

conditions

*

perma-

of the

and

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4217L/ ADF4218L/ADF4219L feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. C

ADF4217L/ADF4218L/ADF4219L

PIN CONFIGURATIONS

TSSOP

1

V

1

DD

V

1

2

P

CP

3

RF

DGND

AGND

MUXOUT

RF

RFINB

REF

DGND

IN

RF

A

RF

IN

IF

4

5

6

7

8

9

10

ADF4217L/

ADF4218L

CHIP SCALE

1

2

DD

V

23 22

24

1

2

VP1

3

CP

RF

DGND

AGND

4

RF

ADF4217L/

5

RF

A

IN

RFINB

REF

NC

ADF4218L

6

7

RF

8

IN

9

10

11 12

IF

DGND

MUXOUT

NC = NO INTERNAL CONNECT

TSSOP

1

20

VDD2

19

VP2

18

CP

IF

17

DGND

IF

16

IF

INA

15

IF

INB

14

AGND

IF

13

LE

12

DATA

11

CLK

V

DD

V

CP

DGND

RF

IN

RFINB

AGND

REF

DGND

MUXOUT

1

2

P

3

RF

4

RF

A

5

ADF4219L

6

7

RF

8

IN

9

IF

10

20

19

18

17

16

15

14

13

12

11

V

DD

VP2

CP

IF

DGND IF

IN

AGND

NC

LE DATA

CLK

2

IF

CHIP SCALE

1

2

DD

P

DD

V

2

P

DD

V

21

NCNC

20

CP

IF

DGND

19

18

17

16

15

14

13

IFINA

IFINB

AGND

LE

DATA

NC

IF

DGND

AGND

NC

VP1

CP

RF

IN

RFINB

REF

NC

1

2

3

RF

4

RF

ADF4219L

A

5

6

7

RF

8

IN

9

10

CLK

NC = NO INTERNAL CONNECT

24

IF

DGND

23 22

11 12

MUXOUT

V

CLK

21

NC

CP

20

IF

19

DGND

IF

18

IN

AGND

17

16

15

14

13

IF

NC

LE

DATA

NC

REV. C

–5–

ADF4217L/ADF4218L/ADF4219L

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

V

1Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as

DD

close as possible to this pin. V potential as V

V

1Power Supply for the RF Charge Pump. This should be greater than or equal to VDD.

P

CP

RF

Output from the RF Charge Pump. When enabled, this provides ±ICP to the external loop filter, which in turn

DD

2.

drives the external VCO. DGND RF RF

RF

A Input to the RF Prescaler. This low level input signal is normally ac-coupled to the external VCO.

IN

BComplementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

IN

Ground Pin for the RF Digital Circuitry

bypass capacitor, typically 100 pF. AGND REF

IN

RF

Ground Pin for the RF Analog Circuitry

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of

100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. DGND

IF

Ground Pin for the IF Digital, Interface, and Control Circuitry MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, or the scaled Reference Frequency to

be accessed externally (Table V). CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input. LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches; the latch is selected using the control bits. AGND

IF

Ground Pin for the IF Analog Circuitry NC This pin is not connected internally (ADF4219L only). IF

BComplementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass

IN

capacitor, typically 100 pF (ADF4217L/ADF4218L only). IF

A Input to the IF Prescaler. This low level input signal is normally ac-coupled to the external VCO.

IN

DGND CP

IF

Ground Pin for the IF Digital, Interface, and Control Circuitry

Output from the IF Charge Pump. When enabled, this provides ±ICP to the external loop filter, which in turn drives

the external VCO. V

2Power Supply for the IF Charge Pump. This should be greater than or equal to VDD.

P

V

2Positive Power Supply for the IF Interface and Oscillator Sections. Decoupling capacitors to the analog ground

DD

plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.6 V and 3.3 V.

VDD2 must have the same potential as VDD1.

1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same

DD

–6–

REV. C

Typical Performance Characteristics–

ADF4217L/ADF4218L/ADF4219L

0

–5

–10

–15

–20

–25

RF INPUT POWER – dBm

–30

–35

–40

0 0.5 1.5 2.51.0 2.0 3.0

RF INPUT FREQUENCY – GHz

TA = 25ⴗC

TPC 1. Input Sensitivity, RF Input

0

–5

–10

–15

–20

–25

IF INPUT POWER – dBm

–30

–35

–40

0.1 0.6 1.1 1.6 IF INPUT FREQUENCY – GHz

V

= 3V

DD

V

= 3V

P

3.5

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

–400kHz

REFERENCE LEVEL = –11.2dBm

–200kHz 1960MHz 200kHz 400kHz

VDD = 3V, VP = 5V

= 4mA

I

CP

PFD FREQUENCY = 200kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 10

FREQUENCY

–78dBc

TPC 4. Reference Spurs, RF Side (1960 MHz, 200 kHz, 20 kHz)

10dB/DIVISION RL = –40dBc/Hz rms NOISE = 1.2ⴗ

V

= 3V

DD

V

= 3V

P

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 1960MHz CARRIER 1MHz

1.2ⴗ rms

TPC 2. Input Sensitivity, IF Input

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL = –11.2dBm

–2kHz –1kHz 1960MHz 1kHz 2kHz

VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20

FREQUENCY

–83dBc/Hz

TPC 3. Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz)

REV. C

TPC 5. Integrated Phase Noise, RF Side (1960 MHz, 200 kHz, 20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL = –4.2dBm

–2kHz –1kHz 900MHz 1kHz 2kHz

V

= 3V, VP = 5V

DD

= 4mA

I

CP

PFD FREQUENCY = 200kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 20

FREQUENCY

–87dBc/Hz

TPC 6. Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz)

–7–

ADF4217L/ADF4218L/ADF4219L

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL = –4.2dBm

–400kHz –200kHz 900MHz 200kHz 400kHz

VDD = 3V, VP = 5V ICP = 4.0mA PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 1.9 SECONDS AVERAGES = 20

FREQUENCY

–83dBc

TPC 7. Reference Spurs, IF Side (900 MHz, 200 kHz, 20 kHz)

10dB/DIVISION RL = –40dBc/Hz rms NOISE = 0.9ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz

TPC 8. Integrated Phase Noise, IF Side (900 MHz, 200 kHz, 20 kHz)

–120

–130

–140

–150

–160

PHASE NOISE – dBc/Hz

–170

–180

1 10000100 1000

10

PHASE DETECTOR FREQUENCY – kHz

V

= 3V

DD

= 5V

V

P

TPC 10. Phase Noise Referred to CP Output vs. PFD Frequency, IF Side

–60

–70

–80

PHASE NOISE – dBc/Hz

–90

–100

–40 100–20

020406080

TEMPERATURE – ⴗC

VDD = 3V

= 5V

V

P

TPC 11. Phase Noise vs. Temperature, RF Side (1960 MHz, 200 kHz, 20 kHz)

–120

–130

–140

–150

–160

PHASE NOISE – dBc/Hz

–170

–180

1 10000100 1000

10

PHASE DETECTOR FREQUENCY – kHz

V

= 3V

DD

= 5V

V

P

TPC 9. Phase Noise Referred to CP Output vs. PFD Frequency, RF Side

–8–

–60

–70

–80

PHASE NOISE – dBc/Hz

–90

–100

–40 100–20

020406080

TEMPERATURE – ⴗC

= 3V

V

DD

V

= 5V

P

TPC 12. Phase Noise vs. Temperature, IF Side (900 MHz, 200 kHz, 20 kHz)

REV. C