ANALOG DEVICES ADF4212L Service Manual

Dual Low Power PLL

V

V

V

V

FEATURES

IDD total: 7.5 mA
Bandwidth RF/IF: 2.4 GHz/1.0 GHz

2.7 V to 3.3 V power supply
Separate V
Programmable dual modulus prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Fastlock mode
Power-down mode
20-lead TSSOP and 20-lead LFCSP packages

APPLICATIONS

Wireless handsets (GSM, PCS, DCS, DSC1800, CDMA,

WCDMA)
Base stations for wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless LANS
Cable TV tuners (CATV)
Communications test equipment

allows extended tuning voltage

P

ADF4212L

IF

IN

REF

CLK

DATA

RF

IN

LE

IN

OSCILLATOR

22-BIT
DATA

REGISTER

FUNCTIONAL BLOCK DIAGRAM

IF

PRESCALER

SDOUT

RF

PRESCALER

DGND

AGNDRFDGNDIFAGND

RF

1

DD

12-BIT IF

B-COUNTER

6-BIT IF

A-COUNTER

15-BIT IF

R-COUNTER

15-BIT RF

R-COUNTER

12-BIT RF

B-COUNTER

6-BIT RF

A-COUNTER

Figure 1.

Frequency Synthesizer

ADF4212L

GENERAL DESCRIPTION

The ADF4212L is a dual frequency synthesizer that can be used
to implement local oscillators (LO) in the up-conversion and
down-conversion sections of wireless receivers and transmitters.
It can provide the LO for both the RF and IF sections. It consists
of a low noise digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A and B counters, and a dual modulus prescaler (P/P + 1). The
A (6-bit) and B (12-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP +
A). In addition, the 15-bit reference counter (R counter) allows
selectable REF
locked loop (PLL) can be implemented if the synthesizer is used
with external loop filters and voltage controlled oscillators (VCOs).

Control of all the on-chip registers is via a simple 3-wire
interface with 1.8 V compatibility. The devices operate with a
power supply ranging from 2.7 V to 3.3 V and can be powered
down when not in use.

2

1

P

IF PHASE

FREQUENCY

DETECTOR

RF PHASE

FREQUENCY

DETECTOR

2

P

DD

IF

frequencies at the PFD input. A complete phase-

IN

R

SET

REFERENCE

IF

LOCK

DETECT

RF

LOCK

DETECT

CHARGE

PUMP

IF CURRENT

SETTING

IFCP3 IFCP2

OUTPUT

MUX

RFCP3 RFCP2

REFERENCE

CHARGE

PUMP

REFERENCE

R

SET

FLOSWITCH

IFCP1

RFCP1

CP

IF

MUXOUT

CP

RF

FL

O

02774-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2002–2010 Analog Devices, Inc. All rights reserved.

ADF4212L

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 13

Reference Input Section ............................................................. 13

RF/IF Input Stage........................................................................ 13

Prescaler (P/P + 1) ...................................................................... 13

RF/IF A and B Counters ............................................................ 13

Pulse Swallow Function ............................................................. 13

RF/IF R Counter ......................................................................... 13

Phase Frequency Detector (PFD) and Charge Pump ............ 14

MUXOUT and Lock Detect ...................................................... 14

Lock Detect ................................................................................. 14

RF/IF Input Shift Register ......................................................... 14

IF R Counter Latch ..................................................................... 16

IF N Counter Latch .................................................................... 17

RF R Counter Latch ................................................................... 18

RF N Counter Latch ................................................................... 19

Program Modes .............................................................................. 20

IF and RF Power-Down ............................................................. 20

IF Section ..................................................................................... 20

RF Section ................................................................................... 21

Applications Information .............................................................. 22

Local Oscillator for GSM Handset Receiver ............................... 22

Wideband PLL ............................................................................ 23

Interfacing ................................................................................... 24

PCB Design Guidelines for Lead Frame

Chip Scale Package ..................................................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 26



REVISION HISTORY

11/10—Rev. B to Rev C

Changes to V
to V

DD

Changes to Ordering Guide .......................................................... 26

9/08—Rev. A to Rev B

Updated Format .................................................................. Universal

Changes to Figure 1 and General Description Section ............... 1

Changes to Prescaler Output Frequency Parameter and RF
Input Frequency (RF

Changes to Table 3 and Figure 2 ..................................................... 5

Changes to Figure 4 .......................................................................... 7

Changes to Figure 27, RF/IF A and B Counters Section, Pulse

Swallow Function Section, and RF/IF R Counter Section ........ 13

Changes to RF/IF Input Shift Register Section ........................... 14

Changes to Programmable IF Reference (R) Counter Section,

IF Program Modes Section, and IF Power-Down Section ........ 20

1, VP2 to GND Parameter, Table 4 and VP1, VP2

P

1, VDD2 Parameter, Table 4 ................................................... 6

) Parameter ................................................. 3

IN

Changes to Programmable RF Reference (R) Counter Section,
RF Program Modes Section, Programmable RF N Counter

Section, and RF Power-Down Section ......................................... 21

Changes to Figure 32 ...................................................................... 23

Changes to Figure 33 and Figure 34............................................. 24

Added PCB Design Guidelines for Lead Frame Chip Scale

Package Section............................................................................... 24

Updated Outline Dimensions ....................................................... 25

Changes to Ordering Guide .......................................................... 25

3/03—Data Sheet changed from REV. 0 to REV. A

Changes to General Description ..................................................... 1

Changes to Specifications ................................................................. 3

Changes to Table 9 .......................................................................... 18

Changes to Table 11 ....................................................................... 20

Changes to Figure 31 ...................................................................... 23

11/02—Revision 0: Initial Version

Rev. C | Page 2 of 28

ADF4212L

SPECIFICATIONS

VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = T
otherwise noted; dBm referred to 50 Ω.

Table 1.

Parameter1 B Version B Chips2 Unit Test Conditions/Comments

RF/IF CHARACTERISTICS

RF Input Frequency (RFIN) 0.2/2.4 0.2/2.4 GHz min/max For lower frequencies, ensure that slew rate (SR)

> 140 V/µs
RF Input Sensitivity −10/0 −10/0 dBm min/max VDD = 3 V
IF Input Frequency (IFIN) 100/1000 100/1000 MHz min/max
IF Input Sensitivity −10/0 −10/0 dBm min/max VDD = 3 V

MAXIMUM ALLOWABLE

Prescaler Output Frequency3 188 188 MHz max

REFIN CHARACTERISTICS

See

Figure 26 for input circuit

REFIN Input Frequency 10/150 10/150 MHz min/max
REFIN Input Sensitivity 500 mV/VDD 500 mV/VDD V p-p min/max AC-coupled; when dc-coupled, 0 V to VDD

maximum (CMOS compatible)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 A max

PHASE DETECTOR

Phase Detector Frequency4 75 75 MHz max

CHARGE PUMP

ICP Sink/Source

High Value 5 5 mA typ With R

Programmable, see

= 2.7 kΩ

SET

Low Value 625 625 A typ
Absolute Accuracy 2 2 % typ With R
R

Range 1.5/5.6 1.5/5.6 kΩ min/max

SET

= 2.7 kΩ

SET

ICP Three-State Leakage Current 1 1 nA max
Sink and Source Current Matching 6 6 % typ 0.5 V < VCP < VP − 0.5 V

ICP vs. VCP 2 2 % typ 0.5 V < VCP < VP − 0.5 V
ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 1.4 V min

INH

V

, Input Low Voltage 0.6 0.6 V max

INL

I

, Input Current ±1 ±1 A max

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 A

POWER SUPPLIES

VDD1 2.7/3.3 2.7/3.3 V min/max
VDD2 VDD1 VDD1 V min/max
VP1, VP2 VDD1/5.5 VDD1/5.5 V min/max

IDD (RF and IF)5 7.5/10 7.5/10 mA typ/max

RF Only 5.0/6 5.0/6 mA typ/max
IF Only 2.5/4 2.5/4 mA typ/max
IP (IP1 + IP2) 0.6 0.6 mA typ
Low Power Sleep Mode 1 1 A typ

1

Operating temperature range is as follows: B version: −40°C to +85°C.

2

The B chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency less

than this value.

4

Guaranteed by design. Sample tested to ensure compliance.

5

TA = 25°C. RF = 1 GHz; prescaler = 32/33. IF = 500 MHz; prescaler = 16/17.

to T

MIN

Table 10

MAX

, unless

Rev. C | Page 3 of 28

ADF4212L

VDD1 = VDD2 = 2.7 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = T
otherwise noted; dBm referred to 50 V.

Table 2.

Parameter1 B Version B Chips2 Unit Test Conditions/Comments

NOISE CHARACTERISTICS

RF Phase Noise Floor3 −170 −170 dBc/Hz typ 25 kHz PFD frequency

−162 −162 dBc/Hz typ 200 kHz PFD frequency
Phase Noise Performance4 VCO output

IF: 540 MHz Output5 −89 −89 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
IF: 900 MHz Output6 −87 −87 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 900 MHz Output6 −89 −89 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 1750 MHz Output7 −84 −84 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
RF: 2400 MHz Output8 −87 −87 dBc/Hz typ 1 kHz Offset and 1 MHz PFD frequency

Spurious Signals

IF: 540 MHz Output5 −88/−90 −88/−90 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
IF: 900 MHz Output6 −90/−94 −90/−94 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 900 MHz Output6 −90/−94 −90/−94 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 1750 MHz Output7 −80/−82 −80/−82 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency
RF: 2400 MHz Output8 −80/−82 −80/−82 dB typ 200 kHz/400 kHz and 200 kHz PFD frequency

1

Operating temperature range is as follows: B version: −40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

See Figure 9.

4

The phase noise is measured with the EVAL-ADF4212EB and the HP8562E spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer

(f

= 10 MHz @ 0 dBm).

REFOUT

5

f

REFIN

6

f

REFIN

7

f

REFIN

8

f

REFIN

= 10 MHz; f
= 10 MHz; f
= 10 MHz; f
= 10 MHz; f

= 200 kHz; offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; loop B/W = 20 kHz

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop B/W = 20 kHz

PFD

= 1 MHz; offset frequency = 1 kHz; fRF = 2400 MHz; N = 9800; loop B/W = 20 kHz

PFD

MIN

to T

MAX

, unless

Rev. C | Page 4 of 28

ADF4212L

TIMING CHARACTERISTICS

VDD1 = VDD2 = 2.6 V to 3.3 V; VP1, VP2 = VDD to 5.5 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; TA = T
otherwise noted; dBm referred to 50 Ω.

Table 3.

Parameter1 Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE setup time
t2 10 ns min Data to clock setup time
t3 10 ns min Data to clock hold time
t4 25 ns min Clock high duration
t5 25 ns min Clock low duration
t6 10 ns min Clock to LE setup time
t7 20 ns min LE pulse width

1

Guaranteed by design but not production tested.

CLK

t

4

t

5

MIN

to T

MAX

, unless

DATA

LE

LE

t

2

DB23 (MSB) DB22 DB2

t

1

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

02774-002

Figure 2. Timing Diagram

Rev. C | Page 5 of 28

ADF4212L

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter

VDD1 to GND −0.3 V to +3.6 V
VDD1 to VDD2 −0.3 V to +0.3 V
VP1, VP2 to GND −0.3 V to +5.8 V
VP1, VP2 to VDD1, VDD2 −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to DVDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN, IFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
LFCSP θJA Thermal Impedance

(Paddle Soldered)

LFCSP θJA Thermal Impedance

(Paddle Not Soldered)

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C

1

This device is a high performance RF integrated circuit with an ESD rating of

<2 kV, and is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

1, 2

Rating

122°C/W

216°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. C | Page 6 of 28

ADF4212L

2

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

1

P

V
20

1CP

RF

VDD1

VP1

CP

DGND

RF

AGND

FL

REF

DGND

MUXOUT

RF

RF

IN

RF

O

IN

IF

1

2

3

ADF4212L

4

(Not to Scale)

5

6

7

8

9

10

TOP VIEW

20

19

18

17

16

15

14

13
12

11

Figure 3. TSSOP Pin Configuration

V

DD

VP2
CP

IF

DGND
IF

IN

AGND
R

SET

LE
DATA
CLK

2

IF

IF

NOTES

1. IT I S RECOMMENDED T HAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPER PLANE
FOR ENHANCED THERM A L P E RF ORMANCE. THE PAD

2774-003

SHOULD BE GRO UNDED AS WELL.

2DGND

RF

ADF4212L

3RF

IN

RF

O

4AGND
5FL

TOP VIEW

(Not to S cale)

6

IN

REF

Figure 4. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.
Mnemonic TSSOP LFCSP Description

CPRF 3 1

RF Charge Pump Output. When enabled, this provides ±I

to the external RF loop filter, which in turn

CP

drives the external RF VCO.
DGNDRF 4 2 Digital Ground Pin for the RF Digital Circuitry.
RFIN 5 3 Input to the RF Prescaler. This small signal input is normally ac-coupled from the RF VCO.
AGNDRF 6 4 Ground Pin for the RF Analog Circuitry.
FLO 7 5 Multiplexed Output of RF/IF Programmable or Reference Dividers, RF/IF Fastlock Mode. CMOS output.
REFIN 8 6

Reference Input. This is a CMOS input with a nominal threshold of V

DD

resistance of 100 kΩ. See Figure 26. This input can be driven from a TTL or CMOS crystal oscillator, or can

be ac-coupled.
DGNDIF 9, 17 7, 15 Digital Ground Pin for the IF Digital, Interface, and Control Circuitry.
MUXOUT 10 8

This multiplexer output allows either the IF/RF lock detect, the scaled RF, the scaled IF, or the scaled

reference frequency to be accessed externally.
CLK 11 9

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA 12 10

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

a high impedance CMOS input.
LE 13 11

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches, with the latch selected using the control bits.
R

14 12

SET

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output

current. The nominal voltage potential at the R

pin is 0.66 V. The relationship between ICP and R

SET

therefore,

13.5

I

where R

MAXCP

= 2.7 kΩ and ICP

SET

=

R

SET

= 5 mA for both the RF and IF charge pumps.

MAX

AGNDIF 15 13 Ground Pin for the IF Analog Circuitry.
IFIN 16 14 Input to the IF Prescaler. This small signal input is normally ac-coupled from the IF VCO.
CPIF 18 16

Output from the IF Charge Pump. This is normally connected to a loop filter that drives the input to an

external VCO.
VP2 19 17

Power Supply for the IF Charge Pump. This should be greater than or equal to V

2 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

V

DD

IF

2

P

DD

DD

P

V

C

V

V

17

16

19

18

PIN 1
INDICATOR

8

7

T

IF

D
DGN

MUXOU

15 DGND

IF

14 IF

IN

13 AGND

IF

12 R

SET

11 LE

9

10

CLK

DATA

02774-004

/2 and an equivalent input

2. In systems where

DD

SET

is,

Rev. C | Page 7 of 28

ADF4212L

Pin No.
Mnemonic TSSOP LFCSP Description

VDD2 20 18

VDD1 1 19

VP1 2 20

EP

Exposed
Pad

Power Supply for the IF, Digital, and Interface Section. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin. V
V

2 must have the same potential as VDD1.

DD

2 should have a value of between 2.6 V and 3.3 V.

DD

Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as close
as possible to this pin. V
potential as V

2.

DD

Power Supply for the RF Charge Pump. This should be greater than or equal to V

1 is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range up to 5.5 V.

V

DD

1 should have a value of between 2.6 V and 3.3 V. VDD1 must have the same

DD

1. In systems where

DD

It is recommended that the exposed pad be thermally connected to a copper plane for enhanced
thermal performance. The pad should be grounded as well.

Rev. C | Page 8 of 28

ADF4212L

TYPICAL PERFORMANCE CHARACTERISTICS

0

VDD = 3V
V

= 5V

P

–5

–10

–15

–20

AMPLITUDE ( dBm)

–25

–30

0 500 1000 1500 2000

FREQUENCY (MHz)

2500 3000

Figure 5. Input Sensitivity (RF Input)

0

V

= 3V

DD

V

= 5V

P

–5

–10

–15

–20

AMPLITUDE (dBm)

–25

–30

–35

0 500 1000 1500

FREQUENCY (MHz)

Figure 6. Input Sensitivity (IF Input)

0

VDD = 3V, VP = 5V
I

= 5mA

–10

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz

–20

RES. BANDWIDTH = 10Hz
VIDEO BANDWI DTH = 10Hz

–30

SWEEP = 1.9 SECONDS
AVERAGES = 22

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2k –1k 1.75G 1k 2k

FREQUENCY (Hz)

REFERENCE
LEVEL = –3. 2d Bm

–84.2dBc/Hz

Figure 7. Phase Noise, RF Side (1750 MHz, 200 kHz, 20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

02774-005

REFERENCE
LEVEL = –3.0dBm

–400k –200k 1.75G 200k 400k

FREQUENCY (Hz)

VDD= 3V, VP= 5V
I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDW IDTH = 20kHz
RES. BANDWIDT H = 1Hz
VIDEO BANDWIDTH = 1Hz
SWEEP = 2.5 SECONDS
AVERAGES = 20

–85.9dB

02774-008

Figure 8. Reference Spurs, RF Side (1750 MHz, 200 kHz, 20 kHz)

= –50dBc/Hz

10dB/DIV

–50

–60

–70

–80

–90

–100

–110

–120

PHASE NOISE (d Bc/Hz)

–130

–140

–150

100Hz

02774-006

R

L

FREQUENCY OFFSET

FROM 1.75GHz CARRIER

RMS NOISE = 1.38 DEGREES

1.38° RMS

1MHz

02774-009

Figure 9. Integrated Phase Noise (1750 MHz, 200 kHz/20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT PO WER (dB)

–80

–90

–100

02774-007

REFERENCE
LEVEL = –4.3 d Bm

–2k –1k 540M 1k 2k

FREQUENCY (Hz)

V

= 3V, VP= 5V

DD

I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDW IDTH = 20kHz
RES. BANDWIDT H = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 22

–88.8dBc/Hz

02774-010

Figure 10. Phase Noise, IF Side (540 MHz, 200 kHz/20 kHz)

Rev. C | Page 9 of 28