ANALOG DEVICES ADF4210, ADF4211, ADF4212, ADF4213 Service Manual

a

Dual RF/IF PLL Frequency Synthesizers

ADF4210/ADF4211/ADF4212/ADF4213

FEATURES
ADF4210: 550 MHz/1.2 GHz
ADF4211: 550 MHz/2.0 GHz
ADF4212: 1.0 GHz/2.7 GHz
ADF4213: 1.0 GHz/3 GHz

2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

RF and IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Analog and Digital Lock Detect
Fastlock Mode
Power-Down Mode

APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

VDD1VDD2VP1VP2

GENERAL DESCRIPTION

The ADF4210/ADF4211/ADF4212/ADF4213 is a dual frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. They can provide the LO for both
the RF and IF sections. They consist of a low-noise digital PFD
(Phase Frequency Detector), a precision charge pump, a pro­grammable reference divider, programmable A and B Counters
and a dual-modulus prescaler (P/P + 1). The A (6-bit) and B
(12-bit) counters, in conjunction with the dual modulus prescaler
(P/P + 1), implement an N divider (N = BP + A). In addition,
the 14-bit reference counter (R Counter), allows selectable
REFIN frequencies at the PFD input. A complete PLL (Phase­Locked Loop) can be implemented if the synthesizer is used with
an external loop filter and VCO (Voltage Controlled Oscillators).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5 V and can be powered down when not in use.

R

SET

12-BIT IF

DGND

B-COUNTER

8-BIT IF

A-COUNTER

14-BIT IF

R-COUNTER

R-COUNTER

12-BIT RF

B-COUNTER

6-BIT RF

A-COUNTER

DGND

IF

14-BIT RF

IF

IN

REF

IN

CLOCK

DATA

LE

RF

IN

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

OSCILLATOR

DGND

REGISTER

RF

PRESCALER

24-BIT

DATA

PRESCALER

AGND

IF

SDOUT

RF

RF

PHASE
COMPARATOR

IF

LOCK

DETECT

RF

LOCK

DETECT

PHASE
COMPARATOR

ADF4210/ADF4211/
ADF4212/ADF4213

AGND

IF

IF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

REFERENCE

CHARGE

PUMP

IF CURRENT

SETTING

IFCP3 IFCP2 IFCP1

OUTPUT

MUX

RFCP3 RFCP2 RFCP1

IF CURRENT

SETTING

CHARGE

PUMP

REFERENCE

R

SET

FLO SWITCH

CP

IF

MUXOUT

CP

RF

FL

O

ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS

1

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V ; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; R
TA = T

to T

MIN

P

arameter B Version B Chips

RF/IF CHARACTERISTICS (3 V)

RF Input Frequency (RFIN) See Figure 3 for Input Circuit.

ADF4210 0.1/1.2 0.1/1.2 GHz min/max Use a square wave for frequencies lower than F
ADF4211 0.1/2.0 0.1/2.0 GHz min/max
ADF4212 0.15/2.7 0.15/2.7 GHz min/max

ADF4213 0.2/3.0 0.2/3.0 GHz min/max
RF Input Sensitivity –10/0 –10/0 dBm min/max
IF Input Frequency (IF

ADF4210 60/550 60/550 MHz min/max

ADF4211 60/550 60/550 MHz min/max

ADF4212 0.06/1.0 0.06/1.0 GHz min/max

ADF4213 0.06/1.0 0.06/1.0 GHz min/max
IF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency

RF/IF CHARACTERISTICS (5 V)

RF Input Frequency (RFIN) See Figure 3 for Input Circuit.

ADF4210 0.18/1.2 0.18/1.2 GHz min/max Use a square wave for frequencies lower than F

ADF4211 0.18/2.0 0.18/2.0 GHz min/max

ADF4212 0.2/2.3 0.2/2.3 GHz min/max

ADF4213 0.2/2.5 0.2/2.5 GHz min/max
RF Input Sensitivity –5/0 –5/0 dBm min/max
IF Input Frequency (IF

ADF4210 100/550 100/550 MHz min/max

ADF4211 100/550 100/550 MHz min/max

ADF4212 0.1/1.0 0.1/1.0 GHz min/max

ADF4213 0.1/1.0 0.1/1.0 GHz min/max
IF Input Sensitivity –5/0 –5/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency

REFIN CHARACTERISTICS See Figure 2 for Input Circuit.

REFIN Input Frequency 0/115 0/115 MHz min/max For F < 5 MHz, use dc-coupled square wave

REFIN Input Sensitivity

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

ICP Sink/Source Programmable: See Table V

High Value 5 5 mA typ With R

Low Value 625 625 µA typ

Absolute Accuracy 3 3 % typ With R

R

SET

Three-State Leakage Current 1 1 nA typ

I

CP

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V

vs. V

I

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

INH

V

INL

I

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

V

, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA

OH

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

unless otherwise noted.)

MAX

2

Unit Test Conditions/Comments

)

IN

3

)

IN

3

4

5

165 165 MHz max

200 200 MHz max

–5/0 –5/0 dBm min/max AC-Coupled. When dc-coupled, 0 to VDD max

55 55 MHz max

Range 1.5/5.6 1.5/5.6 kΩ, min/max

CP

, Input High Voltage 0.8 × DV

, Input Low Voltage 0.2 × DV

2 2 % typ 0.5 V ⱕ VCP ⱕ VP – 0.5 V

DD

DD

0.8 × DV

0.2 × DV

DD

DD

V min
V max

, Input Current ± 1 ± 1 µA max

DD

).

(0 to V

(CMOS-Compatible)

= 2.7 kΩ

SET

= 2.7 kΩ

SET

CP

= 2.7 k dBm to 50 ;

SET

ⱕ VP – 0.5 V

MIN

MIN

.

.

–2–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

Parameter B Version B Chips2Un it Test Conditions/Comments

POWER SUPPLIES

V

1 2.7/5.5 2.7/5.5 V min/V max

DD

2V

V

DD

V

P

I

(RF + IF)

DD

6

ADF4210 11.5 11.5 mA max 9.0 mA typical
ADF4211 15.0 15.0 mA max 11.0 mA typical
ADF4212 17.5 17.5 mA max 13.0 mA typical
ADF4213 20 20 mA max 15 mA typical

I

(RF Only)

DD

ADF4210 6.75 6.75 mA max 5.0 mA typical
ADF4211 10 10 mA max 7.0 mA typical
ADF4212 12.5 12.5 mA max 9.0 mA typical
ADF4213 15 15 mA max 11 mA typical

I

(IF Only)

DD

ADF4210 5.5 5.5 mA max 4.5 mA typical
ADF4211 5.5 5.5 mA max 4.5 mA typical
ADF4212 5.5 5.5 mA max 4.5 mA typical
ADF4213 5.5 5.5 mA max 4.5 mA typical

I

1 + IP2) 1.0 1.0 mA max TA = 25°C, 0.55 mA typical

P (IP

Low-Power Sleep Mode 1 1 µA typ

NOISE CHARACTERISTICS

ADF4213 Phase Noise Floor

Phase Noise Performance

ADF4210/ADF4211, IF: 540 MHz Output
ADF4212/ADF4213, IF: 900 MHz Output
ADF4210/ADF4211, RF: 900 MHz Output
ADF4212/ADF4213, RF: 900 MHz Output

7

8

9

10

10

10

ADF4211/ADF4212, RF: 1750 MHz Output
ADF4211/ADF4212, RF: 1750 MHz Output
ADF4212/ADF4213, RF: 2400 MHz Output

Spurious Signals

ADF4210/ADF4211, IF: 540 MHz Output
ADF4212/ADF4213, IF: 900 MHz Output
ADF4210/ADF4211, RF: 900 MHz Output
ADF4212/ADF4213, RF: 900 MHz Output

9

10

10

10

ADF4211/ADF4212, RF: 1750 MHz Output
ADF4211/ADF4212, RF: 1750 MHz Output
ADF4212/ADF4213, RF: 2400 MHz Output14–80/–82 –80/–82 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is

less than this value.

4

VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels, TA = 25°C.

5

Guaranteed by design. Sample tested to ensure compliance.

6

VDD = 3 V; P = 16; RFIN = 900 MHz; IFIN = 540 MHz, TA = 25°C.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). See

TPC 16.

8

The phase noise is measured with the EVAL-ADF4210/ADF4212/ADF4213EB Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the

REFIN for the synthesizer (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

Same conditions as listed in Note 10.

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

= 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.

PFD

= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

PFD

= 1 MHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.

PFD

= 10 MHz @ 0 dBm).

REFOUT

1V

DD

DD

1

VDD1/6.0 VDD1/6.0 V min/V max VDD1, VDD2 ⱕ VDD1, VDD2 ⱕ 6.0 V

–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency

@ VCO Output
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–89 –89 dBc/Hz typ See Note 11
–89 –89 dBc/Hz typ See Note 11
–91 –91 dBc/Hz typ See Note 11

12

–85 –85 dBc/Hz typ See Note 11

13

–67 –67 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

14

–88 –88 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

–88/–90 –88/–90 dB typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
–90/–94 –90/–94 dB typ See Note 11
–90/–94 –90/–94 dB typ See Note 11
–90/–94 –90/–94 dB typ See Note 11

12

–80/–82 –80/–82 dB typ See Note 11

13

–65/–70 –65/–70 dB typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency

REV. A

–3–

ADF4210/ADF4211/ADF4212/ADF4213

WARNING!

ESD SENSITIVE DEVICE

(VDD1 = VDD2 = 3 V  10%, 5 V  10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6 V  10%; AGNDRF = DGND

TIMING CHARACTERISTICS

Limit at

to T

T

Parameter (B Version) Unit Test Conditions/Comments

MIN

t

1

t

2

t

3

t

4

t

5

t

6

NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.

10 ns min DATA to CLOCK Set-Up Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Set-Up Time
20 ns min LE Pulsewidth

CLOCK

DATA

LE

LE

MAX

DB20

(MSB)

= AGNDIF = DGNDIF = 0 V; TA = T

t

3

t

1

t

2

DB19 DB2

to T

MIN

MAX

t

4

(CONTROL BIT C2)

unless otherwise noted.)

DB1

DB0 (LSB)

(CONTROL BIT C1)

t

5

RF

t

6

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

V

DD

V

1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

P

V

1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . –0.3 V to DV

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB,

IN

A, IFINB to GND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

IF

IN

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ
CSP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122°C/W

JA

1, 2

+ 0.3 V

DD

+ 0.3 V

P

CSP θ

(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

11749 (CMOS) and 522 (Bipolar).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4210/ADF4211/ADF4212/ADF4213 features proprietary ESD protection circuitry, per­manent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4210BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4210BCP –40°C to +85°C Chip Scale Package CP-20
ADF4211BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4211BCP –40°C to +85°C Chip Scale Package CP-20
ADF4212BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4212BCP –40°C to +85°C Chip Scale Package CP-20
ADF4213BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-20
ADF4213BCP –40°C to +85°C Chip Scale Package CP-20

*Contact the factory for chip availability.

–4–

REV. A

ADF4210/ADF4211/ADF4212/ADF4213

PIN FUNCTION DESCRIPTIONS

Pin Number
TSSOP Mnemonic Function

1V

2V

3CP

4 DGND
5RF
6 AGND
7FL
8 REF

9 DGND
10 MUXOUT This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

14 R

15 AGND
16 IF
17 DGND
18 CP

19 VP2 Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where

20 V

1 Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as

DD

close as possible to this pin. V

DD

1 should have a value of between 2.7 V and 5.5 V. VDD1 must have

the same potential as VDD2.

1 Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where

P

RF

V

1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

DD

Output from the RF Charge Pump. This is normally connected to a loop filter which drives the input
to an external VCO.

RF

IN

RF

O

IN

Ground Pin for the RF Digital Circuitry.
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
Ground Pin for the RF Analog Circuitry.
RF/IF Fastlock Mode.
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator.

IF

Digital Ground for the IF Digital, Interface and Control Circuitry.

Reference Frequency to be accessed externally.

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.

input is a high impedance CMOS input.

one of the four latches, the latch being selected using the control bits.

SET

IF

IN

IF

IF

Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the R

13 5.

=

R

SET

= 5 mA for both the RF and IF Charge Pumps.

So, with R

= 2.7 kΩ, I

SET

I

CP MAX

CP MAX

pin is 0.66 V. The relationship between ICP and R

SET

SET

is

Ground Pin for the IF Analog Circuitry.
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
Ground Pin for the IF Digital, Interface, and Control Circuitry.
Output from the IF Charge Pump. This is normally connected to a loop filter which drives the input

to an external VCO.

VDD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.

2 Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should

DD

be placed as close as possible to this pin. V

DD

2 should have a value of between 2.7 V and 5.5 V. VDD2

must have the same potential as VDD1.

REV. A

VDD1

VP1

CP

DGND

RF

AGND

FL

REF

DGND

MUXOUT

1

2

3

RF

4

RF

5

IN

6

RF

7

O

8

IN

9

IF

10

TSSOP

ADF4210/
ADF4211/
ADF4212/
ADF4213

TOP VIEW

(Not to Scale)

20

19

18

17

16

15

14

13

12

11

V

DD

2

V

P

CP

IF

DGND

IF

IN

AGND

R

SET

LE

DATA

CLK

PIN CONFIGURATIONS

CP-20

1

2

DD

IF

2

DD

P

V

V

CLK

MUXOUT

IF

CP

DATA

15

DGND

IF

14

IF

IN

13

AGND

IF

12

R

SET

11

LE

1

P

V

2

CP

1

RF

DGND

2

AGND

RF

3

RF

IN

4

RF

FL

5

O

IF

IF

V

20 19 18 17 16

ADF4210/
ADF4211/
ADF4212/
ADF4213

TOP VIEW

(Not to Scale)

6 7 8 9 10

IN

REF

DGND

–5–

ADF4210/ADF4211/ADF4212/ADF4213

–Typical Performance Characteristics

FREQUENCY S11 REAL S11 IMAG

50000000.0

150000000.0

250000000.0

350000000.0

450000000.0

550000000.0

650000000.0

750000000.0

850000000.0

950000000.0

1050000000.0

1150000000.0

1250000000.0

1350000000.0

1450000000.0

1550000000.0

1650000000.0

1750000000.0

1850000000.0

1950000000.0

2050000000.0

0.955683

0.956993

0.935463

0.919706

0.871631

0.838141

0.799005

0.749065

0.706770

0.671007

0.630673

0.584013

0.537311

0.505090

0.459446

0.381234

0.363150

0.330545

0.264232

0.242065

0.181238

–0.052267
–0.112191
–0.185212
–0.252576
–0.323799
–0.350455
–0.408344
–0.455840
–0.471011
–0.535268
–0.557699
–0.604256
–0.622297
–0.642019
–0.686409
–0.693908
–0.679602
–0.721812
–0.697386
–0.711716
–0.723232

FREQUENCY S11 REAL S11 IMAG

2150000000.0

2250000000.0

2350000000.0

2450000000.0

2550000000.0

2650000000.0

2750000000.0

2850000000.0

2950000000.0

0.138086

0.102483

0.054916

0.018475
–0.019935
–0.054445
–0.083716
–0.129543
–0.154974

–0.699896
–0.704160
–0.696325
–0.669617
–0.668056
–0.666995
–0.634725
–0.615246
–0.610398

TPC 1. S-Parameter Data for the ADF4213 RF Input
(Up to 3.0 GHz)

0

–10

REFERENCE
LEVEL = –5.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

–2kHz –1kHz 900MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–91.2dBc/Hz

TPC 2. ADF4213 Phase Noise (900 MHz, 200 kHz, 20 kHz)

0

–5

VDD = 3V

= 3V

V

P

–10

TA = +85C

–15

TA = +25C

–20

–25

RF INPUT POWER – dBm

TA = –40C

–30

–35

0

123

RF INPUT FREQUENCY – GHz

TPC 4. Input Sensitivity (ADF4213)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.5421

–40

–50

–60

0.54 rms

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

TPC 5. ADF4213 Integrated Phase Noise (900 MHz, 200 kHz,

µ

20 kHz, Typical Lock Time: 400

s)

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.6522

–40

–50

–60

0.65 rms

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz

1kHz 10kHz 100kHz

FREQUENCY OFFSET FROM 900MHz CARRIER

1MHz

TPC 3. ADF4213 Integrated Phase Noise (900 MHz,

µ

200 kHz, 35 kHz, Typical Lock Time: 200

s)

0

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 4.2 SECONDS

AVERAGES = 20

–91.0dBc/Hz

OUTPUT POWER – dB

–10

–20

–30

–40

–50

–60

–70

–80

REFERENCE
LEVEL = –5.7dBm

–90

–100

–400kHz –200kHz

900MHz

200kHz 400kHz

TPC 6. ADF4213 Reference Spurs (900 MHz, 200 kHz, 20 kHz)

–6–

REV. A