Datasheet ADF4196 Datasheet (ANALOG DEVICES)

Low Phase Noise, Fast Settling, 6 GHz

PLL Frequency Synthesizer

ADF4196

Rev. B

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09450-001

N COUNTER

SW1
CP

OUT+

CP

OUT–

SW2

REFERENCE

DATA

LE

24-BIT

DATA

REGISTER

CLK

REF

IN

A

GND

1

A

GND

2 D

GND

1 D

GND

2 D

GND

3

SD

GND

SW

GND

V

DD

DGND

LOCK DETE CT

R

DIV

N

DIV

SDV

DDDVDD

1 DVDD2 DVDD3

AV

DD

VP1 VP2

VP3 R

SET

OUTPUT

MUX

MUX

OUT

–

+

HIGH-Z

PHASE

FREQUENCY

DETECTOR

ADF4196

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

RF

IN+

RF

IN–

×2

DOUBLER

4-BIT R

COUNTER

/2

DIVIDER

CHARGE

PUMP

–

+

+

–

DIFFERENTIAL

AMPLIFIER

CMR

AIN–
AIN+

A

OUT

SW3

Data Sheet

FEATURES

Fast settling, fractional-N PLL architecture
Single PLL replaces ping-pong synthesizers
Frequency hop across GSM band in 5 μs with phase settled

within 20 μs
1 degree rms phase error at 4 GHz RF output
Digitally programmable output phase
RF input range up to 6 GHz
3-wire serial interface
On-chip, low noise differential amplifier
Phase noise figure of merit: −216 dBc/Hz

APPLICATIONS

GSM/EDGE base stations
PHS base stations
Pulse Doppler radar
Instrumentation and test equipment
Beam-forming/phased array systems

GENERAL DESCRIPTION

The ADF4196 frequency synthesizer can be used to implement
local oscillators (LO) in the upconversion and downconversion
sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time require­ments for base stations, and the fast settling feature makes the

ADF4196 suitable for pulse Doppler radar applications.

The ADF4196 consists of a low noise, digital phase frequency
detector (PFD) and a precision differential charge pump.
A differential amplifier converts the differential charge pump
output to a single-ended voltage for the external voltage controlled
oscillator (VCO). The sigma-delta (Σ-Δ) based fractional inter­polator, working with the N divider, allows programmable modulus
fractional-N division. Additionally, the 4-bit reference (R) counter
and on-chip frequency doubler allow selectable reference signal
(REF

) frequencies at the PFD input.

IN

A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a VCO. The
switching architecture ensures that the PLL settles within the
GSM time slot guard period, removing the need for a second
PLL and associated isolation switches. This decreases the cost,
complexity, PCB area, shielding, and characterization found on
previous ping-pong GSM PLL architectures.

FUNCTIONAL BLOCK DIAGRAM

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

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ADF4196 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

Thermal Resistance ...................................................................... 5

Transistor Count ........................................................................... 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 8

Theory of Operation ...................................................................... 11

General Description ................................................................... 11

Reference Input ........................................................................... 11

RF Input Stage ............................................................................. 11

PFD and Charge Pump .............................................................. 12

Differential Charge Pump ......................................................... 12

Fast Lock Timeout Counters ..................................................... 12

Differential Amplifier ................................................................ 13

MUX

and Lock Detect ......................................................... 13

OUT

REVISION HISTORY

12/11—Rev. A t o R e v. B

Changes to Figure 10, Figure 11, Figure 13, and

Figure 14 ............................................................................................ 9

Change to Figure 31 ....................................................................... 17

10/11—Revision A: Initial Version

Input Shift Register .................................................................... 13

Register Map ................................................................................... 14

FRAC/INT Register (R0) Latch Map ....................................... 15

MOD/R Register (R1) Latch Map ............................................ 16

Phase Register (R2) Bit Latch Map .......................................... 17

Function Register (R3) Latch Map ........................................... 18

Charge Pump Register (R4) Latch Map .................................. 19

Power-Down Register (R5) Bit Map ........................................ 20

Mux Register (R6) Latch Map and Truth Table ..................... 21

Programming the ADF4196 .......................................................... 22

Worked Example ........................................................................ 22

Spur Mechanisms ....................................................................... 22

Power-Up Initialization ............................................................. 23

Changing the Frequency of the PLL and the Phase Lookup

Tabl e ............................................................................................. 23

Applications Information .............................................................. 25

Local Oscillator for a GSM Base Station ................................. 25

Interfacing ................................................................................... 27

PCB Design Guidelines ............................................................. 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. B | Page 2 of 28

Data Sheet ADF4196

RF CHARACTERISTICS

CHARGE PUMP

Output Noise

7

nV/√Hz

At 20 kHz offset

Input Low Voltage, VIL

0.7 V

22

27

mA

SPECIFICATIONS

AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; A
R

= 2.4 kΩ; dBm referred to 50 Ω; TA = T

SET

MIN

to T

, unless otherwise noted. Operating temperature range = −40°C to +85°C.

MAX

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

GND

1, A

GND

2 = D

GND

1, D

GND

2, D

GND

3 = 0 V;

RF Input Frequency (RF

) 0.4 6 GHz See Figure 21 for input circuit

IN±

RF Input Sensitivity −10 0 dBm

Maximum Allowable Prescaler Output

Frequency

1

750 MHz

REFIN CHARACTERISTICS

REFIN Input Frequency 300 MHz For f > 120 MHz, set REF/2 bit = 1 (Register R1)

REFIN Edge Slew Rate 300 V/µs

REFIN Input Sensitivity 0.7 VDD V p-p AC-coupled

0 to VDD V CMOS compatible

REFIN Input Capacitance 10 pF

REFIN Input Current ±100 µA

PHASE DETECTOR

Phase Detector Frequency 26 MHz

ICP Up/Down

High Value 6.6 mA R
Low Value 104 µA R

= 2.4 kΩ

SET

= 2.4 kΩ

SET

Absolute Accuracy 5 %

R

Range 1 4 kΩ Nominally R

SET

= 2.4 kΩ

SET

ICP Three-State Leakage 1 nA

ICP Up vs. Down Matching 0.1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. VCP 1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. Temperature 1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

DIFFERENTIAL AMPLIFIER

Input Current 1 nA

Output Voltage Range 1.4 VP3 − 0.3 V

VCO Tuning Range 1.8 VP3 − 0.8 V

LOGIC INPUTS

Input High Voltage, VIH 1.4 V

Input Current, I

Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.4 V IOH = 500 µA

Output Low Voltage, VOL 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 2.7 3.3 V

DVDD1, DVDD2, DVDD3 AVDD V

VP1, VP2 4.5 5.5 V AVDD ≤ VP1, VP2 ≤ 5.5 V

VP3 5.0 5.65 V VP1, VP2 ≤ VP3 ≤ 5.65 V

IDD (AVDD + DVDD1, DVDD2, DVDD3 +

SDV
IDD (VP1 + VP2) 22 27 mA
IDD (VP3) 24 30 mA
IDD Power-Down 10 µA

, I

±1 µA

INH

INL

)

DD

Rev. B | Page 3 of 28

ADF4196 Data Sheet

1800 MHz3

−102

dBc/Hz

At 5 kHz offset and 13 MHz PFD frequency

t6

10 ns min

CLK to LE setup time

09450-002

CLK

DATA

DB23

(MSB)

DB22

DB1 (LSB)

(CONTRO L BIT C2)

DB2 (LSB)

(CONTRO L BIT C3)

DB0 (LSB)

(CONTRO L BIT C1)

LE

LE

t

2

t

4

t

5

t

3

t

7

t

6

t

1

Parameter Min Typ Max Unit Test Conditions/Comments

SW1, SW2, AND SW3

On Resistance

SW1 and SW2 65 Ω
SW3 75 Ω

NOISE CHARACTERISTICS

Output

900 MHz2 −108 dBc/Hz At 5 kHz offset and 26 MHz PFD frequency

Phase Noise

Normalized Phase Noise Floor

)4

(PN

SYNTH

Normalized 1/f Noise (PN

1

Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz).

2

f

= 26 MHz; f

REF

IN

3

f

= 13 MHz; f

REF

IN

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(f

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,

fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL™.

= 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz.

STEP

= 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz.

STEP

). PN

PFD

SYNTH

)5 −110 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz

1_f

= PN

− 10 log(f

TOT

TIMING CHARACTERISTICS

AVDD = DVDD1, DVDD2, DVDD3 = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; A
R

= 2.4 kΩ; dBm referred to 50 Ω; TA = T

SET

−216 dBc/Hz

) − 20 log(N).

PFD

to T

MIN

, unless otherwise noted. Operating temperature = −40°C to +85°C.

MAX

At VCO output with dither off, PLL loop
bandwidth = 500 kHz

1, A

GND

GND

2 = D

GND

1, D

GND

2, D

3 = 0 V;

GND

Table 2.

Parameter Limit Description

t1 10 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 15 ns min CLK high duration
t5 15 ns min CLK low duration

t7 15 ns min LE pulse width

Timing Diagram

Figure 2. Timing Diagram

Rev. B | Page 4 of 28

Data Sheet ADF4196

Peak Temperature

260°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to Ground −0.3 V to +3.6 V
AVDD to DVDD1, DVDD2, DVDD3, SDVDD −0.3 V to +0.3 V
VP1, VP2, VP3 to Ground −0.3 V to +5.8 V
VP1, VP2, VP3 to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to Ground −0.3 V to VDD + 0.3 V
Analog I/O Voltage to Ground −0.3 V to VP1, VP2, VP3 + 0.3 V
REFIN, RF
Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Reflow Soldering

Time at Peak Temperature 40 sec

, RF

to Ground −0.3 V to VDD + 0.3 V

IN+

IN−

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA Unit

32-Lead LFCSP (Paddle Soldered) 27.3 °C/W

TRANSISTOR COUNT

This device includes 75,800 metal oxide semiconductors (MOS)
and 545 bipolar junction transistors (BJT).

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with
an ESD rating of <2 kV, and it is ESD sensitive. Take proper
precautions for handling and assembly.

Rev. B | Page 5 of 28

ADF4196 Data Sheet

09450-003

1CMR
2A

OUT

3SW3
4A

GND

1

5RF

IN–

6RF

IN+

7AV

DD

24 V

P

2

23 R

SET

22 A

GND

2

21

D

GND

3

20 V

P

1

19 LE
18 DATA
17 CLK

8DV

DD

1

ADF4196

TOP VIEW

(Not to Scale)

9D

GND

1

10DV

DD

2

11

REF

IN

12

D

GND

2

13DV

DD

3

14

SD

GND

15

SDV

DD

16

MUX

OUT

32 V

P

3

31 AIN+

30 CP

OUT+

29

SW1

28 SW

GND

27

SW2

26 CP

OUT–

25

AIN–

PIN 1
INDICATOR

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE G ROUND PLANE.

5

RF

8

DVDD1

Power Supply Pin for the N Divider. DVDD1 should be at the same voltage as AVDD. Place a 0.1 µF decoupling

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 CMR

2 A

OUT

Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.

Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to
three-fifths of V

3. Requires a 0.1 µF capacitor to the ground plane.

P

3 SW3 Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active.
4 A

1 Analog Ground. This is the ground return pin for the differential amplifier and the RF section.

GND

IN−

Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF.
6 RF
7 AVDD

Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.

IN+

Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as

close as possible to this pin.

capacitor to the ground plane as close as possible to this pin.
9 D
10 DVDD2

1 Ground Return Pin for DVDD1.

GND

Power Supply Pin for the REF

Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the

IN

ground plane as close as possible to this pin.
11 REFIN

Reference Input. This CMOS input has a nominal threshold of V

/2 and a dc equivalent input resistance of 100 kΩ.

DD

This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
12 D

2 Ground Return Pin for DVDD2 and DVDD3.

GND

13 DVDD3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V.
14 SD
15 SDVDD

Ground Return Pin for the Digital Σ-Δ Modulator.

GND

Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground

plane as close as possible to this pin.
16 MUX

17 CLK

18 DATA

19 LE

20 VP1

21 D
22 A

Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency

to be accessed externally (see Figure 35 for details).

Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

OUT

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the three LSBs.

Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, V

Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.

3 Ground Return Pin for VP1.

GND

2 Ground Return Pin for VP2.

GND

Rev. B | Page 6 of 28

1 should be at the same voltage as VP2.

P

Data Sheet ADF4196

25.0

30

CP

Differential Charge Pump Positive Output Pin. Connect this pin to AIN+ and the loop filter.

Pin No. Mnemonic Description

23 R

24 VP2

25 AIN− Negative Input Pin for the Differential Amplifier.
26 CP
27 SW2 Fast Lock Switch 2. This switch is closed to SW
28 SW
29 SW1 Fast Lock Switch 1. This switch is closed to SW

31 AIN+ Positive Input Pin for the Differential Amplifier.
32 VP3

EP Exposed Paddle. The exposed paddle must be connected to the ground plane.

SET

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at

pin is 0.55 V. The relationship between ICP and R

the R

SET

=

I

CP

R

SET

Therefore, with R

= 2.4 kΩ, ICP = 104 µA.

SET

Power Supply Pin for the Charge Pump. Nominally 5 V, V

is

SET

2 should be at the same voltage as VP1. Place a 0.1 µF

P

decoupling capacitor to the ground plane as close as possible to this pin.

Differential Charge Pump Negative Output Pin. Connect this pin to AIN− and the loop filter.

OUT−

when the SW1/SW2 timeout counter is active.

GND

Ground for SW1 and SW2 Switches. Connect this pin to the ground plane.

GND

when the SW1/SW2 timeout counter is active.

GND

OUT+

Power Supply Pin for the Differential Amplifier. Ranges from 5.0 V to 5.5 V. Place a 0.1 µF decoupling capacitor to
the ground plane as close as possible to this pin. V

3 also requires a 10 µF decoupling capacitor to the ground plane.

P

Rev. B | Page 7 of 28

ADF4196 Data Sheet

–

–

–

–

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ. UNIT GHz KEYWORD R
PARAM TYPE S IMPEDANCE 50
DATA FORMAT MA

FREQ. MAGS11 ANGS11

0.5 0.8897 –16.6691

0.6 0.87693 –19.9279

0.7 0.85834 –23.561

0.8 0.85044 –26.9578

0.9 0.83494 –30.8201

1.0 0.81718 –34.9499

1.1 0.80229 –39.0436

1.2 0.78917 –42.3623

1.3 0.77598 –46.322

1.4 0.75578 –50.3484

1.5 0.74437 –54.3545

1.6 0.73821 –57.3785

1.7 0.7253 –60.695

1.8 0.71365 –63.9152

1.9 0.70699 –66.4365

2.0 0.7038 –68.4453

2.1 0.69284 –70.7986

2.2 0.67717 –73.7038

Figure 4. S-Parameter Data for the RF Input

FREQ. MAGS11 ANGS11

2.3 0.67107 –75.8206

2.4 0.66556 –77.6851

2.5 0.6564 –80.3101

2.6 0.6333 –82.5082

2.7 0.61406 –85.5623

2.8 0.5977 –87.3513

2.9 0.5655 –89.7605

3.0 0.5428 –93.0239

3.1 0.51733 –95.9754

3.2 0.49909 –99.1291

3.3 0.47309 –102.208

3.4 0.45694 –106.794

3.5 0.44698 –111.659

3.6 0.43589 –117.986

3.7 0.42472 –125.62

3.8 0.41175 –133.291

3.9 0.41055 –140.585

4.0 0.40983 –147.97

09450-038

10

5

0

–5

–10

–15

RF SENSITIVITY (d Bm)

–20

–25

–30

01234

4/5 PRESCALER 8/9 PRESCALER

FREQUENCY (GHz)

Figure 7. RF Input (RF

) Sensitivity

IN

09450-005

765

30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130

PHASE NOISE (dBc/Hz)

–140
–150
–160
–170

1k 10k 100k 1M 10M

GSM900 Rx SETUP, 40kHz LOOP BW, DITHER OFF
RF = 1092.8M Hz ,
N = 42 4/130
INTEG ER BOUNDARY S PUR: –103dBc @ 80 0 kHz

f

= 26MHz, MOD = 130

REF

FREQUENC Y (Hz)

100M

Figure 5. Single-Sideband (SSB) Phase Noise Plot at 1092.8 MHz

(GSM900 Rx Setup) vs. Free Running VCO Noise

60

DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13 MHz PFD.
MEASURED ON EVAL-ADF4193EBZ1 BOARD

–70

–80

–90

400kHz SPURS @ 2 5°C

30
–40
–50
–60
–70
–80
–90

–100
–110
–120
–130

PHASE NOISE (dBc/Hz)

–140
–150

09450-006

–160
–170

1k 10k 100k 1M 10M

DCS1800 Tx SETUP, 60kHz LOOP BW, DITHER OFF
RF = 1842.6M Hz ,
DSB INTE GRATED PHASE ERROR = 0 .46° RMS
SIRENZA 184 3T V CO

f

= 13MHz, MOD = 65

REF

FREQUENC Y (Hz)

09450-007

100M

Figure 8. Single-Sideband (SSB) Phase Noise Plot at 1842.6 MHz

(DCS1800 Tx Setup)

60

DCS1800 Tx SETUP WITH DITHER OFF,
60kHz LOOP BW, 13MHz PFD.
MEASURED ON EVAL-ADF4193E BZ 1 BOARD

–70

–80

–90

600kHz SPURS @ 25°C

–100

SPUR LEVEL (dBc)

–110

–120

1846 1859

FREQUENC Y (MHz)

400kHz SPURS @ 85°C

09450-010

1872

Figure 6. 400 kHz Fractional Spur Levels Across All DCS1800 Tx Channels

over Two Integer Multiples of the PFD Reference

–100

SPUR LEVEL (dBc)

–110

–120

1846 1859

FREQUENCY (MHz)

600kHz SPURS @ 85°C

1872

09450-011

Figure 9. 600 kHz Fractional Spur Levels Across All DCS1800 Tx Channels over

Two Integer Multiples of the PFD Reference

Rev. B | Page 8 of 28

Data Sheet ADF4196

09450-040

TIME (µs)

CONTROL VOLTAGE (V)

–1

0

1

2

3

4

5

9876543210

V

TUNE

CP

OUT+

CP

OUT–

DCS1800 Tx SETUP, 60kHz LOO P BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD.
TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

FREQUENCY L OCK IN WIDE BW MODE @ 4µs.

09450-008

TIME (µs)

PHASE ERROR (Deg rees)

–5 0 5 10 15 20 25 30 35 40

–50

50

40

30

20

10

0

–10

–20

–30

–40

45

+25°C

+85°C

–40°C

DCS1800 Tx SETUP, 60kHz LOO P BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD WITH AD8302
PHASE DETECT OR.
TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

PEAK PHASE ERROR < 5° @ 17.8µs

09450-012

CP

OUT

+ / CP

OUT

– VOLTAGE (V)

I

CP

(mA)

CHANGE PUMP MISMATCH (%)

0 0.5 1.0 1.5 2.0 2.5

3.0 3.5 4.0 4.5

–8

–6

–4

–2

0

2

4

6

8

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

5.0

ICP

OUT

+ P, ICP

OUT

– P

CHARGE PUMP MISMATCH (%)

NORMAL OP E RATING RANGE

ICP

OUT

+ N, ICP

OUT

– N

IUP= | ICP

OUT

+ P | + | ICP

OUT

– N |

I

DOWN

= | ICP

OUT

– P | + | ICP

OUT

+ N |

09450-041

TIME (µs)

CONTROL VOLTAGE (V)

–1

0

1

2

3

4

5

9876543210

V

TUNE

CP

OUT–

CP

OUT+

DCS1800 Tx SETUP, 60kHz LOO P BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD.
TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

FREQUENCY L OCK IN WIDE BW MODE @ 5µs.

09450-009

TIME (µs)

PHASE ERROR (Deg rees)

–5 0 5 10 15 20 25 30 35 40

–50

50

40

30

20

10

0

–10

–20

–30

–40

45

+25°C

+85°C

–40°C

DCS1800 Tx SETUP, 60kHz LOO P BW.
MEASURED ON EVAL-ADF4193EBZ1
EVALUATION BOARD WITH AD8302
PHASE DETECT OR.
TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

PEAK PHASE ERROR < 5° @ 19.2µs

09450-013

FREQUENCY (MHz)

CONTROL VOLTAGE (V)

1780 1800 1820 1840 1860 1880 1900 1920 1940

0

2

1

3

4

5

VP1 = V

P

2 = 5V

V

P

3 = 5.5V

V

CMR

= 3.3V

CP

OUT–

(= AIN–)

A

OUT

(= V

TUNE

)

CP

OUT+

(= AIN+)

Figure 10. V

Settling Transient for a 75 MHz Jump from 1818 MHz to

TUNE

1893 MHz with Sirenza 1843T VCO

Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to

1893 MHz (V

= 1.8 V to 3.7 V with Sirenza 1843T VCO)

TUNE

Figure 13. V

Settling Transient for a 75 MHz Jump Down from 1893 MHz

TUNE

to 1818 MHz (Bottom of Allowed Tuning Range) with Sirenza 1843T VCO

Figure 14. Phase Settling Transient for a 75 MHz Jump Down from 1893 MHz

to 1818 MHz (V

= 3.7 V to 1.8 V with Sirenza 1843T VCO)

TUNE

Figure 12. Differential Charge Pump Output Compliance Range and

Charge Pump Mismatch with V

1 = VP2 = 5 V

P

Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential

Amplifier Power Supply Voltage

Rev. B | Page 9 of 28

ADF4196 Data Sheet

09450-042

FREQUENCY ( Hz )

NOISE (nV/ Hz)

1k 10k 100k 1M

1

10

100

1000

10M

7nV/ Hz @ 20kHz

09450-014

DRAIN VOLTAGE (V)

R

ON

(Ω)

0 1 2 3 4

0

100

70

90

80

60

50

40
30

20

10

5

+85°C

SW3

–40°C

+25°C

–40°C

+25°C

+85°C

SW1,

SW2

TUNING VOLTAGE RANGE

09450-044

PHASE CODE

PHASE DETECTOR OUTPUT (V)

0

0

1.8

1.5

1.2

0.9

0.6

0.3

13011710491786552392613

MEASURED USING AD8 3 02 PHAS E DETE CTOR
Y-AXIS SCALE: 10m V/DEGREE
RF = 1880MHz, PFD = 26MHz, MOD = 130
X-AXIS SCALE: 2. 7 7° /STEP

09450-045

INTERVAL BETWEEN R0 WRITES SHOULD BE A MULTIPLE OF MOD
REFERENCE CYCLES (5µs) FOR COHERENT PHASE MEASUREMENTS

SIGNAL

GENERATOR

OSCILLOSCOPE

ADF4193

EVAL BOARD

104MHz

5dBm

10MHz

EXT REF

1880MHz

1805MHz 1880MHz

RF

OUT

REF

IN

SIGNAL

GENERATOR

INPA

AD8302

EVB

VPHS

INPB

Figure 16. Voltage Noise Density Measured at the

Differential Amplifier Output

Figure 17. On Resistance of the SW1, SW2, and SW3 Loop Filter Switches

Figure 18. Detected RF Output Phase for Phase Code Sweep from 0 to MOD

Figure 19. Test Setup for Phase Lock Time Measurements

Rev. B | Page 10 of 28

Data Sheet ADF4196

09450-016

BUFFER

TO R COUNT E R

REF

IN

100kΩ

NC

SW2

SW3

NO

NC

SW1

POWER-DOWN

CONTROL

09450-017

BIAS

GENERATOR

1.6V

AGND

AV

DD

500Ω 500Ω

RF

IN–

RF

IN+

09450-018

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRAC

VALUE

MOD

VALUE

INT

VALUE

RF N DIVIDE R N = INT + FRAC/ M OD

FROM RF

INPUT STAGE

TO PFD

N COUNTER

THEORY OF OPERATION

GENERAL DESCRIPTION

The ADF4196 is targeted at GSM base station requirements,
specifically to eliminate the need for ping-pong solutions.
It can also be used in pulse Doppler radar applications. The

ADF4196 works on the basis of fast lock, using a wide loop

bandwidth during a frequency change and narrowing the loop
bandwidth when frequency lock is achieved.

Widening the loop bandwidth is achieved by increasing the
charge pump current. To maintain stability with the changing
charge pump current, the ADF4196 includes switches that
change the loop filter component values.

The narrow loop bandwidth ensures that phase noise and spur
specifications are met. A differential charge pump and loop filter
topology ensure that the fast lock time benefit obtained from
widening the loop bandwidth is maintained when the loop is
restored to narrow bandwidth mode for normal operation.

REFERENCE INPUT

The reference input stage is shown in Figure 20. Switch SW1
and Switch SW2 are normally closed, and Switch SW3 is
normally open. During power-down, SW3 is closed, and SW1
and SW2 are opened to ensure that there is no loading of the
REF

pin. The falling edge of REFIN is the active edge at the

IN

positive edge triggered PFD.

RF INPUT STAGE

The RF input stage is shown in Figure 21. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the prescaler. Two prescaler options are available:
4/5 and 8/9. Select the 8/9 prescaler for N divider values that
are greater than 80.

Figure 21. RF Input Stage

RF N Divider

The RF N divider allows a fractional division ratio in the PLL
feedback path. The integer and fractional parts of the division
are programmed using separate registers, as shown in Figure 22
and described in the INT, FRAC, and MOD Relationship section.
Integer division ratios from 26 to 511 are allowed, and a third­order Σ-Δ modulator interpolates the fractional value between
the integer steps.

Figure 20. Reference Input Stage

R Counter and Doubler

The 4-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the PFD.
A toggle flip-flop can be inserted after the R counter to provide
an additional divide-by-2. Using this option has the added
advantage of ensuring that the PFD reference clock has a 50/50
mark-to-space ratio. This ratio gives the maximum separation
between the fast lock timer clock, which is generated off the
falling edge of the PFD reference, and the rising edge, which is
the active edge in the PFD. It is recommended that this toggle
flip-flop be enabled for all even R divide values that are greater
than 2. The flip-flop must be enabled if dividing down a REF
frequency that is greater than 120 MHz.

An optional doubler before the 4-bit R counter can be used for
low REF
options, reference division ratios from 0.5 to 30 between REF
and the PFD are possible.

frequencies, up to 20 MHz. With these programmable

IN

IN

IN

Rev. B | Page 11 of 28

Figure 22. Fractional-N RF Divider

INT, FRAC, and MOD Relationship

The INT, FRAC, and MOD values, programmed through the
serial interface, make it possible to generate RF output frequencies
that are spaced by fractions of the PFD reference frequency.
The N divider value, shown inside the brackets of the following
equation for the RF VCO frequency (RF

), is composed of an

OUT

integer part (INT) and a fractional part (FRAC/MOD).

RF

= f

OUT

× [INT + (FRAC/MOD)] (1)

PFD

where:

is the output frequency of the external VCO.

RF

OUT

f

is the PFD reference frequency.

PFD

The value of MOD is chosen to give the desired channel step
with the available reference frequenc y. Then, program the INT
and FRAC words for the desired RF output frequency. See the
Worked Example section for more information.

ADF4196 Data Sheet

09450-019

CLR

QD

R DIVIDER

N DIVIDER

CHARGE

PUMP

ARRAY

[64:1]

CMFB

EN[64:1]

CLR

QD

CP

OUT+

CP

OUT–

09450-035

V

BIAS

P

P P

N N

UP DOWN

DOWN UP

V

BIAS

N

CP

OUT+

C

POUT–

09450-036

SW1/SW2
TIMEOUT

COUNTER

SW3

TIMEOUT

COUNTER

I

CP

TIMEOUT

COUNTER

EN[64:1]

÷4

START

f

PFD

SW3

A

OUT

SW2

SW

GND

SW1

WRITE

TO R0

CHARGE PUMP
ENABLE LOGIC

PFD AND CHARGE PUMP

The PFD takes inputs from the R divider and N divider and
produces up and down outputs with a pulse width difference
that is proportional to the phase difference between the inputs.
The charge pump outputs a net up or down current pulse of
a width that is equal to this difference, to pump up or pump down
the voltage that is integrated into the loop filter, which in turn
increases or decreases the VCO output frequency. If the N divider
phase lags the R divider phase, a net up-current pulse is produced
that increases the VCO frequency (and, thus, the phase). If the
N divider phase leads the R divider edge, a net down-current
pulse is produced to reduce the VCO frequency and phase.
Figure 23 is a simplified schematic of the PFD and charge pump.
The charge pump is made up of an array of 64 identical cells,
each of which is fully differential. All 64 cells are active during
fast lock, and only one cell is active during normal operation.

Because a single-ended control voltage is required to tune the VCO,
an on-chip differential-to-single-ended amplifier is provided for
this purpose. In addition, because the phase-locked loop controls
only the differential voltage generated across the charge pump
outputs, an internal common-mode feedback (CMFB) loop
biases the charge pump outputs at a common-mode voltage of
approximately 2 V.

Figure 23. PFD and Differential Charge Pump Simplified Schematic

DIFFERENTIAL CHARGE PUMP

The charge pump cell has a fully differential design for best up­to-down current matching (see Figure 24). Good matching is
essential to minimize the phase offset created when switching
the charge pump current from its high value (in fast lock mode)
to its nominal value (in normal mode).

To pump up, the up switches are on, and the PMOS current sources
out through CP
loop filter capacitors that are connected to CP
NMOS current sink on CP
external loop filter capacitors that are connected to CP
Therefore, the differential voltage between CP
increases.

To pump down, PMOS current sources out through CP
NMOS current sinks in through CP
(CP

, CP

OUT+

OUT−

, which increases the voltage on the external

OUT+

) differential voltage. The charge pump up/down

OUT+

decreases the voltage on the

OUT−

OUT+

, which decreases the

OUT+

. Similarly, the

.

OUT−

and CP

OUT−

and

OUT−

Rev. B | Page 12 of 28

matching is improved by an order of magnitude over the
conventional single-ended charge pump that depends on the
matching of two different device types. The up/down matching
in this structure depends on how a PMOS matches a PMOS,
and how an NMOS matches an NMOS.

Figure 24. Differential Charge Pump Cell

with External Loop Filter Components

FAST LOCK TIMEOUT COUNTERS

Timeout counters, clocked at one-quarter of the PFD reference
frequency, are provided to precisely control the fast locking
operation (see Figure 25). When a new frequency is programmed,
the fast lock timers start and the PLL locks into wide bandwidth
mode with the 64 identical 100 µA charge pump cells active (for a
total of 6.4 mA).

When the I
reduced to 1× by deselecting cells in binary steps over the next
six timer clock cycles, until only one 100 µA cell is active. The
switching of the charge pump current, from 6.4 mA to 100 µA,
equates to an 8-to-1 change in loop bandwidth; when this happens,
the loop filter must be changed to ensure stability. The SW1,
SW2, and SW3 switches change the loop filter.

The applications circuit shown in Figure 37 shows how the
switches can be used to reconfigure the loop filter time constants.
They close to short out external loop filter resistors during fast lock
and open when their counters time out to restore the filter time
constants to their normal values for the 100 µA charge pump
current. Because it takes six timer clock cycles to reduce the
charge pump current to 1×, it is recommended that both switch
timers be pro-grammed to the value of the I

counter times out, the charge pump current is

CP

timer plus 7.

CP

Figure 25. Fast Lock Timeout Counters

Data Sheet ADF4196

09450-020

AIN–

A

OUT

AIN+

CMR

V

P

3

C EXT =

0.1µF

20kΩ

30kΩ

500Ω 500Ω

500Ω 500Ω

09450-021

R DIVIDER OUTPUT
N DIVIDER OUTPUT

SERIAL DATA OUTPUT

D

GND

DV

DD

CONTROLMUX

MUX

OUT

LOGIC LOW

THREE-STATE OUTPUT

TIMER OUTPUTS

DIGITAL LOCK DETECT

LOGIC HIGH

NOTE:

1. NOT ALL MUX

OUT

MODES THAT ARE S HOWN REFER TO THE

MUX REGISTER.

0 1 1

Function

R3

DIFFERENTIAL AMPLIFIER

The internal, low noise, differential-to-single-ended amplifier
converts the differential charge pump output to a single-ended
control voltage for the tuning port of the VCO. Figure 26 shows
a simplified schematic of the differential amplifier. The output
voltage is equal to the differential voltage, offset by the voltage
on the CMR pin, according to the following equation:

V

= (V

AOUT

The CMR offset voltage is internally biased to three-fifths of
V

3, the differential amplifier power supply voltage, as shown in

P

Figure 26. Connect a 0.1 µF capacitor to the ground plane from
the CMR pin to roll off the thermal noise of the biasing resistors.

As shown in Figure 15, the differential amplifier output voltage
behaves according to Equation 2 over a 4 V range from ~1.2 V
minimum up to V
is guaranteed over a tuning voltage range from 1.8 V up to
V

3 − 0.8 V only. This range allows sufficient room for overshoot

P

in the PLL frequency settling transient.

Noise from the differential amplifier is suppressed inside the
PLL loop bandwidth. For loop bandwidths of >20 kHz, the 1/f
noise has a negligible effect on the PLL output phase noise.
Outside the loop bandwidth, the FM noise of the differential
amplifier modulates the VCO. The passive filter network following
the differential amplifier (see Figure 37) suppresses this noise
contribution to below the VCO noise from offsets of 400 kHz
and greater. This network has a negligible effect on lock time
because it is bypassed when SW3 is closed while the loop is
locking.

− V

AIN+

Figure 26. Differential Amplifier Block Diagram

P

) + V

AIN−

3 − 0.3 V maximum. However, fast settling

(2)

CMR

Figure 27. MUX

OUT

Circuit

Lock Detect

MUX

can be programmed to provide a digital lock detect

OUT

signal. Digital lock detect is active high. Its output goes high if
there are 40 successive PFD cycles with an input error of <3 ns.
For reliable lock detect operation with RF frequencies of <2 GHz,
it is recommended that this threshold be increased to 10 ns by
programming Register R6. The digital lock detect goes low again
when a new channel is programmed or when the error at the
PFD input exceeds 30 ns for one or more cycles.

INPUT SHIFT REGISTER

The ADF4196 serial interface includes a 24-bit input shift register.
Data is clocked in, MSB first, on each rising edge of CLK. Data
from the shift register is latched into one of eight control registers,
R0 to R7, on the rising edge of load enable (LE) The destination
register is determined by the state of the three control bits: C3
(DB2), C2 (DB1), and C1 (DB0) in the shift register. DB2, DB1,
and DB0 are the three LSBs, as shown in the timing diagram
in Figure 2. The truth table for these bits is shown in Tabl e 6.
Figure 28 shows a summary of how the registers are programmed.

Table 6. C3, C2, and C1 Truth Table

Control Bits

C3 (DB2) C2 (DB1) C1 (DB0) Register Name Register

0 0 0 FRAC/INT R0
0 0 1 MOD/R R1
0 1 0 Phase R2

MUX

MUX

The output multiplexer on the ADF4196 allows the user to
access various internal points on the chip. The state of MUX
is controlled by Bits[M4:M1] in the mux register. Figure 35
shows the full truth table; see Figure 27 for a block diagram
of the MUX

AND LOCK DETECT

OUT

Control

OUT

circuit.

OUT

1 0 0 Charge pump R4
1 0 1 Power-down R5
1 1 0 Mux R6

OUT

1 1 1 Test mode R7

Rev. B | Page 13 of 28

ADF4196 Data Sheet

09450-022

DB23F5DB22

F4

DB210DB20

F2

DB19

F1

DB18R4DB17

R3

DB16R2DB15R1DB14

M12

DB13

M11

DB12

M10

DB11M9DB10M8DB9M7DB8

M6

DB7M5DB6

M4

DB5M3DB4

M2

DB3M1DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (1)

DBB DBB DBB DBB DBB

4-BIT RF R
COUNTER

CP ADJ

REF/2

RESERVED

PRESCALER

DOUBLER

ENABLE

12-BIT MODULUS

CONTROL

BITS

MOD/R REGISTER (R1)

DB150DB14

P12

DB13

P11

DB12

P10

DB11P9DB10P8DB9P7DB8P6DB7P5DB6

P4

DB5P3DB4P2DB3P1DB2

C3 (0)

DB1

C2 (1)

DB0

C1 (0)

DBB

RESERVED

12-BIT PHASE

CONTROL

BITS

PHASE REGISTER (R2)

DB150DB140DB13

0

DB120DB110DB100DB90DB8

0

DB70DB61DB5

F3

DB41DB3F1DB2

C3 (0)

DB1

C2 (1)

DB0

C1 (1)

PFD

POLARITY

RESERVED

CPO GND

RESERVED

CONTROL

BITS

FUNCTION REGISTER (R3)

DB15

M13

DB14

M12

DB13

M11

DB12

M10

DB110DB100DB90DB80DB71DB6

M4

DB5M3DB4M2DB3M1DB2

C3 (1)

DB1

C2 (1)

DB0

C1 (0)

RESERVED MUX

OUT

CONTROL

BITS

SIGMA-DELTA

AND

LOCK DETECT MODES

MUX REGISTER (R6)

DB150DB140DB130DB120DB110DB100DB90DB80DB70DB60DB50DB40DB30DB2

C3 (1)

DB1

C2 (1)

DB0

C1 (1)

RESERVED

CONTROL

BITS

TEST MO DE REGISTER (R7)

DB7F5DB6F4DB5F3DB4F2DB3

F1

DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (1)

COUNTER

RESET

CP

3-STATE

PD

CHARGE

PUMP

PD

DIFF AMP

CONTROL

BITS

POWER-DOWN REGISTER (R5)

DB230DB220DB21

0

DB20

0

DB190DB180DB17

0

DB160DB150DB141DB13

C9

DB12C8DB11

C7

DB10C6DB9

C5

DB8C4DB7C3DB6C2DB5

C1

DB4F2DB3

F1

DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (0)

9-BIT TIMEOUT COUNTERRESERVED

CONTROL

BITS

TIMER

SELECT

CHARGE PUMP REGISTER (R4)

DBB = DOUBLE BUFFERED BIT( S )

DB23N9DB22

N8

DB21N7DB20

N6

DB19N5DB18N4DB17N3DB16

N2

DB15N1DB14

F12

DB13

F11

DB12

F10

DB11F9DB10

F8

DB9F7DB8F6DB7

F5

DB6F4DB5

F3

DB4

F2

DB3F1DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (0)

9-BIT RF I NT VALUE

12-BIT RF F RAC V ALUE

CONTROL

BITS

FRAC/INT REGISTER (R0)

REGISTER MAP

Figure 28. Bit Maps for Register R0 to Register R7

Rev. B | Page 14 of 28

Data Sheet ADF4196

09450-023

DB23N9DB22N8DB21N7DB20N6DB19N5DB18N4DB17N3DB16N2DB15N1DB14

F12

DB13

F11

DB12

F10

DB11F9DB10F8DB9F7DB8F6DB7F5DB6F4DB5F3DB4F2DB3F1DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (0)

9-BIT RF INT VALUE 12-BIT RF FRAC VALUE

CONTROL

BITS

F12
0

0
0
0
.
.
.
1
1
1
1

F11
0

0
0
0
.
.
.
1
1
1
1

F10
0

0
0
0
.
.
.
1
1
1
1

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

F3
0

0
0
0
.
.
.
1
1
1
1

F2
0

0
1
1
.
.
.
0
0
1
1

F1
0

1
0
1
.
.
.
0
1
0
1

FRACTIO NAL VALUE (FRAC)
0

1
2
3
.
.
.
4092
4093
4094
4095

N8
0

.
.
.
1

N7
0

.
.
.
1

N9
0

.
.
.
1

N6
0

.
.
.
1

N5
1

.
.
.
1

N4
1

.
.
.
1

N3
0

.
.
.
1

N2
1

.
.
.
1

N1
0

.
.
.
1

INTEGER VALUE (INT)
26

.
.
.
511

0 ≤ FRAC < MOD

FRAC/INT REGISTER (R0) LATCH MAP

R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the PFD cycle following a write to R0,
the N divider section is updated with the new INT and FRAC
values, and the PLL automatically enters fast lock mode. The
charge pump current is increased to its maximum value and
remains at this value until the I

timeout counter times out;

CP

and the SW1, SW2, and SW3 switches close and remain closed
until the SW1/SW2 and SW3 timeout counters time out.

After all the registers are programmed during the initialization
sequence (see Tab l e 9), a new channel can be programmed
by performing a write to R0. However, as described in the
Programming the ADF4196 section, it may also be desirable
to program the R1 and R2 register settings on a channel-by­channel basis. These settings are double buffered by the write to
Register R0. This means that, although the data is loaded through
the serial interface on the respective R1 and R2 write cycles, the
synthesizer is not updated with their data until the next write to
Register R0.

Figure 29. Bit Map for Register R0

Control Bits

To select R0, the FRAC/INT register, the three LSBs (C3, C2,
and C1) should be set to 0, 0, 0.

9-Bit RF INT Value

Bits[DB23:DB15] set the INT value, which determines the
integer part of the feedback division factor. All integer values
from 26 to 511 are allowed (see the Worked Example section).

12-Bit RF FRAC Value

Bits[DB14:DB3] set the numerator of the fraction that is input
to the Σ-Δ modulator. This fraction, along with INT, specifies
the new frequency channel that the synthesizer locks to, as shown
in the Worked Example section. FRAC values from 0 to MOD − 1
cover channels over a frequency range that is equal to the PFD
reference frequency.

Rev. B | Page 15 of 28

ADF4196 Data Sheet

09450-024

DB23F5DB22F4DB210DB20F2DB19F1DB18R4DB17

R3

DB16R2DB15R1DB14

M12

DB13

M11

DB12

M10

DB11M9DB10M8DB9M7DB8M6DB7M5DB6M4DB5M3DB4M2DB3M1DB2

C3 (0)

DB1

C2 (0)

DB0

C1 (1)

4-BIT RF

R COUNTER

CP

ADJ

REF/2

RESERVED

PRESCALER

DOUBLER

ENABLE

12-BIT MO DULUS

CONTROL

BITS

01NOMINAL

ADJUSTED

CP ADJF5

01DISABLED

ENABLED

REF/2F4

0
1

F2

4/5
8/9

PRESCALER

0
1

F1

DOUBLER DIS ABLED
DOUBLER ENABL E D

DOUBLER ENABL E

M12
0

0
0
.
.
.
1
1
1
1

M11
0

0
0
.
.
.
1
1
1
1

M10
0

0
0
.
.
.
1
1
1
1

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

M3
1

1
1
.
.
.
1
1
1
1

M2
0

1
1
.
.
.
0
0
1
1

M1
1

0
1
.
.
.
0
1
0
1

INTERPO LATOR MODULUS VALUE (M OD)
13

14
15
.
.
.
4092
4093
4094
4095

R4
0

0
0
0
.
.
.
1
1
1
1

R3
0

0
0
1
.
.
.
1
1
1
1

R2
0

1
1
0
.
.
.
0
0
1
1

R1
1

0
1
0
.
.
.
0
1
0
1

RF R COUNTER DIVIDE RATI O
1

2
3
4
.
.
.
12
13
14
15

MOD/R REGISTER (R1) LATCH MAP

R1, the MOD/R register, sets the PFD reference frequency and
the channel step size, which is determined by the PFD frequency
divided by the fractional modulus. Note that the 12-bit modulus,
the 4-bit RF R counter, the doubler enable bits, REF/2, and
CP ADJ are double buffered. They do not take effect until the
next write to R0 (the FRAC/INT register) is complete.

Control Bits

Register R1 is selected with C3, C2, and C1 set to 0, 0, 1.

CP ADJ

When the CP ADJ bit is set to 1, the charge pump current is
scaled up 25% from its nominal value on the next write to R0.
When this bit is set to 0, the charge pump current remains at its
nominal value on the next write to R0. See the Programming
the ADF4196 section for more information on how this feature
can be used.

REF/2

Setting the REF/2 bit to 1 inserts a divide-by-2 toggle flip-flop
between the R counter and the PFD, which extends the maximum
REF

input rate.

IN

Reserved Bit

The reserved bit, DB21, must be set to 0.

Figure 30. Bit Map for Register R1

Prescaler (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with INT, FRAC,
and MOD, determine the overall division ratio from RF

to the

IN

PFD input. Operating at CML levels, it takes the clock from the
RF input stage and divides it down for the counters. It is based on
a synchronous 4/5 core. When set to 4/5, the maximum RF
frequency allowed is 3 GHz. Therefore, when operating the

ADF4196 above 3 GHz, the prescaler must be set to 8/9. The

prescaler limits the INT value. If P = 4/5, then N
If P = 8/9, N

MIN

= 80.

Doubler Enable

MIN

= 26.

Setting the doubler enabler bit to 1 inserts a frequency doubler
between REF

and the 4-bit RF R counter. Setting this bit to 0

IN

bypasses the doubler.

4-Bit RF R Counter

The 4-bit RF R counter allows the REFIN frequency to be divided
down to produce the reference clock to the PFD. All integer
values from 1 to 15 are allowed (see the Worked Example section).

12-Bit Modulus

For a given PFD reference frequenc y, the fractional denominator
or modulus sets the channel step resolution at the RF output. All

Rev. B | Page 16 of 28

integer values from 13 to 4095 are allowed. See the Programming
the ADF4196 section for a Worked Example and guidelines for
selecting the value of MOD.

Data Sheet ADF4196

09450-025

DB15

0

DB14

P12

DB13

P11

DB12

P10

DB11

P9

DB10

P8

DB9

P7

DB8

P6

DB7

P5

DB6

P4

DB5

P3

DB4

P2

DB3

P1

DB2

C3 (0)

DB1

C2 (1)

DB0

C1 (0)

RESERVED

12-BIT PHASE

CONTROL

BITS

P12
0

0
0
.
.
.
1
1
1
1

P11
0

0
0
.
.
.
1
1
1
1

P10
0

0
0
.
.
.
1
1
1
1

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

P3
0

0
0
.
.
.
1
1
1
1

P2
0

0
1
.
.
.
0
0
1
1

P1
0

1
0
.
.
.
0
1
0
1

PHASE VALUE

1

0
1
2
.
.
.
4092
4093
4094
4095

1

0 ≤ PHASE VALUE < MOD

PHASE REGISTER (R2) BIT LATCH MAP

Figure 31. Bit Map for Register R2

R2, the phase register, is used to program the phase of the VCO
output signal.

Control Bits

Register R2 is selected with C3, C2, and C1 set to 0, 1, 0.

12-Bit Phase

The 12-bit phase word sets the seed value of the Σ-Δ modulator.
It can be programmed to any integer value from 0 to MOD, where
MOD is the modulus value that is programmed in Register R1,
Bits[DB14:DB3]. As the phase word is swept from 0 to MOD,
the phase of the VCO output sweeps over a 360° range in steps
of 360°/MOD.

Note that the phase bits are double buffered; they do not take
effect until the load enable of the next write to R0 (the FRAC/INT
register). Thus, to change the phase of the VCO output frequency,
it is necessary to rewrite the INT and FRAC values to Register R0
following the write to Register R2.

The output of a fractional-N PLL can settle to any one of the
MOD possible phase offsets with respect to the reference, where
MOD is the fractional modulus.

To keep the output at the same phase offset with respect to the
reference, each time that particular output frequency is pro­grammed, the interval between writes to Register R0 must be an
integer multiple of MOD reference cycles.

To keep the outputs of two ADF4196-based synthesizers phase
coherent with each other (but not necessarily with the reference
they have in common), the write to Register R0 on both chips
must be performed during the same reference cycle. In this
case, the interval between the R0 writes does not need to be
an integer multiple of MOD cycles.

Reserved Bit

Set the reserved bit, DB15, to 0.

Rev. B | Page 17 of 28

ADF4196 Data Sheet

09450-026

DB150DB140DB13

0

DB12

0

DB110DB10

0

DB90DB80DB70DB6

1

DB5F3DB4

1

DB3F1DB2

C3 (0)

DB1

C2 (1)

DB0

C1 (1)

PFD

POLARITY

RESERVED

CPO GND

RESERVED

CONTROL

BITS

0
1

F1

NEGATIVE
POSITIVE

PFD POLARITY

0
1

F3

CPO/CPO GND
NORMAL

CPO GND

FUNCTION REGISTER (R3) LATCH MAP

Figure 32. Bit Map for Register R3

R3, the function register, needs to be programmed only during
the initialization sequence (see Tab l e 9).

Control Bits

Register R3 is selected with C3, C2, and C1 set to 0, 1, 1.

CPO GND

When the CPO GND bit is low, the charge pump outputs are
internally pulled to ground. This is invoked during the initiali­zation sequence to discharge the loop filter capacitors. For
normal operation, this bit should be set to 1.

PFD Polarity

Set the PFD polarity bit to 1 for positive polarity, and set it to 0
for negative polarity.

Reserved Bits

Program the DB15 to DB6 reserved bits to a hexadecimal code of
0x001, and set the DB4 reserved bit to 1.

Rev. B | Page 18 of 28

09450-027

DB23

0

DB220DB210DB20

0

DB190DB180DB170DB160DB150DB141DB13C9DB12C8DB11C7DB10C6DB9C5DB8C4DB7C3DB6C2DB5C1DB4

F2

DB3F1DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (0)

9-BIT TIMEOUT COUNTERRESERVED

CONTROL

BITS

TIMER

SELECT

0
0
1
1

F2

0
1
0
1

F1

SW1/SW2
SW3
I

CP

NOT USED

TIMER SELECT

C9
0

0
0
0
.
.
.
1
1
1
1

C8
0

0
0
0
.
.
.
1
1
1
1

C7
0

0
0
0
.
.
.
1
1
1
1

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

..........

C3
0

0
0
0
.
.
.
1
1
1
1

C2
0

0
1
1
.
.
.
0
0
1
1

C1
0

1
0
1
.
.
.
0
1
0
1

TIMEOUT COUNTER
0

1
2
3
.
.
.
508
509
510
511

xPFD CYCLES
0

4
8
12
.
.
.
2032
2036
2040
2044

DELAY µs

1

0

0.15

0.30

0.46
.
.
.

78.15

78.30

78.46

78.61

1

DELAY WITH 26MHz PFD

Data Sheet ADF4196

CHARGE PUMP REGISTER (R4) LATCH MAP

Figure 33. Bit Map for Register R4

R4, the charge pump register, is used for programming the timers
for loop filter switches. These switches help maintain the stability
of the loop filter after boosting the charge pump current.

Control Bits

Register R4 is selected with C3, C2, and C1 (Bits[DB2:DB0]) set
to 1, 0, 0.

Reserved Bits

For normal operation, set the DB23 to DB14 reserved bits to
a hexadecimal code of 0x001.

9-Bit Timeout Counter

These bits are used to program the fast lock timeout counters.
The counters are clocked at one-quarter the PFD reference
frequency; therefore, their time delay scales with the PFD
frequency according to the following equation:

Delay(s) = (Timeout Counter Value × 4)/(PFD Frequency)

For example, if 35 is loaded with timer select = 00, with
a 13 MHz PFD, SW1 and SW2 switch after the following:

(35 × 4)/13 MHz = 10.8 µs

Timer Select

The two timer select bits select the timeout counter that is to
be programmed. Note that setting up the ADF4196 for correct
operation requires setup of these three timeout counters: I

,

CP

SW1/SW2, and SW3. Therefore, three writes to this register
are required in the initialization sequence. Ta b le 7 shows
example values for a GSM Tx synthesizer with a 60 kHz final
loop bandwidth. See the Applications Information section for
more information.

Table 7. Recommended Values for a GSM Tx LO

Timer
Select

Timeout
Counter

Value

Time (µs) with
PFD = 13 MHz

10 ICP 28 8.6
01 SW3 35 10.8
00 SW1/SW2 35 10.8

On each write to R0, the timeout counters start. Switch SW3 closes
until the SW3 counter times out. Similarly, the SW1 and SW2
switches close until the SW1/SW2 counter times out. When the
I

counter times out, the charge pump current is ramped down

CP

from 64× to 1× in six binary steps. It is recommended that the
SW1/SW2 and SW3 timeout counter values be set equal to the
I

timeout counter value plus 7, as in the example shown in

CP

Tabl e 7.

Rev. B | Page 19 of 28

ADF4196 Data Sheet

09450-028

DB7F5DB6

F4

DB5

F3

DB4

F2

DB3

F1

DB2

C3 (1)

DB1

C2 (0)

DB0

C1 (1)

COUNTER

RESET

CP

3-STATE

PD

CHARGE

PUMP

CONTROL

BITS

PD

DIFF AMP

0
1

F4

0
1

F5

DISABLED
ENABLED

DIFF AMP
POWER-DOWN

0
1

F2

NORMAL OPERATION
3-STATE E NABLED

CHARGE PUMP
3-STATE

0
1

F1

NORMAL OPERATION
COUNTER RES E T

COUNTER RES E T

0
1

F3

DISABLED
ENABLED

CHARGE PUMP
POWER-DOWN

POWER-DOWN REGISTER (R5) BIT MAP

R5, the power-down register, can be used to power down the PLL
and differential amplifier sections. After power is initially applied,
Register R5 must be programmed to clear the power-down bits.
Then, before the ADF4196 comes out of power-down, the R2,
R1, and R0 registers must be programmed.

Control Bits

Register R5 is selected with C3, C2, and C1 set to 1, 0, 1.

Power-Down Differential Amplifier

When the DB7 and DB6 bits are set to 1, the differential
amplifier is put into power-down. When DB7 and DB6 are set
to 0, normal operation resumes.

Power-Down Charge Pump

Setting Bit DB5 to 1 activates a charge pump power-down, and
the following events occur:

• All active dc current paths are removed, except for the

differential amplifier.

• The R and N divider counters are forced to their load state

conditions.

Figure 34. Bit Map for Register R5

• The charge pump is powered down with its outputs in

three-state mode.

• The digital lock detect circuitry is reset.

• The RF

• The reference input buffer circuitry is disabled.

• The serial interface remains active and capable of loading

and latching data.

For normal operation, set Bit DB5 to 0, followed by a write to R0.

CP Three-State

When the CP three-state bit is set to 1, the charge pump outputs
enter three-state. Setting the CP three-state bit to 0 enables the
charge pump outputs.

Counter Reset

When the counter reset bit is set to 1, the counters are held in reset.
For normal operation, set this bit to 0, followed by a write to R0.

input is debiased.

IN

Rev. B | Page 20 of 28

Data Sheet ADF4196

09450-029

DB15

M13

DB14

M12

DB13

M11

DB12

M10

DB11

0

DB10

0

DB9

0

DB8

0

DB7

1

DB6

M4

DB5

M3

DB4

M2

DB3

M1

DB2

C3 (1)

DB1

C2 (1)

DB0

C1 (0)

RESERVED MUX

OUT

CONTROL

BITS

SIGMA-DELTA

AND

LOCK DETE CT MODES

0
1

1

M10

0
1

0

M11

0
0

0

ALL OTHER STATES

M12

0
0

1

M13

INIT STATE, DITHER OFF,
3ns LOCK DETECT THRESHOLD
DITHER ON
10ns LOCK DETECT THRESHOLD
RESERVED

SIGMA-DELTA MODES

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

M4

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

M3

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

M2

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

M1

3-STATE
DIGITAL LOCK DETECT
N DIVIDER O UTPUT
LOGIC HIGH
R DIVIDER O UTPUT
RESERVED
SERIAL DAT A OUTPUT
LOGIC LOW
R DIVIDER/ 2 OUTPUT
N DIVIDER/ 2 OUTPUT
RESERVED
RESERVED
I

CP

TIMEOUT SIGNAL
SW1/SW2 TIMEOUT SIGNAL
SW3 TIMEOUT SIGNAL
RESERVED

MUX

OUT

MUX REGISTER (R6) LATCH MAP AND TRUTH TABLE

R6, the mux register, is used to program MUX
Σ-Δ and lock detect modes.

Control Bits

Register R6 is selected with C3, C2, and C1 set to 1, 1, 0.

Σ-Δ and Lock Detect Modes

Bit DB15 to Bit DB12 are used to reconfigure certain PLL
operating modes. In the initialization sequence after power is
applied to the chip, the four bits must first be programmed to
all zeros. This initializes the PLL to a known state with dither
off in the Σ-Δ modulator and a 3 ns PFD error threshold in the
lock detect circuit.

To turn on dither in the Σ-Δ modulator, an additional write should
be made to Register R6 to program Bits[DB15:DB12] = 0011.
However, for lowest noise operation, it is best to leave dither off.

To change the lock detect threshold from 3 ns to 10 ns, perform
a separate write to R6 to program Bits[DB15:DB12] = 1001.
This separate write is needed for reliable lock detect operation
when the RF frequency is <2 GHz.

A write to R6 that programs Bits[DB15:DB12] = 0000 returns
operation to the default state with both dither off and a 3 ns
lock detect threshold.

Figure 35. Bit Map and MUX

, as well as

OUT

Truth Table for Register R6

OUT

Reserved Bits

For normal operation, the reserved bits (Bits[DB11:DB7]) must
be set to 00001.

MUX

Modes

OUT

These bits control the on-chip multiplexer, Pin 16 (see Figure 35
for the truth table). This pin is useful for diagnosis because it
allows the user to look at various internal points of the chip,
such as the R divider and the INT divider outputs.

In addition, it is possible to monitor the programmed timeout
counter intervals on MUX

. For example, if the ICP timeout

OUT

counter is programmed to 65 (with a 26 MHz PFD), then
following the next write to R0, a pulse width of 10 µs is
observed on the MUX

Digital lock detect is available via the MUX

OUT

pin.

OUT

pin.

Rev. B | Page 21 of 28

ADF4196 Data Sheet

PROGRAMMING THE ADF4196

The ADF4196 can synthesize output frequencies with a channel
step or resolution that is a fraction of the input reference fre­quency. For a given input reference frequency and a desired
output frequency step, the first choice to make is the PFD
reference frequency and the MOD value. After these are chosen,
the desired output frequency channels are set by programming
the INT and FRAC values.

WORKED EXAMPLE

In this example of a GSM900 Rx system, the RF output frequencies
must be generated with channel steps of 200 kHz. A reference
frequency input (REF

) of 104 MHz is available. The R divider

IN

setting that determines the PFD reference is shown in Equation 3.

f

= REFIN × [(1 + D)/(R × (1 + T))] (3)

PFD

where:

is the input reference frequency.

REF

IN

D is the doubler enable bit (0 or 1).
R is the 4-bit R counter code (1 to 15).
T is the REF/2 bit (0 or 1).

The maximum PFD reference frequency of 26 MHz is chosen,
and the following settings are programmed to give an R divider
value of 4:

• Doubler enable = 0

• R = 2

• REF/2 = 1

Next, the modulus is chosen to allow fractional steps of 200 kHz:

MOD = 26 MHz/200 kHz = 130 (4)

When the channel step is defined, Equation 5 shows how output
frequency channels are programmed.

RF

= [INT + (FRAC/MOD)] × f

OUT

(5)

PFD

where:

RF

is the desired RF output frequency.

OUT

INT is the integer part of the division.
FRAC is the numerator part of the fractional division.
MOD is the modulus or denominator part of the fractional

division.

Thus, the frequency channel at 962.4 MHz is synthesized by
programming the following values: INT = 37 and FRAC = 2.

SPUR MECHANISMS

The following sections describe the three different spur
mechanisms that arise with a fractional-N synthesizer and how
the ADF4196 can best be programmed to minimize them.

Fractional Spurs

The fractional interpolator in the ADF4196 is a third-order, Σ-Δ
modulator (SDM) with a modulus MOD that is programmable
to any integer value from 13 to 4095. If dither is enabled, the

minimum allowed value of MOD is 50. The SDM is clocked at
the PFD reference rate (f
to be synthesized at a channel step resolution of f

), which allows PLL output frequencies

PFD

/MOD.

PFD

With dither turned off, the quantization noise from the Σ-Δ
modulator appears as fractional spurs. The interval between spurs
is f

/L, where L is the repeat length of the code sequence in

PFD

the digital Σ-Δ modulator. For the third-order modulator used
in the ADF4196, the repeat length depends on the value of
MOD, as shown in

Tabl e 8.

Table 8. Fractional Spurs with Dither Off

Repeat

Condition (Dither Off)

MOD Is Divisible by 2 but Not by 3 2 × MOD Channel step/2
MOD Is Divisible by 3 but Not by 2 3 × MOD Channel step/3
MOD Is Divisible by 6 6 × MOD Channel step/6
All Other Divisors MOD Channel step

Length Spur Interval

With dither enabled, the repeat length is extended to 221 cycles,
regardless of the value of MOD, which makes the quantization
error spectrum look like broadband noise. This can degrade the
in-band phase noise at the PLL output by as much as 10 dB.
Therefore, for lowest noise, dither off is a better choice, particularly
when the final loop bandwidth is low enough to attenuate even
the lowest frequency fractional spur. The wide loop bandwidth
range that is available with the ADF4196 allows the use of dither
in most applications.

Integer Boundary Spurs

Another mechanism for fractional spur creation involves
interactions between the RF VCO frequency and the reference
frequency. When these frequencies are not integer related
(which is the purpose of a fractional-N synthesizer), spur
sidebands appear on the VCO output spectrum at an offset
frequency that corresponds to the beat note or difference
frequency between an integer multiple of the reference and
the VCO frequency.

These spurs are attenuated by the loop filter and are more
noticeable on channels that are close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth (thus, the name integer boundary spurs).

The 8:1 loop bandwidth switching ratio of the ADF4196 makes
it possible to attenuate all spurs to sufficiently low levels for most
applications. The final loop bandwidth can be chosen to ensure
that all spurs are far enough out of band and meet the lock time
requirements with the 8× bandwidth boost.

The programmable modulus and R divider of the ADF4196 can
also be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.

Rev. B | Page 22 of 28

Data Sheet ADF4196

Reference Spurs

Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism
is feedthrough of low levels of on-chip reference switching noise
out of the RF

pins back to the VCO, resulting in reference

IN±

spur levels as high as −90 dBc. These spurs can be suppressed
below −110 dBc by inserting sufficient reverse isolation, for
example, through an RF buffer between the VCO and RF

IN±

pins.
Also, take care in the printed circuit board (PCB) layout to ensure
that the VCO is well separated from the input reference to avoid
a possible feedthrough path on the board.

POWER-UP INITIALIZATION

After applying power to the ADF4196 for the first time, a 14-2530
sequence is recommended, as described in Table 9.

The divider and timer settings used in the example in Table 9 are
for a DCS1800 Tx synthesizer with a 104 MHz REF

The ADF4196 powers up after Step 13 and locks to the pro­grammed channel frequency after Step 14.

Table 9. Power-Up Initialization Sequence A and
Initialization Sequence B

Register/

Step1

Bits

Hex Code Description

1 R5 [7:0] 0xFD Set all power-down bits.
2 R3 [15:0] 0x005B

Wait
10 ms

PFD polarity = 1, ground
CP

/CP

OUT+

OUT−

Allow time for loop filter

capacitors to discharge.
3 R7 [15:0] 0x0007 Clear test modes.
4 R6 [15:0] 0x000E

Initialize PLL modes, digital

lock detect on MUX
5A R6 [15:0] 0x900E

10 ns lock detect threshold,

digital lock detect on MUX
5B R6 [15:0] 0x000E

Add 16 PFD cycle delay after

LE before starting hop to next

frequency.
6 R4 [23:0] 0x004464 SW1/SW2 timer = 10.8 μs.
7 R4 [23:0] 0x00446C SW3 timer = 10.8 μs.
8 R4 [23:0] 0x004394 ICP timer = 8.6 μs.
9 R2 [15:0] 0x00D2 Phase = 26.
10 R1 [23:0] 0x520209

8/9 prescaler, doubler disabled,

R = 4, toggle FF on, MOD = 65.
11 R0 [23:0] 0x480140

INT = 144, FRAC = 40 for

1880 MHz output frequency.
12 R3 [15:0] 0x007B

PFD polarity = 1, release

+/CP

CP

OUT

OUT−

13 R5 [7:0] 0x05 Clear all power-down bits.
14 R0 [23:0] 0x480140

INT = 144, FRAC = 40 for

1880 MHz output frequency.

1

Initialization Sequence A includes Step 5A and omits Step 5B; Initialization

Sequence B includes Step 5B and omits Step 5A.

IN

.

.

frequency.

.

OUT

.

OUT

Two initialization sequences are available for the ADF4196:
Initialization Sequence A and Initialization Sequence B. One or
the other must be selected. Initialization Sequence A consists of
Step 1 through Step 14 in Table 9, including Step 5A (but not
Step 5B). (For Initialization Sequence B, Step 5A is replaced by
Step 5B.) In Initialization Sequence A, the frequency hop starts
immediately after the rising edge of LE, whereas in Initialization
Sequence B, the ADF4196 waits 16 PFD cycles and then starts the
hop. Initialization Sequence B reduces the overshoot of a
frequency jump, but the start of a jump is delayed by 16 PFD
cycles. Figure 36 shows this phenomenon.

LE

5.5
INITIALIZATION SEQUENCE A

5.0

4.5

4.0

(V)

TUNE

3.5

V

3.0

2.5

2.0

Figure 36. Frequency Jumps for Initialization Sequence A and

INITIALIZATION SEQUENCE B

TIME (µs/DIV)

Initialization Sequence B

CHANGING THE FREQUENCY OF THE PLL AND THE PHASE LOOKUP TABLE

After the ADF4196 is initialized, only a write to Register R0 is
required to program a new output frequency. The N divider is
updated with the values of INT and FRAC on the next PFD cycle
following the LE edge that latches in the R0 word. However, the
settling time and spurious performance of the synthesizer can
be further optimized by modifying the R1 and R2 register settings
on a channel-by-channel basis. These settings are double buffered
by the write to R0. This means that, although the data is loaded
through the serial interface on the respective R1 and R2 write
cycles, the synthesizer is not updated with the new data until
the next write to Register R0.

Register R2 can be used to digitally adjust the phase of the VCO
output relative to the reference edge. The phase can be adjusted
over the full 360° range at RF with a resolution of 360°/MOD.
In most frequency synthesizer applications, the actual phase offset
of the VCO output with respect to the reference is unknown
and is irrelevant. In such applications, the phase adjustment
capability of R2 can, instead, be used to optimize the settling time
performance as described in the Phase Lookup Table section.

09450-136

Rev. B | Page 23 of 28

ADF4196 Data Sheet

Phase Lookup Table

The fast lock sequence of the ADF4196 is initiated after the
write to Register R0. The fast lock timers are programmed so
that after the PLL has settled into wide bandwidth mode, the
charge pump current is reduced and the loop filter resistor
switches are opened, which reduces the loop bandwidth. The
reference cycle on which these events occur is determined by
the values that are preprogrammed into the timeout counters.

The phase locking plots of Figure 11 and Figure 14 show that
the lock time to final phase is dominated by the phase swing
that occurs when the bandwidth is reduced. When the PLL
settles to its final frequency and phase, in wide bandwidth
mode, this phase swing is the same regardless of the size of the
frequency jump of the synthesizer. The amplitude of the phase
swing is related to the current flowing through the loop filter
resistors on the PFD reference cycle that open the SW1 and
SW2 switches.

In an integer-N PLL, this current is zero when the PLL has
settled. In a fractional-N PLL, the current is zero, on average,
but it varies from one reference cycle to the next, depending
on the quantization error sequence output from the digital Σ-Δ
mo dulat or. Because the Σ-Δ modulator is all digital logic, clocked
at the PFD reference rate for a given value of MOD, the actual
quantization error on any given reference cycle is determined
by the value of FRAC and the phase word with which the
modulator is seeded, following the write to R0.

By choosing an appropriate value of phase corresponding to the
value of FRAC that is programmed on the next write to R0, the
size of the error current when the SW1 and SW2 switches are
opened can be minimized. Thus, the phase swing that occurs
when the bandwidth is reduced can be minimized.

With dither off, the fractional spur pattern that is due to the
quantization noise of the SDM also depends on the phase word
with which the modulator is seeded. Tables of optimized FRAC
and phase values for popular SW1/SW2 and I

timer settings can

CP

be downloaded from the ADF4196 product page. If using a phase
table, first write the phase to double buffered Register R2, and
then write the INT and FRAC values to Register R0.

Avoiding Integer Boundary Channels

When programming a new frequency, another option involves
a write to Register R1 to avoid integer boundary spurs. If the
integer boundary spur level is too high, the integer boundary
can be moved away from the desired channel by reprogramming
the R divider to select a different PFD frequency. For example,
if REF

= 104 MHz and R = 4 for a 26 MHz PFD reference,

IN

and MOD = 130 for 200 kHz steps, the frequency channel at

910.2 MHz has a 200 kHz integer boundary spur because it is
offset by 200 kHz from 35 × 26 MHz.

An alternative way to synthesize this channel is to set R = 5 for
a 20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.
The 910.2 MHz channel becomes a 5 MHz offset from the nearest
integer multiple of 20.8 MHz, and the 5 MHz beat note spurs
are well attenuated by the loop. Setting the double buffered DB23
bit (Bit CP ADJ in Register R1) to 1 increases the charge pump
current by 25%, which compensates for the 25% increase in N
with the change to the 20.8 MHz PFD frequency. This maintains
constant loop dynamics and settling time performance for jumps
between the two PFD frequencies. Clear the CP ADJ bit when
returning to 26 MHz-based channels.

The Register R1 settings that are required for integer boundary
spur avoidance are all double buffered and do not become active
on the chip until the next write to Register R0. Always ensure that
Register R0 is the last register written to when programming
a new frequency.

Serial Interface Activity

The serial interface activity when programming the R2 or R1
register causes no noticeable disturbance to the synthesizer’s
settled phase or degradation in its frequency spectrum. Thus,
in a GSM application, serial interface activity can be performed
during the active part of the data burst. Because it takes only

10.2 µs to program the three registers (R2, R1, and R0) with the

6.5 MHz serial interface clock rate typically used, this program­ming can also be performed during the previous guard period
with the LE edge to latch in the R0 data, delayed until it is time
to switch the frequency.

Rev. B | Page 24 of 28

Data Sheet ADF4196

Prescaler

4/5

4/5

8/9

8/9

APPLICATIONS INFORMATION

LOCAL OSCILLATOR FOR A GSM BASE STATION

Figure 37 shows the ADF4196 being used with a VCO to
produce the LO for a GSM1800 base station. For GSM, the
REF

signal can be any integer multiple of 13 MHz, but the

IN

main requirement is that the slew rate be at least 300 V/µs.
The 104 MHz, 5 dBm input sine wave shown in Figure 37
satisfies this requirement.

Recommended parameters for the various GSM/DCS/PCS
synthesizers are listed in Tab l e 10.

Table 10. Recommended Setup Parameters

GSM900 DCS1800/PCS1900
Parameter Tx Rx Tx Rx

Loop BW 60 kHz 40 kHz 60 kHz 40 kHz
PFD 13 MHz 26 MHz 13 MHz 13 MHz
MOD 65 130 65 65
Dither Off Off Off Off

ICP Timer 28 78 28 38
SW1, SW2,

SW3 Timers

VCO KV 18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V

Loop Bandwidth and PFD Frequency

A 60 kHz loop bandwidth is narrow enough to attenuate the
PLL phase noise and spurs to the required level for a Tx low.
A 40 kHz bandwidth is necessary to meet the GSM900 Rx
synthesizer’s particularly tough phase noise and spur requirements
at ±800 kHz offsets. To get the lowest spur levels at ±800 kHz
offsets for Rx, the Σ-Δ modulator should be run at the highest over­sampling rate possible. Therefore, for GSM900 Rx, a 26 MHz PFD
frequency is chosen, and MOD = 130 is required for 200 kHz steps.
Because this value of MOD is divisible by two, certain FRAC
channels have a 100 kHz fractional spur. This is attenuated by the
40 kHz loop filter and, therefore, is not a concern. However, the
60 kHz loop filter that is recommended for Tx has a closed-loop
response that peaks close to 100 kHz. Therefore, a 13 MHz PFD
with MOD = 65, which avoids the 100 kHz spur, is the best choice
for a Tx synthesizer.

Dither

Dither off should be selected for the lowest rms phase error.

Prescaler

The 8/9 prescaler should be selected for the DCS and PCS bands.
The 4/5 prescaler allows an N divider range low enough to cover
the GSM900 Tx and Rx bands with either a 13 MHz or 26 MHz
PFD frequency.

35 85 35 45

Timer Values for Tx

To comply with the GSM spectrum due to switching requirements,
the Tx synthesizer should not switch frequency until the PA output
power has ramped down by at least 50 dB. If it takes 10 µs to ramp
down to this level, only the last 20 µs of the 30 µs guard period is
available for the Tx synthesizer to lock to final frequency and phase.

In fast lock mode, the Tx loop bandwidth is widened by a factor
of 8 to 480 kHz and, therefore, the PLL achieves frequency lock
for a jump across the entire band in <6 µs. After this, the PA
power can start to ramp up again, and the loop bandwidth can
be restored to the final value. With the I

timer = 28, the charge

CP

pump current reduction begins at ~8.6 µs. When the SW1, SW2,
and SW3 timers = 35, the current reaches its final value before
the loop filter switches open at ~10.8 µs.

With these timer values, the phase disturbance created when
the bandwidth is reduced settles back to its final value by 20 µs,
in time for the start of the active part of the GSM burst. If faster
phase settling is desired with the 60 kHz bandwidth setting, the
timer values can be reduced further but should not be brought
less than the 6 µs that is required to achieve frequency lock in
wide bandwidth mode.

Timer Values for Rx

The 40 kHz Rx loop bandwidth is increased by a factor of 8 to
approximately 320 kHz during fast lock. With the Rx timer values
shown in Ta b le 10, the bandwidth is reduced after ~12 µs, which
allows sufficient time for the phase disturbance to settle back
before the start of the active part of the Rx time slot at 30 µs.
As in the Tx synthesizer case, faster Rx settling can be achieved by
reducing these timer values, their lower limit being determined
by the time it takes to achieve frequency lock in wide bandwidth
mode. In addition, the DCS and PCS Rx synthesizers have relaxed
800 kHz blocker specifications and, thus, can tolerate a wider
loop bandwidth, which allows correspondingly faster settling.

VCO KV

In general, the VCO gain, KV, should be set as low as possible to
minimize the reference and integer boundary spur levels that arise
due to feedthrough mechanisms. When deciding on the optimum
VCO K
band, centered on the available tuning range. With V

, a good choice is to allow 2 V to tune across the desired

V

3 regulated

P

to 5.5 V ± 100 mV, the tuning range available is 2.8 V.

Loop Filter Components

For good settling performance, it is important that capacitors
with low dielectric absorption be used in the loop filter. Ceramic
NPO C0G capacitors are a good choice for this application.
A 2% tolerance is recommended for loop filter capacitors and
1% for resistors. A 10% tolerance is adequate for the inductor, L1.

Rev. B | Page 25 of 28

ADF4196 Data Sheet

09450-037

R

SET

23

MUX

OUT

D

GND

1

16

SW2

27

SW

GND

28

SW1

29

CP

OUT+

30

CP

OUT–

26

REF

IN

11

RF

IN–

5

RF

IN+

6

CLK

17

SD

GND

14

A

GND

1

4

A

GND

2

22

LOCK DETE CT OUT

DATA

18

LE

19

REFERENCE

104MHz, 5dBm

ADF4196

SDV

DD

15

DVDDx

8, 10, 13

VP1

20

V

P

224AV

DD

7

V

P

3

32

9

D

GND

2

12

D

GND

3

21

R

SET

2.40kΩ

AIN+
AIN–

31

25

3

2

A

OUT

SW3

INTEGRATED

DIFFERENTIAL

AMPLIFIER

C1B
120pF

C1A
120pF

C3
470pF

100nF

1

CMR

Ct
30pF

R1B1

820Ω

R1B2

6.20kΩ

R1A2

6.20kΩ

R1A1

820Ω

C2B

1.20nF

C2A

1.20nF
R3

62Ω

R2

1.80kΩ

L1

2.2mH

SIRENZA VCO190-1843T

38MHz/V

100pF

100pF

1nF1nF

51Ω

51Ω

100nF

10µF

+

10µF

+

100nF

100nF 100nF

100pF

10µF

+

100nF

100nF

3V

5V

5.5V

10pF 100pF

18Ω

18Ω

18Ω

RF OUT

ADIsimPLL Support

The ADF4193 loop filter design is supported on ADIsimPLL v2.7
or later. Example files for popular applications are available for
download from the ADF4193 and ADF4196 product pages.

Also available is a technical note (ADF4193-TN-001, ADF4193
Loop Filter Design Using ADIsimPLL) that outlines a loop filter
design procedure that takes full advantage of the new degree of
freedom in the filter design that the differential amplifier and
loop filter switches provide.

Figure 37. LO for DCS1800 Tx Using the ADF4196

Rev. B | Page 26 of 28

Data Sheet ADF4196

INTERFACING

The ADF4196 has a simple SPI-compatible serial interface for
writing to the device. The CLK, DATA, and LE pins control the
data transfer. When LE goes high, the 24 bits that have been
clocked into the input register on each rising edge of CLK are
latched into the appropriate register. See Figure 2 for the timing
diagram and Table 6 for the register address table.

The maximum allowable serial clock rate is 33 MHz.

ADuC70xx Interface

Figure 38 shows the interface between the ADF4196 and the

ADuC70xx family of analog microcontrollers. The ADuC70xx

family is based on an ARM7™ core, although the same interface
can be used with any 8051-based microcontroller. The micro­controller is set up for SPI master mode with CPHA = 0. To
initiate the operation, the I/O port driving LE is brought low.
Each latch of the ADF4196 needs a 24-bit word. This is achieved
by writing three 8-bit bytes from the microcontroller to the device.
When the third byte is written, bring the LE input high to
complete the transfer.

When power is first applied to the ADF4196, an initialization
sequence is required for the output to become active (see Table 9).

I/O port lines on the microcontroller are also used to detect lock
(MUX

When operating in the SPI master mode, the maximum SPI transfer
rate of the ADuC7023, for example, is 20 Mbps. This means that
the maximum rate at which the output frequency can be changed
is 833 kHz. If using a faster SPI clock, ensure adherence to the
SPI timing requirements that are listed in Table 2.

configured as lock detect and polled by the port input).

OUT

ADuC70xx

SPICLK

MOSI

I/O PORTS

Figure 38. ADuC70xx-to-ADF4196 Interface

ADF4196

CLK

DATA

LE

MUX

OUT

(LOCK DETECT )

09450-033

Blackfin ADSP-BF527 Interface

Figure 39 shows the interface between the ADF4196 and the
Blackfin® ADSP-BF527 digital signal processor (DSP). The

ADF4196 needs a 24-bit serial word for each latch write. The

easiest way to accomplish this, when using the Blackfin family,
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.

Set up the word length for eight bits, and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer. Ensure that the clock speeds are
within the maximum limits that are outlined in Table 2.

ADSP-BF527

SCLK

MOSI
GPIO

I/O FLAGS

Figure 39. ADSP-BF527-to-ADF4196 Interface

ADF4196

CLK

DATA

LE

MUX

OUT

(LOCK DETECT)

09450-034

PCB DESIGN GUIDELINES

The lands on the chip scale package (CP-32-2) are rectangular.
The printed circuit board (PCB) pad for these lands should be

0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. To ensure that the solder joint size
is maximized, center the land on the pad.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as the
exposed pad. To avoid shorting, provide a clearance on the PCB
of at least 0.25 mm between the thermal pad and the inner edges
of the pad pattern.

Thermal vias can be used on the PCB thermal pad to improve the
thermal performance of the package. If vias are used, incorporate
them into the thermal pad at a 1.2 mm pitch grid. Provide a via
diameter between 0.3 mm and 0.33 mm, and plate the via barrel
with 1 oz copper to plug the via. Connect the PCB thermal pad
to A

GND

1 or A

GND

2.

Rev. B | Page 27 of 28

ADF4196 Data Sheet

3.25

3.10 SQ

2.95

FOR PROPE R CONNECTIO N OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DE S CRIPTIO NS
SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

1

32

8

9

25

24

17

16

COPLANARITY

0.08

3.50 REF

0.50

BSC

PIN 1
INDICATOR

PIN 1

INDICATOR

0.30

0.25

0.18

0.20 REF

12° MAX

0.80 MAX

0.65 TYP

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50

0.40

0.30

5.00

BSC SQ

4.75

BSC SQ

0.60 MAX

0.60 MAX

0.25 MIN

05-25-2011-A

TOP VIEW

EXPOSED

PAD

BOTTOM VIEW

ADF4196BCPZ-RL7

−40°C to +85°C

32-Lead LFCSP_VQ

CP-32-2

©2011 Analog Devices, Inc. All rights reserved. Trademarks and

OUTLINE DIMENSIONS

Figure 40. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

1, 2

Model

ADF4196BCPZ −40°C to +85°C 32-Lead LFCSP_VQ CP-32-2

EVAL-ADF4193EBZ1 Evaluation Board (GSM1800)
EVAL-ADF4193EBZ2 Evaluation Board (No VCO or Loop Filter)

1

Z = RoHS Compliant Part.

2

The EVAL-ADF4193EBZ1 and EVAL-ADF4193EBZ2 evaluation boards are designed to accommodate either the ADF4193 or the ADF4196.

Temperature Range Package Description Package Option

registered trademarks are the property of their respective owners.
D09450-0-12/11(B)

Rev. B | Page 28 of 28