ANALOG DEVICES ADF4196 Service Manual

Low Phase Noise, Fast Settling, 6 GHz

PLL Frequency Synthesizer

ADF4196

Rev. B

Trademarks and registered trademarks are the prop erty of their respective owner s.

09450-001

N COUNTER

SW1 CP

OUT+

CP

OUT–

SW2

REFERENCE

DATA

LE

24-BIT

DATA

REGISTER

CLK

REF

IN

A

GND

1

A

GND

2 D

GND

1 D

GND

2 D

GND

3

SD

GND

SW

GND

V

DD

DGND

LOCK DETE CT

R

DIV

N

DIV

SDV

DDDVDD

1 DVDD2 DVDD3

AV

DD

VP1 VP2

VP3 R

SET

OUTPUT

MUX

OUT

–

+

HIGH-Z

PHASE

FREQUENCY

DETECTOR

ADF4196

FRACTIONAL

INTERPOLATOR

MODULUS

REG

FRACTION

REG

INTEGER

REG

RF

IN+

RF

IN–

×2

DOUBLER

4-BIT R

COUNTER

/2

DIVIDER

CHARGE

PUMP

–

+

–

DIFFERENTIAL

AMPLIFIER

CMR

AIN– AIN+

A

OUT

SW3

Data Sheet

FEATURES

Fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 μs with phase settled

within 20 μs 1 degree rms phase error at 4 GHz RF output Digitally programmable output phase RF input range up to 6 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit: −216 dBc/Hz

APPLICATIONS

GSM/EDGE base stations PHS base stations Pulse Doppler radar Instrumentation and test equipment Beam-forming/phased array systems

GENERAL DESCRIPTION

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the

ADF4196 suitable for pulse Doppler radar applications.

The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REF

) frequencies at the PFD input.

IN

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.

FUNCTIONAL BLOCK DIAGRAM

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com

ADF4196 Data Sheet

REVISION HISTORY

12/11—Rev. A t o R e v. B

Changes to Figure 10, Figure 11, Figure 13, and

Figure 14 ............................................................................................ 9

Change to Figure 31 ....................................................................... 17

10/11—Revision A: Initial Version

Input Shift Register .................................................................... 13

Register Map ................................................................................... 14

FRAC/INT Register (R0) Latch Map ....................................... 15

MOD/R Register (R1) Latch Map ............................................ 16

Phase Register (R2) Bit Latch Map .......................................... 17

Function Register (R3) Latch Map ........................................... 18

Charge Pump Register (R4) Latch Map .................................. 19

Power-Down Register (R5) Bit Map ........................................ 20

Mux Register (R6) Latch Map and Truth Table ..................... 21

Programming the ADF4196 .......................................................... 22

Worked Example ........................................................................ 22

Spur Mechanisms ....................................................................... 22

Power-Up Initialization ............................................................. 23

Changing the Frequency of the PLL and the Phase Lookup

Tabl e ............................................................................................. 23

Applications Information .............................................................. 25

Local Oscillator for a GSM Base Station ................................. 25

Interfacing ................................................................................... 27

PCB Design Guidelines ............................................................. 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

Rev. B | Page 2 of 28

Data Sheet ADF4196

RF CHARACTERISTICS

CHARGE PUMP

Output Noise

7

nV/√Hz

At 20 kHz offset

Input Low Voltage, VIL

0.7 V

22

27

mA

SPECIFICATIONS

AVDD = DVDD1, DVDD2, DVDD3 = SDVDD = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; A R

= 2.4 kΩ; dBm referred to 50 Ω; TA = T

SET

MIN

to T

, unless otherwise noted. Operating temperature range = −40°C to +85°C.

MAX

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

GND

1, A

GND

2 = D

GND

1, D

GND

2, D

GND

3 = 0 V;

RF Input Frequency (RF

) 0.4 6 GHz See Figure 21 for input circuit

IN±

RF Input Sensitivity −10 0 dBm

Maximum Allowable Prescaler Output

Frequency

1

750 MHz

REFIN CHARACTERISTICS

REFIN Input Frequency 300 MHz For f > 120 MHz, set REF/2 bit = 1 (Register R1)

REFIN Edge Slew Rate 300 V/µs

REFIN Input Sensitivity 0.7 VDD V p-p AC-coupled

0 to VDD V CMOS compatible

REFIN Input Capacitance 10 pF

REFIN Input Current ±100 µA

PHASE DETECTOR

Phase Detector Frequency 26 MHz

ICP Up/Down

High Value 6.6 mA R Low Value 104 µA R

= 2.4 kΩ

SET

= 2.4 kΩ

SET

Absolute Accuracy 5 %

R

Range 1 4 kΩ Nominally R

SET

= 2.4 kΩ

SET

ICP Three-State Leakage 1 nA

ICP Up vs. Down Matching 0.1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. VCP 1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

ICP vs. Temperature 1 % 0.75 V ≤ VCP ≤ VP1, VP2, VP3 − 1.5 V

DIFFERENTIAL AMPLIFIER

Input Current 1 nA

Output Voltage Range 1.4 VP3 − 0.3 V

VCO Tuning Range 1.8 VP3 − 0.8 V

LOGIC INPUTS

Input High Voltage, VIH 1.4 V

Input Current, I

Input Capacitance, CIN 10 pF

LOGIC OUTPUTS

Output High Voltage, VOH VDD − 0.4 V IOH = 500 µA

Output Low Voltage, VOL 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 2.7 3.3 V

DVDD1, DVDD2, DVDD3 AVDD V

VP1, VP2 4.5 5.5 V AVDD ≤ VP1, VP2 ≤ 5.5 V

VP3 5.0 5.65 V VP1, VP2 ≤ VP3 ≤ 5.65 V

IDD (AVDD + DVDD1, DVDD2, DVDD3 +

SDV IDD (VP1 + VP2) 22 27 mA IDD (VP3) 24 30 mA IDD Power-Down 10 µA

, I

±1 µA

INH

INL

)

DD

Rev. B | Page 3 of 28

ADF4196 Data Sheet

1800 MHz3

−102

dBc/Hz

At 5 kHz offset and 13 MHz PFD frequency

t6

10 ns min

CLK to LE setup time

09450-002

CLK

DATA

DB23

(MSB)

DB22

DB1 (LSB)

(CONTRO L BIT C2)

DB2 (LSB)

(CONTRO L BIT C3)

DB0 (LSB)

(CONTRO L BIT C1)

LE

t

2

t

4

t

5

t

3

t

7

t

6

t

1

Parameter Min Typ Max Unit Test Conditions/Comments

SW1, SW2, AND SW3

On Resistance

SW1 and SW2 65 Ω SW3 75 Ω

NOISE CHARACTERISTICS

Output

900 MHz2 −108 dBc/Hz At 5 kHz offset and 26 MHz PFD frequency

Phase Noise

Normalized Phase Noise Floor

)4

(PN

SYNTH

Normalized 1/f Noise (PN

1

Choose a prescaler value that ensures that the frequency on the RF input is less than the maximum allowable prescaler frequency (750 MHz).

2

f

= 26 MHz; f

REF

IN

3

f

= 13 MHz; f

REF

IN

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

value) and 10 log(f

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency,

fRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL™.

= 200 kHz; fRF = 900 MHz; loop bandwidth = 40 kHz.

STEP

= 200 kHz; fRF = 1800 MHz; loop bandwidth = 60 kHz.

STEP

). PN

PFD

SYNTH

)5 −110 dBc/Hz Measured at 10 kHz offset, normalized to 1 GHz

1_f

= PN

− 10 log(f

TOT

TIMING CHARACTERISTICS

AVDD = DVDD1, DVDD2, DVDD3 = 3 V ± 10%; VP1, VP2 = 5 V ± 10%; VP3 = 5.35 V ± 5%; A R

= 2.4 kΩ; dBm referred to 50 Ω; TA = T

SET

−216 dBc/Hz

) − 20 log(N).

PFD

to T

MIN

, unless otherwise noted. Operating temperature = −40°C to +85°C.

MAX

At VCO output with dither off, PLL loop bandwidth = 500 kHz

1, A

GND

2 = D

GND

1, D

GND

2, D

3 = 0 V;

GND

Table 2.

Parameter Limit Description

t1 10 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 15 ns min CLK high duration t5 15 ns min CLK low duration

t7 15 ns min LE pulse width

Timing Diagram

Figure 2. Timing Diagram

Rev. B | Page 4 of 28

Data Sheet ADF4196

Peak Temperature

260°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to Ground −0.3 V to +3.6 V AVDD to DVDD1, DVDD2, DVDD3, SDVDD −0.3 V to +0.3 V VP1, VP2, VP3 to Ground −0.3 V to +5.8 V VP1, VP2, VP3 to AVDD −0.3 V to +5.8 V Digital I/O Voltage to Ground −0.3 V to VDD + 0.3 V Analog I/O Voltage to Ground −0.3 V to VP1, VP2, VP3 + 0.3 V REFIN, RF Operating Temperature Range

Industrial −40°C to +85°C

Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C Reflow Soldering

Time at Peak Temperature 40 sec

, RF

to Ground −0.3 V to VDD + 0.3 V

IN+

IN−

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA Unit

32-Lead LFCSP (Paddle Soldered) 27.3 °C/W

TRANSISTOR COUNT

This device includes 75,800 metal oxide semiconductors (MOS) and 545 bipolar junction transistors (BJT).

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Take proper precautions for handling and assembly.

Rev. B | Page 5 of 28

ADF4196 Data Sheet

09450-003

1CMR 2A

OUT

3SW3 4A

GND

1

5RF

IN–

6RF

IN+

7AV

DD

24 V

P

2

23 R

SET

22 A

GND

2

21

D

GND

3

20 V

P

1

19 LE 18 DATA 17 CLK

8DV

DD

1

ADF4196

TOP VIEW

(Not to Scale)

9D

GND

1

10DV

DD

2

11

REF

IN

12

D

GND

2

13DV

DD

3

14

SD

GND

15

SDV

DD

16

MUX

OUT

32 V

P

3

31 AIN+

30 CP

OUT+

29

SW1

28 SW

GND

27

SW2

26 CP

OUT–

25

AIN–

PIN 1 INDICATOR

NOTES

1. THE EXPOSED PADDLE MUST BE CONNECTED TO THE G ROUND PLANE.

5

RF

8

DVDD1

Power Supply Pin for the N Divider. DVDD1 should be at the same voltage as AVDD. Place a 0.1 µF decoupling

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 CMR

2 A

OUT

Differential Amplifier Output. This pin is the differential amplifier output to tune the external VCO.

Common-Mode Reference Voltage for the Output Voltage Swing of the Differential Amplifier. Internally biased to three-fifths of V

3. Requires a 0.1 µF capacitor to the ground plane.

P

3 SW3 Fast Lock Switch 3. This switch is closed when the SW3 timeout counter is active. 4 A

1 Analog Ground. This is the ground return pin for the differential amplifier and the RF section.

GND

IN−

Complementary Input to the RF Prescaler. This pin must be decoupled to the ground plane with a small bypass

capacitor, typically 100 pF. 6 RF 7 AVDD

Input to the RF Prescaler. This small-signal input is ac-coupled to the external VCO.

IN+

Power Supply Pin for the RF Section. Nominally 3 V. Place a 100 pF decoupling capacitor to the ground plane as

close as possible to this pin.

capacitor to the ground plane as close as possible to this pin. 9 D 10 DVDD2

1 Ground Return Pin for DVDD1.

GND

Power Supply Pin for the REF

Buffer and R Divider. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the

IN

ground plane as close as possible to this pin. 11 REFIN

Reference Input. This CMOS input has a nominal threshold of V

/2 and a dc equivalent input resistance of 100 kΩ.

DD

This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 12 D

2 Ground Return Pin for DVDD2 and DVDD3.

GND

13 DVDD3 Power Supply Pin for the Serial Interface Logic. Nominally 3 V. 14 SD 15 SDVDD

Ground Return Pin for the Digital Σ-Δ Modulator.

GND

Power Supply Pin for the Digital Σ-Δ Modulator. Nominally 3 V. Place a 0.1 µF decoupling capacitor to the ground

plane as close as possible to this pin. 16 MUX

17 CLK

18 DATA

19 LE

20 VP1

21 D 22 A

Multiplexer Output. This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency

to be accessed externally (see Figure 35 for details).

Serial Clock Input. Data is clocked into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

OUT

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that is

selected by the three LSBs.

Power Supply Pin for the Phase Frequency Detector (PFD). Nominally 5 V, V

Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin.

3 Ground Return Pin for VP1.

GND

2 Ground Return Pin for VP2.

GND

Rev. B | Page 6 of 28

1 should be at the same voltage as VP2.

P

Data Sheet ADF4196

25.0

30

CP

Differential Charge Pump Positive Output Pin. Connect this pin to AIN+ and the loop filter.

Pin No. Mnemonic Description

23 R

24 VP2

25 AIN− Negative Input Pin for the Differential Amplifier. 26 CP 27 SW2 Fast Lock Switch 2. This switch is closed to SW 28 SW 29 SW1 Fast Lock Switch 1. This switch is closed to SW

31 AIN+ Positive Input Pin for the Differential Amplifier. 32 VP3

EP Exposed Paddle. The exposed paddle must be connected to the ground plane.

SET

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage bias at

pin is 0.55 V. The relationship between ICP and R

the R

SET

=

I

CP

R

SET

Therefore, with R

= 2.4 kΩ, ICP = 104 µA.

SET

Power Supply Pin for the Charge Pump. Nominally 5 V, V

is

SET

2 should be at the same voltage as VP1. Place a 0.1 µF

P

decoupling capacitor to the ground plane as close as possible to this pin.

Differential Charge Pump Negative Output Pin. Connect this pin to AIN− and the loop filter.

OUT−

when the SW1/SW2 timeout counter is active.

GND

Ground for SW1 and SW2 Switches. Connect this pin to the ground plane.

GND

when the SW1/SW2 timeout counter is active.

GND

OUT+

Power Supply Pin for the Differential Amplifier. Ranges from 5.0 V to 5.5 V. Place a 0.1 µF decoupling capacitor to the ground plane as close as possible to this pin. V

3 also requires a 10 µF decoupling capacitor to the ground plane.

P

Rev. B | Page 7 of 28

ADF4196 Data Sheet

–

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ. UNIT GHz KEYWORD R PARAM TYPE S IMPEDANCE 50 DATA FORMAT MA

FREQ. MAGS11 ANGS11

0.5 0.8897 –16.6691

0.6 0.87693 –19.9279

0.7 0.85834 –23.561

0.8 0.85044 –26.9578

0.9 0.83494 –30.8201

1.0 0.81718 –34.9499

1.1 0.80229 –39.0436

1.2 0.78917 –42.3623

1.3 0.77598 –46.322

1.4 0.75578 –50.3484

1.5 0.74437 –54.3545

1.6 0.73821 –57.3785

1.7 0.7253 –60.695

1.8 0.71365 –63.9152

1.9 0.70699 –66.4365

2.0 0.7038 –68.4453

2.1 0.69284 –70.7986

2.2 0.67717 –73.7038

Figure 4. S-Parameter Data for the RF Input

FREQ. MAGS11 ANGS11

2.3 0.67107 –75.8206

2.4 0.66556 –77.6851

2.5 0.6564 –80.3101

2.6 0.6333 –82.5082

2.7 0.61406 –85.5623

2.8 0.5977 –87.3513

2.9 0.5655 –89.7605

3.0 0.5428 –93.0239

3.1 0.51733 –95.9754

3.2 0.49909 –99.1291

3.3 0.47309 –102.208

3.4 0.45694 –106.794

3.5 0.44698 –111.659

3.6 0.43589 –117.986

3.7 0.42472 –125.62

3.8 0.41175 –133.291

3.9 0.41055 –140.585

4.0 0.40983 –147.97

09450-038

10

5

0

–5

–10

–15

RF SENSITIVITY (d Bm)

–20

–25

–30

01234

4/5 PRESCALER 8/9 PRESCALER

FREQUENCY (GHz)

Figure 7. RF Input (RF

) Sensitivity

IN

09450-005

765

30 –40 –50 –60 –70 –80 –90

–100 –110 –120 –130

PHASE NOISE (dBc/Hz)

–140 –150 –160 –170

1k 10k 100k 1M 10M

GSM900 Rx SETUP, 40kHz LOOP BW, DITHER OFF RF = 1092.8M Hz , N = 42 4/130 INTEG ER BOUNDARY S PUR: –103dBc @ 80 0 kHz

f

= 26MHz, MOD = 130

REF

FREQUENC Y (Hz)

100M

Figure 5. Single-Sideband (SSB) Phase Noise Plot at 1092.8 MHz

(GSM900 Rx Setup) vs. Free Running VCO Noise

60

DCS1800 Tx SETUP WITH DITHER OFF, 60kHz LOOP BW, 13 MHz PFD. MEASURED ON EVAL-ADF4193EBZ1 BOARD

–70

–80

–90

400kHz SPURS @ 2 5°C

30 –40 –50 –60 –70 –80 –90

–100 –110 –120 –130

PHASE NOISE (dBc/Hz)

–140 –150

09450-006

–160 –170

1k 10k 100k 1M 10M

DCS1800 Tx SETUP, 60kHz LOOP BW, DITHER OFF RF = 1842.6M Hz , DSB INTE GRATED PHASE ERROR = 0 .46° RMS SIRENZA 184 3T V CO

f

= 13MHz, MOD = 65

REF

FREQUENC Y (Hz)

09450-007

100M

Figure 8. Single-Sideband (SSB) Phase Noise Plot at 1842.6 MHz

(DCS1800 Tx Setup)

60

DCS1800 Tx SETUP WITH DITHER OFF, 60kHz LOOP BW, 13MHz PFD. MEASURED ON EVAL-ADF4193E BZ 1 BOARD

–70

–80

–90

600kHz SPURS @ 25°C

–100

SPUR LEVEL (dBc)

–110

–120

1846 1859

FREQUENC Y (MHz)

400kHz SPURS @ 85°C

09450-010

1872

Figure 6. 400 kHz Fractional Spur Levels Across All DCS1800 Tx Channels

over Two Integer Multiples of the PFD Reference

–100

SPUR LEVEL (dBc)

–110

–120

1846 1859

FREQUENCY (MHz)

600kHz SPURS @ 85°C

1872

09450-011

Figure 9. 600 kHz Fractional Spur Levels Across All DCS1800 Tx Channels over

Two Integer Multiples of the PFD Reference

Rev. B | Page 8 of 28

Data Sheet ADF4196

09450-040

TIME (µs)

CONTROL VOLTAGE (V)

–1

0

1

2

3

4

5

9876543210

V

TUNE

CP

OUT+

CP

OUT–

DCS1800 Tx SETUP, 60kHz LOO P BW. MEASURED ON EVAL-ADF4193EBZ1 EVALUATION BOARD. TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

FREQUENCY L OCK IN WIDE BW MODE @ 4µs.

09450-008

TIME (µs)

PHASE ERROR (Deg rees)

–5 0 5 10 15 20 25 30 35 40

–50

50

40

30

20

10

0

–10

–20

–30

–40

45

+25°C

+85°C

–40°C

DCS1800 Tx SETUP, 60kHz LOO P BW. MEASURED ON EVAL-ADF4193EBZ1 EVALUATION BOARD WITH AD8302 PHASE DETECT OR. TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

PEAK PHASE ERROR < 5° @ 17.8µs

09450-012

CP

OUT

+ / CP

OUT

– VOLTAGE (V)

I

CP

(mA)

CHANGE PUMP MISMATCH (%)

0 0.5 1.0 1.5 2.0 2.5

3.0 3.5 4.0 4.5

–8

–6

–4

–2

0

2

4

6

8

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

5.0

ICP

OUT

+ P, ICP

OUT

– P

CHARGE PUMP MISMATCH (%)

NORMAL OP E RATING RANGE

ICP

OUT

+ N, ICP

OUT

– N

IUP= | ICP

OUT

+ P | + | ICP

OUT

– N |

I

DOWN

= | ICP

OUT

– P | + | ICP

OUT

+ N |

09450-041

TIME (µs)

CONTROL VOLTAGE (V)

–1

0

1

2

3

4

5

9876543210

V

TUNE

CP

OUT–

CP

OUT+

DCS1800 Tx SETUP, 60kHz LOO P BW. MEASURED ON EVAL-ADF4193EBZ1 EVALUATION BOARD. TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

FREQUENCY L OCK IN WIDE BW MODE @ 5µs.

09450-009

TIME (µs)

PHASE ERROR (Deg rees)

–5 0 5 10 15 20 25 30 35 40

–50

50

40

30

20

10

0

–10

–20

–30

–40

45

+25°C

+85°C

–40°C

DCS1800 Tx SETUP, 60kHz LOO P BW. MEASURED ON EVAL-ADF4193EBZ1 EVALUATION BOARD WITH AD8302 PHASE DETECT OR. TIMERS: I

CP

= 28, SW1/S W2, SW3 = 35.

PEAK PHASE ERROR < 5° @ 19.2µs

09450-013

FREQUENCY (MHz)

CONTROL VOLTAGE (V)

1780 1800 1820 1840 1860 1880 1900 1920 1940

0

2

1

3

4

5

VP1 = V

P

2 = 5V

V

P

3 = 5.5V

V

CMR

= 3.3V

CP

OUT–

(= AIN–)

A

OUT

(= V

TUNE

)

CP

OUT+

(= AIN+)

Figure 10. V

Settling Transient for a 75 MHz Jump from 1818 MHz to

TUNE

1893 MHz with Sirenza 1843T VCO

Figure 11. Phase Settling Transient for a 75 MHz Jump from 1818 MHz to

1893 MHz (V

= 1.8 V to 3.7 V with Sirenza 1843T VCO)

TUNE

Figure 13. V

Settling Transient for a 75 MHz Jump Down from 1893 MHz

TUNE

to 1818 MHz (Bottom of Allowed Tuning Range) with Sirenza 1843T VCO

Figure 14. Phase Settling Transient for a 75 MHz Jump Down from 1893 MHz

to 1818 MHz (V

= 3.7 V to 1.8 V with Sirenza 1843T VCO)

TUNE

Figure 12. Differential Charge Pump Output Compliance Range and

Charge Pump Mismatch with V

1 = VP2 = 5 V

P

Figure 15. Tuning Range with a Sirenza 1843T VCO and a 5.5 V Differential

Amplifier Power Supply Voltage

Rev. B | Page 9 of 28

ANALOG DEVICES ADF4196 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

TRANSISTOR COUNT

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS