ANALOG DEVICES ADF4159 Service Manual

Direct Modulation/

Fast

Waveform Generating

13 GHz Fractional-N Frequency Synthesizer

VDDV

R

A

B

MUXOUT

Preliminary Technical Data

FEATURES

RF bandwidth to 13 GHz
High and low speed FMCW Ramps Generation
25-bit fixed modulus allows sub-hertz frequency resolution
PFD Frequencies up to 110MHz
Frequency and Phase modulation capability
Sawtooth and triangular waveforms generation
Parabolic ramp
Ramp superimposed with FSK
Ramp with 2 different sweep rates
Ramp Delay
Ramp Frequency Readback
Ramp Interruption

2.7 V to 3.3 V analog power supply

1.8 V digital power supply
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Cycle Slip Reduction for faster lock times
Switched Bandwidth Fast Lock Mode

APPLICATIONS

FMCW radar
Communications test equipment

ADF4159

GENERAL DESCRIPTION

The ADF4159 is a 13 GHz, fractional-N frequency synthesizer
with modulation and both fast and slow waveform generation
capability. It contains a 25-bit fixed modulus, allowing subhertz
resolution at 13 GHz. It consists of a low noise digital phase
frequency detector (PFD), a precision charge pump, and a
programmable reference divider. There is a sigma-delta (Σ-Δ)
based fractional interpolator to allow programmable fractional­N division. The INT and FRAC registers define an overall N­divider as N = INT + (FRAC/225).

The ADF4159 can be used to implement frequency shift keying
(FSK) and phase shift keying (PSK) modulation. There are also
a number of frequency sweep modes available, which generate
various waveforms in the frequency domain, for example,
sawtooth and triangular waveforms. The ADF4159 features
cycle slip reduction circuitry, which leads to faster lock times,
without the need for modifications to the loop filter.

Control of all on-chip registers is via a simple 3-wire inter­face. The device operates with an analog power supply in the
range from 2.7 V to 3.3 V and digital power supply in the range
from 1.6 V to 2 V. It can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

ADF4159

REF

IN

HIGH Z

CE

TXDATA

CLK

DATA

LE

Rev. PrC

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

×2

DOUBLER

OUTPUT

MUX

32-BIT

DATA

REGISTER

V
DGND

SD
V
R
N

AGND

5-BIT

R COUNTER

DD

LOCK

DETECT

OUT

DD
DIV

DIV

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

FRACTION

REG

DGND CPGND

÷2

DIVIDER

MODULUS

25

2

P

+

PHASE

FREQUENCY

DETECTOR

–

N COUNTER

INTEGER

REG

SET

REFERENCE

CHARGE

PUMP

FLO SWITCH

CSR

SW2

CP

SW1

RF
RF

IN

IN

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

ADF4159 Preliminary Technical Data
TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

LSB FRAC Register (R1) Map ................................................... 14

R-Divider Register (R2) Map .................................................... 16

Function Register (R3) Map...................................................... 18

Functional Block Diagram .............................................................. 1

Specifications ..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings ............................................................ 6

ESD Caution .................................................................................. 6

Pin Configuration and Pin Function Descriptions ...................... 7

Typical Performance Characteristics ............................................. 8

Reference Input Section ............................................................... 9

RF Input Stage ............................................................................... 9

RF INT Divider ............................................................................. 9

25-Bit Fixed Modulus .................................................................. 9

INT, FRAC, and R Relationship ................................................. 9

R-Counter ...................................................................................... 9

Phase Frequency Detector (PFD) and Charge Pump ............ 10

MUXOUT and LOCK Detect ................................................... 10

Input Shift Registers ................................................................... 10

Program Modes .......................................................................... 10

Register Maps .................................................................................. 11

FRAC/INT Register (R0) Map .................................................. 13

Test Register (R4) Map .............................................................. 20

Deviation Register (R5) Map .................................................... 21

Step Register (R6) Map .............................................................. 22

Delay Register (R7) Map ........................................................... 23

Applications Information .............................................................. 24

Initialization Sequence............................................................... 24

RF Synthesizer: A Worked Example ......................................... 24

Reference Doubler and Reference Divider ............................. 24

Cycle Slip Reduction for Faster Lock Times ........................... 24

Modulation .................................................................................. 25

Waveform Generation ............................................................... 25

Other Waveforms ....................................................................... 27

Fast Lock Mode........................................................................... 31

Spur Mechanisms ....................................................................... 32

Filter Design—ADIsimPLL ....................................................... 32

PCB Design Guidelines for the Chip Scale Package .............. 32

Application of ADF4159 in FMCW Radar.................................. 33

Outline Dimensions ....................................................................... 34

Rev. PrC | Page 2 of 35

Preliminary Technical Data ADF4159

SET

INL

INH/IINL

SPECIFICATIONS

AVDD = 2.7 V to 3.3 V, DVDD = SDVDD = 1.8V; VP = AVDD, AGND = DGND = 0 V, TA = T

MIN

to T

, dBm referred to 50 Ω, unless

MAX

otherwise noted.

Table 1.

C Version1

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN) 0.5 13 GHz −10 dBm min to 0 dBm max; for lower frequencies, ensure

slew rate (SR) > 400 V/µs

REFERENCE CHARACTERISTICS

REFIN Input Frequency 10 260 MHz For f < 10 MHz, use a dc-coupled CMOS-compatible

square wave, slew rate > 25 V/µs
TBD MHz If an internal reference doubler is enabled
REFIN Input Sensitivity TBD V p-p Biased at 1.8/22
REFIN Input Capacitance 10 pF
REFIN Input Current ±100 µA

PHASE DETECTOR

Phase Detector Frequency3 110 MHz

CHARGE PUMP

ICP Sink/Source Programmable

High Value 5 mA With R

= 5.1 kΩ

SET

Low Value 312.5 µA
Absolute Accuracy 2.5 % With R
R

Range 2.7 10 kΩ

= 5.1 kΩ

SET

ICP Three-State Leakage Current 1 nA Sink and source current
Matching 2 % 0.5 V < VCP < VP – 0.5 V
ICP vs. VCP 2 % 0.5 V < VCP < VP – 0.5 V
ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 V

INH

V

, Input Low Voltage 0.6 V

I

, Input Current ±1 µA

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V Open-drain output chosen; 1 kΩ pull-up to 1.8 V
VOH, Output High Voltage VDD − 0.4 V CMOS output chosen
IOH, Output High Current 100 µA
VOL, Output Low Voltage 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 2.7 3.3 V
DVDD 1.6 1.8 2 V
SDVDD 1.6 1.8 2 V
VP 2.7 3.3 V
IDD 33 42 mA

Rev. PrC | Page 3 of 35

ADF4159 Preliminary Technical Data

1_f

t4t

Parameter Min Typ Max Unit Test Conditions/Comments
NOISE CHARACTERISTICS

Normalized Phase Noise Floor4 TBD dBc/Hz PLL loop BW = 500 kHz
Normalized 1/f Noise (PN

)5 TBD Measured at 10 kHz offset, normalized to 1 GHz

Phase Noise Performance6 @ VCO output

12000 MHz Output7 TBD dBc/Hz @ 50 kHz offset, 100 MHz PFD frequency

1

Operating temperature for C version: −40°C to +125°C.

2

AC-coupling ensures 1.8/2 bias.

3

Guaranteed by design. Sample tested to ensure compliance.

4

This figure can be used to calculate phase noise for any application. Use the formula TBD + 10 log(f

at the VCO output.

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,

and at an offset frequency, f, is given by PN = P

6

The phase noise is measured with the EVAL-ADF4159EB1Z and the Agilent E5052A phase noise system.

7

fREFIN = 100 MHz; fPFD = 100 MHz; offset frequency = 50 kHz; RFOUT = 12000 MHz; N = 120; loop bandwidth = 200 kHz.

TIMING SPECIFICATIONS

AVDD = 2.7 V to 3.3 V; DVDD = SDVDD = 1.8V; VP = AVDD; AGND = DGND = SDGND = 0V; TA = T
unless otherwise noted.

Table 2. Write Timing

Parameter Limit at T

t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

MIN

to T

MAX

C Version1

+ 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

1_f

) + 20 logN to calculate in-band phase noise performance as seen

PFD

to T

MIN

, dBm referred to 50 Ω,

MAX

(C Version) Unit Test Conditions/Comments

Write Timing Diagram

CLK

DATA

LE

LE

t

2

DB31 (MSB) DB30

t

1

t

3

DB2

(CONTROL BIT C3)

Figure 2. Write Timing Diagram

Rev. PrC | Page 4 of 35

5

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

08728-026

Preliminary Technical Data ADF4159

DATA

Table 3. Read Timing

Parameter Limit at T

t1 20 ns min TX
t2 10 ns min DATA (on MUXOUT) to CLK setup time
t3 10 ns min DATA (on MUXOUT) to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time

Read Timing Diagram

TXDATA

CLK

to T

MIN

(C Version) Unit Test Conditions/Comments

MAX

setup time

t

1

t

4

t

5

MUXOUT

LE

t

2

DB36 DB35

t

3

Figure 3. Read Timing Diagram

DB1DB2

DB0

t

6

08728-026

Rev. PrC | Page 5 of 35

ADF4159 Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, GND = AGND = DGND = SDGND = 0 V,
VDD = AVDD , DVDD = SDVDD, unless otherwise noted.

Table 4.

Parameter Rating

AVDD to GND −0.3 V to +4 V
DVDD to GND −0.3 V to +2.4 V
VP to GND −0.3 V to +4 V
VP to AVDD −0.3 V to +0.6 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (C Version) −40°C to +125°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C

LFCSP θJA Thermal Impedance

(Paddle Soldered)
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

30.4°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. PrC | Page 6 of 35

Preliminary Technical Data ADF4159

T

DD

5.25

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

SETVP

CP24

R

232221

PIN1

1

CPGND

AGND 2
AGND
RFINB 4

RFINA 5
AV

DD

NOTES

1. THE LFCSP HAS AN EXPOSED PADDLE
THAT MUST BE CONNECTED TO GND.

3

6

IDENTIFIER

ADF4159

TOPVIEW

(Not to Scale)

789

IN

DD

DD

REF

AV

AV

DV

SW2

SW1

20

19

18

SDV

DD

17

MUXOU

16

LE

15

DATA

14

CLK

CE13

10

11

12

DATA

DGND

TX

SDGND

Figure 4. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
4 RFINB Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,

typically 100 pF.
5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
6, 7, 8 AVDD Positive Power Supply for the RF Section. Place decoupling capacitors to the ground plane as close as possible to this

pin.
9 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.

It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10 DGND Digital Ground.
11 SDGND Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
12 TX
13 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode.
14 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift

15 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high

16 LE Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,

17 MUXOUT Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be

18 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be 1.8V. Place decoupling capacitors to the ground

19 DVDD Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as

20 , 21 SW1, SW2 Switches for Fast Lock.
22 VP Charge Pump Power Supply. This should be greater than or equal to VDD. The max value of VP is 3.3V.
23 R

24 CP Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO.
25 EPAD Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.

Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.

DATA

register on the CLK rising edge. This input is a high impedance CMOS input.

impedance CMOS input.

with the latch being selected using the control bits.

accessed externally.

plane as close as possible to this pin.

possible to this pin. DVDD must be 1.8V.

Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship

SET

between ICP and R

I



CPmax

R

SET

is

SET

where:

I

= 5 mA.

CPmax

R

= 5.1 kΩ.

SET

Rev. PrC | Page 7 of 35

ADF4159 Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS

TBD

Figure 5.

TBD

TBD

Figure 8

TBD

Figure 6

TBD

Figure 7.

Rev. PrC | Page 8 of 35

TBD

Figure 9.

Figure 10

Preliminary Technical Data ADF4159

POWER-DOWN

08728-016

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.

CONTROL

25-BIT FIXED MODULUS

The ADF4159 has a 25-bit fixed modulus. This allows output
frequencies to be spaced with a resolution of

f

= f

RES

where f
(PFD). For example, with a PFD frequency of 10 MHz,
frequency steps of 0.298 Hz are possible.

/225 (1)

PFD

is the frequency of the phase frequency detector

PFD

100kΩ

NC

REF

IN

NC

SW2

SW1

SW3

NO

Figure 11. Reference Input Stage

BUFFER

TO R-COUNTER

08728-027

RF INPUT STAGE

The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.

1.6V

2kΩ 2kΩ

AV

DD

AGND

RFINA

RFINB

BIAS

GENERATOR

Figure 12. RF Input Stage

INT, FRAC, AND R RELATIONSHIP

The INT and FRAC values, in conjunction with the R-counter,
make it possible to generate output frequencies that are spaced
by fractions of the phase frequency detector (PFD). The RF
VCO frequency (RF

RF

= f

OUT

PFD

where:

RF

is the output frequency of external voltage controlled

OUT

oscillator (VCO).

INT is the preset divide ratio of binary 12-bit counter (23 to 4095).
FRAC is the numerator of the fractional division (0 to 225 − 1).

f

= REFIN × [(1 + D)/(R × (1 + T))] (3)

PFD

where:
REFIN is the reference input frequency.
D is the REFIN doubler bit (0 or 1).
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary, 5-bit, programmable

reference counter (1 to 32).

FROM RF

INPUT STAGE

08728-015

) equation is

OUT

× (INT + (FRAC/225)) (2)

RF N-DIVIDER

N-COUNTER

N = INT + FRAC/MOD

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

TO PFD

RF INT DIVIDER

The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 23 to 4095 are allowed.

Rev. PrC | Page 9 of 35

INT

REG

Figure 13. RF N-Divider

MOD
REG

FRAC

VALUE

R-COUNTER

The 5-bit R-counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 32 are allowed.

ADF4159 Preliminary Technical Data

+IN

MUXOUT

PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP

The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 shows a simplified sche­matic of the PFD. The PFD includes a fixed delay element that
sets the width of the antibacklash pulse, which is typically 3 ns.
This pulse ensures that there is no dead zone in the PFD transfer
function and gives a consistent reference spur level.

HIGH

HIGH

–IN

UP

Q1D1

U1

CLR1

DELAY

CLR2

DOWN

Q2D2

U2

Figure 14. PFD Simplified Schematic

U3

CHARGE

PUMP

CP

08728-017

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4159 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by the M4, M3, M2, and M1 bits
(see Figure 18). Figure 15 shows the MUXOUT section in
block diagram form.

DV

THREE-STATE OUTPUT

DV

DD

DGND
R DIVIDER OUTPUT
N DIVIDER OUTPUT

DIGITAL LOCK DETECT

CLK DIVIDER OUTPUT

R DIVIDER/2
N DIVIDER/2

READBACK

MUX

Figure 15. MUXOUT Schematic

CONTROL

DD

DGND

INPUT SHIFT REGISTERS

The ADF4159 digital section includes a 5-bit RF R-counter,
a 12-bit RF N-counter, and a 25-bit FRAC counter. Data is
clocked into the 32-bit shift register on each rising edge of
CLK. The data is clocked in MSB first. Data is transferred
from the shift register to one of eight latches on the rising edge
of LE. The destination latch is determined by the state of the
three control bits (C3, C2, and C1) in the shift register. These
are the three LSBs—DB2, DB1, and DB0—as shown in Figure 2.
The truth table for these bits is shown in Table 6. Figure 16 and
Figure 17 show a summary of how the latches are programmed.

PROGRAM MODES

Table 6 and Figure 18 through Figure 25 show how to set up
the program modes in the ADF4159.

Several settings in the ADF4159 are double buffered. These
include the LSB fractional value, R-counter value, reference
doubler, current setting, and RDIV2. This means that two
events must occur before the part uses a new value for any
of the double-buffered settings. First, the new value is latched
into the device by writing to the appropriate register. Second,
a new write must be performed on Register R0.

For example, updating the fractional value can involve a write
to the 13 LSB bits in R1 and the 12 MSB bits in R0. R1 should
be written to first, followed by the write to R0. The frequency
change begins after the write to R0. Double buffering ensures
that the bits written to in R1 do not take effect until after
the write to R0.

Table 6. C3, C2, and C1 Truth Table

Control Bits

C3 C2 C1 Register

0 0 0 R0
0 0 1 R1
0 1 0 R2
0 1 1 R3
1 0 0 R4
1 0 1 R5
1 1 0 R6
1 1 1 R7

Rev. PrC | Page 10 of 35

Preliminary Technical Data ADF4159

C1(0)

FRAC/INT REGISTER (R0)

C1(1)

C1(1)

C1(0)

REGISTER MAPS

MUXOUT

CONTROL

RAMP ON

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R1 M4 M3 M2 M1 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 C3(0) C2(0)

12-BIT INTEGER VALUE (INT)

12-BIT MSB FRACTIONAL VALUE

(FRAC)

CONTROL

BITS

LSB FRAC REGISTER (R1)

RESERVED

PHASE ADJ

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 P1 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 0 0 0 0 0 0 0 0 0 0 0 0 C3(0) C2(0)

13-BIT LSB FRACTIONAL VALUE

(FRAC) (DBB)

12-BIT PHASE WORD

(DBB)

CONTROL

BITS

R DIVIDER REGISTER (R2)

DBB DBB

CURRENT

SETTING

RESERVED

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1)

CSR EN

RESERVED

RDIV2 DBB

PRESCALER

5-BIT R COUNTER

REFERENCE

DOUBLER DBB

12-BIT MOD DIVIDER

(DBB)

CONTROL

BITS

FUNCTION REGISTER (R3)

RESERVED

RESERVED

DB31

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 L1 NS1 U12 0 0 RM2 RM1 PE1 FE1 U11 U10 U9 U8 U7 C3(0) C2(1)

NOTES

1. DBB = DOUBLE BUFFERED BIT(S).

SD

RESET

N SEL

LOL EN

RESERVED

RAMP MODE

PSK ENABLE

LDP

FSK ENABLE

Figure 16. Register Summary 1

PD

PD

CP

RESET

POLARITY

COUNTER

THREE-STATE

CONTROL

BITS

Rev. PrC | Page 11 of 35