ANALOG DEVICES ADF4157 Service Manual
N
Frequency Synthesizer
ADF4157
Rev. C
Trademarks and registered trademarks are the property of their respective owners.
Fax: 781.461.3113 ©2007–2012 Analog Devices, Inc. All rights reserved.
LOCK
DETECT
N COUNTER
CP
RFCP3 RFCP2RFCP4 RFCP1
REFERENCE
DATA
LE
32-BIT
DATA
REGISTER
CLK
REF
IN
AV
DD
AGND
V
DD
V
DD
DGND
R
DIV
SD
OUT
N
DIV
DGND CPGND
DVDDV
P
CE
R
SET
RFINA
RF
IN
B
OUTPUT
MUX
MUXOUT
–
+
HIGH Z
PHASE
FREQUENCY
DETECTOR
ADF4157
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
2
25
FRACTION
REG
INTEGER
REG
CURRENT
SETTING
×2
DOUBLER
5-BIT
R COUNTER
CHARGE
PUMP
CSR
÷2
DIVIDER
05874-001
Data Sheet
FEATURES
RF bandwidth to 6 GHz
25-bit fixed modulus allows subhertz frequency resolution
2.7 V to 3.3 V power supply
Separate V
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with the following frequency synthesizers:
ADF4110/ADF4111/ADF4112/ADF4113/
ADF4106/ADF4153/ADF4154/ADF4156
Cycle slip reduction for faster lock times
APPLICATIONS
Satellite communications terminals, radar equipment
Instrumentation equipment
Personal mobile radio (PMR)
Base stations for mobile radio
Wireless handsets
allows extended tuning voltage
P
High Resolution 6 GHz Fractional-
GENERAL DESCRIPTION
The ADF4157 is a 6 GHz fractional-N frequency synthesizer with
a 25-bit fixed modulus, allowing subhertz frequency resolution
at 6 GHz. It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT and FRAC values
define an overall N divider, N = INT + (FRAC/2
features cycle slip reduction circuitry, which leads to faster lock
times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
25
). The ADF4157
FUNCTIONAL BLOCK DIAGRAM
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADF4157 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Circuit Description ........................................................................... 9
Reference Input Section ............................................................... 9
RF Input Stage ............................................................................... 9
RF INT Divider ............................................................................. 9
25-Bit Fixed Modulus .................................................................. 9
INT, FRAC, and R Relationship ................................................. 9
RF R Counter ................................................................................ 9
Phase Frequency Detector (PFD) and Charge Pump ............ 10
MUXOUT and Lock Detect ...................................................... 10
Input Shift Register..................................................................... 10
Program Modes .......................................................................... 10
Register Maps .................................................................................. 11
FRAC/INT Register (R0) Map.................................................. 12
LSB FRAC Register (R1) Map .................................................. 13
R Divider Register (R2) Map .................................................... 14
Function Register (R3) Map ..................................................... 16
Test Register (R4) Map .............................................................. 17
Applications Information .............................................................. 18
Initialization Sequence .............................................................. 18
RF Synthesizer: A Worked Example ........................................ 18
Reference Doubler and Reference Divider ............................. 18
Cycle Slip Reduction for Faster Lock Times ........................... 18
Fastlock Timer and Register Sequences .................................. 19
Fastlock: An Example ................................................................ 19
Fastlock: Loop Filter Topology ................................................. 19
Spur Mechanisms ....................................................................... 19
Low Frequency Applications .................................................... 20
Filter Design—ADIsimPLL....................................................... 20
Operating with Wide Loop Filter Bandwidths ....................... 20
PCB Design Guidelines for the Chip Scale Package .............. 20
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/12—Rev. B to Rev. C
Changes to Table 1 ............................................................................ 3
Changes to Ordering Guide .......................................................... 21
9/11—Rev. A to Rev. B
Changes to Noise Characteristics Parameter ................................ 3
Changes to EPAD Note .................................................................... 6
1/09—Rev. 0 to Rev. A
Changes to Figure 1 .......................................................................... 1
Changes to Reference Characteristics Parameter, Table 1 .......... 3
Changes to Table 3 ............................................................................ 5
Changes to Figure 4 and Table 5 ..................................................... 6
Changes to Figure 15 ...................................................................... 10
Changes to Figure 16 ...................................................................... 11
Rev. C | Page 2 of 24
Changes to Figure 17 ...................................................................... 12
Changes to Figure 19 ...................................................................... 15
Added Negative Bleed Current Section, CLK Divider Mode
Section, and 12-Bit Clock Divider Value Section....................... 17
Changes to Reserved Bits Section and Figure 21 ....................... 17
Deleted Interfacing Section ........................................................... 18
Added Fastlock Timer and Register Sequences Section,
Fastlock: An Example Section, and Fastlock: Loop Filter
Topology Section ............................................................................ 19
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Added Operating with Wide Loop Filter Bandwidths
Section .............................................................................................. 20
Updated Outline Dimensions ....................................................... 21
7/07—Revision 0: Initial Ver s i on
Data Sheet ADF4157
Parameter
B Version1
Unit
Test Conditions/Comments
RF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
0.5/6.0
GHz min/max
−10 dBm/0 dBm min/max; for lower frequencies, ensure slew rate
REFIN Input Sensitivity
0.4/AVDD
V p-p min/max
For 10 MHz < f
< 250 MHz, biased at AVDD/22
For 250 MHz < f
< 300 MHz, biased at AVDD/22
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
µA max
Phase Detector Frequency3
32
MHz max
CHARGE PUMP
ICP Sink/Source
Programmable
Low Value
312.5
µA typ
R
Range
2.7/10
kΩ min/max
ICP Three-State Leakage Current
1
nA typ
Sink and source current
ICP vs. VCP
2
% typ
0.5 V < VCP < VP – 0.5
ICP vs. Temperature
2
% typ
VCP = VP/2
LOGIC INPUTS
V
INL
, Input Low Voltage
0.6
V max
CIN, Input Capacitance
10
pF max
VOH, Output High Voltage
1.4
V min
Open-drain 1 kΩ pull-up to 1.8 V
VOL, Output Low Voltage
0.4
V max
IOL = 500 µA
AVDD
2.7/3.3
V min/max
VP
AVDD/5.5
V min/V max
IDD
29
mA max
23 mA typical
Normalized Phase Noise Floor
−211
dBc/Hz typ
PLL loop B/W = 500 kHz;
Normalized 1/f Noise (PN
)5
−110
dBc/Hz typ
10 kHz offset; normalized to 1 GHz
−133
dBc/Hz typ
@ 25 MHz PFD frequency
Phase Noise Performance7
@ VCO output
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
dBm referred to 50 Ω.
Table 1.
(SR) > 400 V/µs
REFERENCE CHARACTERISTICS
REFIN Input Frequency 10/300 MHz min/max For f
0.7/AVDD V p-p min/max
PHASE DETECTOR
to T
MIN
< 10 MHz, ensure slew rate > 50 V/µs
REFIN
, unless otherwise noted;
MAX
REFIN
REFIN
High Value 5 mA typ With R
Absolute Accuracy 2.5 % typ With R
SET
= 5.1 kΩ
SET
= 5.1 kΩ
SET
Matching 2 % typ 0.5 V < VCP < VP – 0.5
V
, Input High Voltage 1.4 V min
INH
I
, Input Current ±1 µA max
INH/IINL
LOGIC OUTPUTS
VOH, Output High Voltage VDD – 0.4 V min CMOS output chosen
POWER SUPPLIES
DVDD AVDD
Low Power Sleep Mode 10 µA typ
NOISE CHARACTERISTICS
(PN
SYNTH
4
)
1_f
measured at 100 kHz
Phase Noise Floor6 −137 dBc/Hz typ @ 10 MHz PFD frequency
5800 MHz Output8 −87 dBc/Hz typ @ 2 kHz offset, 25 MHz PFD frequency
1
Operating temperature of B version is −40°C to +85°C.
2
AC-coupling ensures AVDD/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN
6
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
7
The phase noise is measured with the EV-ADF4157SD1Z and the Agilent E5052A phase noise system.
8
f
= 100 MHz; f
REFIN
). PN
= PN
PFD
SYNTH
= 25 MHz; offset frequency = 2 kHz; RF
PFD
− 10 log(F
TOT
PFD
+ 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
1_f
) − 20 log(N).
= 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
OUT
Rev. C | Page 3 of 24
ADF4157 Data Sheet
CLK
DATA
LE
LE
DB23 (MSB) DB22
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
05874-002
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
dBm referred to 50 Ω.
Table 2.
Parameter Limit at T
MIN
to T
(B Version) Unit Test Conditions/Comments
MAX
t1 20 ns min LE setup time
t2 10 ns min Data to clock setup time
t3 10 ns min Data to clock hold time
t4 25 ns min Clock high duration
t5 25 ns min Clock low duration
t6 10 ns min Clock to LE setup time
t7 20 ns min LE pulse width
MIN
to T
, unless otherwise noted;
MAX
Figure 2. Timing Diagram
Rev. C | Page 4 of 24
Data Sheet ADF4157
REFIN, RFINx to AGND/DGND
−0.3 V to VDD + 0.3 V
Package Type
θ
Unit
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted.
Table 3.
Parameter Rating
AVDD/DVDD to AGND/DGND −0.3 V to +4 V
AVDD to DVDD −0.3 V to +0.3 V
VP to AGND/DGND −0.3 V to +5.8 V
VP to AVDD/DVDD −0.3 V to +5.8 V
Digital I/O Voltage to AGND/DGND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to AGND/DGND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
JA
TSSOP 112 °C/W
LFCSP (Paddle Soldered) 30.4 °C/W
ESD CAUTION
Rev. C | Page 5 of 24
ADF4157 Data Sheet
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CP
CPGND
AGND
AV
DD
RF
IN
A
RF
IN
B
R
SET
DV
DD
MUXOUT
LE
CE
REF
IN
DGND
CLK
DATA
V
P
ADF4157
TOP VIEW
(Not to S cale)
05874-003
PIN 1
INDICATOR
1CPGND
2AGND
3AGND
4RF
IN
B
5RF
IN
A
13 DATA
14 LE
15 MUXOUT
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED PAD
BE THERMALLY CONNECTED TO A COPPE R
PLANE FO R E NHANCE D THERMAL PERF ORMANCE.
THIS PAD SHOULD BE CONNECT E D TO AGND.
12 CLK
11 CE
6AVDD7AVDD8REF
IN
10DGND
9DGND
18
V
P
19
R
SET
20
CP
17
DV
DD
16
DV
DD
TOP VIEW
(Not to S cale)
ADF4157
05874-004
7
6, 7
AVDD
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
TSSOP
Pin No.
1 19 R
LFCSP
Pin No. Mnemonic Description
Connecting a resistor between this pin and ground sets the maximum charge pump output
SET
current.
The relationship between I
5.25
I
CPMAX
=
R
SET
and R
CP
where:
R
= 5.1 kΩ.
SET
= 5 mA.
I
CPMAX
2 20 CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter, which, in
turn, drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane
with a small bypass capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
should be placed as close as possible to this pin. AVDD has a value of 3 V ± 10%. AVDD must have
the same voltage as DV
.
DD
8 8 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent
input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it
can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode.
11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
12 13 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits.
13 14 LE Load Enable, CMOS Input. When LE is high, the data stored in the input shift register is loaded
14 15 MUXOUT This multiplexer output allows the lock detect, the scaled RF, or the scaled reference frequency
latched into the input shift register on the CLK rising edge. This input is a high impedance
CMOS input.
This input is a high impedance CMOS input.
into one of the five latches, with the latch selected using the control bits.
to be accessed externally.
Rev. C | Page 6 of 24
SET
Figure 4. LFCSP Pin Configuration
is
Data Sheet ADF4157
TSSOP
Pin No.
15 16, 17 DVDD Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground
16 18 VP Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD
17 (EPAD) 21 (EPAD) Exposed Pad
LFCSP
Pin No. Mnemonic Description
plane should be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD
must have the same voltage as AV
is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
It is recommended that the exposed pad be thermally connected to a copper plane for
(EPAD)
enhanced thermal performance. The pad should be connected to AGND.
.
DD
Rev. C | Page 7 of 24
ADF4157 Data Sheet
10
–40
0 9
FREQUENCY ( GHz)
POWER (dBm)
5
0
–5
–10
–15
–20
–25
–30
–35
1 2 3 4 5 6 7 8
P = 4/5
P = 8/9
05874-016
0
–40
0 500
FREQUENCY (MHz)
POWER (dBm)
–5
–10
–15
–20
–25
–30
–35
100 200 300 400
V
DD
= 3V
05874-017
0
–160
1k 10M
FREQUENCY ( Hz )
PHASE NOISE (dBc/Hz)
–20
–40
–60
–80
–100
–120
–140
10k 100k 1M
RF = 5800.25MHz, P FD = 25MHz, N = 232,
FRAC = 335544, FREQUENCY RESOLUTION = 0.74Hz,
20kHz LOOP BW, I
CP
= 313µA, DSB INTEGRATED P HAS E
ERROR = 0.97° RM S , PHASE NOIS E @ 2kHz = –87dBc/Hz.
05874-018
6.00
5.65
–100 900
TIME (µs)
FREQUENCY ( GHz)
5.95
5.90
5.85
5.80
5.75
5.70
0 100 200 300 400 500 600 700 800
CSR OFF
CSR ON
05874-019
5.65
5.60
5.95
5.90
5.85
5.80
5.75
5.70
–100 900
TIME (µs)
FREQUENCY ( GHz)
0 100 200 300 400 500 600 700 800
CSR ON
CSR OFF
05874-020
6
–6
0 5.0
05874-021
VCP (V)
I
CP
(mA)
4
2
0
–2
–4
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
TYPICAL PERFORMANCE CHARACTERISTICS
PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 μA, phase noise measurements taken on the Agilent E5052A
phase noise system.
Figure 5. RF Input Sensitivity
Figure 6. Reference Input Sensitivity
Figure 8. Lock Time for 200 MHz Jump from 5705 MHz to 5905 MHz
with CSR On and Off
Figure 9. Lock Time for 200 MHz Jump from 5905 MHz to 5705 MHz
with CSR On and Off
(Note that the 250 kHz spur is an integer boundary spur; see the Spur
Figure 7. Phase Noise and Spurs
Mechanisms section for more information.)
Figure 10. Charge Pump Output Characteristics, Pump Up and Pump Down
Rev. C | Page 8 of 24
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