AV
6.2 GHz Fractional-N Frequency Synthesizer
Data Sheet
FEATURES
RF bandwidth to 6.2 GHz
2.7 V to 3.3 V power supply
Separate V
Programmable fractional modulus
Programmable charge-pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,
ADF4106, ADF4153, and ADF4154 frequency synthesizers
Programmable RF output phase
Loop filter design possible with ADIsimPLL
Cycle slip reduction for faster lock times
APPLICATIONS
CATV equipment
Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs, PMR
Communications test equipment
pin allows extended tuning voltage
P
ADF4156
GENERAL DESCRIPTION
The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer
that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It
consists of a low noise digital phase frequency detector (PFD), a
precision charge pump, and a programmable reference divider.
There is a Σ- based fractional interpolator to allow programmable
fractional-N division. The INT, FRAC, and MOD registers define
an overall N divider (N = (INT + (FRAC/MOD))). The RF output
phase is programmable for applications that require a particular
phase relationship between the output and the reference. The
ADF4156 also features cycle slip reduction circuitry, leading
to faster lock times without the need for modifications to the
loop filter.
Control of all on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
REF
MUXOUT
CLOCK
DATA
IN
CE
LE
ADF4156
HIGH Z
×2
DOUBLER
OUTPUT
MUX
32-BIT
DATA
REGISTER
FUNCTIONAL BLOCK DIAGRAM
DV
DD
DDVP
5-BIT
AGND
R-COUNTER
V
DD
DGND
SD
OUT
V
DD
R
DIV
N
DIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOL ATOR
FRACTION
REG
DGND CPGND
DIVIDE R
MODULUS
REG
Figure 1.
/2
+
PHASE
FREQUENCY
DETECTOR
–
N-COUNTER
INTEGER
REG
R
SET
REFERENCE
CHARGE
PUMP
CURRENT
SETTING
RFCP3 RFCP2RFCP4 RFCP1
CSR
CP
RFINA
RF
IN
B
05863-001
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADF4156 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Register Maps.................................................................................. 10
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Impedance..................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 8
Reference Input Section............................................................... 8
RF Input Stage............................................................................... 8
RF INT Divider............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
FRAC/INT Register, R0............................................................. 11
Phase Register, R1 ...................................................................... 12
MOD/R Register, R2.................................................................. 13
Function Register, R3................................................................. 15
CLK DIV Register, R4................................................................ 16
Reserved Bits............................................................................... 16
Initialization Sequence .............................................................. 16
RF Synthesizer: A Worked Example........................................ 17
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus................................................ 17
Fast Lock Times with the ADF4156 ........................................ 17
Spur Mechanisms....................................................................... 19
Spur Consistency and Fractional Spur Optimization ........... 19
Phase Resync............................................................................... 20
Low Frequency Applications .................................................... 20
RF R-Counter................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect........................................................ 9
Input Shift Registers..................................................................... 9
Program Modes ............................................................................9
REVISION HISTORY
3/12—Rev. C to Rev. D
Changes to Table 1............................................................................ 3
Changes to Ordering Guide.......................................................... 22
9/11—Rev. B to Rev. C
Changes to Noise Characteristics Parameter................................ 3
4/11—Rev. A to Rev. B
Changes to Product Title, Features Section and General
Description Section .......................................................................... 1
Changes to RF Input Frequency RF
Changes to Figure 4 and Table 5..................................................... 6
5/09—Rev. 0 to Rev. A
Added Low Power Sleep Mode Parameter and Changes to
Endnote 4, Table 1 ............................................................................ 3
Change to Figure 9 Caption............................................................ 7
Change to Program Modes Section ............................................... 9
Changes to Figure 16...................................................................... 10
Parameter, Table 1........... 3
IN
Filter Design—ADIsimPLL....................................................... 20
Interfacing ................................................................................... 21
PCB Design Guidelines for Chip Scale Package .................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Changes to Figure 17...................................................................... 11
Changes to CSR Enable Section ................................................... 13
Changes to Figure 19...................................................................... 14
Changes to Function Register, R3 Section and Figure 20 ......... 15
Changes to 12-Bit Clock Divider Value Section, to
Clock Divider Mode Section, and to Figure 21.......................... 16
Changes to Reference Doubler and Reference Divider Section
and to Fast Lock Times with the ADF4156 Section .................. 17
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Change to Phase Resync Section.................................................. 20
Changes to Interfacing Section and to PCB Design Guidelines
for Chip Scale Package Section..................................................... 21
Changes to Outline Dimensions .................................................. 23
Changes to Ordering Guide.......................................................... 23
5/06—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet ADF4156
SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = T
Table 1.
Parameter B Version Unit Test Conditions/Comments1
RF CHARACTERISTICS
RF Input Frequency (RFIN) 0.5/6.2 GHz min/max −10 dBm min to 0 dBm max. For lower frequencies,
REFERENCE CHARACTERISTICS
REFIN Input Frequency 10/250 MHz min/max For f < 10 MHz, use a dc-coupled CMOS-compatible
REFIN Input Sensitivity 0.4/AVDD V p-p min/max Biased at AVDD/2.2
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 μA max
PHASE DETECTOR
Phase Detector Frequency3 32 MHz max
CHARGE PUMP
ICP Sink/Source Programmable.
High Value 5 mA typ With R
Low Value 312.5 μA typ
Absolute Accuracy 2.5 % typ With R
R
Range 2.7/10 kΩ min/max
SET
ICP Three-State Leakage Current 1 nA typ Sink and source current.
Matching 2 % typ 0.5 V < VCP < VP − 0.5.
ICP vs. VCP 2 % typ 0.5 V < VCP < VP − 0.5.
ICP vs. Temperature 2 % typ VCP = VP/2.
LOGIC INPUTS
V
, Input High Voltage 1.4 V min
INH
V
, Input Low Voltage 0.6 V max
INL
I
, Input Current ±1 μA max
INH/IINL
CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V min Open-drain output chosen; 1 kΩ pull-up to 1.8 V.
VOH, Output High Voltage VDD − 0.4 V min CMOS output chosen.
IOH, Output High Current 100 μA max
VOL, Output Low Voltage 0.4 V max IOL = 500 μA.
POWER SUPPLIES
AVDD 2.7/3.3 V min/max
DVDD AVDD
VP AVDD/5.5 V min/max
IDD 32 mA max 26 mA typical.
Low Power Sleep Mode 1 μA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN
)5 −110 dBc/Hz typ 10 kHz offset; normalized to 1 GHz.
1_f
)4 −220 dBc/Hz typ PLL loop BW = 500 kHz. Measured at 100 kHz offset.
SYNTH
Phase Noise Performance6 @ VCO output.
5800 MHz Output7 −89 dBc/Hz typ @ 5 kHz offset, 25 MHz PFD frequency.
1
Operating temperature for B version: −40°C to +85°C.
2
AC coupling ensures AVDD/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN
6
The phase noise is measured with the EV-ADF4156SD1Z evaluation board and the Agilent E5500 phase noise system.
7
f
= 100 MHz, f
REFIN
). PN
= PN
PFD
SYNTH
= 25 MHz, offset frequency = 5 kHz, RF
PFD
− 10 log(F
TOT
+ 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
1_f
) − 20 log(N).
PFD
= 5800 MHz, N = 232, loop bandwidth = 20 kHz, ICP = 313 μA, and lowest noise mode.
OUT
MIN
to T
, dBm referred to 50 Ω, unless otherwise noted.
MAX
ensure slew rate (SR) > 400 V/μs.
square wave, slew rate > 25 V/μs.
= 5.1 kΩ.
SET
= 5.1 kΩ.
SET
Rev. D | Page 3 of 24
ADF4156 Data Sheet
TIMING SPECIFICATIONS
AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = T
Table 2.
Parameter Limit at T
MIN
to T
(B Version) Unit Test Conditions/Comments
MAX
t1 20 ns min LE setup time
t2 10 ns min DATA to CLOCK setup time
t3 10 ns min DATA to CLOCK hold time
t4 25 ns min CLOCK high duration
t5 25 ns min CLOCK low duration
t6 10 ns min CLOCK to LE setup time
t7 20 ns min LE pulse width
Timing Diagram
t
4
CLOCK
to T
MIN
t
5
, dBm referred to 50 Ω, unless otherwise noted.
MAX
DATA
t
2
DB23 (MSB) DB22 DB2
LE
t
1
LE
t
3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
t
6
05863-002
Figure 2. Timing Diagram
Rev. D | Page 4 of 24
Data Sheet ADF4156
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD,
unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +4 V
VDD to VDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to VDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Maximum Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.
THERMAL IMPEDANCE
Table 4. Thermal Impedance
Package Type θJA Unit
TSSOP 112 °C/W
LFCSP_VQ (Paddle Soldered) 30.4 °C/W
ESD CAUTION
Rev. D | Page 5 of 24
ADF4156 Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DD
DD
SET
P
R
CP
20
R
SET
CP
CPGND
AGND
RF
IN
RFINA
AV
REF
B
DD
IN
1
2
3
ADF4156
TOP VIEW
4
(Not to Scale)
5
6
7
8
16
15
14
13
12
11
10
9
Figure 3. TSSOP Pin Configuration
V
P
DV
DD
MUXOUT
LE
DATA
CLOCK
CE
DGND
05863-003
1CPGND
2AGND
ADF4156
3AGND
TOP VIEW
4RF
B
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED T O GROUND.
A
5RF
(Not to Scale)
6
AV
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 R
2 20 CP
SET
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The
relationship between I
I
=
CPmax
R
SET
where R
= 5.1 kΩ and I
SET
and R
CP
5.25
CPmax
Charge-Pump Output. When enabled, this pin provides ±I
is
SET
= 5 mA.
to the external loop filter, which in turn drives
CP
the external VCO.
3 1 CPGND Charge-Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD
8 8 REFIN
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
DD
DD
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode.
11 12 CLOCK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input.
12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input.
13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch.
14 15 MUXOUT
Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally.
15 16, 17 DVDD
16 18 VP
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD.
DD
Charge-Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
EPAD The exposed pad must be connected to ground.
DV
DV
V
16
17
19
18
PIN 1
INDICATOR
8
7
IN
DD
DD
AV
REF
9
DGND
10
DGND
15 MUXO UT
14 LE
13 DATA
12 CLOCK
11 CE
05863-004
/2 and an equivalent input resistance
. In systems where VDD is 3 V, it can
DD
Rev. D | Page 6 of 24
Data Sheet ADF4156
TYPICAL PERFORMANCE CHARACTERISTICS
PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 A, phase noise measurements taken on the Agilent E5500
phase noise system.
10
5
0
–5
–10
P=4/5 P=8/9
–15
–20
POWER (dBm)
–25
–30
–35
–40
09
12345678
FREQUENCY (GHz)
05863-017
Figure 5. RF Input Sensitivity
0
LOW NOISE MODE
RF = 5800. 25MHz, P FD = 25MHz, N = 232,
–20
FRAC = 2, MOD = 200, 20kHz LOOP BW, I
–40
–60
–80
–100
–120
PHASE NOISE ( dBc/Hz)
–140
DSB INTEGRAT ED PHASE ERROR = 0.73° RMS,
–160
PHASE NOI SE @ 5kHz = –89.5d Bc/Hz,
ZCOMM V940ME03 VCO
–180
1k 100M
10k 100k 1M 10M
FREQUENCY (Hz)
CP
= 313µA,
05863-018
Figure 6. Phase Noise and Spurs, Low Noise Mode
0
LOW SPUR MODE
RF = 5800. 25MHz, PFD = 25M Hz, N = 232, FRAC = 2,
–20
MOD = 200, 20kHz L OOP BW, I
DSB INTEGRAT ED PHASE ERROR = 1. 09° RMS,
–40
PHASE NOI SE @ 5kHz = –83dBc/ Hz, ZCO MM V940M E03 VCO
–60
–80
–100
–120
PHASE NOISE ( dBc/Hz)
–140
–160
–180
1k 100M
10k 100k 1M 10M
FREQUENCY (Hz)
CP
= 313µA,
05863-019
Figure 7. Phase Noise and Spurs, Low Spur Mode
(Note that Fractional Spurs Are Removed and Only
the Integer Boundary Spur Remains in Low Spur Mode)
Rev. D | Page 7 of 24
6.00
5.95
5.90
5.85
5.80
FREQUENCY (G Hz)
5.75
5.70
5.65
–100 900
0 100 200 300 400 500 600 700 800
CSR ON
CSR OFF
TIME (µs)
Figure 8. Lock Time for 200 MHz Jump, from 5705 MHz to 5905 MHz,
with CSR On and Off
5.95
5.90
5.85
5.80
5.75
FREQUENCY (G Hz)
5.70
5.65
5.60
–100 900
0 100 200 300 400 500 600 700 800
CSR OFF
CSR ON
TIME (µs)
Figure 9. Lock Time for 200 MHz Jump, from 5905 MHz to 5705 MHz,
with CSR On and Off
6
5
4
3
2
1
(mA)
0
CP
I
–1
–2
–3
–4
–5
–6
012345
VCP(V)
Figure 10. Charge-Pump Output Characteristics
05863-021
05863-022
05863-020
ADF4156 Data Sheet
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 11. While the
device is operating, SW1 and SW2 are usually closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
pin is not loaded while the device is powered down.
IN
POWER-DOW N
CONTROL
100kΩ
NC
REF
IN
NC
SW2
SW1
SW3
NO
Figure 11. Reference Input Stage
BUFFER
TO R-COUNTER
5863-005
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
two-stage limiting amplifier to generate the current-mode logic
(CML) clock levels needed for the prescaler.
1.6V
AV
DD
2kΩ2kΩ
RF
IN
RFINB
BIAS
GENERATOR
A
RF INT DIVIDER
The RF INT counter allows a division ratio in the PLL feedback
counter. Division ratios from 23 to 4095 are allowed.
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced
by fractions of the phase frequency detector (PFD). See the RF
Synthesizer: A Worked Example section for more information.
The RF VCO frequency (RF
= F
RF
where RF
OUT
× (INT + (FRAC/MOD)) (1)
PFD
is the output frequency of an external voltage-
OUT
controlled oscillator (VCO).
F
= REFIN × [(1 + D)/(R × (1 + T))] (2)
PFD
where:
REF
is the reference input frequency.
IN
D is the REF
T is the REF
doubler bit.
IN
divide-by-2 bit (0 or 1).
IN
R is the preset divide ratio of the binary 5-bit programmable
reference counter (1 to 32).
INT is the preset divide ratio of the binary 12-bit counter
(23 to 4095).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
RF N-DIVIDER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
N-COUNTER
) equation is
OUT
INTERPOL ATOR
THIRD-ORDER
FRACTIONAL
TO PFD
MOD
REG
Figure 12. RF Input Stage
AGND
05863-006
INT
REG
Figure 13. RF INT Divider
FRAC
VALUE
05863-007
RF R-COUNTER
Rev. D | Page 8 of 24
The 5-bit RF R-counter allows the input reference frequency
) to be divided down to produce the reference clock to
(REF
IN
the PFD. Division ratios from 1 to 32 are allowed.
Data Sheet ADF4156
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 14 is a simplified schematic of the
phase frequency detector. The PFD includes a fixed-delay element
that sets the width of the antibacklash pulse, which is typically 3 ns.
This pulse ensures that there is no dead zone in the PFD transfer
function and results in a consistent reference spur level.
HI
+IN
HI
–IN
UP
Q1D1
U1
CLR1
U3
CLR2
U2
DELAY
DOWN
Q2D2
Figure 14. PFD Simplified Schematic
CHARGE
PUMP
CP
05863-008
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4156 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M4, M3, M2, and M1 (for details,
see Figure 16). Figure 15 shows the MUXOUT section in block
diagram form.
THREE-STATE OUTPUT
DV
DGND
R-DIVIDER OUTPUT
N-DIVIDER OUTPUT
ANALOG LO CK DETECT
DIGITAL LOCK DETECT
SERIAL DATA OUTPUT
CLOCK DIVI DER OUTPUT
R-DIVIDER/2
N-DIVIDER/2
DD
MUX
Figure 15. MUXOUT Schematic
CONTROL
DV
DGND
DD
MUXOUT
05863-009
INPUT SHIFT REGISTERS
The ADF4156 digital section includes a 5-bit RF R-counter,
a 12-bit RF N-counter, a 12-bit FRAC counter, and a 12-bit
modulus counter. Data is clocked into the 32-bit shift register
on each rising edge of CLOCK. The data is clocked in MSB first.
Data is transferred from the shift register to one of five latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. These bits are the three LSBs (DB2, DB1, and DB0), as
shown in Figure 2. The truth table for these bits is shown in
Tabl e 6 . Figure 16 shows a summary of how the latches are
programmed.
PROGRAM MODES
Tabl e 6 and Figure 16 through Figure 21 show how to set up the
program modes in the ADF4156.
Several settings in the ADF4156 are double buffered, including
the modulus value, phase value, R-counter value, reference doubler,
reference divide-by-2, and current setting. This means that two
events must occur before the part can use a new value for any of
the double buffered settings. The new value must first be latched
into the device by writing to the appropriate register, and then a
new write must be performed on Register R0. For example, after
the modulus value is updated, Register R0 must be written to in
order to ensure that the modulus value is loaded correctly.
Table 6. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 Register R0
0 0 1 Register R1
0 1 0 Register R2
0 1 1 Register R3
1 0 0 Register R4
Rev. D | Page 9 of 24
ADF4156 Data Sheet
REGISTER MAPS
FRAC/INT REGISTER (R0)
RE-
SERVED
MUXOUT CO NTROL 12-BIT I NTEGER VALUE (I NT) 12-BIT F RACTIONAL VALUE ( FRAC)
DB31 DB30 DB29 DB28 DB27 DB 26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 D B17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 M4 M3 M2 M1 N12 N11 N10 N9
N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F 7 F6 F 5 F4 F3 F2 F 1 C3( 0) C2(0) C1(0)
PHASE REGISTER (R1)
RESERVED 12-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0000000 00
0 0 0 0 0 0 0 0 P12 P11 P10 P9 P8 P 7 P6 P5 P4 P3 P 2 P1 C3( 0) C2(0) C1(1)
1
MOD/R REGISTER (R2)
1
CONTROL
BITS
CONTROL
BITS
NOISE
MODE
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 C1 CPI4 CP I3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 M12 M11 M10 M9 M8 M7 M6 M 5 M4 M3 M2 M 1 C3(0) C2( 1) C1(0)
CURRENT
1
SETTING
CSR EN
RESERVED
PRESCALER
RDIV21REFERENCE
5-BIT R CO UNTER
DOUBLER
1
12-BIT MODULUS WORD
1
CONTROL
BITS
FUNCTION REGISTER (R3)
RESERVED RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000000000000U12000000U7U6U5U4U3C3(0)C2(1)C1(1)
Σ-∆ RESET
LDPPDPOLARITY
PD
CP THREE-
CONTROL
STATE
BITS
COUNTER
RESET
CLK DIV REGISTER (R4)
CLK
DIV
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 C3(1) C2(0) C1(0)
1
DOUBLE BUFFERED BIT.
12-BIT CL OCK DIVI DER VALUE
RESERVEDRESERVED
CONTROL
BITS
Figure 16. Register Summary
05863-010
Rev. D | Page 10 of 24
Data Sheet ADF4156
FRAC/INT REGISTER, R0
With the control bits (Bits[2:0]) of Register R0 set to 000, the
on-chip FRAC/INT register is programmed. Figure 17 shows
the input data format for programming this register.
12-Bit Integer Value (INT)
These 12 bits control what is loaded as the INT value. This
determines the overall feedback division factor. It is used in
Equation 1 (see the INT, FRAC, MOD, and R Relationship
section).
12-Bit Fractional Value (FRAC)
These 12 bits control what is loaded as the FRAC value into
the fractional interpolator. This is part of what determines the
overall feedback division factor. It is also used in Equation 1.
The FRAC value must be less than the value loaded into the
MOD register.
MUXOUT
The on-chip multiplexer is controlled by DB30, DB29, DB28,
and DB27 on the ADF4156. See Figure 17 for the truth table.
RE-
SERVED
MUXOUT CONT ROL 12- BIT INTE GER VALUE ( INT) 12-BIT FRACTI ONAL VAL UE (FRAC)
DB31 DB30 DB29 DB28 DB27 DB26 DB2 5 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB1 5 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 M4 M3 M2 M1 N12 N11 N10 N9
M4 M3 M2 M1 OUTPUT
0 0 0 0 THREE-STATE O UTPUT
00 01DV
0 0 1 0 DGND
0 0 1 1 R-DIVIDER OUTP UT
0 1 0 0 N-DIVIDER OUTP UT
0 1 0 1 ANALOG LOCK DET ECT
0 1 1 0 DIGITAL LO CK DETECT
0 1 1 1 SERIAL DATA OUT PUT
1 0 0 0 RESERVED
1 0 0 1 RESERVED
1 0 1 0 CLOCK DIVIDER
1 0 1 1 RESERVED
1 1 0 0 FAST- LOCK SWITCH
1 1 0 1 R-DIVIDER/2
1 1 1 0 N-DIVIDER/2
1 1 1 1 RESERVED
DD
N12N11N10N9N8N7N6N5N4N3N2N1 INTEGER VALUE (INT)
000000010111 23
000000011000 24
000000011001 25
000000011010 26
............ .
............ .
............ .
111111111101 4093
111111111110 4094
111111111111 4095
N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F 7 F6 F 5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC)
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 ......... 1 1 4095
CONTROL
BITS
Figure 17. FRAC/INT Register (R0) Map
5863-011
Rev. D | Page 11 of 24
ADF4156 Data Sheet
PHASE REGISTER, R1
With the control bits (Bits[2:0]) of Register R1 set to 001, the
on-chip phase register is programmed. Figure 18 shows the
input data format for programming this register.
12-Bit Phase Value
These 12 bits control what is loaded as the phase word. The
word must be less than the MOD value programmed in the
MOD/R register (R2). The word is used to program the RF
output phase from 0° to 360° with a resolution of 360°/MOD.
See the Phase Resync section for more information. In most
applications, the phase relationship between the RF signal and
the reference is not important. In such applications, the phase
value can be used to optimize the fractional and subfractional
spur levels. See the Spur Consistency and Fractional Spur
Optimization section for more information.
If neither the phase resync nor the spurious optimization
functions are being used, it is recommended that the phase
value be set to 1.
RESERVED 12-BIT PHASE VALUE (PHASE)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000 0
0 0 0 0 0 0 0 0 P12 P11 P 10 P9 P8 P 7 P6 P5 P4 P3 P 2 P1 C3(0) C2( 0) C1(1)
P12 P11 ..... ..... P2 P1 PHASE VALUE (PHASE)
0 0 .......... 0 0 0
0 0 .......... 0 1 1 (RECOMMENDED)
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . ..... ..... . . .
. . ..... ..... . . .
. . ..... ..... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
CONTROL
BITS
Figure 18. Phase Register (R1) Map
5863-012
Rev. D | Page 12 of 24
Data Sheet ADF4156
MOD/R REGISTER, R2
With the control bits (Bits[2:0]) of Register R1 set to 010, the
on-chip MOD/R register is programmed. Figure 19 shows the
input data format for programming this register.
Noise and Spur Mode
The noise modes on the ADF4156 are controlled by DB30 and
DB29 in the MOD/R register. See Figure 19 for the truth table.
The noise modes allow the user to optimize a design either for
improved spurious performance or for improved phase noise
performance.
When the lowest spur setting is chosen, dither is enabled. This
randomizes the fractional quantization noise so that it resembles
white noise, rather than spurious noise. As a result, the part is
optimized for improved spurious performance. This operation
is typically used when the PLL closed-loop bandwidth is wide
for fast-locking applications. Wide loop bandwidth is defined as
a loop bandwidth greater than 1/10 of the RF
resolution (f
). A wide loop filter does not attenuate the spurs
RES
to the same level as a narrow loop bandwidth.
For best noise performance, use the lowest noise setting option.
As well as disabling the dither, using the lowest noise setting
ensures that the charge pump is operating in an optimum
region for noise performance. This setting is useful if a narrow
loop filter bandwidth is available. The synthesizer ensures
extremely low noise, and the filter attenuates the spurs. The
typical performance characteristics show the trade-offs in a
typical WCDMA setup for various noise and spur settings.
CSR Enable
Setting this bit to 1 enables cycle slip reduction, which can
improve lock times. Note that the signal at the phase frequency
detector (PFD) must have a 50% duty cycle for cycle slip
reduction to work. The charge-pump current setting must also
be set to a minimum value. See the Fast Lock Times section for
more information. Note that CSR cannot be used if the phase
detector polarity is set to negative.
Charge-Pump Current Setting
DB[27:24] set the charge-pump current setting. These bits
should be set to the charge-pump current as indicated by the
loop filter design (see Figure 19).
Prescaler (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the INT,
FRAC, and MOD counters, determines the overall division ratio
from the RF
to the PFD input.
IN
channel step
OUT
Operating at CML levels, the prescaler uses the clock from the
RF input stage and divides it down for the counters. The prescaler
is based on a synchronous 4/5 core. When it is set to 4/5, the
maximum RF frequency allowed is 3 GHz. Therefore, when
operating the ADF4156 with frequencies greater than 3 GHz,
the prescaler must be set to 8/9. The prescaler limits the INT
value as follows:
With P = 4/5, N
With P = 8/9, N
MIN
MIN
= 23
= 75
RDIV/2
Setting this bit to 1 inserts a divide-by-2 toggle flip-flop
between the R-counter and PFD, which extends the maximum
input rate.
REF
IN
Reference Doubler
Setting DB20 to 0 feeds the REFIN signal directly into the 5-bit
RF R-counter, disabling the doubler. Setting this bit to 1 multiplies
the REF
R-counter. When the doubler is disabled, the REF
frequency by a factor of 2 before feeding it into the 5-bit
IN
falling edge
IN
is the active edge at the PFD input to the fractional synthesizer.
When the doubler is enabled, both the rising and falling edges
of REF
become active edges at the PFD input.
IN
When the doubler is enabled and the lowest spur mode is chosen,
the in-band phase noise performance is sensitive to the REF
IN
duty cycle. The phase noise degradation can be as much as 5 dB
for REF
phase noise is insensitive to the REF
duty cycles that are outside a 45% to 55% range. The
IN
duty cycle when the device
IN
is in the lowest noise mode and when the doubler is disabled.
The maximum allowable REF
frequency when the doubler is
IN
enabled is 30 MHz.
5-Bit R-Counter
The 5-bit R-counter allows the input reference frequency
) to be divided down to produce the reference clock to
(REF
IN
the phase frequency detector (PFD). Division ratios from
1 to 32 are allowed.
12-Bit Interpolator MOD Value
This programmable register sets the fractional modulus, which is
the ratio of the PFD frequency to the channel step resolution on
the RF output. Refer to the RF Synthesizer: A Worked Example
section for more information.
Rev. D | Page 13 of 24
ADF4156 Data Sheet
NOISE
MODE
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L 2 L1 C1 CPI4 CPI3 CPI2 CPI1 0 P1 U2 U1 R5 R4 R3 R2 R1 M12 M11 M10 M9 M 8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(1) C1(0)
C1
0 DISABLED
1 ENABLED
L2 L1 NOISE MODE
0 0 LOW NOISE MO DE
0 1 RESERVED
1 0 RESERVED
1 1 LOW SPUR MODE
1
CYCLE SLIP RE DUCTION CANNOT BE USE D IF THE PHASE DETECTOR POL ARITY IS S ET TO NEGAT IVE.
CURRENT
SETTING
CSR EN
CYCLE SLIP
REDUCTION
1
CPI4 CPI3 CPI2 CPI1
00000.31
00010.63
00100.94
00111.25
01001.57
01011.88
01102.19
01112.5
10002.81
10013.13
10103.44
10113.75
11004.06
11014.38
11104.69
11115.0
RESERVED
PRESCALER
U2 R-DIVIDER
0 DI SABLED
1 ENABL ED
P1 PRESCALER
04/5
18/9
(mA)
I
CP
5.1kΩ
RDIV2
REFERENCE
DOUBLER
U1
0 DISABL ED
1 ENABLED
5-BIT R-COUNTER
REFERENCE
DOUBLER
R5 R4 R3 R2 R1 R-COUNTER DIVIDE RATIO
000011
000102
000113
001004
......
......
......
1110129
1111. 30
1111131
0000032
M12 M11 .......... M2 M1 INTERPOLATOR MO DULUS (MOD)
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .... ...... 0 0 4092
1 1 .... ...... 0 1 4093
1 1 .... ...... 1 0 4094
1 1 .... ...... 1 1 4095
12-BIT MODULUS WORD
CONTROL
BITS
Figure 19. MOD/R Register (R2) Map
05863-013
Rev. D | Page 14 of 24
Data Sheet ADF4156
FUNCTION REGISTER, R3
With the control bits (Bits[2:0]) of Register R2 set to 011, the
on-chip function register is programmed. Figure 20 shows the
input data format for programming this register.
Counter Reset
DB3 is the counter reset bit for the ADF4156. When this bit is
set to 1, the synthesizer counters are held in reset. For normal
operation, this bit should be 0.
Charge-Pump Three-State
When programmed to 1, DB4 puts the charge pump into threestate mode. This bit should be set to 0 for normal operation.
Power-Down
DB5 on the ADF4156 provides the programmable power-down
mode. Setting this bit to 1 performs a power-down. Setting this
bit to 0 returns the synthesizer to normal operation. While in
software power-down mode, the part retains all information in
its registers. Only when supplies are removed are the register
contents lost.
When a power-down is activated, the following events occur:
1. The synthesizer counters are forced to their load state
conditions.
2. The charge pump is forced into three-state mode.
3. The digital lock detect circuitry is reset.
4. The RF
5. The input register remains active and capable of loading
and latching data.
input is debiased.
IN
Phase Detector Polarity
DB6 in the ADF4156 sets the phase detector polarity. When the
VCO characteristics are positive, this bit should be set to 1.
When the characteristics are negative, DB6 should be set to 0.
Note that the cycle slip reduction function cannot be used if the
phase detector polarity is set to negative.
Lock Detect Precision (LDP)
When DB7 is programmed to 0, the digital lock detect is set
high when the phase error on 40 consecutive phase detector
cycles is less than 10 ns each. When this bit is programmed to 1,
40 consecutive phase detector cycles of less than 6 ns each must
occur before the digital lock detect is set.
Σ-Δ Reset
For most applications, DB14 should be programmed to 0. When
DB14 is programmed to 0, the Σ- modulator is reset to its starting
point, or starting phase word, on every write to Register R0. This
has the effect of producing consistent spur levels.
If it is not required that the Σ- modulator be reset on each
write to Register R0, DB14 should be set to 1.
RESERVED RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000000000000U12000000U11U10U9U8U7C3(0)C2(1)C1(1)
U12 Σ-∆ RESET
0 ENABL ED
1 DI SABLED
Figure 20. Function Register (R3) Map
Σ-∆ RESET
U11 LDP
010ns
16ns
U10 PD POLARITY
0NEGATIVE
1POSITIVE
LDP
PD
POLARITYPDCP THREE-
U8
0DISABLED
1 ENABLED
U9 POWER-DO WN
0 DI SABLED
1 ENABL ED
CONTROL
STATE
BITS
COUNTER
RESET
COUNTER
U7
RESET
0DISABLED
1 ENABLE D
CP
THREE-STATE
Rev. D | Page 15 of 24
05863-014
ADF4156 Data Sheet
CLK DIV REGISTER, R4
With the control bits (Bits[2:0]) of Register R3 set to 100, the
on-chip clock divider register (R4) is programmed. Figure 21
shows the input data format for programming this register.
12-Bit Clock Divider Value
The 12-bit clock divider value sets the timeout counter for
activation of the fast-lock mode or a phase resync. See the Phase
Resync section for more information.
Clock Divider Mode
DB[20:19] control the mode of the clock divider in the ADF4156.
These bits should be set to 01 to activate the fast-lock mode, or
to 10 to activate a phase resync. In most applications, neither a
fast lock nor a phase resync is required. In this case, DB[20:19]
should be set to 00.
CLK
DIV
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 M2 M1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 R4 R3 R2 R1 C3(1) C2(0) C1(0)
RESERVED BITS
All reserved bits should be set to 0 for normal operation.
INITIALIZATION SEQUENCE
After powering up the part, the correct register programming
sequence is as follows:
1. CLK DIV register (R4)
2. Function register (R3)
3. MOD/R register (R2)
4. Phase register (R1)
5. FRAC/INT register (R0)
CONTROL
12-BIT CLOCK DIVIDER VALUE
RESERVEDRESERVED
BITS
M2 M1 CLK DIV MODE
0 0 CLK DIV OFF
0 1 FAST -LOCK M ODE
1 0 RESYNC TIMER ENABLED
1 1 RESERVED
D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
05863-015
Figure 21. CLK DIV Register (R4) Map
Rev. D | Page 16 of 24
Data Sheet ADF4156
RF SYNTHESIZER: A WORKED EXAMPLE
The following equation governs how the synthesizer should be
programmed:
RF
= [INT + (FRAC/MOD)] × [F
OUT
] (3)
PFD
where:
RF
is the RF frequency output.
OUT
INT is the integer division factor.
FRAC is the fractionality.
MOD is the modulus.
The PFD frequency can be calculated as follows:
F
= REFIN × [(1 + D)/(R × (1 + T))] (4)
PFD
where:
REF
is the reference frequency input.
IN
D is the RF REF
doubler bit.
IN
T is the reference divide-by-2 bit, which is set to 0 or 1.
R is the RF reference division factor.
For example, in a GSM 1800 system, 1.8 GHz RF frequency
output (RF
(REF
IN
) is required, 13 MHz reference frequency input
OUT
) is available, and 200 kHz channel resolution (f
RES
) is
required on the RF output.
MOD = REF
IN/fRES
MOD = 13 MHz/200 kHz = 65
Therefore, from Equation 4,
F
= [13 MHz × (1 + 0)/1] = 13 MHz (5)
PFD
1.8 GHz = 13 MHz × (INT + FRAC/65) (6)
where INT = 138 and FRAC = 30.
MODULUS
The choice of modulus (MOD) depends on the reference signal
) available and the channel resolution (f
(REF
IN
the RF output. For example, a GSM system with 13 MHz REF
) required at
RES
IN
sets
the modulus to 65, resulting in the required RF output resolution
(f
) of 200 kHz (13 MHz/65). With dither off, the fractional spur
RES
interval depends on the modulus values chosen. See Table 7 for
more information.
REFERENCE DOUBLER AND REFERENCE DIVIDER
The on-chip reference doubler allows the input reference signal
to be doubled. This is useful for increasing the PFD comparison
frequency, which in turn improves the noise performance of the
system. Doubling the PFD frequency usually improves noise
performance by 3 dB. It is important to note that the PFD cannot
operate with frequencies greater than 32 MHz due to a limitation
in the speed of the Σ- circuit of the N-divider.
for the correct operation of the cycle slip reduction (CSR)
function. See the Fast Lock Times section for more information.
12-BIT PROGRAMMABLE MODULUS
Unlike most other fractional-N PLLs, the ADF4156 allows the user
to program the modulus over a 12-bit range. Therefore, several
configurations of the ADF4156 are possible for an application by
varying the modulus value, the reference doubler, and the 5-bit
R-counter.
For example, consider an application that requires 1.75 GHz RF
and 200 kHz channel step resolution. The system has a 13 MHz
reference signal.
One possible setup is feeding the 13 MHz directly into the PFD
and programming the modulus to divide by 65. This results in
the required 200 kHz resolution.
Another possible setup is using the reference doubler to create
26 MHz from the 13 MHz input signal. The 26 MHz signal is then
fed into the PFD, which programs the modulus to divide by 130.
This setup also results in 200 kHz resolution, but offers superior
phase noise performance compared with the previous setup.
The programmable modulus is also useful for multistandard
applications. If a dual-mode phone requires PDC and GSM
1800 standards, the programmable modulus is a great benefit.
The PDC requires 25 kHz channel step resolution, whereas
GSM 1800 requires 200 kHz channel step resolution.
A 13 MHz reference signal can be fed directly into the PFD, and
the modulus can be programmed to 520 when in PDC mode
(13 MHz/520 = 25 kHz). However, the modulus must be
reprogrammed to 65 for GSM 1800 operation (13 MHz/65
= 200 kHz).
It is important that the PFD frequency remains constant (13 MHz).
This allows the user to design one loop filter that can be used in
both setups without running into stability issues. It is the ratio
of the RF frequency to the PFD frequency that affects the loop
design. By keeping this relationship constant, the same loop
filter can be used in both applications.
FAST LOCK TIMES WITH THE ADF4156
As mentioned in the Noise and Spur Mode section, the ADF4156
can be optimized for noise performance. However, in fast-locking
applications, the loop bandwidth needs to be wide; therefore,
the filter does not provide much attenuation of the spurs.
There are two methods of achieving a fast lock time for the
ADF4156: using cycle slip reduction or using dynamic bandwidth
switching mode. In both cases, the idea is to keep the loop bandwidth narrow to attenuate spurs while obtaining a fast lock time.
The reference divide-by-2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency. This is necessary
Rev. D | Page 17 of 24
Cycle slip reduction mode is the preferred technique because it
does not require modifications to the loop filter or optimization
of the timeout counter values and is therefore easier to implement.
ADF4156 Data Sheet
In most cases, this method also provides faster lock times than
the bandwidth switching mode method. In extreme cases, where
cycle slips do not exist in the settling transient, the bandwidth
switching mode can be used.
Cycle Slip Reduction Mode
Cycle slips occur in integer-N/fractional-N synthesizers when
the loop bandwidth is narrow compared with the PFD frequency.
The phase error at the PFD inputs accumulates too fast for the
PLL to correct, and the charge pump temporarily pumps in the
wrong direction. This slows down the lock time dramatically.
The ADF4156 contains a cycle slip reduction circuit to extend
the linear range of the PFD, allowing faster lock times without
requiring loop filter changes.
When the ADF4156 detects that a cycle slip is about to occur, it
turns on an extra charge-pump current cell. This either outputs
a constant current to the loop filter or removes a constant current
from the loop filter, depending on whether the VCO tuning
voltage needs to increase or decrease to acquire the new frequency.
As a result, the linear range of the PFD is increased. Stability is
maintained because the current is constant, not pulsed.
If the phase error increases to a point where another cycle slip
is likely, the ADF4156 turns on another charge-pump cell. This
process continues until the ADF4156 detects that the VCO
frequency is beyond the desired frequency. The extra charge-pump
cells then begin to turn off one by one until they are all turned
off and the frequency is settled.
Up to seven extra charge-pump cells can be turned on. In most
applications, this is sufficient to eliminate cycle slips altogether,
resulting in much faster lock times.
Setting Bit DB28 in the MOD/R register (R2) to 1 enables cycle
slip reduction. A 45% to 55% duty cycle is needed on the signal
at the PFD for CSR to operate correctly. Note that CSR cannot
be used if the phase detector polarity is set to negative; therefore,
a noninverting loop filter topology should be used with CSR.
Dynamic Bandwidth Switching Mode
The dynamic bandwidth switching mode involves increasing
the loop filter bandwidth for a set time at the beginning of the
locking transient. This is achieved by boosting the charge-pump
current from the set value in Register R2 to the maximum setting.
To maintain loop stability during this period, it is necessary to
modify the loop filter by adding a switch and resistor. When the
new frequency is programmed to the ADF4156 in this mode, three
events occur simultaneously to put the device in wideband mode:
• A timeout counter is started.
• The charge-pump current is boosted from its set current to
the maximum setting.
• The fast-lock switch (available via MUXOUT) is activated.
The timeout counter in Register R4 defines the period that the
device is kept in wideband mode. During wideband mode, the
PLL acquires lock faster due to the wider loop filter bandwidth.
Stability is maintained at the optimal 45° setting due to the use
of the extra resistor in the loop filter.
When the timeout counter times out, the charge-pump current
is reduced from the maximum setting to its set current, and the
fast-lock switch is deactivated. The device is then in narrowband mode, and spurs are attenuated.
To ensure optimum lock time, the timeout counter should be
set to time out when the PLL is close to the final frequency. If
the switch is deactivated, a spike in the settling transient will be
observed due to charge insertion from the switch. Because the
PLL is in narrow-band mode, this spike can take some time to
settle out. This is one of the disadvantages of the bandwidth
switching mode compared with the cycle slip reduction mode.
Fast Lock: An Example
If a PLL has a reference frequency of 13 MHz, a f
of 13 MHz,
PFD
and a required lock time of 50 µs, the PLL is set to wide bandwidth
for 40 µs.
If the time set for the wide bandwidth is 40 µs, then
Fast-Lock Timer Value = Time in Wide Bandwidth × f
PFD
Fast-Lock Timer Value = 40 µs × 13 MHz = 520
Therefore, 520 must be loaded into Bits DB[18:7] of Register R4.
The clock divider mode bits (DB[20:19]) in Register R4 must also
be set to 01 to activate this mode. To activate the fast-lock switch
on the MUXOUT pin, the MUXOUT control bits (DB[30:27])
in Register R0 must be set to 1100.
Fast Lock: Loop Filter Topology
To use fast-lock mode, an extra connection from the PLL to the
loop filter is needed. The damping resistor in the loop filter
must be reduced to ¼ of its value while in wide bandwidth
mode. This is required because the charge-pump current is
increased by 16 while in wide bandwidth mode and stability
must be ensured. When the ADF4156 is in fast-lock mode (that
is, when the fast-lock switch is programmed to appear at the
MUXOUT pin), the MUXOUT pin is automatically shorted to
ground. The following two topologies can be used:
• Topology 1: Divide the damping resistor (R1) into two
values (R1 and R1A) that have a ratio of 1:3 (see Figure 22).
• Topology 2: Connect an extra resistor (R1A) directly from
MUXOUT, as shown in Figure 23. The extra resistor must
be chosen such that the parallel combination of an extra
resistor and the damping resistor (R1) is reduced to ¼ of
the original value of R1 (see Figure 23).
Rev. D | Page 18 of 24
Data Sheet ADF4156
ADF4154
CP
C1
MUXOUT
Figure 22. Topology 1—Fast-Lock Loop Filter Topology
ADF4154
CP
C1
MUXOUT
R1R1A
C2
R1
R1A
C2
R2
VCO
C3
In low spur mode (dither enabled), the repeat length is extended
21
cycles, regardless of the value of MOD, which makes the
to 2
quantization error spectrum look like broadband noise. As a
result, the in-band phase noise at the PLL output can be degraded
by as much as 10 dB. Therefore, for lowest noise, keeping dither
off is a better choice, particularly when the final loop bandwidth is
low enough to attenuate even the lowest frequency fractional spur.
04833-029
Integer Boundary Spurs
Another mechanism for fractional spur creation is interactions
R2
VCO
C3
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (as is the case
with fractional-N synthesizers), spur sidebands appear on the
VCO output spectrum at an offset frequency that corresponds
to the beat note or the difference in frequency between an
integer multiple of the reference and the VCO frequency.
Figure 23. Topology 2—Fast-Lock Loop Filter Topology
SPUR MECHANISMS
04833-030
These spurs are attenuated by the loop filter and are more
noticeable on channels close to integer multiples of the
reference, where the difference frequency can be inside the loop
bandwidth, hence the name integer boundary spurs.
This section describes the three spur mechanisms that arise
with a fractional-N synthesizer and how to minimize these
spurs in the ADF4156.
Fractional Spurs
The fractional interpolator in the ADF4156 is a third-order Σ-
modulator with a modulus (MOD) that is programmable to any
integer value from 2 to 4095. In low spur mode (dither enabled),
the minimum allowable value of MOD is 50. The Σ- modulator
is clocked at the PFD reference rate (f
) that allows PLL output
PFD
frequencies to be synthesized at a channel step resolution of
f
/MOD.
PFD
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism that
bypasses the loop can cause a problem. One such mechanism is
feedthrough of low levels of switching noise from the on-chip
reference through the RF
in reference spur levels as high as −90 dBc. Care should be taken in
the PCB layout to ensure that the VCO is well separated from the
input reference to avoid a possible feedthrough path on the board.
SPUR CONSISTENCY AND FRACTIONAL SPUR
In low noise mode (dither off), the quantization noise from the
Σ- modulator appears as fractional spurs. The interval between
spurs is f
/L, where L is the repeat length of the code sequence
PFD
in the digital Σ- modulator. For the third-order modulator used
in the ADF4156, the repeat length depends on the value of MOD,
as listed in Tab l e 7 .
Table 7. Fractional Spurs with Dither Off
Repeat
Condition
Length Spur Interval
If MOD is divisible by 2, but not 3 2 × MOD Channel step/2
If MOD is divisible by 3, but not 2 3 × MOD Channel step/3
If MOD is divisible by 6 6 × MOD Channel step/6
Otherwise MOD Channel step
OPTIMIZATION
With dither off, the fractional spur pattern due to the quantization
noise of the Σ- modulator also depends on the phase word set
as the starting point of the modulator. Setting the Σ- reset bit
(DB14 in Register R3) to 0 ensures that this starting point is used
for the Σ- modulator on every write to Register R0.
The phase word can be varied to optimize the fractional and
subfractional spur levels on any particular frequency. Therefore,
a look-up table of phase values corresponding to each frequency
can be constructed for use when programming the ADF4156.
The evaluation software has a sweep function to sweep the
phase word so that the user can observe the spur levels on a
spectrum analyzer.
pin and back to the VCO, resulting
IN
If a look-up table is not used, keep the phase word at a constant
value to ensure consistent spur levels on a particular frequency.
Rev. D | Page 19 of 24
ADF4156 Data Sheet
PHASE RESYNC
The output of a fractional-N PLL can settle to any MOD phase
offset with respect to the input reference, where MOD is the
fractional modulus. The phase resync feature in the ADF4156 is
used to produce a consistent output phase offset with respect to
the input reference. This is necessary in applications where the
output phase and frequency are important, such as digital beam
forming. See the Phase Programmability section for information
about how to program a specific RF output phase when using
the phase resync feature.
LE
SYNC
(Internal)
FREQUENCY
PHASE
LAST CYCLE SLIP
t
SYNC
PLL SETTLES TO
INCORRECT PHASE
PLL SETTLES TO
CORRECT PHASE
AFTER RESYNC
Phase resync is enabled by setting Bits DB[20:19] in Register R4
to 10. When phase resync is enabled, an internal timer generates
sync signals at intervals of t
as indicated by the following
SYNC
formula:
t
= CLK_DIV_VALUE × MOD × t
SYNC
PFD
where:
t
is the PFD reference period.
PFD
CLK_DIV_VALUE is the decimal value programmed in
Bit DB[18:7] of Register R4. This value can be any integer in the
range of 1 to 4095.
MOD is the modulus value programmed in Bit DB[14:3] of
Register R2.
When a new frequency is programmed, the second sync pulse
after the LE rising edge is used to resynchronize the output
phase to the reference. The t
time should be programmed to
SYNC
a value that is at least as long as the worst-case lock time. Doing
so guarantees that the phase resync occurs after the last cycle
slip in the PLL settling transient.
In the example shown in Figure 24, the PFD reference is
25 MHz and the MOD value is 125 for a 200 kHz channel
spacing. Therefore, t
is set to 400 µs by programming
SYNC
CLK_DIV_VALUE to 80.
–100 0 100 200 1000
Figure 24. Phase Resync Example
300 400 500 600 700 800 900
TIME (µs)
05863-016
Phase Programmability
To program a specific RF output phase, change the phase word
in Register R1. As this word is swept from 0 to MOD, the RF output
o
phase sweeps over a 360
/MOD range in steps of 360o/MOD.
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum; however,
lower RF frequencies can be used if the minimum slew rate
specification of 400 V/µs is met. An appropriate LVDS driver, such
as the FIN1001 from Fairchild Semiconductor, can be used to
square up the RF signal before it is fed back into the ADF4156
RF input.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help implement
the PLL design. Visit www.analog.com/pll for a free download
of the ADIsimPLL™ software. This software designs, simulates,
and analyzes the entire PLL frequency domain and time domain
response. Various passive and active filter architectures are allowed.
When designing the loop filter, keep the ratio of the PFD frequency
to the loop bandwidth >200:1 to attenuate the Σ- modulator noise.
Rev. D | Page 20 of 24
Data Sheet ADF4156
INTERFACING
The ADF4156 has a simple SPI-compatible serial interface for
writing to the device. CLOCK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 29 bits that have
been clocked into the input register on each rising edge of serial
clock are transferred to the appropriate latch. The maximum
allowable serial clock rate is 20 MHz. See Figure 2 for the timing
diagram and Tab le 6 for the latch truth table.
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The lands on the lead frame chip scale package (CP-20-1) are
rectangular. The printed circuit board pad for these lands should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The package land should be centered
on the pad to ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that shorting
is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad on a 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and
0.33 mm, and the via barrel should be plated with 1 oz of
copper to plug the via. In addition, the printed circuit board
thermal pad should be connected to AGND.
Rev. D | Page 21 of 24
ADF4156 Data Sheet
C
OUTLINE DIMENSIONS
5.10
5.00
4.90
INDI
ATO R
1.00
0.85
0.80
SEATING
PLANE
PIN 1
0.15
0.05
4.50
4.40
4.30
PIN 1
16
0.65
BSC
COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AB
0.10
0.30
0.19
9
81
1.20
MAX
SEATING
PLANE
6.40
BSC
0.20
0.09
8°
0°
Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
0.08
0.50
BSC
0.75
0.60
0.50
0.60 MAX
15
16
EXPOSED
(BOTTOM VIEW)
10
11
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DAT A SHEET.
12° MAX
4.00
BSC SQ
TOP VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT
0.60 MAX
3.75
BCS SQ
0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
TO
JEDEC STANDARDS MO-220-VGGD-1
Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
PAD
0.75
0.60
0.45
1
P
N
I
R
C
I
A
O
T
N
I
2.25
2.10 SQ
1.95
0.25 MIN
D
012508-B
20
1
5
6
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADF4156BRUZ −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4156BRUZ-RL −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4156BRUZ-RL7 −40°C to +85°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4156BCPZ −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADF4156BCPZ-RL −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADF4156BCPZ-RL7 −40°C to +85°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
EV-ADF4156SD1Z Evaluation Board
1
Z = RoHS Compliant Part.
Rev. D | Page 22 of 24
Data Sheet ADF4156
NOTES
Rev. D | Page 23 of 24
ADF4156 Data Sheet
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05863-0-3/12(D)
Rev. D | Page 24 of 24
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