ANALOG DEVICES ADF4156 Service Manual

AV
6.2 GHz Fractional-N Frequency Synthesizer
Data Sheet

FEATURES

RF bandwidth to 6.2 GHz
2.7 V to 3.3 V power supply Separate V Programmable fractional modulus Programmable charge-pump currents 3-wire serial interface Digital lock detect Power-down mode Pin compatible with ADF4110/ADF4111/ADF4112/ADF4113,
ADF4106, ADF4153, and ADF4154 frequency synthesizers Programmable RF output phase Loop filter design possible with ADIsimPLL Cycle slip reduction for faster lock times

APPLICATIONS

CATV equipment Base stations for mobile radio (WiMAX, GSM, PCS, DCS,
SuperCell 3G, CDMA, WCDMA) Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANs, PMR Communications test equipment
pin allows extended tuning voltage
P
ADF4156

GENERAL DESCRIPTION

The ADF4156 is a 6.2 GHz fractional-N frequency synthesizer that implements local oscillators in the upconversion and down­conversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ- based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4156 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.
Control of all on-chip registers is via a simple 3-wire interface. The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
REF
MUXOUT
CLOCK
DATA
IN
CE
LE
ADF4156
HIGH Z
×2
DOUBLER
OUTPUT
MUX
32-BIT
DATA
REGISTER

FUNCTIONAL BLOCK DIAGRAM

DV
DD
DDVP
5-BIT
AGND
R-COUNTER
V
DD
DGND
SD
OUT
V
DD
R
DIV
N
DIV
LOCK
DETECT
THIRD-ORDER
FRACTIONAL
INTERPOL ATOR
FRACTION
REG
DGND CPGND
DIVIDE R
MODULUS
REG
Figure 1.
/2
+
PHASE
FREQUENCY
DETECTOR
N-COUNTER
INTEGER
REG
R
SET
REFERENCE
CHARGE
PUMP
CURRENT
SETTING
RFCP3 RFCP2RFCP4 RFCP1
CSR
CP
RFINA
RF
IN
B
05863-001
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2012 Analog Devices, Inc. All rights reserved.
ADF4156 Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1
Register Maps.................................................................................. 10
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
Thermal Impedance..................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Circuit Description........................................................................... 8
Reference Input Section............................................................... 8
RF Input Stage............................................................................... 8
RF INT Divider............................................................................. 8
INT, FRAC, MOD, and R Relationship ..................................... 8
FRAC/INT Register, R0............................................................. 11
Phase Register, R1 ...................................................................... 12
MOD/R Register, R2.................................................................. 13
Function Register, R3................................................................. 15
CLK DIV Register, R4................................................................ 16
Reserved Bits............................................................................... 16
Initialization Sequence .............................................................. 16
RF Synthesizer: A Worked Example........................................ 17
Modulus....................................................................................... 17
Reference Doubler and Reference Divider ............................. 17
12-Bit Programmable Modulus................................................ 17
Fast Lock Times with the ADF4156 ........................................ 17
Spur Mechanisms....................................................................... 19
Spur Consistency and Fractional Spur Optimization ........... 19
Phase Resync............................................................................... 20
Low Frequency Applications .................................................... 20
RF R-Counter................................................................................ 8
Phase Frequency Detector (PFD) and Charge Pump.............. 9
MUXOUT and Lock Detect........................................................ 9
Input Shift Registers..................................................................... 9
Program Modes ............................................................................9

REVISION HISTORY

3/12—Rev. C to Rev. D
Changes to Table 1............................................................................ 3
Changes to Ordering Guide.......................................................... 22
9/11—Rev. B to Rev. C
Changes to Noise Characteristics Parameter................................ 3
4/11—Rev. A to Rev. B
Changes to Product Title, Features Section and General
Description Section .......................................................................... 1
Changes to RF Input Frequency RF
Changes to Figure 4 and Table 5..................................................... 6
5/09—Rev. 0 to Rev. A
Added Low Power Sleep Mode Parameter and Changes to
Endnote 4, Table 1 ............................................................................ 3
Change to Figure 9 Caption............................................................ 7
Change to Program Modes Section ............................................... 9
Changes to Figure 16...................................................................... 10
Parameter, Table 1........... 3
IN
Filter Design—ADIsimPLL....................................................... 20
Interfacing ................................................................................... 21
PCB Design Guidelines for Chip Scale Package .................... 21
Outline Dimensions....................................................................... 22
Ordering Guide .......................................................................... 22
Changes to Figure 17...................................................................... 11
Changes to CSR Enable Section ................................................... 13
Changes to Figure 19...................................................................... 14
Changes to Function Register, R3 Section and Figure 20 ......... 15
Changes to 12-Bit Clock Divider Value Section, to
Clock Divider Mode Section, and to Figure 21.......................... 16
Changes to Reference Doubler and Reference Divider Section
and to Fast Lock Times with the ADF4156 Section .................. 17
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Change to Phase Resync Section.................................................. 20
Changes to Interfacing Section and to PCB Design Guidelines
for Chip Scale Package Section..................................................... 21
Changes to Outline Dimensions .................................................. 23
Changes to Ordering Guide.......................................................... 23
5/06—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet ADF4156

SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = T
Table 1.
Parameter B Version Unit Test Conditions/Comments1
RF CHARACTERISTICS
RF Input Frequency (RFIN) 0.5/6.2 GHz min/max −10 dBm min to 0 dBm max. For lower frequencies,
REFERENCE CHARACTERISTICS
REFIN Input Frequency 10/250 MHz min/max For f < 10 MHz, use a dc-coupled CMOS-compatible
REFIN Input Sensitivity 0.4/AVDD V p-p min/max Biased at AVDD/2.2
REFIN Input Capacitance 10 pF max
REFIN Input Current ±100 μA max
PHASE DETECTOR
Phase Detector Frequency3 32 MHz max
CHARGE PUMP
ICP Sink/Source Programmable.
High Value 5 mA typ With R Low Value 312.5 μA typ Absolute Accuracy 2.5 % typ With R R
Range 2.7/10 kΩ min/max
SET
ICP Three-State Leakage Current 1 nA typ Sink and source current.
Matching 2 % typ 0.5 V < VCP < VP − 0.5.
ICP vs. VCP 2 % typ 0.5 V < VCP < VP − 0.5.
ICP vs. Temperature 2 % typ VCP = VP/2.
LOGIC INPUTS
V
, Input High Voltage 1.4 V min
INH
V
, Input Low Voltage 0.6 V max
INL
I
, Input Current ±1 μA max
INH/IINL
CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS
VOH, Output High Voltage 1.4 V min Open-drain output chosen; 1 kΩ pull-up to 1.8 V.
VOH, Output High Voltage VDD − 0.4 V min CMOS output chosen.
IOH, Output High Current 100 μA max
VOL, Output Low Voltage 0.4 V max IOL = 500 μA.
POWER SUPPLIES
AVDD 2.7/3.3 V min/max
DVDD AVDD
VP AVDD/5.5 V min/max
IDD 32 mA max 26 mA typical.
Low Power Sleep Mode 1 μA typ
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN
)5 −110 dBc/Hz typ 10 kHz offset; normalized to 1 GHz.
1_f
)4 −220 dBc/Hz typ PLL loop BW = 500 kHz. Measured at 100 kHz offset.
SYNTH
Phase Noise Performance6 @ VCO output.
5800 MHz Output7 −89 dBc/Hz typ @ 5 kHz offset, 25 MHz PFD frequency.
1
Operating temperature for B version: −40°C to +85°C.
2
AC coupling ensures AVDD/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(F
5
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at a frequency offset f is given by PN = PN
6
The phase noise is measured with the EV-ADF4156SD1Z evaluation board and the Agilent E5500 phase noise system.
7
f
= 100 MHz, f
REFIN
). PN
= PN
PFD
SYNTH
= 25 MHz, offset frequency = 5 kHz, RF
PFD
− 10 log(F
TOT
+ 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
1_f
) − 20 log(N).
PFD
= 5800 MHz, N = 232, loop bandwidth = 20 kHz, ICP = 313 μA, and lowest noise mode.
OUT
MIN
to T
, dBm referred to 50 Ω, unless otherwise noted.
MAX
ensure slew rate (SR) > 400 V/μs.
square wave, slew rate > 25 V/μs.
= 5.1 kΩ.
SET
= 5.1 kΩ.
SET
Rev. D | Page 3 of 24
ADF4156 Data Sheet

TIMING SPECIFICATIONS

AVDD = DVDD = 2.7 V to 3.3 V, VP = AVDD to 5.5 V, AGND = DGND = 0 V, TA = T
Table 2.
Parameter Limit at T
MIN
to T
(B Version) Unit Test Conditions/Comments
MAX
t1 20 ns min LE setup time t2 10 ns min DATA to CLOCK setup time t3 10 ns min DATA to CLOCK hold time t4 25 ns min CLOCK high duration t5 25 ns min CLOCK low duration t6 10 ns min CLOCK to LE setup time t7 20 ns min LE pulse width

Timing Diagram

t
4
CLOCK
to T
MIN
t
5
, dBm referred to 50 Ω, unless otherwise noted.
MAX
DATA
t
2
DB23 (MSB) DB22 DB2
LE
t
1
LE
t
3
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
t
6
05863-002
Figure 2. Timing Diagram
Rev. D | Page 4 of 24
Data Sheet ADF4156

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND −0.3 V to +4 V VDD to VDD −0.3 V to +0.3 V VP to GND −0.3 V to +5.8 V VP to VDD −0.3 V to +5.8 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V REFIN, RFIN to GND −0.3 V to VDD + 0.3 V Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
Maximum Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

THERMAL IMPEDANCE

Table 4. Thermal Impedance
Package Type θJA Unit
TSSOP 112 °C/W LFCSP_VQ (Paddle Soldered) 30.4 °C/W

ESD CAUTION

Rev. D | Page 5 of 24
ADF4156 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD
DD
SET
P
R
CP
20
R
SET
CP
CPGND
AGND
RF
IN
RFINA
AV
REF
B
DD
IN
1
2
3
ADF4156
TOP VIEW
4
(Not to Scale)
5
6
7
8
16
15
14
13
12
11
10
9
Figure 3. TSSOP Pin Configuration
V
P
DV
DD
MUXOUT
LE
DATA
CLOCK
CE
DGND
05863-003
1CPGND 2AGND
ADF4156
3AGND
TOP VIEW
4RF
B
IN
IN
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED T O GROUND.
A
5RF
(Not to Scale)
6
AV
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 R
2 20 CP
SET
Connecting a resistor between this pin and ground sets the maximum charge-pump output current. The relationship between I
I
=
CPmax
R
SET
where R
= 5.1 kΩ and I
SET
and R
CP
5.25
CPmax
Charge-Pump Output. When enabled, this pin provides ±I
is
SET
= 5 mA.
to the external loop filter, which in turn drives
CP
the external VCO. 3 1 CPGND Charge-Pump Ground. This is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass
capacitor, typically 100 pF. 6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO. 7 6, 7 AVDD
8 8 REFIN
Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. AV
Reference Input. This is a CMOS input with a nominal threshold of V
has a value of 3 V ± 10%. AVDD must have the same voltage as DVDD.
DD
DD
of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE
Chip Enable. A logic low on this pin powers down the device and puts the charge-pump output into
three-state mode. 11 12 CLOCK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the shift register on the CLOCK rising edge. This input is a high impedance CMOS input. 12 13 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs serving as the control bits. This
input is a high impedance CMOS input. 13 14 LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the
five latches. The control bits are used to select the latch. 14 15 MUXOUT
Multiplexer Output. This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled
reference frequency to be accessed externally. 15 16, 17 DVDD
16 18 VP
Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should be
placed as close as possible to this pin. DV
has a value of 3 V ± 10%. DVDD must have the same voltage as AVDD.
DD
Charge-Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V. EPAD The exposed pad must be connected to ground.
DV
DV
V
16
17
19
18
PIN 1 INDICATOR
8
7
IN
DD
DD
AV
REF
9
DGND
10
DGND
15 MUXO UT 14 LE 13 DATA 12 CLOCK 11 CE
05863-004
/2 and an equivalent input resistance
. In systems where VDD is 3 V, it can
DD
Rev. D | Page 6 of 24
Data Sheet ADF4156

TYPICAL PERFORMANCE CHARACTERISTICS

PFD = 25 MHz, loop bandwidth = 20 kHz, reference = 100 MHz, ICP = 313 A, phase noise measurements taken on the Agilent E5500 phase noise system.
10
5
0
–5
–10
P=4/5 P=8/9
–15
–20
POWER (dBm)
–25
–30
–35
–40
09
12345678
FREQUENCY (GHz)
05863-017
Figure 5. RF Input Sensitivity
0
LOW NOISE MODE RF = 5800. 25MHz, P FD = 25MHz, N = 232,
–20
FRAC = 2, MOD = 200, 20kHz LOOP BW, I
–40
–60
–80
–100
–120
PHASE NOISE ( dBc/Hz)
–140
DSB INTEGRAT ED PHASE ERROR = 0.73° RMS,
–160
PHASE NOI SE @ 5kHz = –89.5d Bc/Hz, ZCOMM V940ME03 VCO
–180
1k 100M
10k 100k 1M 10M
FREQUENCY (Hz)
CP
= 313µA,
05863-018
Figure 6. Phase Noise and Spurs, Low Noise Mode
0
LOW SPUR MODE RF = 5800. 25MHz, PFD = 25M Hz, N = 232, FRAC = 2,
–20
MOD = 200, 20kHz L OOP BW, I DSB INTEGRAT ED PHASE ERROR = 1. 09° RMS,
–40
PHASE NOI SE @ 5kHz = –83dBc/ Hz, ZCO MM V940M E03 VCO
–60
–80
–100
–120
PHASE NOISE ( dBc/Hz)
–140
–160
–180
1k 100M
10k 100k 1M 10M
FREQUENCY (Hz)
CP
= 313µA,
05863-019
Figure 7. Phase Noise and Spurs, Low Spur Mode
(Note that Fractional Spurs Are Removed and Only
the Integer Boundary Spur Remains in Low Spur Mode)
Rev. D | Page 7 of 24
6.00
5.95
5.90
5.85
5.80
FREQUENCY (G Hz)
5.75
5.70
5.65 –100 900
0 100 200 300 400 500 600 700 800
CSR ON
CSR OFF
TIME (µs)
Figure 8. Lock Time for 200 MHz Jump, from 5705 MHz to 5905 MHz,
with CSR On and Off
5.95
5.90
5.85
5.80
5.75
FREQUENCY (G Hz)
5.70
5.65
5.60 –100 900
0 100 200 300 400 500 600 700 800
CSR OFF
CSR ON
TIME (µs)
Figure 9. Lock Time for 200 MHz Jump, from 5905 MHz to 5705 MHz,
with CSR On and Off
6
5
4
3
2
1
(mA)
0
CP
I
–1
–2
–3
–4
–5
–6
012345
VCP(V)
Figure 10. Charge-Pump Output Characteristics
05863-021
05863-022
05863-020
ADF4156 Data Sheet

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 11. While the device is operating, SW1 and SW2 are usually closed switches and SW3 is open. When a power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that the REF
pin is not loaded while the device is powered down.
IN
POWER-DOW N
CONTROL
100k
NC
REF
IN
NC
SW2
SW1
SW3
NO
Figure 11. Reference Input Stage
BUFFER
TO R-COUNTER
5863-005

RF INPUT STAGE

The RF input stage is shown in Figure 12. It is followed by a two-stage limiting amplifier to generate the current-mode logic (CML) clock levels needed for the prescaler.
1.6V
AV
DD
2k2k
RF
IN
RFINB
BIAS
GENERATOR
A

RF INT DIVIDER

The RF INT counter allows a division ratio in the PLL feedback counter. Division ratios from 23 to 4095 are allowed.

INT, FRAC, MOD, AND R RELATIONSHIP

The INT, FRAC, and MOD values, in conjunction with the R-counter, enable generating output frequencies that are spaced by fractions of the phase frequency detector (PFD). See the RF Synthesizer: A Worked Example section for more information. The RF VCO frequency (RF
= F
RF
where RF
OUT
× (INT + (FRAC/MOD)) (1)
PFD
is the output frequency of an external voltage-
OUT
controlled oscillator (VCO).
F
= REFIN × [(1 + D)/(R × (1 + T))] (2)
PFD
where:
REF
is the reference input frequency.
IN
D is the REF T is the REF
doubler bit.
IN
divide-by-2 bit (0 or 1).
IN
R is the preset divide ratio of the binary 5-bit programmable reference counter (1 to 32). INT is the preset divide ratio of the binary 12-bit counter (23 to 4095).
MOD is the preset fractional modulus (2 to 4095). FRAC is the numerator of the fractional division (0 to MOD − 1).
RF N-DIVIDER N = INT + FRAC/MOD
FROM RF
INPUT STAGE
N-COUNTER
) equation is
OUT
INTERPOL ATOR
THIRD-ORDER
FRACTIONAL
TO PFD
MOD REG
Figure 12. RF Input Stage
AGND
05863-006
INT
REG
Figure 13. RF INT Divider
FRAC
VALUE
05863-007

RF R-COUNTER

Rev. D | Page 8 of 24
The 5-bit RF R-counter allows the input reference frequency
) to be divided down to produce the reference clock to
(REF
IN
the PFD. Division ratios from 1 to 32 are allowed.
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