Analog Devices ADF4153 a Datasheet

Fractional-N Frequency Synthesizer

FEATURES

RF bandwidth 500 MHz to 4 GHz

2.7 V to 3.3 V power supply
Separate V
Programmable dual-modulus prescaler 4/5, 8/9
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Power-down mode
Pin compatible with the

ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106
Programmable modulus on fractional-N synthesizer
Trade-off noise versus spurious performance

APPLICATIONS

CATV equipment
Base stations for mobile radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment

allows extended tuning voltage

P

ADF4153

REF

IN

HIGH Z

MUXOUT

CLOCK

DATA

LE

OUTPUT

24-BIT

DATA

REGISTER

FUNCTIONAL BLOCK DIAGRAM

×2

DOUBLER

MUX

V

DD

DGND

V

DD

R

DIV

N

DIV

AV

DD

4-BIT

R COUNTER

LOCK

DETECT

THIRD ORDER

FRACTIONAL

INTERPOLATOR

FRACTION

REG

ADF4153

GENERAL DESCRIPTION

The ADF4153 is a fractional-N frequency synthesizer that
implements local oscillators in the upconversion and
downconversion sections of wireless receivers and transmitters.
It consists of a low noise digital phase frequency detector
(PFD), a precision charge pump, and a programmable reference
divider. There is a Σ-Δ based fractional interpolator to allow
programmable fractional-N division. The INT, FRAC, and
MOD registers define an overall N divider (N = (INT +
(FRAC/MOD))). In addition, the 4-bit reference counter (R
counter) allows selectable REFIN frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the
synthesizer is used with an external loop filter and a voltage
controlled oscillator (VCO).

Control of all on-chip registers is via a simple 3-wire interface.
The device operate with a power supply ranging from 2.7 V to

3.3 V and can be powered down when not in use.

DV

DDVP

MODULUS

REG

SDV

DD

+

PHASE

FREQUENCY

DETECTOR

–

N-COUNTER

INTEGER

REG

R

SET

REFERENCE

CHARGE

PUMP

CURRENT

SETTING

RFCP3 RFCP2 RFCP1

CP

RFINA
RF

IN

B

AGND

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DGND CPGND

Figure 1.

03685-A-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADF4153

TABLE OF CONTENTS

Specifications..................................................................................... 3

R Divider Register, R1................................................................ 17

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Pin Function Descriptions...................... 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

RF Input Stage............................................................................. 10

RF INT Divider........................................................................... 10

INT, FRAC, MOD, and R Relationship.................................... 10

RF R COUNTER ........................................................................10

Phase Frequency Detector (PFD) and Charge Pump............ 11

MUXOUT and LOCK Detect................................................... 11

Input Shift Registers................................................................... 11

Program Modes .......................................................................... 11

Control Register, R2................................................................... 17

Noise and Spur Register, R3 ...................................................... 18

Reserved Bits............................................................................... 18

RF Synthesizer: A Worked Example ........................................ 18

Modulus....................................................................................... 19

Reference Doubler and Reference Divider ............................. 19

12-Bit Programmable Modulus................................................ 19

Spurious Optimization and Fastlock ....................................... 19

Phase Resync and Spur Consistency ....................................... 19

Spurious Signals—Predicting Where They Will Appear....... 20

Filter Design—ADIsimPLL....................................................... 20

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package .................... 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

N Divider Register, R0 ............................................................... 17

REVISION HISTORY

1/04—Data Sheet Changed from a REV. 0 to a REV. A

Renumbered Figures and Tables.............................. UNIVERSAL

Changes to Specifications............................................................... 3

Changes to Pin Function Description ..........................................7

Changes to RF Power-Down section ..........................................17

Changes to PCB Design Guidelines for Chip Scale

Package section .............................................................................. 21

Updated Outline Dimensions...................................................... 22

Updated Ordering Guide.............................................................. 22

7/03—Revision 0: Initial Version

Rev. A | Page 2 of 24

ADF4153

SPECIFICATIONS1

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
referred to 50 Ω.

Table 1.

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Frequency (RFIN)2 0.5/4.0 GHz min/max

1.0/4.0 GHz min/max −10 dBm/0 dBm min/max.

REFERENCE CHARACTERISTICS See Figure 16 for input circuit.

REFIN Input Frequency2 10/250 MHz min/max

REFIN Input Sensitivity 0.7/AVDD V p-p min/max AC-coupled.

0 to AVDD V max CMOS compatible.

REFIN Input Capacitance 10 pF max

REFIN Input Current ±100 µA max
PHASE DETECTOR

Phase Detector Frequency3 32 MHz max
CHARGE PUMP

ICP Sink/Source Programmable. See Table 5.

High Value 5 mA typ With R
Low Value 312.5 µA typ
Absolute Accuracy 2.5 % typ With R
R

Range 1.5/10 kΩ min/max

SET

ICP Three-State Leakage Current 1 nA typ Sink and source current.

Matching 2 % typ 0.5 V < VCP < VP – 0.5.

ICP vs. VCP 2 % typ 0.5 V < VCP < VP – 0.5.

ICP vs. Temperature 2 % typ VCP = VP/2.
LOGIC INPUTS

V

, Input High Voltage 1.4 V min

INH

V

, Input Low Voltage 0.6 V max

INL

I

, Input Current ±1 µA max

INH/IINL

CIN, Input Capacitance 10 pF max
LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain 1 kΩ pull-up to 1.8 V.

VOL, Output Low Voltage 0.4 V max IOL = 500 µA.
POWER SUPPLIES

AVDD 2.7/3.3 V min/V max

DVDD, SDVDD AVDD

VP AVDD/5.5 V min/V max

4

I

24 mA max 20 mA typical.

DD

Low Power Sleep Mode 1 µA typ
NOISE CHARACTERISTICS

Phase Noise Figure of Merit5 −217 dBc/Hz typ

ADF4153 Phase Noise Floor6 −147 dBc/Hz typ @ 10 MHz PFD frequency.

−143 dBc/Hz typ @ 26 MHz PFD frequency.

Phase Noise Performance7 @ VCO output.

1750 MHz Output8 −106 dBc/Hz typ @ 1 kHz offset, 26 MHz PFD frequency.

See footnotes on next page.

MIN

to T

, unless other wise noted; dBm

MAX

See Figure 17 for input circuit.

−8 dBm/0 dBm min/max. For lower frequencies,
ensure slew rate (SR) > 396 V/µs.

For f < 10 MHz, use a dc-coupled CMOS compatible
square wave, slew rate > 21 V/µs.

= 5.1 kΩ.

SET

= 5.1 kΩ.

SET

Rev. A | Page 3 of 24

ADF4153

1

Operating temperature is B version: −40°C to +80°C.

2

Use a square wave for frequencies below f

3

Guaranteed by design. Sample tested to ensure compliance.

4

AC coupling ensures AVDD/2 bias. See Figure 16 for typical circuit.

5

This figure can be used to calculate phase noise for any application. Use the formula –217 + 10log(f

at the VCO output. The value given is the lowest noise mode.

6

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

The value given is the lowest noise mode.

7

The phase noise is measured with the EVAL-ADF4153EB1 evaluation board and the HP8562E spectrum analyzer.

8

f

= 26 MHz; f

REFIN

= 10 MHz; offset frequency = 1 kHz; RF

PFD

.

MIN

) + 20logN to calculate in-band phase noise performance as seen

PFD

= 1750 MHz; N = 175; loop B/W = 20 kHz; lowest noise mode.

OUT

Rev. A | Page 4 of 24

ADF4153

K

TIMING CHARACTERISTICS1

AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T
referred to 50 Ω.

Table 2.

Parameter Limit at T

MIN

to T

(B Version) Unit Test Conditions/Comments

MAX

t1 20 ns min LE Setup Time
t2 10 ns min DATA to CLOCK Setup Time
t3 10 ns min DATA to CLOCK Hold Time
t4 25 ns min CLOCK High Duration
t5 25 ns min CLOCK Low Duration
t6 10 ns min CLOCK to LE Setup Time
t7 20 ns min LE Pulse Width

1

Guaranteed by design but not production tested.

CLOC

t

4

t

5

MIN

to T

, unless other wise noted; dBm

MAX

DATA

t

2

DB23 (MSB) DB22 DB2

LE

t

1

LE

t

3

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

7

t

6

04414-0-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 24

ADF4153

ABSOLUTE MAXIMUM RATINGS1, 2, 3, 4

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +4 V
VDD to VDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to VDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN, RFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 150.4°C/W
LFCSP θJA Thermal Impedance (Paddle Soldered) 122°C/W
LFCSP θJA Thermal Impedance (Paddle Not Soldered) 216°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared 220°C

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating of < 2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and

assembly.

3

GND = AGND = DGND = 0 V.

4

VDD = AVDD = DVDD = SDVDD.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 24

ADF4153

D

D

PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS

D

1

R

SET

CP

2

CPGND

3

DD

IN

ADF4153

4

TOP VIEW

5

(Not to Scale)

6
7
8

AGND
RFINB

RFIINA

AV

REF

Figure 3. TSSOP Pin Configuration

16
15
14
13
12
11
10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
SDV

DD

DGND

CPGND 1

AGND 2
AGND 3

RFINB4
RF

A5

IN

03685-A-002

Figure 4. LFCSP Pin Configuration

CP
201917

ADF4153

TOP VIEW

6

AV

Table 4. Pin Function Descriptions

TSSOP LFCSP Mnemonic Description

1 19 R

2 20 CP

SET

Connecting a resistor between this pin and ground sets the maximum charge pump output current.

= 5 mA.

and R

CP

The relation ship between I

525I.

=

CP

max

R

SET

With R

= 5.1 kΩ, I

SET

CPmax

Charge Pump Output. When enabled, this provides ±I

SET

is

to the external loop filter, which in turn drives

CP

the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF (see Figure 17).
6 5 RFINA Input to the RF Prescaler. This small-signal input is normally ac-coupled from the VCO.
7 6, 7 AVDD

8 8 REFIN

Positive Power Supply for the RF Section. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. AV

as DV

.

DD

has a value of 3 V ± 10%. AVDD must have the same voltage

DD

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ (see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it

can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 SDVDD

11 12 CLK

∑-∆ Power. Decoupling capacitors to the digital ground plane should be placed as close as possible to

this pin. SDV

has a value of 3 V ± 10%. SDVDD must have the same voltage as DVDD.

DD

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input

is a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of

the four latches, the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the RF lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.
15 16, 17 DVDD

Positive Power Supply for the Digital Section. Decoupling capacitors to the digital ground plane should

be placed as close as possible to this pin. DVDD has a value of 3 V ± 10%. DVDD must have the same

.

DD

16 18 VP

voltage as AV

Charge Pump Power Supply. This should be greater than or equal to V

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

D

SET

R

VPDV

DV

191817

16

16

PIN 1
INDICATOR

7

8

IN

DD

DD

AV

REF

DGND 9

MUXOUT

15

LE

14

DATA

13

CLK

12

SDV

11

DD

DGND 10

03685-A-003

/2 and an equivalent input

DD

. In systems where VDD is 3 V, it

DD

Rev. A | Page 7 of 24

ADF4153

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 5 to Figure 10: RF

= 5 mA.

and I

CP

Loop Bandwidth = 20 kHz, Reference = Fox 10 MHz TCXO, VCO = Vari-L VCO190-1750T, Eval Board = Eval-ADF4153EB1,
measurements taken on HP8562E spectrum analyzer.

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

0

0

REFERENCE
LEVEL = –4dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

Figure 5. Phase Noise (Lowest Noise Mode)

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

Figure 6. Phase Noise (Low Noise Mode and Spur Mode)

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 1kHz 2kHz1.722GHz

Figure 7. Phase Noise (Lowest Spur Mode)

= 1.722 GHz, PFD Freq = 26 MHz, INT = 66, Channel Spacing = 200 kHz, Modulus = 130, Fraction = 1/130,

OUT

0

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 1/130
RBW = 10Hz

–102dBc/Hz

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

03685-A-004

–100

REFERENCE
LEVEL = –4.2dBm

–71dBc@200kHz

–400kHz –200kHz 200kHz 400kHz1.722GHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST NOISE MODE
N = 66 1/130
RBW = 10Hz

Figure 8. Spurs (Lowest Noise Mode)

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 1/130
RBW = 10Hz

–95dBc/Hz

0

–10

REFERENCE
LEVEL = –4.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

03685-A-005

–100

–74dBc@200kHz

–400kHz –200kHz 200kHz 400kHz1.722GHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOW NOISE AND
SPUR MODE
N = 66 1/130
RBW = 10Hz

Figure 9. Spurs (Low Noise and Spur Mode)

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR MODE
N = 66 1/130
RBW = 10Hz

–90dBc/Hz

0

–10

REFERENCE
LEVEL = –4.2dBm

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

03685-A-006

–100

–400kHz –200kHz 200kHz 400kHz1.722GHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 26MHz
CHANNEL STEP = 200kHz
LOOP BANDWIDTH = 20kHz
LOWEST SPUR NOISE
N = 66 1/130
RBW = 10Hz

Figure 10. Spurs (Lowest Spur Mode)

03685-A-007

03685-A-008

03685-A-009

Rev. A | Page 8 of 24