ANALOG DEVICES ADF4151 Service Manual

Fractional-N/Integer-N PLL Synthesizer

ADF4151

Rev. B

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MUXOUT

CP

OUT

LD

SW

REF

IN

CLK

DATA

LE

AV

DD

xSDV

DD

DV

DD

V

P

A

GND

CE CP

GND

SD

GNDDGND

R

SET

RFIN+

RF

IN

–

PHASE

COMPARATOR

FL

O

SWITCH

CHARGE

PUMP

10-BIT R

COUNTER÷2DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGISTER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

ADF4151

10265-001

Data Sheet

FEATURES

Fractional-N synthesizer and integer-N synthesizer RF bandwidth to 3.5 GHz

3.0 V to 3.6 V power supply

1.8 V logic compatibility Separate charge pump supply (V

voltage (up to 5.5 V) in 3 V systems Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable RF output phase 3-wire serial interface Analog and digital lock detect Switched bandwidth fast lock mode Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT) Test equipment Wireless LANs, CATV equipment Clock generation

) allows extended tuning

P

GENERAL DESCRIPTION

The ADF4151 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external voltage controlled oscillator (VCO), loop filter, and external reference frequency.

The ADF4151 is used with external VCO parts and is footprint and software compatible with the ADF4350. The part consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider [N = (INT + (FRAC/MOD))]. The RF output phase is programmable for applications that require a particular phase relationship between the output and the reference. The ADF4151 also features cycle slip reduction circuitry, leading to faster lock times without the need for modifications to the loop filter.

Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V that can be powered down when not in use.

The ADF4151 is available in a 5 mm × 5 mm package.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of thi rd parties that may result from its use. Specifications subject to change with out notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADF4151 Data Sheet

REVISION HISTORY

12/11—Rev. A to Rev. B

Changes to Normalized 1/f Noise Parameter, Table 1 ................. 4

11/11—Rev. 0 to Rev. A

Changes to Figure 28 ...................................................................... 23

10/11—Revision 0: Initial Version

Rev. B | Page 2 of 28

Data Sheet ADF4151

Fractional-N Mode

Input Capacitance, CIN

5.0 pF

Low Power Sleep Mode

1

µA

SPECIFICATIONS

AVDD = DVDD = SD temperature range is −40°C to +85°C.

Table 1.

Parameter

REFIN CHARACTERISTICS

Input Frequency 10 250 MHz For f < 10 MHz, ensure slew rate > 21 V/µs

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21

Input Capacitance 10 pF

Input Current ±60 µA

RF INPUT CHARACTERISTICS For lower frequencies, ensure slew rate > 400 V/µs

RF Input Frequency (RFIN) 0.5 3.5 GHz −10 dBm ≤ RF input power ≤ +5 dBm

Prescaler Output Frequency 750 MHz

MAXIMUM PFD FREQUENCY

Low Spur Mode 26 MHz Low Noise Mode 32 MHz

Integer-N Mode 32 MHz

CHARGE PUMP

ICP Sink/Source R

High Value 4.5 mA Low Value 0.281 mA R

Range 2.7 10 kΩ

SET

ICP Leakage 1 nA VCP = VP/2

Sink and Source Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

= 3.3 V ± 10%; VP = AVDD to 5.5 V; A

VDD

GND

= D

= 0 V; TA = T

GND

B Version

Unit Conditions/Comments Min Typ Max

1.5 V

INH

0.6 V

INL

±1 µA

INH/IINL

MIN

to T

, unless otherwise noted. Operating

MAX

= 5.1 kΩ

SET

LOGIC OUTPUTS

Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen

Output High Current, IOH 500 µA

Output Low Voltage, VO 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 3.0 3.6 V

DVDD, SD

VP AVDD 5.5 V

DIDD + AI

VPI

DD

AVDD

VDD

2

40 50 mA

DD

2

2 mA VP = 5 V

Rev. B | Page 3 of 28

ADF4151 Data Sheet

B Version

Parameter

NOISE CHARACTERISTICS

Normalized In-Band Phase Noise

Floor (PN

Normalized 1/f Noise (PN

SYNTH

)3

)4 −118 dBc/Hz 10 kHz offset. Normalized to 1 GHz (ABP = 3 ns)

1_f

Normalized In-Band Phase Noise

Floor (PN

Normalized 1/f Noise (PN

Spurious Signals Due to PFD

Frequency

1

AC coupling ensures AVDD/2 bias.

2

TA = 25°C; AVDD = DVDD = 3.6 V; prescaler = 4/5; f

3

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log F

4

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)

and at a frequ ency offset (f) is given by PN = P

5

Spurious measured on EVAL-ADF4151EB1Z with RF buffer between VCO output and RF input by-passed, using a Rohde & Schwarz FSUP signal source analyzer.

SYNTH

5

)3

)4 −115 dBc/Hz 10 kHz offset; normalized to 1 GHz (ABP = 6 ns);

1_f

. PN

= PN

PFD

SYNTH

– 10 log f

TOT

−221 dBc/Hz PLL loop BW = 500 kHz (ABP = 3 ns)

−220 dBc/Hz PLL loop BW = 500 kHz (ABP = 6 ns);

−107 dBc PFD = 25 MHz

= 130 MHz; f

REFIN

– 20 log N

PFD

+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL

1_f

= 26 MHz; fRF = 1.742 GHz.

PFD

Unit Conditions/Comments Min Typ Max

low noise mode

Rev. B | Page 4 of 28

Data Sheet ADF4151

CLK

DATA

LE

DB31 (MSB) DB30

DB1 (LSB)

(CONTROL BIT C2)

DB2 (LSB)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t

1

t

2

t

3

t

7

t

6

t

4

t

5

10265-002

TIMING CHARACTERISTICS

AVDD1, AVDD2 = DVDD = SD Operating temperature range is −40°C to +85°C.

Table 2.

Parameter Limit (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

= 3.3 V ± 10%; VP = AVDD to 5 . 5 V; A

VDD

GND

= D

= 0 V; TA = T

GND

MIN

to T

, unless otherwise noted.

MAX

Figure 2. Timing Diagram

Rev. B | Page 5 of 28

ADF4151 Data Sheet

Peak Temperature

260°C

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD1, AVDD2 to GND1 −0.3 V to +3.9 V AVDD1, AVDD2 to DVDD −0.3 V to +0.3 V VP to AVDD1, AVDD2 −0.3 V to +5.8 V Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND1 −0.3 V to VDD + 0.3 V REFIN to GND1 −0.3 V to VDD + 0.3 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C LFCSP θJA Thermal Impedance

(Paddle-Soldered) 27.3°C/W

Reflow Soldering

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TRANSISTOR COUNT

36685 (CMOS) and 967 (bipolar)

ESD CAUTION

Time at Peak Temperature 40 sec

1

GND = A

GND

= D

GND

= 0 V.

Rev. B | Page 6 of 28

Data Sheet ADF4151

1

CLK

2

DATA

3

LE

4

CE

5

SW

6 7

24 23

NC

22 21 20 19 18 17

8

SDV

DD

ADF4151

TOP VIEW

(Not to Scale)

9

A

GND

10

11

REF

IN

12

D

GND

13

DV

DD

141516

3231302928

SD

GND

27

26

25

PIN 1 INDICATOR

V

P

CP

OUT

CP

GND

MUXOUT

R

SET

NC

RF

IN

+

RF

IN

−

NC

NC NC

D

GND

LD

A

GND

A

GND

A

GND

NC

AV

DD

2

AV

DD

2

AV

DD

1

NOTES

1. NC = NO CONNE CT. DO NOT CONNECT TO THIS PIN.

2. THE LFCSP HAS AN EXPO S E D P ADDLE THAT MUST BE CONNECTED TO GND.

10265-003

5

SW

Fast Lock Switch. Make a connection to this pin from the loop filter when using the fast lock mode.

8

CP

Charge Pump Ground. This is the ground return pin for CP

.

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2 D ATA Serial Data Input. The serial data is loaded, MSB first, with the three LSBs as the control bits. This input is a high

impedance CMOS input.

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.

6 VP Charge Pump Power Supply. This pin should be greater than or equal to AVDD. In systems where AVDDx is 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.

7 CP

9, 11, 18,

Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter

OUT

GND

A

Analog Ground. This is a ground return pin for AVDD1 and AVDD2.

GND

is connected to V

to drive the external VCO.

TUNE

21 10 AVDD1 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

12, 13, 19,

are to be placed as close as possible to this pin. AV

NC No connect. Do not connect to this pin.

DD

20, 23, 24 14 RFIN+ Input to the RF Input. This small signal input is ac-coupled to the external VCO. 15 RFIN− Complementary Input to the RF Input. This pin must be decoupled to the ground plane with a small bypass

16, 17 AVDD2 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

capacitor, typically 100 pF.

are to be placed as close as possible to this pin. AV

Rev. B | Page 7 of 28

DD

OUT

must have the same value as DVDD.

x must have the same value as DVDD.

ADF4151 Data Sheet

SET

CP

R

I

22.95

=

28

DVDD

Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

Pin No. Mnemonic Description

22 R

25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of PLL

26, 27 D

29 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance

30 MUXOUT

31 SD 32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDDx. Decoupling capacitors

EP The exposed pad must be connected to GND.

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

SET

bias at the R

pin is 0.49 V. The relationship between ICP and R

SET

is

where:

R

= 5.1 kΩ.

SET

= 4.5 mA.

I

CP

lock.

Digital Ground. Ground return path for DVDD.

GND

should be placed as close as possible to this pin.

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

frequency to be accessed externally.

Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.

GND

to the ground plane are to be placed as close as possible to this pin.

Rev. B | Page 8 of 28

Data Sheet ADF4151

0

–40

–35

–30

–25

–20

–15

–10

–5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

POWER (dBm)

FREQUENCY ( GHz)

–40°C

+25°C

+85°C

10265-004

6.0

–6.0

–5.5

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.04.54.0

I

CP

(mA)

VCP (V)

0.28mA

0.56mA

1.13mA

2.25mA

4.5mA

SOURCE SINK

10265-005

–90

–100

–99

–98

–97

–96

–95

–94

–93

–92

–91

2.60 2.61 2.62 2.63 2.64 2.65 2.66 2.67 2.68 2.702.69

PHASE NOISE (dBc/Hz)

FREQUENCY ( GHz)

LOW NOISE MODE

LOW SP UR M ODE

10265-006

6.0

–6.0

–5.5

–5.0

–4.5

–4.0

–3.5

–3.0

–2.5

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5.04.54.0

I

CP

MISMATCH ( %)

V

CP

(V)

ICP = 0.28mA ICP = 0.56mA ICP = 1.13mA ICP = 2.25mA ICP = 4.5mA

10265-007

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. RF Input Sensitivity

Figure 5. Charge Pump Output Characteristics, VP = 5 V, Selected ICP Values

Between 0.28 mA (Min) and 4.5 mA (Max), R

= 5.1 kΩ

SET

Figure 6. In-Band Phase Noise Measured at 10 kHz Offset

for Low Noise Mode and Low Spur Mode,

PFD = 25 MHz, PLL Loop Bandwidth = 50 kHz

Figure 7. Charge Pump Output Mismatch vs. VCP , Selected ICP Values Between

0.28 mA (Min) and 4.5 mA (Max), R

= 5.1 kΩ

SET

Rev. B | Page 9 of 28

ANALOG DEVICES ADF4151 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

TRANSISTOR COUNT

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS