ANALOG DEVICES ADF4150HV Service Manual

High Voltage, Fractional-N/

V

FEATURES

Fractional-N synthesizer and integer-N synthesizer High voltage charge pump: V

Tuning range: 1.0 V to 29 V (or ±1 V from V RF bandwidth to 3.0 GHz Programmable divide-by-1/-2/-4/-8/-16 outputs Synthesizer power supply: 3.0 V to 3.6 V Programmable dual-modulus prescaler of 4/5 or 8/9 Programmable output power level Programmable charge pump currents RF output mute function 3-wire serial interface Analog and digital lock detect

APPLICATIONS

Wireless infrastructure Microwave point-to-point/point-to-multipoint radios VSAT radios Test equipment Private land mobile radios

= 6 V to 30 V

P

SDV

DD

supply rails)

P

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

Integer-N PLL Synthesizer

ADF4150HV

GENERAL DESCRIPTION

The ADF4150HV is a 3.0 GHz, fractional-N or integer-N frequency synthesizer with an integrated high voltage charge pump. The synthesizer can be used to drive external wideband VCOs directly, eliminating the need for operational amplifiers to achieve higher tuning voltages. This simplifies design and reduces cost while improving phase noise, in contrast to active filter topologies, which tend to degrade phase noise compared to passive filter topologies.

The VCO frequency can be divided by 1, 2, 4, 8, or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.

A simple 3-wire interface controls all on-chip registers. The charge pump operates from a power supply ranging from 6 V to 30 V, whereas the rest of the device operates from 3.0 V to 3.6 V. The ADF4150HV can be powered down when not in use.

DD

P

R

SET

REF

IN

CLK

DATA

LE

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

×2

DOUBLER

DATA REG ISTE R

N COUNTER

INTEGER

VALUE

10-BIT R

COUNTER

FRACTION

VALUE

THIRD-ORDER

FRACTIONAL

INTERPOL ATOR

÷2

DIVIDER

FUNCTION

LATCH

MODULUS

VALUE

LOCK

DETECT

PHASE

COMPARATOR

MULTIPLEXER

HIGH VOL TAGE

CHARGE

PUMP

CURRENT

SETTING

DIVIDE -BY-1/

-2/-4/-8/-16

BOOST

MODE

OUTPUT

STAGE

INPUT

RF

MUXOUT

LD

CP

RF

PDB

RF

ADF4150HV

GNDCE CP

GND

SD

GND

Figure 1.

OUT

IN

+

–

RF

+

–

09058-001

ADF4150HV

REVISION HISTORY

8/11—Revision 0: Initial Version



Register 1 ..................................................................................... 17

Register 2 ..................................................................................... 17

Register 3 ..................................................................................... 19

Register 4 ..................................................................................... 19

Register 5 ..................................................................................... 19

Register Initialization Sequence ............................................... 19

RF Synthesizer—A Worked Example ...................................... 20

Reference Doubler and Reference Divider ............................. 20

12-Bit Programmable Modulus ................................................ 20

Spurious Optimization and Boost Mode ................................ 21

Spur Mechanisms ....................................................................... 21

Spur Consistency and Fractional Spur Optimization ........... 21

Phase Resync ............................................................................... 22

Applications Information .............................................................. 23

Ultrawideband PLL .................................................................... 23

Microwave PLL ........................................................................... 23

Generating the High Voltage Supply ....................................... 24

Interfacing to the ADuC702x and the ADSP-BF527 ............. 25

PCB Design Guidelines for a Chip Scale Package ................. 25

Output Matching ........................................................................ 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

Rev. 0 | Page 2 of 28

ADF4150HV

SPECIFICATIONS

AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = 6.0 V to 30 V; GND = 0 V; TA = T range is −40°C to +85°C.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

REFIN CHARACTERISTICS

Input Frequency 10 300 MHz For f < 10 MHz, ensure slew rate > 21 V/μs

10 30 MHz

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/2; ac coupling ensures AVDD/2 bias

Input Capacitance 5.0 pF

Input Current ±60 μA

RF INPUT CHARACTERISTICS

RF Input Frequency (RFIN) 0.5 3.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm

Prescaler Output Frequency 750 MHz

PHASE DETECTOR

Phase Detector Frequency 26 MHz Low noise mode

20 MHz Low spur mode

26 MHz Integer-N mode

HIGH VOLTAGE CHARGE PUMP

ICP Sink/Source

High Value 384 μA R Low Value 48 μA R R

Range 3.3 10 kΩ

SET

High Value vs. R

196 μA R

SET

594 μA R Sink and Source Current Matching 6 % 1.0 V ≤ VCP ≤ (VP − 1.0 V); VP = 6 V to 30 V Absolute ICP Accuracy 3 % ICP vs. VCP 2.5 % 1.0 V ≤ VCP ≤ (VP − 1.0 V) ICP vs. Temperature 2.5 % VCP = VP/2 ICP Leakage 2.5 nA VCP = VP/2

LOGIC INPUTS

Input High Voltage, V Input Low Voltage, V Input Current, I

INH/IINL

2.0 V

INH

0.6 V

INL

±1 μA

Input Capacitance, CIN 15.0 pF

LOGIC OUTPUTS

Output High Voltage, VOH DVDD − 0.4 V CMOS output selected Output High Current, IOH 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 3.0 3.6 V DVDD, SDVDD AVDD V VP 6.0 30 V

IP 1 2.5 mA VP = 30 V DIDD + AI

1

50 60 mA

DD

Current per Output Divider 6 to 24 mA Each output divide-by-2 consumes 6 mA typ

2

I

RFOUT

20 32 mA RF output stage is programmable

Low Power Sleep Mode 1 μA

MIN

to T

, unless otherwise noted. Operating temperature

MAX

Reference doubler enabled (DB25 bit in Register 2 is set to 1)

For lower RF

frequencies, ensure slew

IN

rate > 400 V/μs

= 5.1 kΩ

SET

= 5.1 kΩ

SET

= 10 kΩ

SET

= 3.3 kΩ

SET

Set the V

supply at least 1 V above the

P

maximum desired tuning voltage

Rev. 0 | Page 3 of 28

ADF4150HV

Parameter Min Typ Max Unit Test Conditions/Comments

RF OUTPUT CHARACTERISTICS

Output Frequency Using RF Output

Dividers

Harmonic Content (Second) −19 dBc Fundamental VCO output

−20 dBc Divided VCO output Harmonic Content (Third) −13 dBc Fundamental VCO output

−10 dBc Divided VCO output Minimum RF Output Power Maximum RF Output Power

2

−4 dBm Programmable in 3 dB steps

2

5 dBm Programmable in 3 dB steps

Output Power Variation vs. Supply ±1 dB

Output Power Variation vs. Temperature ±1 dB From −40°C to +85°C Level of Signal with RF Mute Enabled −37 dBm PDBRF pin brought low; RF = 2 GHz

NOISE CHARACTERISTICS

Normalized In-Band Phase Noise

Floor (PN

SYNTH

3

)

−203 dBc/Hz Low spur mode Normalized 1/f Noise (PN

4

)

−113 dBc/Hz Low noise mode

1_f

−108 dBc/Hz Low spur mode RF Output Divider Noise Floor −155 dBc/Hz Measured at 10 MHz offset Spurious Signals Due to PFD Frequency −70 dBc At RF

−85 dBc At VCO output

1

TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; f

2

Using 50 Ω resistors to AVDD, into a 50 Ω load.

3

This figure can be used to calculate phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:

PN

= PN

SYNTH

4

The PLL phase noise is composed of flicker (1/f) noise plus the normalized PLL noise floor. The flicker noise is specified at a 10 kHz offset and normalized to 1 GHz. The

formula for calculating the 1/f noise contribution at an RF frequency (fRF) and at a frequency offset (f) is given by PN = PN the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

− 10 log(f

TOT

) − 20 log N.

PFD

31.25 MHz 500 MHz VCO input and divide-by-16 selected

Pull-up supply on Pin 18 and Pin 19 varied from 3.0 V to 3.6 V

−213 dBc/Hz Low noise mode

+/RF

− pins

OUT

+ 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both

1_f

= 100 MHz; f

REFIN

= 25 MHz; fRF = 1.75 GHz.

PFD

OUT

Rev. 0 | Page 4 of 28

ADF4150HV

TIMING CHARACTERISTICS

AVDD = DVDD = SDVDD = 3.3 V ± 10%; VP = 6.0 V to 30 V; GND = 0 V; TA = T range is −40°C to +85°C.

Table 2.

Parameter Limit Unit Description

t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

Timing Diagram

t

4

CLK

to T

MIN

t

5

, unless otherwise noted. Operating temperature

MAX

DATA

DB31 (MSB) DB30

LE

t

1

LE

t

2

t

3

DB2

(CONTROL BIT C3)

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

t

7

09058-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF4150HV

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V AVDD to DVDD −0.3 V to +0.3 V VP to GND1 −0.3 V to +33 V Digital I/O Voltage to GND1 −0.3 V to AVDD + 0.3 V Analog I/O Voltage to GND1 −0.3 V to DVDD + 0.3 V REFIN to GND1 −0.3 V to AVDD + 0.3 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +125°C Maximum Junction Temperature 150°C Reflow Soldering

Peak Temperature 260°C Time at Peak Temperature 40 sec

1

GND = CP

GND

= SD

GND

= 0 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TRANSISTOR COUNT

The transistor count for the ADF4150HV is 23,380 (CMOS) and 809 (bipolar).

THERMAL RESISTANCE

Thermal impedance (θJA) is specified for a device with the exposed pad soldered to GND.

Table 4. Thermal Resistance

Package Type θJA Unit

32-Lead LFCSP (CP-32-11) 27.3 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

ADF4150HV

–

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

SDVDDMUXOUTLDREF

–

+

DD

IN

AV

RF

IN

25

GND

24 GND 23

GND DV

22

PDB

21 20

AV

19

RF

18

RF

17 GND

DD

OUT

RF

+

09058-003

GND

SET

GND

R

GND

SD

32313029282726

GND

1 2

CLK

DAT

3 4 5 6

P

7 8

ADF4150HV

TOP VIEW

(Not to Scale)

9

10111213141516

DD

OUT

GND

AV

CP

LE CE

V GND GND

NOTES

1. THE LFCSP HAS AN EXPO SED PAD THAT MUST BE CONNECTED TO GND.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1, 7, 8, 12, 16, 17,

GND Ground. All ground pins should be tied together.

23, 24, 30, 32

2 CLK

Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

3 DATA

Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high impedance CMOS input.

4 LE

Load Enable. When LE goes high, the data stored in the 32-bit shift register is loaded into the register that is selected by the three control bits. This input is a high impedance CMOS input.

5 CE

6 VP

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A logic high on this pin powers up the device.

High Voltage Charge Pump Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible. The decoupling capacitors should have the appropriate voltage rating (a value of 10 μF is recommended). Care should be taken to ensure that V

does not exceed the absolute maximum

P

ratings on power-up (see Table 3 ). A 10 Ω series resistor can help to significantly reduce voltage overshoot with minimal IR drop.

9 CP

10 CP 11, 13, 20 AVDD

OUT

High Voltage Charge Pump Output. When enabled, this output provides ±I filter. The output of the loop filter is connected to the voltage tuning port of the external VCO.

High Voltage Charge Pump Ground. All ground pins should be tied together.

GND

Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Place decoupling capacitors to the ground plane as close to this pin as possible. AV

must have the same value as DVDD.

DD

to the external passive loop

CP

14 RFIN+ Positive RF Input. The output of the VCO or external prescaler should be ac-coupled to this pin. 15 RFIN−

Complementary RF Input. If a single-ended input is required, this pin can be tied to ground via a 100 pF capacitor.

18 RF

OUT

−

Divided-Down Output of RF

−. This pin can be left unconnected if the divider functionality is not

IN

required.

19 RF

OUT

+

Divided-Down Output of RF

+. This pin can be left unconnected if the divider functionality is not

IN

required. 21 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable. 22 DVDD

25 REFIN

Digital Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible.

must have the same value as AVDD.

DV

DD

Reference Input. This CMOS input has a nominal threshold of AV

/2 and a dc equivalent input resistance

DD

of 100 kΩ. This input can be driven from a crystal oscillator, TCXO, or other reference. 26 LD

Lock Detect Output. A logic high output on this pin indicates PLL lock. A logic low output indicates loss

of PLL lock.

Rev. 0 | Page 7 of 28

ADF4150HV

Pin No. Mnemonic Description

27 MUXOUT

28 SDVDD

29 SD 31 R

Digital Σ-Δ Modulator Ground. All ground pins should be tied together.

GND

SET

EP Exposed Pad Exposed Pad. The LFCSP has an exposed pad that must be connected to GND.

Multiplexer Output. The multiplexer output allows the lock detect, the N divider value, or the R counter value to be accessed externally.

Digital Σ-Δ Modulator Power Supply. Place decoupling capacitors to the ground plane as close to this pin as possible. SDVDD must have the same value as AVDD.

Connecting a resistor between this pin and GND sets the charge pump output current. Place the resistor as close to this pin as possible. The nominal voltage bias at the R I

and R

CP

is as follows:

SET

ICP = 1.96/R

SET

pin is 0.55 V. The relationship between

SET

where:

= 5.1 kΩ.

R

SET

I

= 384 μA.

CP

Rev. 0 | Page 8 of 28

ADF4150HV

–

TYPICAL PERFORMANCE CHARACTERISTICS

600 550 500 450 400 350 300 250 200 150 100

50

(µA)

0

CP

I

–50 –100 –150 –200 –250 –300 –350 –400 –450 –500

0 2 4 6 8 10121416182022242628

ICP = 400µ A SOURCE ICP = 350µ A SOURCE ICP = 300µ A SOURCE ICP = 250µ A SOURCE ICP = 200µ A SOURCE ICP = 150µ A SOURCE ICP = 100µ A SOURCE

ICP = 50µA SOURCE

ICP = 50µA SINK ICP = 100µA SINK ICP = 150µA SINK ICP = 200µA SINK ICP = 250µA SINK ICP = 300µA SINK ICP = 350µA SINK ICP = 400µA SINK

VCP (V)

Figure 4. Charge Pump Output Characteristics, VP = 28 V,

Varied from 50 μA to 400 μA, R

I

CP

= 5.1 kΩ

SET

09058-004

16

14

12

10

8

6

4

2

0

–2

MISMATCH (%)

–4

CP

I

–6

–8

–10

–12

–14

–16

0 2 4 6 8 10121416182022242628

VP = 6V MISMATCH (%) VP = 9V MISMATCH (%) VP = 12V MISMATCH (%) VP = 15V MISMATCH (%) VP = 18V MISMATCH (%) VP = 21V MISMATCH (%) VP = 24V MISMATCH (%) VP = 28V MISMATCH (%)

VCP (V)

Figure 7. Charge Pump Output Mismatch vs. VP, ICP = 200 μA

09058-007

80 –85 –90 –95

–100 –105 –110 –115 –120 –125 –130 –135 –140

PHASE NOISE (d Bc/Hz)

–145 –150 –155 –160 –165 –170

100 1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

ADF4150HV RMS NOISE = 0.28°

ADF4156 RMS NOISE = 0.36°

Figure 5. Active Filter Phase Noise, ADF4150HV vs. ADF4156;

Active Filter Implemented Using OP27 Op Amp; PFD = 20 MHz, Loop

Bandwidth = 10 kHz, I

2.0

1.9

1.8

1.7

1.6

1.5

1.4

FREQUENCY (GHz)

1.3

1.2

1.1

1.0 0 50 100 150 200 250 300

= 300 μA, Carrier Frequency = 1.7 GHz, VP = 28 V

CP

BOOST MODE ON

BOOST MODE O FF

TIME (µs)

Figure 6. PLL Lock Time with Boost Mode On and Off;

Locking over Octave Range Jump (1 GHz to 2 GHz) for PFD = 20 MHz,

Loop Bandwidth = 100 kHz, I

= 300 μA, VP = 28 V, VDD = 3.3 V, REFIN = 100 MHz

CP

40

–50

BEAT NOTE

–60

–70

–80

–90

–100

SPUR LEVEL (dBc)

–110

–120

–130

1500 15251520151515101505

09058-005

SPUR

200kHz 400kHz

FREQUE NCY (MHz)

600kHz 800kHz

BEAT NOTE

SPUR

09058-008

Figure 8. Fractional Spur Levels vs. Frequency, Low Spur Mode;

Measured at VCO Output, PFD = 25 MHz, MOD = 125

40

–50

–60

–70

–80

–90

–100

SPUR LEVEL (dBc)

–110

–120

–130

09058-006

1500 15251520151515101505

200kHz 400kHz

FREQUENCY (MHz)

600kHz 800kHz

09058-009

Figure 9. Fractional Spur Levels vs. Frequency, Low Noise Mode;

Measured at VCO Output, PFD = 25 MHz, MOD = 125

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADF4150HV Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING CHARACTERISTICS

Timing Diagram

ABSOLUTE MAXIMUM RATINGS

TRANSISTOR COUNT

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS