ANALOG DEVICES ADF4150 Service Manual

ADF4150

MUXOUT

CP

OUT

LD

SW

REF

IN

CLK

DATA

LE

AV

DD

SDV

DD

DV

DD

V

P

A

GND

CE CP

GND

SD

GND

R

SET

RF

OUT

+

RF

OUT

–

RF

IN

+

RF

IN

–

PHASE

COMPARATOR

FL

O

SWITCH

CHARGE

PUMP

OUTPUT

STAGE

RF

INPUT

PDB

RF

MULTIPLEXER

10-BIT R

COUNTER

÷2

DIVIDER

×2

DOUBLER

FUNCTION

LATCH

DATA REGIS TER

INTEGER

REG

N COUNTER

FRACTION

REG

THIRD-ORDER

FRACTIONAL

INTERPOLATOR

MODULUS

REG

MULTIPLEXER

LOCK

DETECT

ADF4150

08226-001

DIVIDE-BY-1/

-2/-4/-8/-16

Fractional-N/Integer-N PLL Synthesizer

FEATURES

Fractional-N synthesizer and integer-N synthesizer
Programmable divide-by-1/-2/-4/-8/-16 output

5.0 GHz RF bandwidth

3.0 V to 3.6 V power supply

1.8 V logic compatibility
Separate charge pump supply (V

voltage in 3 V systems
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction

APPLICATIONS

Wireless infrastructure (W-CDMA, TD-SCDMA, WiMax, GSM,

PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation

) allows extended tuning

P

GENERAL DESCRIPTION

The ADF4150 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external voltage-controlled oscillator (VCO),
loop filter, and external reference frequency.

The ADF4150 is for use with external VCO parts and is
software compatible with the ADF4350. The VCO frequency
can be divided by 1/2/4/8/16 to allow the user to generate RF
output frequencies as low as 31.25 MHz. For applications that
require isolation the RF output stage can be muted. The mute
function is both pin and software controllable.

Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.

The ADF4150 is available in a 4 mm × 4 mm package.

FUNCTIONAL BLOCK DIAGRAM

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of thi rd parties that may result from its use. Specifications subject to change with out notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

www.analog.com

ADF4150

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Circuit Description ......................................................................... 11

Reference Input Section ............................................................. 11

RF N Divider ............................................................................... 11

INT, FRAC, MOD, and R Counter Relationship.................... 11

INT N Mode ................................................................................ 11

R Counter .................................................................................... 11

Phase Frequency Detector (PFD) and Charge Pump ............ 11

MUXOUT and Lock Detect ...................................................... 12

Input Shift Registers ................................................................... 12

Program Modes .......................................................................... 12

Output Stage ................................................................................ 12

Register Maps .................................................................................. 13

Register 0 ..................................................................................... 18

Register 1 ..................................................................................... 18

Register 2 ..................................................................................... 18

Register 3 ..................................................................................... 20

Register 4 ..................................................................................... 20

Register 5 ..................................................................................... 20

Initialization Sequence .............................................................. 20

RF Synthesizer—A Worked Example ...................................... 21

Modulus ....................................................................................... 21

Reference Doubler and Reference Divider ............................. 21

12-Bit Programmable Modulus ................................................ 21

Cycle Slip Reduction for Faster Lock Times ........................... 22

Spurious Optimization and Fast lock ...................................... 22

Fast Lock Timer and Register Sequences ................................ 22

Fast Lock—An Example ............................................................ 23

Fast Lock—Loop Filter Topology ............................................. 23

Spur Mechanisms ....................................................................... 23

Spur Consistency and Fractional Spur Optimization ........... 24

Phase Resync ............................................................................... 24

Applications Information .............................................................. 25

Direct Conversion Modulator .................................................. 25

Interfacing ................................................................................... 26

PCB Design Guidelines for Chip Scale Package .................... 26

Output Matching ........................................................................ 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

7/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADF4150

INL

SPECIFICATIONS

AVDD = DVDD = SD
operating temperature range is −40°C to +85°C.

Table 1.

Parameter

REFIN CHARACTERISTICS

Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/µs

Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21

Input Capacitance 5.0 pF

Input Current ±60 µA

RF INPUT CHARACTERISTICS

RF Input Frequency (RFIN), RF Output

Buffer Disabled

RF Input Frequency (RFIN), RF Output

Buffer Disabled

RF Input Frequency (RFIN) RF Output

Buffer Enabled

RF Input Frequency (RFIN) RF Output

Buffer and Dividers Enabled

Prescaler Output Frequency 750 MHz

MAXIMUM PFD FREQUENCY

Fractional-N (Low Spur Mode) 26 MHz

Fractional-N Mode (Low Noise Mode) 32 MHz

Integer-N Mode 32 MHz

CHARGE PUMP

ICP Sink/Source R

High Value 4.65 mA
Low Value 0.29 mA
R

Range 2.7 10 kΩ

SET

I

Leakage 1 nA VCP = VP/2

CP

Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP 1 % 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

Input High Voltage, V

Input Low Voltage, V

Input Current, I

Input Capacitance, CIN 3.0 pF

LOGIC OUTPUTS

Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen

Output High Current, IOH 500 µA

Output Low Voltage, VO 0.4 V IOL = 500 µA

POWER SUPPLIES

AVDD 3.0 3.6 V

DVDD, SD

AVDD

VDD

VP AVDD 5.5 V

DIDD + AI

2

50 60 mA

DD

Output Dividers 6 to 24 mA Each output divide by two consumes 6 mA

2

I

24 32 mA RF output stage is programmable

RFOUT

Low Power Sleep Mode 1 µA

= 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T

VDD

B Version

Unit Conditions/Comments Min Typ Max

0.5 4.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm

0.5 5.0 GHz −5 dBm ≤ RF input power ≤ +5 dBm

0.5 3.5 GHz −10 dBm ≤ RF input power ≤ +5 dBm

0.5 3.0 GHz −10 dBm ≤ RF input power ≤ +5 dBm

1.5 V

INH

0.6 V

±1 µA

INH/IINL

MIN

to T

SET

, unless otherwise noted. The

MAX

= 5.1 kΩ

Rev. 0 | Page 3 of 28

ADF4150

B Version

Parameter

RF OUTPUT CHARACTERISTICS

Minimum Output Frequency Using RF

31.25 MHz 500 MHz VCO input and divide-by-16 selected

Output Dividers

Maximum RFIN Frequency Using RF

4400 MHz

Output Dividers
Harmonic Content (Second) −19 dBc Fundamental VCO output
Harmonic Content (Third) −13 dBc Fundamental VCO output
Harmonic Content (Second) −20 dBc Divided VCO output
Harmonic Content (Third) −10 dBc Divided VCO output
Output Power 3 −4 dBm Maximum setting
+5 dBm Minimum setting
Output Power Variation ±1 dB
Level of Signal With RF Mute Enabled −40 dBm

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

(PN

SYNTH

4

)
Normalized 1/f Noise (PN
Normalized Phase Noise Floor

(PN

SYNTH

4

)
Normalized 1/f Noise (PN

Spurious Signals Due to PFD
Frequency

6

)5

1_f

)5

1_f

−223 dBc/Hz

−123

dBc/Hz

−222 dBc/Hz

−119

dBc/Hz

−90 dBc VCO output

−75 dBc RF output buffers

1

AC coupling ensures AVDD/2 bias.

2

TA = 25°C; AVDD = DVDD = 3.3 V; prescaler = 8/9; f

3

Using a tuned load.

4

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider

value) and 10 log F

5

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (FRF)

and at a frequ ency offset (f) is given by PN = P

6

Spurious measured on EVAL-ADF4150EB1Z, using a Rohde & Schwarz FSUP signal source analyzer.

. PN

= PN

PFD

SYNTH

− 10logF

TOT

= 100 MHz; f

REFIN

− 20logN.

PFD

+ 10log(10 kHz/f) + 20log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

1_f

= 26 MHz; fRF = 1.7422 GHz.

PFD

Unit Conditions/Comments Min Typ Max

PLL loop BW = 500 kHz (ABP = 3 ns)

10 kHz offset. Normalized to 1 GHz. (ABP = 3 ns)
PLL loop BW = 500 kHz (ABP = 6 ns); low noise

mode selected
10 kHz offset; normalized to 1 GHz; (ABP = 6 ns);

low noise mode selected

Rev. 0 | Page 4 of 28

ADF4150

CLK

DATA

LE

LE

DB31 (MSB) DB30

DB1

(CONTROL BIT C2)

DB2

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t

1

t

2

t

3

t

7

t

6

t

4

t

5

08226-002

TIMING CHARACTERISTICS

AVDD = DVDD = SD
temperature range is −40°C to +85°C.

Table 2.

Parameter Limit (B Version) Unit Test Conditions/Comments

t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width

= 3.3 V ± 10%; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = T

VDD

MIN

to T

, unless otherwise noted. Operating

MAX

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF4150

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND1 −0.3 V to VDD + 0.3 V
REFIN to GND1 −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance

(Paddle-Soldered) 27.3°C/W

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 40 sec

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

TRANSISTOR COUNT

23380 (CMOS) and 809 (bipolar)

ESD CAUTION

Rev. 0 | Page 6 of 28

ADF4150

A

GND

AV

DD

2

DV

DD

REF

IN

SDV

DD

SD

GND

MUXOUT

R

SET

RF

OUT

+

RF

OUT

−

PDB

RF

LD

NOTES

1. THE LFCSP HAS AN EXPO S E D P ADDLE
THAT MUST BE CONNECTED TO GND.

PIN 1
INDICATOR

1CLK
2DATA
3LE
4CE
5SW
6V

P

15

16

17

18

14
13

7CP

OUT

8

CP

GND

9

AV

DD

1

11

RF

IN

–

12A

GND

10

RF

IN

+

21

22

23

24

20

19

ADF4150

TOP VIEW

(Not to S cale)

08226-003

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.

2 DATA Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high

impedance CMOS input.

3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register

that is selected by the three LSBs.

4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state

mode. Taking the pin high powers up the device depending on the status of the power-down bits.
5 SW Fastlock Switch. Make a connection to this pin from the loop filter when using the fastlock mode.
6 VP Charge Pump Power Supply. This pin should be greater than or equal to AVDD. In systems where AVDD is 3 V, it

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
7 CP

8 CP
9 AVDD1 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

10 RFIN+ Input to the RF Input. This small signal input is ac-coupled to the external VCO.
11 RFIN− Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass

12, 13 A
14 RF

15 RF

16 AVDD2 Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane

17 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
18 DVDD Digital Power Supply. This pin should be the same voltage as AVDD. Place decoupling capacitors to the ground

19 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance

20 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock; a logic low output indicates loss of

21 MUXOUT

Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter

OUT

is connected to V

Charge Pump Ground. This is the ground return pin for CP

GND

are to be placed as close as possible to this pin. AV

to drive the external VCO.

TUNE

.

OUT

must have the same value as DVDD.

DD

capacitor, typically 100 pF.

Analog Ground. This is a ground return pin for AVDD1 and AVDD2.

GND

− Complementary RF Output. The output level is programmable. The VCO fundamental output or a divided

OUT

down version is available.

+ RF Output. The output level is programmable. The VCO fundamental output or a divided down version is

OUT

available.

are to be placed as close as possible to this pin. AV

2 must have the same value as DVDD.

DD

plane as close as possible to this pin.

of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

PLL lock.

frequency to be accessed externally.

Rev. 0 | Page 7 of 28

ADF4150

SET

CP

R

I

23.9

=

Pin No. Mnemonic Description

22 SDVDD Power Supply Pin for the Digital Sigma-Delta (Σ-Δ) Modulator. This pin should be the same voltage as AVDD.

Decoupling capacitors to the ground plane are to be placed as close as possible to this pin.
23 SD
24 R

25 EP The exposed pad must be connected to GND.

Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.

GND

Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage

SET

bias at the R

pin is 0.48 V. The relationship between ICP and R

SET

SET

is

where:

R

= 5.1 kΩ.

SET

= 5 mA.

I

CP

Rev. 0 | Page 8 of 28

ADF4150

0

–50

0 5.0

POWER (dBm)

FREQUENCY ( GHz)

08226-042

–45

–40

–35

–30

–25

–20

–15

–10

–5

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

+25°C
+85°C
–40°C

10

–50

0 6

POWER (dBm)

FREQUENCY (MHz)

08226-043

–40

–30

–20

–10

0

1 2 3 4 5

+25°C
+85°C
–40°C

0

–40

0 4.0

POWER (dBm)

FREQUENCY ( GHz)

08226-044

–35

–30

–25

–20

–15

–10

–5

0.5 1.0 1.5 2.0 3.02.5 3.5

+25°C
+85°C
–40°C

–180

–160

–140

–120

–100

–80

–60

POWER (dBc)

08226-045

1k 10k 100k 1M 10M

FREQUENCY (Hz)

1M 10M 100M 1G 10G

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

POWER (dBc)

08226-046

1k 10k 100k 1M 10M

FREQUENCY (Hz)

–180

–160

–140

–120

–100

–80

–60

POWER (dBc)

08226-047

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. RF Input Sensitivity; RF Output Enabled; Output Divide-by-1

Selected

Figure 5. RF Input Sensitivity; RF Output Disabled

Figure 7. Integer-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REF

= 100 MHz, PFD = 25 MHz, Loop Filter

IN

Bandwidth= 50 kHz

Figure 8. Fractional-N Phase Noise and Spur Performance; Low Noise Mode;

VCOOUT = 1750 MHz, REF

Bandwidth= 15 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

= 100 MHz, PFD = 25 MHz, Loop Filter

IN

Figure 6. RF Sensitivity; RF Output Enabled (RF Dividers-by-2/-4/-8/-16

Enabled)

Figure 9. Fractional-N Phase Noise and Spur Performance; Low Spur Mode;

VCOOUT = 1750 MHz, REF

Bandwidth= 50 kHz, Channel Spacing = 200 kHz. FRAC = 26, MOD = 125

= 100 MHz, PFD = 25 MHz, Loop Filter

IN

Rev. 0 | Page 9 of 28