ANALOG DEVICES ADF4117 Service Manual

V

RF PLL Frequency Synthesizers

FEATURES

ADF4116: 550 MHz
ADF4117: 1.2 GHz
ADF4118: 3.0 GHz

2.7 V to 5.5 V power supply
Separate V
Y Grade: −40°C to +125°C
Dual-modulus prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33
3-wire serial interface
Digital lock detect
Power-down mode
Fastlock mode

APPLICATIONS

Base stations for wireless radio

(GSM, PCS, DCS, CDMA, WCDMA)
Wireless handsets

(GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment

allows extended tuning voltage in 3 V systems

P

AV

ADF4116/ADF4117/ADF4118

GENERAL DESCRIPTION

The ADF411x family of frequency synthesizers can be used to
implement local oscillators (LO) in the upconversion and
downconversion sections of wireless receivers and transmitters.
They consist of a low noise digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, programmable A and B counters, and a dual-modulus
prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in
conjunction with the dual-modulus prescaler (P/P + 1),
implement an N divider (N = BP + A). In addition, the 14-bit
reference counter (R counter) allows selectable REF
at the PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO).

All of the on-chip registers are controlled via a simple 3-wire
interface. The devices operate with a power supply ranging
from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

DV

DD

DD

CPGND

P

frequencies

IN

ADF4116/ADF4117/ADF4118

REF

IN

CLK

DATA

LE

A

RF

IN

RF

B

IN

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

21-BIT

INPUT REGISTER

SD

FROM

FUNCTION LATCH

PRESCALER

P/P + 1

19

OUT

N = BP + A

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13

13-BIT

B COUNTER

LOAD

LOAD

5-BIT

A COUNTER

14

5

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

18

AV

DD

SD

OUT

DGNDAGNDCE

CHARGE

PUMP

MUX

M3 M2 M1

FL

SWITCH

CP

HIGH Z

MUXOUT

O

FL

O

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2000–2007 Analog Devices, Inc. All rights reserved.

00392-001

ADF4116/ADF4117/ADF4118

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 12

Reference Input Section............................................................. 12

RF Input Stage............................................................................. 12

Prescaler (P/P + 1)...................................................................... 12

A Counter and B Counter......................................................... 12

R Counter ....................................................................................12

Phase Frequency Detector (PFD) and Charge Pump............ 13

MUXOUT and Lock Detect...................................................... 13

Input Shift Register..................................................................... 13

REVISION HISTORY

4/07—Rev. C to Rev. D

Changes to REF

Changes to Table 4............................................................................ 7

Changes to Figure 35...................................................................... 22

Changes to Ordering Guide.......................................................... 25

11/05—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changed OSC 3B1-13M0 to FOX801BH-130............................ 21

Changes to Ordering Guide.......................................................... 25

Characteristics Section..................................... 3

IN

Latch Summaries........................................................................ 14

Latch Maps.................................................................................. 15

Function Latch................................................................................ 19

Counter Reset ............................................................................. 19

Power-Down ............................................................................... 19

MUXOUT Control..................................................................... 19

Phase Detector Polarity ............................................................. 19

Charge Pump Three-State......................................................... 19

Fastlock Enable Bit..................................................................... 19

Fastlock Mode Bit....................................................................... 19

Timer Counter Control............................................................. 19

Initialization Latch..................................................................... 20

Device Programming After Initial Power-Up........................ 20

Applications Information.............................................................. 21

Local Oscillator for the GSM Base Station Transmitter........ 21

Shutdown Circuit ....................................................................... 21

Direct Conversion Modulator .................................................. 21

Interfacing ................................................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide .......................................................................... 25

9/04—Rev. A to Rev. B

Changes to Specifications.................................................................3

Changes to Ordering Guide.......................................................... 25

3/01—Rev. 0 to Rev. A

4/00—Rev. 0: Initial Version

Rev. D | Page 2 of 28

ADF4116/ADF4117/ADF4118

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; TA = T
noted; dBm referred to 50 Ω.

MIN

to T

, unless otherwise

MAX

Table 1.

Parameter B Version

1

Y Version2Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity −15 to 0 −10 to 0 dBm min to max AV

−10 to 0 −10 to 0 dBm min to max AV
RF Input Frequency

= 3 V

DD

= 5 V

DD

Figure 26 for input circuit

See
ADF4116 80 to 550 MHz min to max
45 to 550 MHz min to max

Input level = −8 dBm; for lower frequencies,

ensure slew rate (SR) > 36 V/μs
ADF4117 0.1 to 1.2 GHz min to max
ADF4118 0.1 to 3.0 0.1 to 3.0 GHz min to max Input level = −10 dBm

0.2 to 3.0 GHz min to max Input level = −15 dBm

, DV
, DV

DD

DD

= 3 V
= 5 V

Maximum Allowable Prescaler

Output Frequency

3

165
200

165
200

MHz max
MHz max

AV

AV

DD

DD

REFIN CHARACTERISTICS

Reference Input Frequency 5 to 100 5 to 100 MHz min to max For f < 5 MHz, ensure SR > 100 V/μs
Reference Input Sensitivity

4, 5

0.4 to AVDD 0.4 to AVDD V p-p min to max AVDD = 3.3 V, biased at AVDD/2

0.7 to AVDD 0.7 to AVDD V p-p min to max For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/2
REFIN Input Capacitance 10 10 pF max

REFIN Input Current ±100 ±100 μA max
PHASE DETECTOR FREQUENCY5 55 55 MHz max
CHARGE PUMP

I

Sink/Source

CP

High Value 1 1 mA typ
Low Value 250 250 μA typ

Absolute Accuracy 2.5 2.5 % typ
ICP Three-State Leakage Current 3 25 nA max
1 16 nA typ
Sink and Source Current Matching 3 3 % typ 0.5 V ≤ VCP ≤ VP − 0.5

ICP vs. VCP 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min

INH

V

, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max

INL

I

, Input Current ±1 ± 1 μA max

INH/IINL

CIN, Input Capacitance 10 10 pF max
Reference Input Current ±100 ± 100 μA max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD − 0.4 DVDD − 0.4 V min IOH = 500 μA
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

Rev. D | Page 3 of 28

ADF4116/ADF4117/ADF4118

Parameter B Version

1

Y Version2Unit Test Conditions/Comments

POWER SUPPLIES

AVDD 2.7 to 5.5 2.7 to 5.5 V min to V max
DVDD AVDD AVDD
VP AVDD to 6.0 AVDD to 6.0 V min to V max AVDD ≤ VP ≤ 6.0 V
IDD (AIDD + DIDD)

6

ADF4116 5.5 mA max 4.5 mA typical
ADF4117 5.5 mA max 4.5 mA typical

ADF4118 7.5 7.5 mA max 6.5 mA typical
IP 0.4 0.4 mA max TA = 25°C
Low-Power Sleep Mode 1 1 μA typ

NOISE CHARACTERISTICS

ADF4118 Normalized Phase Noise

7

Floor

−213 −213 dBc/Hz typ

Phase Noise Performance8 @ VCO output

ADF4116 540 MHz Output

ADF4117 900 MHz Output

ADF4118 900 MHz Output

9

10

10

−89 −89 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−87 −87 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−90 −90 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency
ADF4117 836 MHz Output11 −78 −78 dBc/Hz typ @ 300 Hz offset and 30 kHz PFD frequency
ADF4118 1750 MHz Output12 −85 −85 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency
ADF4118 1750 MHz Output13 −65 −65 dBc/Hz typ @ 200 Hz offset and 10 kHz PFD frequency
ADF4118 1960 MHz Output14 −84 −84 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

Spurious Signals

ADF4116 540 MHz Output
ADF4117 900 MHz Output
ADF4118 900 MHz Output

10

10

10

−88/−99 −88/−99 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

−90/−104 −90/−104 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

−91/−100 −91/−100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency
ADF4117 836 MHz Output11 −80/−84 −80/−84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD frequency
ADF4118 1750 MHz Output
ADF4118 1750 MHz Output

12

13

−88/−90 −88/−90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

−65/−73 −65/−73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD frequency
ADF4118 1960 MHz Output14 −80/−86 −80/−86 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency

1

Operating temperature range for the B version is −40°C to +85°C.

2

Operating temperature range for the Y version is −40°C to +125°C.

3

This is the maximum operating frequency of the CMOS counters.

4

AC coupling ensures AVDD/2 bias. See Figure 35 for typical circuit.

5

Guaranteed by design.

6

TA = 25°C; AVDD = DVDD = 3 V; RFIN for ADF4116 = 540 MHz; RFIN for ADF4117, ADF4118 = 900 MHz.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN

: PN

= PN

divider value) and 10logF

8

The phase noise is measured with the EVAL-ADF411xEB and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer

= 10 MHz @ 0 dBm).

(f

REFOUT

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

PFD

SYNTH

= 200 kHz; offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; loop bandwidth = 20 kHz.

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop bandwidth = 20 kHz.

PFD

= 30 kHz; offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; loop bandwidth = 3 kHz.

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; loop bandwidth = 20 kHz.

PFD

= 10 kHz; offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; loop bandwidth = 1 kHz.

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; loop bandwidth = 20 kHz.

PFD

– 10logF

TOT

– 20logN.

PFD

, and subtracting 20logN (where N is the N

TOT

Rev. D | Page 4 of 28

ADF4116/ADF4117/ADF4118

A

TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; AVDD ≤ VP < 6.0 V; AGND = DGND = CPGND = 0 V; TA = T
Guaranteed by design, but not production tested.

Table 2.

Parameter Limit at T

MIN

to T

(B, Y Version) Unit Test Conditions/Comments

MAX

t1 10 ns min DATA to CLK setup time
t2 10 ns min DATA to CLK hold time
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
t6 20 ns min LE pulse width

t

4

CLK

t

3

MIN

to T

, unless otherwise noted.

MAX

t

2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

00392-002

DAT

t

1

DB20 (MSB) DB19 DB2

LE

LE

Figure 2. Timing Diagram

Rev. D | Page 5 of 28

ADF4116/ADF4117/ADF4118

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +7 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND1 −0.3 V to +7 V
VP to AVDD −0.3 V to +5.5 V
Digital I/O Voltage to GND1 −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND1 −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND1 −0.3 V to VDD + 0.3 V
RFINA to RFINB ±320 mV
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Extended (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 112°C/W
Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec
Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

Rev. D | Page 6 of 28

ADF4116/ADF4117/ADF4118

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FL

CP

CPGND

AGND

RF

IN

RFINA

AV

REF

O

B

DD

IN

1

2

ADF4116/

3

ADF4117/

4

ADF4118

5

TOP VIEW

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT

LE

DATA

CLK

CE

DGND

00392-003

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 FLO

Fast Lock Switch Output. This can be used to switch an external resistor to change the loop filter bandwidth
and speed up locking the PLL.

2 CP

Charge Pump Output. When enabled, this provides the ± I

to the external loop filter, which in turn drives the

CP

external VCO.
3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path for the prescaler.
5 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See

Figure 26.
6 RFINA Input to the RF Prescaler. This small signal input is ac-coupled from the VCO.
7 AVDD

8 REFIN

Analog Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to this pin. AV

Reference Input. This is a CMOS input with a nominal threshold of V
See

Figure 25. The oscillator input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

must have the same value as DVDD.

DD

/2 and an equivalent input resistance of 100 kΩ.

DD

9 DGND Digital Ground.
10 CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state
mode. Taking the pin high powers up the device depending on the status of the power-down bit F2.

11 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the
21-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

12 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs as the control bits. This input is a high
impedance CMOS input.

13 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four
latches, the latch being selected using the control bits.

14 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.

15 DVDD

Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1 μF, 1 nF)
should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm
of the pin. The placing of the 1 nF capacitor is less critical, but should still be within 5 mm of the pin.

must have the same value as AVDD.

DV

DD

16 VP

Charge Pump Power Supply. This should be greater than or equal to V

. In systems where VDD is 3 V, this supply can

DD

be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.

Rev. D | Page 7 of 28

ADF4116/ADF4117/ADF4118

TYPICAL PERFORMANCE CHARACTERISTICS

PARAM-TYPE DATA-F ORMAT KEYWORD IMPEDANCE-

FREQ­UNIT

GHz S MA R 50

FREQ MagS11 AngS11

0.05 0.89207 –2.0571

0.10 0.8886 –4.4427

0.15 0.89022 –6.3212

0.20 0.96323 –2.1393

0.25 0.90566 –12.13

0.30 0.90307 –13.52

0.35 0.89318 –15.746

0.40 0.89806 –18.056

0.45 0.89565 –19.693

0.50 0.88538 –22.246

0.55 0.89699 –24.336

0.60 0.89927 –25.948

0.65 0.87797 –28.457

0.70 0.90765 –29.735

0.75 0.88526 –31.879

0.80 0.81267 –32.681

0.85 0.90357 –31.522

0.90 0.92954 –34.222

FREQ MagS11 AngS11

0.95 0.92087 –36.961

1.00 0.93788 –39.343

1.05 0.9512 –40.134

1.10 0.93458 –43.747

1.15 0.94782 –44.393

1.20 0.96875 –46.937

1.25 0.92216 –49.6

1.30 0.93755 –51.884

1.35 0.96178 –51.21

1.40 0.94354 –53.55

1.45 0.95189 –56.786

1.50 0.97647 –58.781

1.55 0.98619 –60.545

1.60 0.95459 –61.43

1.65 0.97945 –61.241

1.70 0.98864 –64.051

1.75 0.97399 –66.19

1.80 0.97216 –63.775

OHMS

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

00392-004

100Hz FREQUENCY OF FSET F ROM 900MHz CARRIER 1MHz

RL= –40dBc/Hz10dB/DIVI SION RMS NOISE = 0.64°

0.64° rms

00392-007

Figure 4. S-Parameter Data for the ADF4118 RF Input (Up to 1.8 GHz)

Figure 7. ADF4118 Integrated Phase Noise

(900 MHz, 200 kHz, 35 kHz, Typical Lock Time: 200 μs)

0

–5

–10

–15

–20

–25

–30

RF INPUT POW ER (dBm)

–35

–40

–45

04

TA = –40°C

= +25°C

T

A

1.0

RF INPUT FREQUENCY (GHz)

VDD = 3V
V

= 3V

P

T

= +85°C

A

00392-005

.00.5 1.5 2.0 2.5 3.0 3.5

Figure 5. Input Sensitivity (ADF4118)

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

100Hz FREQUENCY OF FSET F ROM 900MHz CARRIER 1MH

Figure 8. ADF4118 Integrated Phase Noise

(900 MHz, 200 kHz, 20 kHz, Typical Lock Time: 400 μs)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT PO WER (dB)

–80

–90

–100

–400kHz –200kHz 900MHz 200kHz 400kHz

–10

–20

–30

–40

–50

–60

–70

OUTPUT PO WER (dB)

–80

–90

–100

0

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 900MHz 1kHz 2kHz

= 3V, VP = 5V

V

DD

I

= 1mA

CP

PFD FREQ UENCY = 200kHz

LOOP BANDWI DTH = 20kHz

RES. BANDWIDT H = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECO NDS

AVERAGES = 22

–90.2dBc/Hz

00392-006

Figure 6. ADF4118 Phase Noise

(900 MHz, 200 kHz, 20 kHz)

RL= –40dBc/Hz10dB/DIVI SION RMS NOISE = 0.575°

0.575° rms

REFERENCE
LEVEL = –3.8dBm

V

= 3V, VP = 5V

DD

= 1mA

I

CP

PFD FREQ UENCY = 200kHz

LOOP BANDW IDTH = 20kHz

RES. BANDWIDT H = 1kHz

VIDEO BANDWI DTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 4

Figure 9. ADF4118 Reference Spurs

(900 MHz, 200 kHz, 20 kHz)

–91.5dBc

00392-008

z

00392-009

Rev. D | Page 8 of 28

ADF4116/ADF4117/ADF4118

–10

–20

–30

–40

–50

–60

–70

OUTPUT POW ER (dB)

–80

–90

–100

0

REFERENCE
LEVEL = –4.2dBm

–400kHz –200kHz 900MHz 200kHz 400kHz

V

= 3V, VP = 5V

DD

= 1mA

I

CP

PFD FREQ UENCY = 200kHz

LOOP BANDW IDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWI DTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 10

–90.67dBc

Figure 10. ADF4118 Reference Spurs

(900 MHz, 200 kHz, 35 kHz)

OUTPUT PO WER (dB)

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –7.0dBm

–400kHz –200kHz 1750MHz 200kHz 400kHz

V

= 3V, VP = 5V

DD

= 1mA

I

CP

PFD FREQUENCY = 30kHz

LOOP BANDW IDTH = 5kHz

RES. BANDWIDT H = 10kHz

VIDEO BANDWI DTH = 10kHz

SWEEP = 477ms

AVERAGES = 25

–71.5dBc/Hz

Figure 11. ADF4118 Phase Noise

(1750 MHz, 30 kHz, 3 kHz)

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE ( dBc/Hz)

–120

–130

–140

100Hz FREQUENCY OF FSET F ROM 1.75GHz CARRIER 1MHz

RL = –40dBc/Hz10dB/DIVI SION RMS NOI SE = 2.0°

2.0° rms

Figure 12. ADF4118 Integrated Phase Noise

(1750 MHz, 30 kHz, 3 kHz)

00392-010

00392-011

00392-012

OUTPUT PO WER (dB)

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –7.0dBm

–60kHz –30k Hz 1750MHz 30kHz 60kHz

V

= 3V, VP = 5V

DD

I

= 5mA

CP

PFD FREQ UENCY = 30kHz

LOOP BANDWI DTH = 5kHz

RES. BANDWIDTH = 300Hz

VIDEO BANDWIDTH = 300Hz

SWEEP = 4.2ms

AVERAGES = 20

–72.3dBc

Figure 13. ADF4118 Reference Spurs

(1750 MHz, 30 kHz, 3 kHz)

–10

–20

–30

–40

–50

–60

–70

OUTPUT PO WER (dB)

–80

–90

–100

0

REFERENCE
LEVEL = –10.3dBm

–2kHz –1kHz

VVDD = 3V, VP = 5V

= 1mA

I

CP

PFD FREQUENCY = 1MHz

LOOP BANDW IDTH = 100kHz

RES. BANDWIDT H = 10Hz

VIDEO BANDWI DTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 26

–85.2dBc/Hz

2800MHz

1kHz 2kHz

Figure 14. ADF4118 Phase Noise

(2800 MHz, 1 MHz, 100 kHz)

10dB/DIVI SION RL = –40dBc/Hz RMS NOISE = 1. 552°

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

100Hz FREQUENCY OFFS ET FROM 2.8GHz CARRIE R 1MHz

1.55° rms

Figure 15. ADF4118 Integrated Phase Noise

(2800 MHz, 1 MHz, 100 kHz)

00392-013

00392-014

00392-015

Rev. D | Page 9 of 28