ANALOG DEVICES ADF4113HV Service Manual

High Voltage

VDDA

FEATURES

High voltage charge pump (15 V)

2.7 V to 5.5 V power supply 200 MHz to 4.0 GHz frequency range Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113

ADF4106, and ADF4002 synthesizers Two selectable charge pump currents Digital lock detect Power-down mode Loop filter design possible with ADIsimPLL™

APPLICATIONS

Applications using high voltage VCOs IF/RF local oscillator (LO) generation in base stations Point-to-point radio LO generation Clock for analog-to-digital and digital-to-analog converters Wireless LANs, PMR Communications test equipment

Charge Pump, PLL Synthesizer

ADF4113HV

GENERAL DESCRIPTION

The ADF4113HV is an integer-N frequency synthesizer with a high voltage charge pump (15 V). The synthesizer is designed for use with voltage controlled oscillators (VCOs) that have high tuning voltages (up to 15 V). Active loop filters are often used to achieve high tuning voltages, but the ADF4113HV charge pump can drive a high voltage VCO directly with a passive-loop filter. The ADF4113HV can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision high voltage charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P + 1).

A simple 3-wire interface controls all of the on-chip registers. The devices operate with a power supply ranging from 2.7 V to

5.5 V and can be powered down when not in use.

REF

CLK

DATA

RFINA

FUNCTIONAL BLOCK DIAGRAM

24-BIT

INPUT REGISTER

FROM

FUNCTION

LATCH

PRESCALER

P/P + 1

OUT

N=BP+A

R COUNTER

FUNCTION

A, B COUNT ER

13-BIT

B COUNTER

LOAD

6-BIT

A COUNTER

14-BIT

LATCH

CPGND

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

OUT

REFERENCE

CHARGE

PUMP

CURRENT

SETTING

MUX

M3 M2 M1

ADF4113HV

SET

HIGH Z

MUXOUT

CE AGND DGND

06223-001

Figure 1.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADF4113HV

TABLE OF CONTENTS

Features .............................................................................................. 1

Prescaler (P/P + 1) ........................................................................9

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings ............................................................ 5

Transistor Count ........................................................................... 5

Thermal Resistance ...................................................................... 5

ESD Caution .................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Circuit Description ........................................................................... 9

Reference Input Section ............................................................... 9

RF Input Stage ............................................................................... 9

A and B Counters ..........................................................................9

R Counter .......................................................................................9

Phase Frequency Detector (PFD) and Charge Pump ............ 10

Muxout and Lock Detect ........................................................... 10

Input Shift Register .................................................................... 10

Function Latch ............................................................................ 13

Applications ..................................................................................... 15

Using a Digitial-to-Analog Converter to Drive the R

Pin .................................................................................. 15

SET

Interfacing ................................................................................... 15

PCB Design Guidelines for Chip Scale Package .................... 16

Outline Dimensions ....................................................................... 17

Ordering Guide .......................................................................... 17

REVISION HISTORY

9/08—Rev. 0 to Rev. A

Changes to Figure 22 ...................................................................... 13

1/07—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADF4113HV

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V < VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; R T

= T

to T

MIN

, unless otherwise noted. Operating temperature range for B version: −40°C to +85°C.

MAX

Table 1.

Parameter B Version B Chips

Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V)

RF Input Sensitivity −15/0 −15/0 dBm min/max

RF Input Frequency 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/s

Prescaler Output Frequency

165 165 MHz max

RF CHARACTERISTICS (5 V)

RF Input Sensitivity −10/0 −10/0 dBm min/max

RF Input Frequency 0.2/3.7 0.2/3.7 GHz min/max For lower frequencies, ensure SR > 130 V/µs

0.2/4.0 0.2/4.0 GHz min/max Input level = −5 dBm Prescaler Output Frequency 200 200 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 5/150 5/150 MHz min/max For f < 5 MHz, ensure SR > 100 V/µs Reference Input Sensitivity 0.4/AVDD 0.4/AVDD V p-p min/max AVDD = 3.3 V, biased at AVDD/2

1.0/AVDD 1.0/AVDD V p-p min/max For f ≥ 10 MHz, AVDD = 5 V, biased at AVDD/2 REFIN Input Capacitance 10 10 pF max REFIN Input Current ±100 ±100 µA max

PHASE DETECTOR FREQUENCY 5 5 MHz max CHARGE PUMP

Sink/Source R

= 4.7 kΩ

SET

High Value 640 640 A typ

Low Value 80 80 µA typ Absolute Accuracy 2.5 2.5 % typ R

Range 3.9/10 3.9/10 kΩ typ

SET

ICP Three-State Leakage Current 5 5 nA max Sink and Source Current Matching 3 3 % typ 1 V ≤ VCP ≤ VP – 1 V ICP vs. VCP 1.5 1.5 % typ 1 V ≤ VCP ≤ VP – 1 V ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

, Input High Voltage 0.8 × DVDD 0.8 × DVDD V min

INH

, Input Low Voltage 0.2 × DVDD 0.2 × DVDD V max

INL

, Input Current ±1 ±1 µA max

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD − 0.4 DVDD − 0.4 V min IOH = 500 µA VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AVDD 2.7/5.5 2.7/5.5 V min/V max DVDD AVDD AVDD VP 13.5/16.5 13.5/16.5 V min/V max

(AIDD + DIDD) 16 11 mA max 11 mA typical

IP 0.25 0.25 mA max TA = 25°C Low Power Sleep Mode 1 1 µA typ

NOISE CHARACTERISTICS

= PN

− 10logf

TOT

−212 −212 dBc/Hz typ

− 20logN.

PFD

Normalized Phase Noise Floor

The B chip specifications are given as typical values.

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

AC coupling ensures AVDD/2 bias.

Guaranteed by characterization.

TA = 25oC; AVDD = DVDD = 5.5 V; P = 16; RFIN = 900 MHz.

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO, PN

value) and 10logf

: PN

PFD

SYNTH

= 4.7 kΩ; dBm referred to 50 Ω;

SET

, and subtracting 20logN (where N is the N divider

TOT

3, 4

Rev. A | Page 3 of 20

ADF4113HV

TIMING CHARACTERISTICS

Guaranteed by design but not production tested. AVDD = DVDD = 3 V ± 10%, 5 V ± 10%; 13.5 V ≤ VP ≤ 16.5 V; AGND = DGND = CPGND = 0 V; R

Table 2.

Parameter Limit at T

t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width

Timing Diagram

CLK

= 4.7 kΩ; TA = T

SET

to T

MIN

(B Version) Unit Test Conditions/Comments

MAX

MIN

to T

, unless otherwise noted.

MAX

DATA

DB23 (MSB) DB22 DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

06223-002

Figure 2. Timing Diagram

Rev. A | Page 4 of 20

ADF4113HV

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +7 V AVDD to DVDD −0.3 V to +0.3 V VP to GND −0.3 V to +18 V Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V Analog I/O Voltage to GND −0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V RFINA to RFINB ±320 mV Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +150°C Maximum Junction Temperature 150°C Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TRANSISTOR COUNT

The transistor count is 12,150 (CMOS) and 348 (bipolar).

THERMAL RESISTANCE

Table 4. Thermal Resistance

Package Type θJA Unit

TSSOP 150.4 °C/W LFCSP (Paddle Soldered) 122 °C/W LFCSP (Paddle Not Soldered) 216 °C/W

ESD CAUTION

This device is a high performance RF integrated circuit with an ESD rating of <1 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

Rev. A | Page 5 of 20

ADF4113HV

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

SET

PGND

AGND

REF

FIN

ADF4113HV

TOP VIEW

(Not to Scale)

Figure 3. TSSOP Pin Configuration

MUXOUT

DATA

CLK

DGND

1CPGND 2AGND 3AGND 4RF

5RF

6223-003

Figure 4. LFCSP Pin Configuration

Table 5. Pin Function Descriptions

TSSOP Pin No.

1 19 R

2 20 CP

LFCSP Pin No. Mnemonic Description

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the R I

and R

SET

is I

Charge Pump Output. When enabled, this pin provides ±I

CPmax

= 3/R

. Therefore, with R

SET

pin is 0.56 V for the ADF4113HV. The relationship between

SET

= 4.7 kΩ, I

SET

CPmax

drives the external VCO. 3 1 CPGND Charge Pump Ground. CPGND is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB

Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF. 6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. 7 6, 7 AVDD

Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the

analog ground plane should be placed as close as possible to this pin. AVDD must be the same value

as DV

8 8 REFIN

Reference Input. This pin is a CMOS input with a nominal threshold of V

input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be

ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE

Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output

into three-state mode. Taking the pin high powers up the device depending on the status of the

Power-Down Bit PD1. 11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is

latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS

input. 12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

input is a high impedance CMOS input. 13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into

one of the four latches; the latch is selected using the control bits. 14 15 MUXOUT

Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the

scaled reference frequency to be externally accessed. 15 16, 17 DVDD

Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground

plane (1µF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 µF

capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical

16 18 VP

but should still be within 5 mm of the pin. DV

Charge Pump Power Supply. V

can range from 13.5 V to 16.5 V and should be decoupled

must have the same value as AVDD.

appropriately.

PIN 1 INDICATO R

ADF4113HV

TOP VIEW

(Not to Scale)

REF

15 MUXO UT 14 LE 13 DATA 12 CLK 11 CE

DGND

= 640 A.

to the external loop filter; in turn, this

/2, and an equivalent

06223-004

Rev. A | Page 6 of 20

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