a
RF PLL Frequency Synthesizers
ADF4110/ADF4111/ADF4112/ADF4113
FEATURES
ADF4110: 550 MHz
ADF4111: 1.2 GHz
ADF4112: 3.0 GHz
ADF4113: 4.0 GHz
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V
) Allows Extended
P
Tuning Voltage in 3 V Systems
Programmable Dual Modulus Prescaler 8/9, 16/17,
32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode
APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment
FUNCTIONAL BLOCK DIAGRAM
AV
DV
DD
DD
GENERAL DESCRIPTION
The ADF4110 family of frequency synthesizers can be used
to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be implemented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).
Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to
5.5 V and can be powered down when not in use.
V
CPGND
P
R
SET
REF
CLK
DATA
RF
RF
IN
24-BIT
LE
A
IN
B
IN
INPUT REGISTER
FROM
FUNCTION
LATCH
PRESCALER
P/P +1
SD
OUT
N = BP + A
22
DGNDAGNDCE
14-BIT
R COUNTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
13-BIT
B COUNTER
LOAD
LOAD
6-BIT
A COUNTER
14
19
13
6
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
REFERENCE
PHASE
FREQUENCY
DETECTOR
LOCK
DETECT
AV
SD
DD
OUT
CHARGE
PUMP
CURRENT
SETTING 1
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
MUX
M3 M2 M1
CURRENT
SETTING 2
HIGH Z
CP
MUXOUT
ADF4110/ADF4111
ADF4112/ADF4113
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS
1
(AV
= DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; R
DD
Parameter B Version B Chips
2
Unit Test Conditions/Comments
RF CHARACTERISTICS (3 V) See Figure 25 for Input Circuit.
RF Input Frequency Use a square wave for lower frequencies.
ADF4110 45/550 45/550 MHz min/max
ADF4110 25/550 25/550 MHz min/max Input Level = –10 dBm
ADF4111 0.045/1.2 0.045/1.2 GHz min/max
ADF4112 0.2/3.0 0.2/3.0 GHz min/max
ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input Level = –10 dBm
ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input Level = –10 dBm
RF Input Sensitivity –15/0 –15/0 dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
165 165 MHz max
RF CHARACTERISTICS (5 V)
RF Input Frequency Use a square wave for lower frequencies.
ADF4110 25/550 25/550 MHz min/max
ADF4111 0.025/1.4 0.025/1.4 GHz min/max
ADF4112 0.1/3.0 0.1/3.0 GHz min/max
ADF4113 0.2/3.7 0.2/3.7 GHz min/max
ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input Level = –5 dBm
RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
200 200 MHz max
REFIN CHARACTERISTICS
REFIN Input Frequency 0/100 0/100 MHz min/max
Reference Input Sensitivity
4
–5/0 –5/0 dBm min/max AC-Coupled. When DC-Coupled:
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max
PHASE DETECTOR
Phase Detector Frequency
5
55 55 MHz max
CHARGE PUMP
I
Sink/Source Programmable: See Table V
CP
High Value 5 5 mA typ With R
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With R
Range 2.7/10 2.7/10 kΩ typ See Table V
R
SET
I
3-State Leakage Current 1 1 nA typ
CP
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ V
I
CP
vs. V
CP
1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5
ICP vs. Temperature 2 2 % typ VCP = VP/2
LOGIC INPUTS
V
, Input High Voltage 0.8 × DV
INH
, Input Low Voltage 0.2 × DV
V
INL
I
, Input Current ± 1 ± 1 µA max
INH/IINL
DD
DD
0.8 × DV
0.2 × DV
DD
DD
V min
V max
CIN, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA
OH
VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA
POWER SUPPLIES
AV
DD
DV
DD
V
P
6
(AIDD + DI
I
DD
) See Figures 22 and 23
DD
2.7/5.5 2.7/5.5 V min/V max
AV
DD
AV
DD
AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V
ADF4110 5.5 4.5 mA max 4.5 mA Typical
ADF4111 5.5 4.5 mA max 4.5 mA Typical
ADF4112 7.5 6.5 mA max 6.5 mA Typical
ADF4113 11 8.5 mA max 8.5 mA Typical
I
P
0.5 0.5 mA max TA = 25°C
Low Power Sleep Mode 1 1 µA typ
= 4.7 k⍀; TA = T
SET
0 to V
to T
MIN
DD
unless otherwise noted)
MAX
max (CMOS-Compatible)
= 4.7 kΩ
SET
= 4.7 kΩ
SET
≤ VP – 0.5
CP
–2–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Parameter B Version B Chips
NOISE CHARACTERISTICS
ADF4113 Phase Noise Floor
Phase Noise Performance
ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output
ADF4113: 3100 MHz Output
Spurious Signals
ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output
7
8
–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency
9
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
10
–87 –87 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
10
–90 –90 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
10
–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
11
–78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency
12
–86 –86 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
13
–66 –66 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency
14
–84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
14
–85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
15
–86 –86 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency
9
–97/–106 –97/–106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
10
–98/–110 –98/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
10
–91/–100 –91/–100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
10
–100/–110 –100/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
11
–81/–84 –81/–84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency
12
–88/–90 –88/–90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
13
–65/–73 –65/–73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency
14
–80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
14
–80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
ADF4113: 3100 MHz Output15–80/–82 –82/–82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.
4
AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.
5
Guaranteed by design.
6
TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f
9
f
= 10 MHz; f
REFIN
10
f
= 10 MHz; f
REFIN
11
f
= 10 MHz; f
REFIN
12
f
= 10 MHz; f
REFIN
13
f
= 10 MHz; f
REFIN
14
f
= 10 MHz; f
REFIN
15
f
= 10 MHz; f
REFIN
Specifications subject to change without notice.
= 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).
REFOUT
= 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.
PFD
= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.
PFD
= 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.
PFD
= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.
PFD
= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.
PFD
= 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.
PFD
= 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.
PFD
2
Unit Test Conditions/Comments
@ VCO Output
(AV
TIMING CHARACTERISTICS
Limit at T
= DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AV
DD
1
R
= 4.7 k⍀; TA = T
SET
to T
MIN
MAX
MIN
to T
unless otherwise noted)
MAX
≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;
DD
Parameter (B Version) Unit Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
NOTES
1
Guaranteed by design but not production tested.
Specifications subject to change without notice.
REV. 0
10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth
–3–
ADF4110/ADF4111/ADF4112/ADF4113
CLOCK
DATA
LE
LE
t
1
DB20 (MSB) DB19 DB2
t
2
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
1, 2
AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AV
DD
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
P
V
to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
P
Digital I/O Voltage to GND . . . . . . . . –0.3 V to V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
REF
, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V
IN
+ 0.3 V
DD
+ 0.3 V
P
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
TSSOP θ
CSP θ
Thermal Impedance . . . . . . . . . . . . . 150.4°C/W
JA
Thermal Impedance (Paddle Soldered) . . . 122°C/W
JA
t
3
CSP θ
t
4
DB1
(CONTROL BIT C2)
Thermal Impedance
JA
DB0 (LSB)
(CONTROL BIT C1)
t
5
t
6
(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
6425 (CMOS) and 303 (Bipolar).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the
WARNING!
ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ESD SENSITIVE DEVICE
ORDERING GUIDE
Model Temperature Range Package Description Package Option*
ADF4110BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4110BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4111BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4111BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4112BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4112BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4113BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BCHIPS –40°C to +85°C DICE DICE
*Contact the factory for chip availability.
–4–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1R
SET
2 CP Charge Pump Output. When enabled this provides ±I
3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the prescaler.
5RF
6RF
7AV
8 REF
B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
IN
A Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
IN
DD
IN
9 DGND Digital Ground.
10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-
11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency
15 DV
16 V
DD
P
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R
SET
I
CP
So, with R
= 4.7 kΩ, I
SET
CPmax
= 5 mA.
pin is 0.56 V. The relationship between ICP and R
max
.=23 5
R
SET
to the external loop filter, which in turn drives the
CP
SET
is
external VCO.
a small bypass capacitor, typically 100 pF. See Figure 25.
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV
must be the same value as DVDD.
DD
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
input is a high impedance CMOS input.
of the four latches, the latch being selected using the control bits.
to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DV
must be the same value as AVDD.
DD
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.
REV. 0
TSSOP
1
R
SET
2
CP
ADF4110
ADF4111
3
CPGND
AGND
RF
RF
AV
REF
B
IN
A
IN
DD
IN
ADF4112
4
ADF4113
5
TOP VIEW
(Not to Scale)
6
7
8
16
15
14
13
12
11
10
9
V
P
DV
DD
MUXOUT
LE
DATA
CLK
CE
DGND
PIN CONFIGURATIONS
–5–
CHIP SCALE PACKAGE
VPDVDDDV
8
9
10
IN
REF
DGND
DGND
DD
15
14
13
12
11
MUXOUT
LE
DATA
CLK
CE
CPGND
AGND
AGND
RF
IN
RF
IN
CP
2019181716
1
2
3
B
4
(Not to Scale)
5
A
6
AVDDAV
SET
R
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW
7
DD
ADF4110/ADF4111/ADF4112/ADF4113
–Typical Performance Characteristics
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
GHz S MA R 50
FREQ MAGS11 ANGS11
0.05 0.89207 –2.0571
0.10 0.8886 –4.4427
0.15 0.89022 –6.3212
0.20 0.96323 –2.1393
0.25 0.90566 –12.13
0.30 0.90307 –13.52
0.35 0.89318 –15.746
0.40 0.89806 –18.056
0.45 0.89565 –19.693
0.50 0.88538 –22.246
0.55 0.89699 –24.336
0.60 0.89927 –25.948
0.65 0.87797 –28.457
0.70 0.90765 –29.735
0.75 0.88526 –31.879
0.80 0.81267 –32.681
0.85 0.90357 –31.522
0.90 0.92954 –34.222
0.95 0.92087 –36.961
1.00 0.93788 –39.343
FREQ MAGS11 ANGS11
1.05 0.9512 –40.134
1.10 0.93458 –43.747
1.15 0.94782 –44.393
1.20 0.96875 –46.937
1.25 0.92216 –49.6
1.30 0.93755 –51.884
1.35 0.96178 –51.21
1.40 0.94354 –53.55
1.45 0.95189 –56.786
1.50 0.97647 –58.781
1.55 0.98619 –60.545
1.60 0.95459 –61.43
1.65 0.97945 –61.241
1.70 0.98864 –64.051
1.75 0.97399 –66.19
1.80 0.97216 –63.775
Figure 2. S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)
0
VDD = 3V
= 3V
V
P
3
4
5
–10
–15
–20
–25
RF INPUT POWER – dBm
–30
–35
–5
TA = +85ⴗC
TA = +25ⴗC
TA = –40ⴗC
0
1
2
RF INPUT FREQUENCY – GHz
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
–80
–90
–100
REFERENCE
LEVEL = –4.2dBm
–2kHz –1kHz 900MHz +1kHz +2kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
–92.5dBc/Hz
Figure 5. ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled
10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.52ⴗ
–40
–50
–60
–70
–80
–90
–100
–110
PHASE NOISE – dBc/Hz
–120
–130
–140
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
0.52ⴗ rms
Figure 3. Input Sensitivity (ADF4113)
0
REFERENCE
LEVEL = –4.2dBm
–2kHz –1kHz 900MHz +1kHz +2kHz
OUTPUT POWER – dB
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 19
–91.0dBc/Hz
Figure 4. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)
Figure 6. ADF4113 Integrated Phase Noise (900 MHz,
µ
200 kHz, 20 kHz, Typical Lock Time: 400
10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.62ⴗ
–40
–50
–60
–70
–80
–90
–100
–110
PHASE NOISE – dBc/Hz
–120
–130
–140
100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz
s)
0.62ⴗ rms
Figure 7. ADF4113 Integrated Phase Noise (900 MHz,
µ
200 kHz, 35 kHz, Typical Lock Time: 200
s)
–6–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.6ⴗ
100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER 1MHz
1.6ⴗ rms
PHASE NOISE – dBc/Hz
–90
–80
–70
–60
–50
–40
–100
–110
–120
–130
–140
–80kHz –40kHz
1750MHz +40kHz +80kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 3Hz
VIDEO BANDWIDTH = 3Hz
SWEEP = 255 SECONDS
POSITIVE PEAK DETECT
MODE
REFERENCE
LEVEL = –5.7dBm
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
POWER OUTPUT – dB
–79.6dBc
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
–80
–90
–100
0
REFERENCE
LEVEL = –4.2dBm
–400kHz –200kHz 900MHz +200kHz +400kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–90.2dBc
Figure 8. ADF4113 Reference Spurs (900 MHz, 200 kHz,
20 kHz)
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
–80
–90
–100
0
REFERENCE
LEVEL = –4.2dBm
–400kHz –200kHz 900MHz +200kHz +400kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 35kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30
–89.3dBc
Figure 11. ADF4113 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)
Figure 9. ADF4113 Reference Spurs (900 MHz, 200 kHz,
35 kHz)
0
–10
–20
–30
–40
–50
–60
–70
OUTPUT POWER – dB
REV. 0
–80
–90
–100
Figure 10. ADF4113 Phase Noise (1750 MHz, 30 kHz,
3 kHz)
REFERENCE
LEVEL = –8.0dBm
–400Hz –200Hz 1750MHz +200Hz +400Hz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 30kHz
LOOP BANDWIDTH = 3kHz
RES. BANDWIDTH = 10kHz
VIDEO BANDWIDTH = 10kHz
SWEEP = 477ms
AVERAGES = 10
–75.2dBc/Hz
Figure 12. ADF4113 Reference Spurs (1750 MHz, 30 kHz,
3 kHz)
OUTPUT POWER – dB
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
REFERENCE
LEVEL = –4.2dBm
–2kHz –1kHz 3100MHz +1kHz +2kHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 45
–86.6dBc/Hz
Figure 13. ADF4113 Phase Noise (3100 MHz, 1 MHz,
100 kHz)
–7–
ADF4110/ADF4111/ADF4112/ADF4113
10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.7ⴗ
–40
–50
–60
–70
–80
–90
–100
–110
PHASE NOISE – dBc/Hz
–120
–130
–140
100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER 1MHz
Figure 14. ADF4113 Integrated Phase Noise (3100 MHz,
1 MHz, 100 kHz)
1.7ⴗ rms
–60
VDD = 3V
= 3V
V
–70
–80
PHASE NOISE – dBc/Hz
–90
–100
–20
TEMPERATURE – ⴗC
P
Figure 17. ADF4113 Phase Noise vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
100–40 0 20 40 60 80
OUTPUT POWER – dB
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
REFERENCE
LEVEL = –17.2dBm
–2MHz –1MHz 3100MHz +1MHz +2MHz
VDD = 3V, VP = 5V
ICP = 5mA
PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES. BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1
–80.6dBc
Figure 15. ADF4113 Reference Spurs (3100 MHz, 1 MHz,
100 kHz)
–120
–130
–140
–150
–160
PHASE NOISE – dBc/Hz
–170
–180
1 10000100 1000
10
PHASE DETECTOR FREQUENCY – kHz
VDD = 3V
V
= 5V
P
Figure 16. ADF4113 Phase Noise (Referred to CP Output)
vs. PFD Frequency
–60
VDD = 3V
= 5V
V
–70
–80
–90
FIRST REFERENCE SPUR – dBc
–100
–20
TEMPERATURE – ⴗC
P
100–40 0 20 40 60 80
Figure 18. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)
–5
FIRST REFERENCE SPUR – dBc
–105
–15
–25
–35
–45
–55
–65
–75
–85
–95
1
TUNING VOLTAGE – Volts
VDD = 3V
= 5V
V
P
50234
Figure 19. ADF4113 Reference Spurs (200 kHz) vs.
(900 MHz, 200 kHz, 20 kHz)
V
TUNE
–8–
REV. 0
–60
0
AI
DD
– mA
1
PRESCALER VALUE
8/9 16/17 32/33 64/65
2
3
6
8
9
10
4
5
7
0
ADF4113
ADF4112
ADF4110
ADF4111
–70
–80
PHASE NOISE – dBc/Hz
–90
VDD = 3V
= 5V
V
P
ADF4110/ADF4111/ADF4112/ADF4113
–100
–20
TEMPERATURE – ⴗC
100–40 0 20 40 60 80
Figure 20. ADF4113 Phase Noise vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
–60
VDD = 3V
= 5V
V
–70
–80
–90
FIRST REFERENCE SPUR – dBc
–100
–20
TEMPERATURE – ⴗC
P
100–40 0 20 40 60 80
Figure 21. ADF4113 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
Figure 22. AIDD vs. Prescaler Value
3.0
VDD = 3V
= 3V
V
P
2.5
2.0
1.5
– mA
DD
DI
1.0
0.5
0
PRESCALER OUTPUT FREQUENCY – MHz
10050
Figure 23. DIDD vs. Prescaler Output Frequency
(ADF4110, ADF4111, ADF4112, ADF4113)
2000 150
REV. 0
–9–
ADF4110/ADF4111/ADF4112/ADF4113
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 24. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
POWER-DOWN
CONTROL
100k⍀
NC
REF
SW1
NO
SW2
SW3
IN
NC
BUFFER
TO R COUNTER
Figure 24. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 25. It is followed by a
2-stage limiting amplifier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
1.6V
AV
DD
500⍀500⍀
AGND
RFINA
RF
IN
BIAS
GENERATOR
B
Figure 25. RF Input Stage
PRESCALER (P/P+1)
The dual-modulus prescaler (P/P+1), along with the A and B
counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B counters.
The prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core.
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feedback counter. The counters are specified to work when the
prescaler output is 200 MHz or less. Thus, with an RF input
frequency of 2.5 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
f
f
VCO
= [(P × B) + A] × f
VCO
Output frequency of external voltage controlled oscilla-
REFIN
/R
tor (VCO).
P Preset modulus of dual modulus prescaler
B Preset Divide Ratio of binary 13-bit counter (3 to 8191).
A Preset Divide Ratio of binary 6-bit swallow counter (0 to
63).
f
Output frequency of the external reference frequency
REFIN
oscillator.
R Preset divide ratio of binary 14-bit programmable refer-
ence counter (1 to 16383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
FROM RF
INPUT STAGE
N = BP + A
PRESCALER
MODULUS
CONTROL
P/P + 1
13-BIT B
COUNTER
LOAD
LOAD
6-BIT A
COUNTER
TO PFD
Figure 26. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP
The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the phase
and frequency difference between them. Figure 27 is a simplified schematic. The PFD includes a programmable delay element
which controls the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width
of the pulse. See Table III.
–10–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
V
P
CHARGE
PUMP
CP
CPGND
HI
R DIVIDER
HI
N DIVIDER
R DIVIDER
N DIVIDER
CP OUTPUT
Q1D1
U1
CLR1
PROGRAMMABLE
ABP1 ABP2
CLR2
Q2D2
U2
UP
DELAY
DOWN
U3
Figure 27. PFD Simplified Schematic and Timing
(In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 28 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
The N-channel open-drain analog lock detect should be operated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected this output will be high with narrow lowgoing pulses.
DV
DD
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
CONTROLMUX
MUXOUT
DGND
Figure 28. MUXOUT Circuit
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
Table I. C2, C1 Truth Table
Control Bits
C2 C1 Data Latch
0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch
REV. 0
–11–
ADF4110/ADF4111/ADF4112/ADF4113
Table II. ADF4110 Family Latch Summary
REFERENCE COUNTER LATCH
SYNC
DLY
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18
X
X = DON'T CARE
RESERVED
DB23
XX
X = DON'T CARE
PRESCALER
VALUE
DB23 DB22
SYNCDLY ABP2 ABP1
CP GAIN
DB22 DB21 DB20
G1 B10 B9
POWER-
DB21
PD2 CPI3 CPI2
P1P2
MODE BITS
DETECT
PRECISION
LDP T2 T1 R14 R13 R12 R11 R10 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)R9
DB19
DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6
B13 B12 B11 B8 B7 B6 B5 B4 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)B3
CURRENT
SETTING
DOWN 2
2
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)F5
TEST
LOCK
ANTI-
BACKLASH
WIDTH
DB17
DB16
CURRENT
SETTING
DB15
13-BIT B COUNTER
1
14-BIT REFERENCE COUNTER, R
DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6
N COUNTER LATCH
DB13
FUNCTION LATCH
PD
TIMER COUNTER
CONTROL
MODE
FASTLOCK
CP
THREE-
ENABLE
FASTLOCK
STATE
POLARITY
DB6
DB5 DB4
6-BIT A COUNTER
DB5
DB4 DB3
MUXOUT
CONTROL
DB5 DB4 DB3DB13
DB3DB13
POWER-
DB2
DB2 DB1
DOWN 1
COUNTER
DB2 DB1
CONTROL
DB1 DB0
CONTROL
CONTROL
RESET
BITS
BITS
DB0
BITS
DB0
PRESCALER
VALUE
DB23 DB22 DB21 DB20
P1P2
DOWN 2
POWER-
CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)F5
PD2 CPI3 CPI2
CURRENT
SETTING
2
DB19
DB18
DB17
CURRENT
SETTING
1
DB16
INITIALIZATION LATCH
TIMER COUNTER
CONTROL
DB15
DB14 DB12 DB11 DB10 DB9 DB8 DB7 DB6
MODE
FASTLOCK
CP
ENABLE
FASTLOCK
–12–
STATE
THREE-
PD
POLARITY
MUXOUT
CONTROL
DB5 DB4
DOWN 1
POWER-
COUNTER
DB3DB13
DB2 DB1 DB0
CONTROL
RESET
BITS
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
Table III. Reference Counter Latch Map
DLY
RESERVED
DB23 DB22
X
X = DON'T
CARE
SYNC
DB21
SYNCDLY ABP2 ABP1
MODE BITS
DETECT
PRECISION
DB20 DB19 DB18
LDP T2 T1 R14 R13 R12 R11 R10 R8 R7 R6 R5 R4 R3 R2 R1 C2 (0) C1 (0)R9
TEST
LOCK
ANTI-
BACKLASH
WIDTH
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
DB17
ANTIBACKLASH PULSEWIDTH
ABP1ABP2
3.0ns
0
0
1.5ns
1
0
6.0ns
0
1
3.0ns
1
1
DB13
14-BIT REFERENCE COUNTER
R14
R13
0
0
0
0
•
•
•
1
1
1
1
R12
0
0
0
0
0
0
0
0
•
•
•
•
•
•
1
1
1
1
1
1
1
1
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
DB6
CONTROL
BITS
DB5
DB4 DB3
R3
R2
0
0
0
1
0
1
1
0
•
•
•
•
•
•
1
0
1
0
1
1
1
1
R1
1
0
1
0
•
•
•
0
1
0
1
DB2 DB1
DIVIDE RATIO
DB0
1
2
3
4
•
•
•
16380
16381
16382
16383
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
OPERATION
LDP
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
0
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
1
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
SYNCDLY
OPERATION
NORMAL OPERATION
0
0
OUTPUT OF PRESCALER IS RESYNCHRONIZED
1
0
1
1
WITH NONDELAYED VERSION OF RF INPUT
NORMAL OPERATION
0
OUTPUT OF PRESCALER IS RESYNCHRONIZED
1
WITH DELAYED VERSION OF RF INPUT
REV. 0
–13–
ADF4110/ADF4111/ADF4112/ADF4113
Table IV. AB Counter Latch Map
RESERVED
DB23 DB22
X
X
CP GAIN
DB21
DB20 DB19 DB18
B13 B12 B11 B8 B7 B6 B5 B4 B2 B1 A6 A5 A4 A3 A2 A1 C2 (0) C1 (1)B3
G1 B10 B9
X = DON'T CARE
B13
0
0
0
0
0
•
•
•
1
1
1
1
DB17
B12
0
0
0
0
0
•
•
•
1
1
1
1
13-BIT B COUNTER
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
B11
0
••••••••••
0
••••••••••
0
••••••••••
0
••••••••••
0
••••••••••
•
••••••••••
•
••••••••••
•
••••••••••
1
••••••••••
1
••••••••••
1
••••••••••
1
••••••••••
B3 B2 B1 B COUNTER DIVIDE RATIO••••••••••
6-BIT A COUNTER
DB6
DB5 DB4 DB3DB13
A6
0
0
0
0
•
•
•
1
1
1
1
0
0
0
0
1
•
•
•
1
1
1
1
0
0
1
1
0
•
•
•
0
0
1
1
A5
••••••••••
0
••••••••••
0
••••••••••
0
••••••••••
0
••••••••••
•
••••••••••
•
••••••••••
•
••••••••••
1
••••••••••
1
••••••••••
1
••••••••••
1
••••••••••
0
1
0
1
0
•
•
•
0
1
0
1
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
3
4
8188
8189
8190
8191
A2
0
0
1
1
0
0
1
1
•
•
•
A1
0
1
0
1
•
•
•
•
•
•
0
1
0
1
CONTROL
DB2 DB1
A COUNTER
DIVIDE RATIO
0
1
2
3
•
•
•
60
61
62
63
BITS
DB0
F4 (FUNCTION LATCH)
FASTLOCK ENABLE*
0
0
1
1
*SEE TABLE 5
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS
CP GAIN OPERATION
0
1
0
1
CHARGE PUMP CURRENT
SETTTING 1 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
2 IS PERMANENTLY USED
CHARGE PUMP CURRENT SETTING
1 IS USED
CHARGE PUMP CURRENT IS SWITCHED
TO SETTING 2. THE TIME SPENT IN
SETTING 2 IS DEPENDENT UPON WHICH
FASTLOCK MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION
–14–
N = BP + A, P IS PRESCALER VALUE SET IN THE
FUNCTION LATCH B MUST BE GREATER THAN OR
EQUAL TO A. FOR CONTINUOUSLY ADJACENT VALUES
OF (N
), AT THE OUTPUT, N
X FREF
IS (P2-P).
MIN
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
M3
0
0
0
0
1
1
1
1
M2
0
0
1
1
0
0
1
1
M1
0
1
0
1
0
1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SERIAL DATA OUTPUT
DGND
F1
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
F2
0
1
PD POLARITY
NEGATIVE
POSITIVE
F3
0
1
CHARGE PUMP OUTPUT
NORMAL
THREE-STATE
0
1
1
1
CE PIN PD2 PD1 MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
X
X
0
1
X
0
1
1
F5
X
0
1
FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE2
F4
0
1
1
P1
0
1
0
1
PRESCALER VALUE
8/9
16/17
32/33
64/65
P2
0
0
1
1
CPI6
CPI3
CPI5
CPI2
CPI4
CPI1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
I
CP
(mA)
2.7k⍀ 4.7k⍀ 10k⍀
1.09
2.18
3.26
4.35
5.44
6.53
7.62
8.70
0.63
1.25
1.88
2.50
3.13
3.75
4.38
5.00
0.29
0.59
0.88
1.76
1.47
1.76
2.06
2.35
CURRENT
SETTTING
2
DB23 DB22
DB21
DB20 DB19 DB18
DB17
DB16 DB15 DB14 DB12 DB11 DB10 DB9 DB8 DB7
DB6
DB5 DB4 DB3DB13
CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (0)F5
CONTROL
BITS
PRESCALER
VALUE
DB2 DB1
DB0
PD2P1 CPI3 CPI2
POWER-
DOWN 2
CURRENT
SETTTING
1
TIMER COUNTER
CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP
THREE-
STATE
PD
POLARITY
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
P2
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TIMEOUT
(PFD CYCLES)
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
SEE PAGE 17
Table V. Function Latch Map
REV. 0
–15–
ADF4110/ADF4111/ADF4112/ADF4113
Table VI. Initialization Latch Map
CURRENT
PRESCALER
VALUE
DB23 DB22 DB21 DB20 DB19
P2
SETTTING
DOWN 2
POWER-
PD2P1 CPI3 CPI2
CPI6 CPI5 CPI4 CPI1 TC4 TC3 TC2 TC1 F4 F3 F2 M3 M2 M1 PD1 F1 C2 (1) C1 (1)F5
CPI6
CPI3
0
0
0
0
1
1
1
1
CURRENT
CPI5
CPI2
SETTTING
1
DB16
DB17
0
0
1
1
0
0
1
1
DB15 DB14 DB12 DB11 DB10
TC4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPI4
2.7k⍀ 4.7k⍀ 10k⍀
CPI1
0
1
0
1
0
1
0
1
2
DB18
1.09
2.18
3.27
4.35
5.44
6.53
7.62
8.70
TIMER COUNTER
CONTROL
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
(mA)
I
CP
0.63
0.29
1.25
0.59
1.88
0.88
2.50
1.76
3.13
1.47
3.75
1.76
4.38
2.06
5.00
2.35
TC2
FASTLOCK
F4
0
1
1
TC1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
CP
MODE
ENABLE
FASTLOCK
DB9 DB8 DB7
F3
0
1
F5
FASTLOCK MODE
FASTLOCK DISABLED
X
FASTLOCK MODE 1
0
FASTLOCK MODE2
1
TIMEOUT
(PFD CYCLES)
SEE PAGE 17
PD
STATE
THREE-
POLARITY
DB6 DB5 DB4 DB3DB13
F2
PD POLARITY
0
NEGATIVE
1
POSITIVE
CHARGE PUMP
OUTPUT NORMAL
THREE-STATE
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
MUXOUT
CONTROL
M3
0
0
0
0
1
1
1
1
CONTROL
RESET
DOWN 1
POWER-
F1
0
1
M1
M2
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
BITS
COUNTER
DB2 DB1 DB0
COUNTER
OPERATION
NORMAL
R, A, B
COUNTERS
HELD IN RESET
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N-CHANNEL OPEN-DRAIN)
SERIAL DATA OUTPUT
DGND
CE PIN PD2 PD1 MODE
X
0
X
1
0
1
1
1
P1
P2
0
0
1
1
PRESCALER VALUE
8/9
0
16/17
1
32/33
0
64/65
1
ASYNCHRONOUS POWER-
X
DOWN
0
NORMAL OPERATION
ASYNCHRONOUS POWER-
1
DOWN
1
SYNCHRONOUS POWER-DOWN
–16–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
THE FUNCTION LATCH
With C2, C1 set to 1, 0, the on-chip function latch will be programmed. Table V shows the input data format for programming
the Function Latch.
Counter Reset
DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,
the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)
Power-Down
DB3 (PD1) and DB21 (PD2) on the ADF4110 family, provide
programmable power-down modes. They are enabled by the
CE pin.
When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.
In the programmed asynchronous power-down, the device powers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”
In the programmed synchronous power-down, the device powerdown is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a “1” into
bit PD1 (on condition that a “1” has also been loaded to PD2),
the device will go into power-down on the occurrence of the next
charge pump event.
When a power-down is activated (either synchronous or asynchronous mode including CE-pin-activated power-down), the
following events occur:
All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF
input is debiased.
IN
The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 family. Table V shows the truth table.
Fastlock Enable Bit
DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.
Fastlock Mode Bit
DB10 of the Function Latch is the Fastlock Enable bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0” then Fastlock Mode 1
is selected and if the Fastlock Mode bit is “1,” then Fastlock
Mode 2 is selected.
Fastlock Mode 1
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock by
having a “0” written to the CP Gain bit in the AB counter latch.
Fastlock Mode 2
The charge pump current is switched to the contents of Current
Setting 2.
The device enters Fastlock by having a “1” written to the CP
Gain bit in the AB counter latch. The device exits Fastlock under
the control of the Timer Counter. After the timeout period determined by the value in TC4–TC1, the CP Gain bit in the AB
counter latch is automatically reset to “0” and the device reverts
to normal mode instead of Fastlock. See Table V for the timeout periods.
Timer Counter Control
The user has the option of programming two charge pump currents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed).
The normal sequence of events is as follows:
The user initially decides what the preferred charge pump currents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as the Current Setting 2.
At the same time, they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the Function Latch. The truth
table is given in Table V.
When the user wishes to program a new output frequency, he
can simply program the AB counter latch with new values for A
and B. At the same time, he can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3– CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time the user wishes
to change the frequency again.
Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”
Charge Pump Currents
CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.
Prescaler Value
P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 200 MHz. Thus, with
an RF frequency of 2 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not.
PD Polarity
This bit sets the PD Polarity Bit. See Table V.
CP Three-State
This bit the CP output pin. With the bit set high, the CP output
is put into three-state. With the bit set low, the CP output is
enabled.
REV. 0
–17–
ADF4110/ADF4111/ADF4112/ADF4113
THE INITIALIZATION LATCH
When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).
However, when the Initialization Latch is programmed an additional internal reset pulse is applied to the R and AB counters.
This pulse ensures that the AB counter is at load point when the
AB counter data is latched and the device will begin counting in
close phase alignment.
If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse and
so close phase alignment is maintained when counting resumes.
When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER INITIAL POWER-UP
After initially powering up the device, there are three ways to
program the device.
Initialization Latch Method
Apply VDD. Program the Initialization Latch (“11” in 2 LSBs
of input word). Make sure that F1 bit is programmed to “0.”
Then do an R load (“00” in 2 LSBs). Then do an AB load (“01”
in 2 LSBs).
When the Initialization Latch is loaded, the following occurs:
1. The function latch contents are loaded.
2. An internal pulse resets the R, A, B, and timeout counters
to load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes.
3. Latching the first AB counter data after the initialization word
will activate the same internal reset pulse. Successive AB loads
will not trigger the internal reset pulse unless there is another
initialization.
The CE Pin Method
Apply VDD.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
Program the Function Latch (10). Program the R Counter Latch
(00). Program the AB Counter Latch (01).
Bring CE high to take the device out of power-down. The R
and AB counters will now resume counting in close alignment.
Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.
CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
DD
was
initially applied.
The Counter Reset Method
Apply VDD.
Do a Function Latch Load (“10” in 2 LSBs). As part of this, load
“1” to the F1 bit. This enables the counter reset.
Do an R Counter Load (“00” in 2 LSBs) Do an AB Counter Load
(“01” in 2 LSBs). Do a Function Latch Load (“10” in 2 LSBs).
As part of this, load “0” to the F1 bit. This disables the counter
reset.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and threestates the charge pump, but does not trigger synchronous powerdown. The counter reset method requires an extra function latch
load compared to the initialization latch method.
RESYNCHRONIZING THE PRESCALER OUTPUT
Table III (the Reference Counter Latch Map) shows two bits,
DB22 and DB21 that are labelled DLY and SYNC respectively.
These bits affect the operation of the prescaler.
With SYNC = “1,” the prescaler output is resynchronized with
the RF input. This has the effect of reducing jitter due to the
prescaler and can lead to an overall improvement in synthesizer
phase noise performance. Typically, a 1 dB to 2 dB improvement is seen in the ADF4113. The lower bandwidth devices can
show an even greater improvement. For example, the ADF4110
phase noise is typically improved by 3 dB when SYNC is enabled.
With DLY = “1,” the prescaler output is resynchronized with a
delayed version of the RF input.
If the SYNC feature is used on the synthesizer, some care must
be taken. At some point, (at certain temperatures and output
frequencies), the delay through the prescaler will coincide with
the active edge on RF input and this will cause the SYNC feature to break down. So, it is important when using the SYNC
feature to be aware of this. Adding a delay to the RF signal, by
programming DLY = “1,” will extend the operating frequency
and temperature somewhat. Using the SYNC feature will also
increase the value of the AI
output, the ADF4113 AI
for the device. With a 900 MHz
DD
increases by about 1.3 mA when
DD
SYNC is enabled and a further 0.3 mA if DLY is enabled.
All the typical performance plots on the data sheet except for
Figure 5 apply for DLY and SYNC = “0,” i.e., no resynchronization or delay enabled.
–18–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
APPLICATIONS SECTION
Local Oscillator for GSM Base Station Transmitter
The following diagram shows the ADF4111/ADF4112/ADF4113
being used with a VCO to produce the LO for a GSM base station
transmitter.
The reference input signal is applied to the circuit at FREF
IN
and, in this case, is terminated in 50 Ω. Typical GSM system
would have a 13 MHz TCXO driving the Reference Input
without any 50 Ω termination. In order to have a channel
spacing of 200 kHz (the GSM standard), the reference input
must be divided by 65, using the on-chip reference divider of
the ADF4111/ADF4112/ADF4113.
The charge pump output of the ADF4111/ADF4112/ADF4113
(Pin 2) drives the loop filter. In calculating the loop filter component values, a number of items need to be considered. In this
example, the loop filter was designed so that the overall phase
margin for the system would be 45 degrees. Other PLL system
specifications are:
FREF
V
DD
71516
1000pF
AVDDDV
REF
8
1000pF
IN
51⍀
ADF4111
ADF4112
ADF4113
CE
CLK
DATA
LE
1
R
SET
4.7k⍀
CPGND
349
IN
AGND
V
V
DD
CP
MUXOUT
RFINA
RFINB
DGND
P
P
2
1nF
14
LOCK
DETECT
100pF
6
5
51⍀
100pF
KD = 5 mA
K
= 12 MHz/V
V
Loop Bandwidth = 20 kHz
= 200 kHz
F
REF
N = 4500
Extra Reference Spur Attenuation = 10 dB
All of these specifications are needed and used to come up with
the loop filter components values shown in Figure 29.
The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives
the RF Output terminal. A T-circuit configuration provides
50 Ω matching between the VCO output, the RF output and
the RF
terminal of the synthesizer.
IN
In a PLL system, it is important to know when the system is in
lock. In Figure 29, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be programmed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.
RF
OUT
100pF
18⍀
18⍀
18⍀
3.3k⍀
5.6k⍀
8.2nF
620pF
V
CC
C
VCO190-902T
B
100pF
P
REV. 0
SPI COMPATIBLE SERIAL BUS
Figure 29. Local Oscillator for GSM Base Station
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF411
AND ON THE POSITIVE SUPPLY OF THE VCO190-902T HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
–19–
X
ADF4110/ADF4111/ADF4112/ADF4113
100pF
RF
OUT
FREF
2
8
IN
REF
IN
ADF4111
CP
R
SET
LOOP
FILTER
ADF4112
ADF4113
CE
CLK
DATA
LE
1
R
SET
2.7k⍀
AD5320
12-BIT
V-OUT DAC
SPI COMPATIBLE SERIAL BUS
Figure 30. Driving the R
USING A D/A CONVERTER TO DRIVE R
You can use a D/A converter to drive the R
MUXOUT
RFINA
RF
IN
PIN
SET
pin of the
SET
14
LOCK
DETECT
100pF
6
5
B
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FOR CLARITY.
SET
ADF4110 family and thus increase the level of control over the
charge pump current I
. This can be advantageous in wideband
CP
applications where the sensitivity of the VCO varies over the
tuning range. To compensate for this, the I
may be varied to
CP
maintain good phase margin and ensure loop stability. See
Figure 30.
SHUTDOWN CIRCUIT
The attached circuit in Figure 31 shows how to shut down both
the ADF4110 family and the accompanying VCO. The ADG701
switch goes closed circuit when a Logic 1 is applied to the IN
input. The low-cost switch is available in both SOT-23 and
micro SO packages.
WIDEBAND PLL
Many of the wireless applications for synthesizers and VCOs in
PLLs are narrowband in nature. These applications include
the various wireless standards like GSM, DSC1800, CDMA or
WCDMA. In each of these cases, the total tuning range for the
local oscillator is less than 100 MHz. However, there are also
INPUT
GND
OUTPUT
100pF
VCO
18⍀
18⍀
18⍀
Pin with a D/A Converter
wide band applications where the local oscillator could have up
to an octave tuning range. For example, cable TV tuners have a
total range of about 400 MHz. Figure 32 shows an application where the ADF4113 is used to control and program the
Micronetics M3500-2235. The loop filter was designed for an
RF output of 2900 MHz, a loop bandwidth of 40 kHz, a PFD
frequency of 1 MHz, I
of 10 mA (2.5 mA synthesizer I
CP
CP
multiplied by the gain factor of 4), VCO KD of 90 MHz/V (sensitivity of the M3500-2235 at an output of 2900 MHz) and a
phase margin of 45°C.
In narrow-band applications, there is generally a small variation
in output frequency (generally less than 10%) and also a small
variation in VCO sensitivity over the range (typically 10% to 15%).
However, in wide band applications both of these parameters
have a much greater variation. In Figure 32, for example, we have
–25% and +17% variation in the RF output from the nominal
2.9 GHz. The sensitivity of the VCO can vary from 120 MHz/V
at 2750 MHz to 75 MHz/V at 3400 MHz (+33%, –17%).
Variations in these parameters will change the loop bandwidth.
This in turn can affect stability and lock time. By changing the
programmable I
, it is possible to get compensation for these
CP
varying loop conditions and ensure that the loop is always operating close to optimal conditions.
–20–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
V
P
FREF
FREF
POWER-DOWN CONTROL
V
DD
71516
AVDDDV
8
IN
REF
DD
IN
ADF4110
V
CE
P
2
CP
1
R
SET
4.7k⍀
LOOP
FILTER
IN
V
GND
S
ADG701
D
CC
VCO
V
GND
DD
100pF
100pF
18⍀
18⍀
18⍀
RF
OUT
ADF4111
ADF4112
ADF4113
100pF
6
RFINA
5
RF
AGND
CPGND
DGND
349
B
IN
51⍀
100pF
DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 31. Local Oscillator Shutdown Circuit
RF
V
DD
7
AVDDDV
1000pF
1000pF
IN
51⍀
REF
8
15 16
DD
IN
R
ADF4113
V
V
SET
CP
P
1k⍀
P
2
2.8nF
4.7k⍀
3.3k⍀
19nF
680⍀
20V
3k⍀
AD820
130pF
12V
V
CC
V_TUNE
M3500-2235
GND
OUT
100pF
100pF
18⍀
OUT
18⍀
18⍀
REV. 0
CE
CLK
MUXOUT
DATA
LE
AGND
CPGND
3
4
SPI-COMPATIBLE SERIAL BUS
14
LOCK
DETECT
100pF
6
RFINA
5
RF
B
IN
DGND
9
51⍀
100pF
DECOUPLING CAPACITORS ON AVDD, DVDD, VP OF THE ADF4113
AND ON VCC OF THE M3500-2250 HAVE BEEN OMITTED FROM
THE DIAGRAM TO AID CLARITY.
Figure 32. Wideband Phase Locked Loop
–21–
ADF4110/ADF4111/ADF4112/ADF4113
DIRECT CONVERSION MODULATOR
In some applications a direct conversion architecture can be used
in base station transmitters. Figure 33 shows the combination
available from ADI to implement this solution.
The circuit diagram shows the AD9761 being used with the
AD8346. The use of dual integrated DACs such as the AD9761
with specified ±0.02 dB and ± 0.004 dB gain and offset matching characteristics ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The Local Oscillator (LO) is implemented using the ADF4113.
In this case, the OSC 3B1-13M0 provides the stable 13 MHz
reference frequency. The system is designed for a 200 kHz
channel spacing and an output center frequency of 1960 MHz.
MODULATED
DIGITAL
DATA
OSC 3B1-13M0
TCXO
SERIAL
DIGITAL
NTERFACE
REFIO
AD9761
FS ADJ
2k⍀
REF
TxDAC
R
SET
IN
ADF4113
IOUTA
IOUTB
QOUTA
QOUTB
4.7k⍀
RFINARFINB
CP
910pF
3.3k⍀
3.9k⍀
9.1nF
LOW-PASS
FILTER
LOW-PASS
FILTER
620pF
The target application is a WCDMA base station transmitter.
Typical phase noise performance from this LO is –85 dBc/Hz at
a 1 kHz offset.
The LO port of the AD8346 is driven in single-ended fashion.
LOIN is ac-coupled to ground with the 100 pF capacitor and
LOIP is driven through the ac coupling capacitor from a 50 Ω
source. An LO drive level of between –6 dBm and –12 dBm is
required. The circuit of Figure 33 gives a typical level of –8 dBm.
The RF output is designed to drive a 50 Ω load but must be
ac-coupled as shown in Figure 33. If the I and Q inputs are
driven in quadrature by 2 V p-p signals, the resulting output
power will be around –10 dBm.
VOUT
100pF
RF
OUT
VCO190-1960T
IBBP
IBBN
AD8346
QBBP
QBBN
LOIN LOIP
100pF 100pF
18⍀
18⍀
18⍀
100pF
100pF
100pF
51⍀
POWER SUPPLY CONNECTIONS AND DECOUPLING
CAPACITORS ARE OMITTED FROM DIAGRAM FOR CLARITY.
Figure 33. Direct Conversion Transmitter Solution
–22–
REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
INTERFACING
The ADF4110 family has a simple SPI-compatible serial interface for writing to the device. SCLK, SDATA and LE control
the data transfer. When LE (Latch Enable) goes high, the 24 bits
which have been clocked into the input register on each rising
edge of SCLK will get transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.
The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz or
one update every 1.2 microseconds. This is certainly more than
adequate for systems that will have typical lock times in hundreds
of microseconds.
ADuC812 Interface
Figure 34 shows the interface between the ADF4110 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4110 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written the LE input should be brought high to
complete the transfer.
On first applying power to the ADF4110 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.
I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be
166 kHz.
ADSP-2181 Interface
Figure 35 shows the interface between the ADF4110 family and
the ADSP-21xx Digital Signal Processor. The ADF4110 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate
Framing. This provides a means for transmitting an entire
block of serial data before an interrupt is generated.
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4110
ADF4111
ADF4112
ADF4113
ADSP-21xx
I/O FLAGS
SCLK
DT
TFS
Figure 35. ADSP-21xx to ADF4110 Family Interface
Set up the word length for 8 bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store
the three 8-bit bytes, enable the Autobuffered mode and then
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
SCLK
SDATA
LE
CE
MUXOUT
(LOCK DETECT)
ADF4110
ADF4111
ADF4112
ADF4113
ADuC812
SCLOCK
MOSI
I/O PORTS
Figure 34. ADuC812 to ADF4110 Family Interface
REV. 0
–23–
ADF4110/ADF4111/ADF4112/ADF4113
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Chip Scale
(CP-20)
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
0.039 (1.00)
0.035 (0.90)
0.031 (0.80)
SEATING
PLANE
0.159 (4.05)
0.157 (4.00)
0.156 (3.95)
TOP VIEW
0.0079 (0.20)
REF
0.018 (0.45)
0.016 (0.40)
0.014 (0.35)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
0.016 (0.40)
0.014 (0.35)
DETAIL E
0.020 (0.5) REF
LEAD PITCH
0.0083 (0.211)
0.0079 (0.200)
0.0077 (0.195)
LEAD OPTION
DETAIL E
0.011 (0.275)
0.010 (0.250)
0.009 (0.225)
0.0059 (0.15)
REF
0.079 (2.0) REF
16
15
11
BOTTOM VIEW
(ROTATED 180ⴗ)
0.0059
(0.15)
REF
Thin Shrink Small Outline
(RU-16)
0.201 (5.10)
0.193 (4.90)
0.014 (0.35) ⴛ 45°0.018 (0.45)
20
1
0.079
(2.0)
REF
5
610
C3766–5–4/00 (rev. 0)
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
16
0.0256 (0.65)
BSC
9
0.177 (4.50)
0.169 (4.30)
81
0.0433 (1.10)
MAX
0.0118 (0.30)
0.0075 (0.19)
0.256 (6.50)
0.246 (6.25)
0.0079 (0.20)
0.0035 (0.090)
8ⴗ
0ⴗ
0.028 (0.70)
0.020 (0.50)
PRINTED IN U.S.A.
–24–
REV. 0
Loading...