Analog Devices ADF4111, ADF4110, ADF4113, ADF4112 Datasheet

a

RF PLL Frequency Synthesizers

ADF4110/ADF4111/ADF4112/ADF4113

FEATURES
ADF4110: 550 MHz
ADF4111: 1.2 GHz
ADF4112: 3.0 GHz
ADF4113: 4.0 GHz

2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler 8/9, 16/17,

32/33, 64/65
Programmable Charge Pump Currents
Programmable Antibacklash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode

APPLICATIONS
Base Stations for Wireless Radio (GSM, PCS, DCS,

CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANS
Communications Test Equipment
CATV Equipment

FUNCTIONAL BLOCK DIAGRAM

AV

DV

DD

DD

GENERAL DESCRIPTION

The ADF4110 family of frequency synthesizers can be used
to implement local oscillators in the upconversion and down­conversion sections of wireless receivers and transmitters. They
consist of a low-noise digital PFD (Phase Frequency Detector),
a precision charge pump, a programmable reference divider,
programmable A and B counters and a dual-modulus prescaler
(P/P+1). The A (6-bit) and B (13-bit) counters, in conjunction
with the dual modulus prescaler (P/P+1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter), allows selectable REFIN frequencies at the PFD
input. A complete PLL (Phase-Locked Loop) can be imple­mented if the synthesizer is used with an external loop filter and
VCO (Voltage Controlled Oscillator).

Control of all the on-chip registers is via a simple 3-wire interface.
The devices operate with a power supply ranging from 2.7 V to

5.5 V and can be powered down when not in use.

V

CPGND

P

R

SET

REF

CLK

DATA

RF

RF

IN

24-BIT

LE

A

IN

B

IN

INPUT REGISTER

FROM

FUNCTION

LATCH

PRESCALER

P/P +1

SD

OUT

N = BP + A

22

DGNDAGNDCE

14-BIT

R COUNTER

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

6-BIT

A COUNTER

14

19

13

6

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

AV

SD

DD

OUT

CHARGE

PUMP

CURRENT

SETTING 1

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

MUX

M3 M2 M1

CURRENT

SETTING 2

HIGH Z

CP

MUXOUT

ADF4110/ADF4111
ADF4112/ADF4113

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

ADF4110/ADF4111/ADF4112/ADF4113–SPECIFICATIONS

1

(AV

= DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AVDD ≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V; R

DD

Parameter B Version B Chips

2

Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V) See Figure 25 for Input Circuit.

RF Input Frequency Use a square wave for lower frequencies.

ADF4110 45/550 45/550 MHz min/max
ADF4110 25/550 25/550 MHz min/max Input Level = –10 dBm
ADF4111 0.045/1.2 0.045/1.2 GHz min/max
ADF4112 0.2/3.0 0.2/3.0 GHz min/max
ADF4112 0.1/3.0 0.1/3.0 GHz min/max Input Level = –10 dBm

ADF4113 0.2/3.7 0.2/3.7 GHz min/max Input Level = –10 dBm
RF Input Sensitivity –15/0 –15/0 dBm min/max
Maximum Allowable Prescaler
Output Frequency

3

165 165 MHz max

RF CHARACTERISTICS (5 V)

RF Input Frequency Use a square wave for lower frequencies.

ADF4110 25/550 25/550 MHz min/max

ADF4111 0.025/1.4 0.025/1.4 GHz min/max

ADF4112 0.1/3.0 0.1/3.0 GHz min/max

ADF4113 0.2/3.7 0.2/3.7 GHz min/max

ADF4113 0.2/4.0 0.2/4.0 GHz min/max Input Level = –5 dBm
RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable Prescaler
Output Frequency

3

200 200 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 0/100 0/100 MHz min/max
Reference Input Sensitivity

4

–5/0 –5/0 dBm min/max AC-Coupled. When DC-Coupled:

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

5

55 55 MHz max

CHARGE PUMP

I

Sink/Source Programmable: See Table V

CP

High Value 5 5 mA typ With R

Low Value 625 625 µA typ

Absolute Accuracy 2.5 2.5 % typ With R

Range 2.7/10 2.7/10 kΩ typ See Table V

R

SET

I

3-State Leakage Current 1 1 nA typ

CP

Sink and Source Current Matching 2 2 % typ 0.5 V ≤ V
I

CP

vs. V

CP

1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 0.8 × DV

INH

, Input Low Voltage 0.2 × DV

V

INL

I

, Input Current ± 1 ± 1 µA max

INH/IINL

DD

DD

0.8 × DV

0.2 × DV

DD

DD

V min
V max

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

V

, Output High Voltage DVDD – 0.4 DVDD – 0.4 V min IOH = 500 µA

OH

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV

DD

DV

DD

V

P

6

(AIDD + DI

I

DD

) See Figures 22 and 23

DD

2.7/5.5 2.7/5.5 V min/V max
AV

DD

AV

DD

AVDD/6.0 AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V

ADF4110 5.5 4.5 mA max 4.5 mA Typical

ADF4111 5.5 4.5 mA max 4.5 mA Typical

ADF4112 7.5 6.5 mA max 6.5 mA Typical

ADF4113 11 8.5 mA max 8.5 mA Typical

I

P

0.5 0.5 mA max TA = 25°C

Low Power Sleep Mode 1 1 µA typ

= 4.7 k⍀; TA = T

SET

0 to V

to T

MIN

DD

unless otherwise noted)

MAX

max (CMOS-Compatible)

= 4.7 kΩ

SET

= 4.7 kΩ

SET

≤ VP – 0.5

CP

–2–

REV. 0

ADF4110/ADF4111/ADF4112/ADF4113

Parameter B Version B Chips

NOISE CHARACTERISTICS

ADF4113 Phase Noise Floor

Phase Noise Performance

ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output
ADF4113: 3100 MHz Output

Spurious Signals

ADF4110: 540 MHz Output
ADF4111: 900 MHz Output
ADF4112: 900 MHz Output
ADF4113: 900 MHz Output
ADF4111: 836 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1750 MHz Output
ADF4112: 1960 MHz Output
ADF4113: 1960 MHz Output

7

8

–171 –171 dBc/Hz typ @ 25 kHz PFD Frequency
–164 –164 dBc/Hz typ @ 200 kHz PFD Frequency

9

–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

10

–87 –87 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

10

–90 –90 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

10

–91 –91 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

11

–78 –78 dBc/Hz typ @ 300 Hz Offset and 30 kHz PFD Frequency

12

–86 –86 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

13

–66 –66 dBc/Hz typ @ 200 Hz Offset and 10 kHz PFD Frequency

14

–84 –84 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

14

–85 –85 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

15

–86 –86 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

9

–97/–106 –97/–106 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

10

–98/–110 –98/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

10

–91/–100 –91/–100 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

10

–100/–110 –100/–110 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

11

–81/–84 –81/–84 dBc typ @ 30 kHz/60 kHz and 30 kHz PFD Frequency

12

–88/–90 –88/–90 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

13

–65/–73 –65/–73 dBc typ @ 10 kHz/20 kHz and 10 kHz PFD Frequency

14

–80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

14

–80/–84 –80/–84 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

ADF4113: 3100 MHz Output15–80/–82 –82/–82 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

The B Chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency
which is less than this value.

4

AVDD = DVDD = 3 V; For AVDD = DVDD = 5 V, use CMOS-compatible levels.

5

Guaranteed by design.

6

TA = 25°C; AVDD = DVDD = 3 V; P = 16; SYNC = 0; DLY = 0; RFIN for ADF4110 = 540 MHz; RFIN for ADF4111, ADF4112, ADF4113 = 900 MHz.

7

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

8

The phase noise is measured with the EVAL-ADF411XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (f

9

f

= 10 MHz; f

REFIN

10

f

= 10 MHz; f

REFIN

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

= 10 MHz @ 0 dBm). SYNC = 0; DLY = 0 (See Table III).

REFOUT

= 200 kHz; Offset frequency = 1 kHz; fRF = 540 MHz; N = 2700; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz.

PFD

= 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz.

PFD

= 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz.

PFD

= 1 MHz; Offset frequency = 1 kHz; fRF = 3100 MHz; N = 3100; Loop B/W = 20 kHz.

PFD

2

Unit Test Conditions/Comments

@ VCO Output

(AV

TIMING CHARACTERISTICS

Limit at T

= DVDD = 3 V ⴞ 10%, 5 V ⴞ 10%; AV

DD

1

R

= 4.7 k⍀; TA = T

SET

to T

MIN

MAX

MIN

to T

unless otherwise noted)

MAX

≤ VP ≤ 6.0 V; AGND = DGND = CPGND = 0 V;

DD

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

Guaranteed by design but not production tested.

Specifications subject to change without notice.

REV. 0

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

–3–

ADF4110/ADF4111/ADF4112/ADF4113

CLOCK

DATA

LE

LE

t

1

DB20 (MSB) DB19 DB2

t

2

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1, 2

AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AV

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

P

V

to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V

IN

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP θ
CSP θ

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance (Paddle Soldered) . . . 122°C/W

JA

t

3

CSP θ

t

4

DB1

(CONTROL BIT C2)

Thermal Impedance

JA

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

(Paddle Not Soldered) . . . . . . . . . . . . . . . . . . . . . 216°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

TRANSISTOR COUNT

6425 (CMOS) and 303 (Bipolar).

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu­late on the human body and test equipment and can discharge without detection. Although the

WARNING!

ADF4110/ADF4111/ADF4112/ADF4113 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ESD SENSITIVE DEVICE

ORDERING GUIDE

Model Temperature Range Package Description Package Option*

ADF4110BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4110BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4111BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4111BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4112BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4112BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4113BCP –40°C to +85°C Chip Scale Package (CSP) CP-20
ADF4113BCHIPS –40°C to +85°C DICE DICE

*Contact the factory for chip availability.

–4–

REV. 0

ADF4110/ADF4111/ADF4112/ADF4113

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1R

SET

2 CP Charge Pump Output. When enabled this provides ±I

3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the prescaler.
5RF

6RF
7AV

8 REF

B Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with

IN

A Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.

IN

DD

IN

9 DGND Digital Ground.
10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency

15 DV

16 V

DD

P

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R

SET

I

CP

So, with R

= 4.7 kΩ, I

SET

CPmax

= 5 mA.

pin is 0.56 V. The relationship between ICP and R

max

.=23 5

R

SET

to the external loop filter, which in turn drives the

CP

SET

is

external VCO.

a small bypass capacitor, typically 100 pF. See Figure 25.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV

must be the same value as DVDD.

DD

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resis­tance of 100 kΩ. See Figure 24. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.

state mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.

the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

input is a high impedance CMOS input.

of the four latches, the latch being selected using the control bits.

to be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V.

REV. 0

TSSOP

1

R

SET

2

CP

ADF4110
ADF4111

3

CPGND

AGND

RF

RF

AV

REF

B

IN

A

IN

DD

IN

ADF4112

4

ADF4113

5

TOP VIEW

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT

LE

DATA

CLK

CE

DGND

PIN CONFIGURATIONS

–5–

CHIP SCALE PACKAGE

VPDVDDDV

8

9

10

IN

REF

DGND

DGND

DD

15

14

13

12

11

MUXOUT

LE

DATA

CLK

CE

CPGND

AGND

AGND

RF

IN

RF

IN

CP

2019181716

1

2

3

B

4

(Not to Scale)

5

A

6

AVDDAV

SET

R

ADF4110
ADF4111
ADF4112
ADF4113

TOP VIEW

7

DD

ADF4110/ADF4111/ADF4112/ADF4113

–Typical Performance Characteristics

FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD IMPEDANCE – OHMS
GHz S MA R 50

FREQ MAGS11 ANGS11

0.05 0.89207 –2.0571

0.10 0.8886 –4.4427

0.15 0.89022 –6.3212

0.20 0.96323 –2.1393

0.25 0.90566 –12.13

0.30 0.90307 –13.52

0.35 0.89318 –15.746

0.40 0.89806 –18.056

0.45 0.89565 –19.693

0.50 0.88538 –22.246

0.55 0.89699 –24.336

0.60 0.89927 –25.948

0.65 0.87797 –28.457

0.70 0.90765 –29.735

0.75 0.88526 –31.879

0.80 0.81267 –32.681

0.85 0.90357 –31.522

0.90 0.92954 –34.222

0.95 0.92087 –36.961

1.00 0.93788 –39.343

FREQ MAGS11 ANGS11

1.05 0.9512 –40.134

1.10 0.93458 –43.747

1.15 0.94782 –44.393

1.20 0.96875 –46.937

1.25 0.92216 –49.6

1.30 0.93755 –51.884

1.35 0.96178 –51.21

1.40 0.94354 –53.55

1.45 0.95189 –56.786

1.50 0.97647 –58.781

1.55 0.98619 –60.545

1.60 0.95459 –61.43

1.65 0.97945 –61.241

1.70 0.98864 –64.051

1.75 0.97399 –66.19

1.80 0.97216 –63.775

Figure 2. S-Parameter Data for the ADF4113 RF Input (Up
to 1.8 GHz)

0

VDD = 3V

= 3V

V

P

3

4

5

–10

–15

–20

–25

RF INPUT POWER – dBm

–30

–35

–5

TA = +85ⴗC

TA = +25ⴗC

TA = –40ⴗC

0

1

2

RF INPUT FREQUENCY – GHz

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 900MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–92.5dBc/Hz

Figure 5. ADF4113 Phase Noise (900 MHz, 200 kHz,
20 kHz) with DLY and SYNC Enabled

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.52ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz

0.52ⴗ rms

Figure 3. Input Sensitivity (ADF4113)

0

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 900MHz +1kHz +2kHz

OUTPUT POWER – dB

–100

–10

–20

–30

–40

–50

–60

–70

–80

–90

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 19

–91.0dBc/Hz

Figure 4. ADF4113 Phase Noise (900 MHz, 200 kHz, 20 kHz)

Figure 6. ADF4113 Integrated Phase Noise (900 MHz,

µ

200 kHz, 20 kHz, Typical Lock Time: 400

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 0.62ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 900MHz CARRIER 1MHz

s)

0.62ⴗ rms

Figure 7. ADF4113 Integrated Phase Noise (900 MHz,

µ

200 kHz, 35 kHz, Typical Lock Time: 200

s)

–6–

REV. 0

ADF4110/ADF4111/ADF4112/ADF4113

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.6ⴗ

100Hz FREQUENCY OFFSET FROM 1750MHz CARRIER 1MHz

1.6ⴗ rms

PHASE NOISE – dBc/Hz

–90

–80

–70

–60

–50

–40

–100

–110

–120

–130

–140

–80kHz –40kHz

1750MHz +40kHz +80kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 3Hz

VIDEO BANDWIDTH = 3Hz

SWEEP = 255 SECONDS

POSITIVE PEAK DETECT

MODE

REFERENCE
LEVEL = –5.7dBm

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

POWER OUTPUT – dB

–79.6dBc

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –4.2dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 20kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 2.5 SECONDS

AVERAGES = 30

–90.2dBc

Figure 8. ADF4113 Reference Spurs (900 MHz, 200 kHz,
20 kHz)

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

0

REFERENCE
LEVEL = –4.2dBm

–400kHz –200kHz 900MHz +200kHz +400kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 35kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 2.5 SECONDS

AVERAGES = 30

–89.3dBc

Figure 11. ADF4113 Integrated Phase Noise (1750 MHz,
30 kHz, 3 kHz)

Figure 9. ADF4113 Reference Spurs (900 MHz, 200 kHz,
35 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

REV. 0

–80

–90

–100

Figure 10. ADF4113 Phase Noise (1750 MHz, 30 kHz,
3 kHz)

REFERENCE
LEVEL = –8.0dBm

–400Hz –200Hz 1750MHz +200Hz +400Hz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 30kHz

LOOP BANDWIDTH = 3kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 477ms

AVERAGES = 10

–75.2dBc/Hz

Figure 12. ADF4113 Reference Spurs (1750 MHz, 30 kHz,
3 kHz)

OUTPUT POWER – dB

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –4.2dBm

–2kHz –1kHz 3100MHz +1kHz +2kHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 10Hz

VIDEO BANDWIDTH = 10Hz

SWEEP = 1.9 SECONDS

AVERAGES = 45

–86.6dBc/Hz

Figure 13. ADF4113 Phase Noise (3100 MHz, 1 MHz,
100 kHz)

–7–

ADF4110/ADF4111/ADF4112/ADF4113

10dB/DIVISION RL = –40dBc/Hz RMS NOISE = 1.7ⴗ

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz FREQUENCY OFFSET FROM 3100MHz CARRIER 1MHz

Figure 14. ADF4113 Integrated Phase Noise (3100 MHz,

1 MHz, 100 kHz)

1.7ⴗ rms

–60

VDD = 3V

= 3V

V

–70

–80

PHASE NOISE – dBc/Hz

–90

–100

–20

TEMPERATURE – ⴗC

P

Figure 17. ADF4113 Phase Noise vs. Temperature

(900 MHz, 200 kHz, 20 kHz)

100–40 0 20 40 60 80

OUTPUT POWER – dB

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

REFERENCE
LEVEL = –17.2dBm

–2MHz –1MHz 3100MHz +1MHz +2MHz

VDD = 3V, VP = 5V

ICP = 5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 100kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

SWEEP = 13 SECONDS

AVERAGES = 1

–80.6dBc

Figure 15. ADF4113 Reference Spurs (3100 MHz, 1 MHz,
100 kHz)

–120

–130

–140

–150

–160

PHASE NOISE – dBc/Hz

–170

–180

1 10000100 1000

10

PHASE DETECTOR FREQUENCY – kHz

VDD = 3V
V

= 5V

P

Figure 16. ADF4113 Phase Noise (Referred to CP Output)
vs. PFD Frequency

–60

VDD = 3V

= 5V

V

–70

–80

–90

FIRST REFERENCE SPUR – dBc

–100

–20

TEMPERATURE – ⴗC

P

100–40 0 20 40 60 80

Figure 18. ADF4113 Reference Spurs vs. Temperature
(900 MHz, 200 kHz, 20 kHz)

–5

FIRST REFERENCE SPUR – dBc

–105

–15

–25

–35

–45

–55

–65

–75

–85

–95

1

TUNING VOLTAGE – Volts

VDD = 3V

= 5V

V

P

50234

Figure 19. ADF4113 Reference Spurs (200 kHz) vs.

(900 MHz, 200 kHz, 20 kHz)

V

TUNE

–8–

REV. 0