Datasheet ADF4106-EP Datasheet (ANALOG DEVICES)

V

PLL Frequency Synthesizer

FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

Support defense and aerospace applications (AQEC)

Military temperature range (−55°C to +125°C)

Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios

ADF4106-EP

GENERAL DESCRIPTION

The ADF4106-EP frequency synthesizer can be used to
implement local oscillators in the up-conversion and down­conversion sections of wireless receivers and transmitters. It
consists of a low noise, digital phase frequency detector (PFD),
a precision charge pump, a programmable reference divider,
programmable A counter and B counter, and a dual-modulus
prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in
conjunction with the dual-modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REF
PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.

Additional application and technical information can be found
in the ADF4106 data sheet.

frequencies at the

IN

DV

AV

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

FUNCTION

PRESCALER

DD

FROM

LATCH

P/P + 1

CE

DD

22

N = BP + A

AGND

DGND

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13

13-BIT

B COUNTER

LOAD

LOAD

6-BIT

A COUNTER

6

19

Figure 1.

CPGND

P

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

MUX

M3 M2 M1

REFERENCE

CHARGE

PUMP

R

SET

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4106-EP

09272-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADF4106-EP

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characterisitics ............................................................... 4

REVISION HISTORY

11/10—Rev. 0 to Rev. A

Changes to Figure 6.......................................................................... 7

Changes to Figure 11........................................................................ 8

Changes to Ordering Guide.......................................................... 10

8/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configurations and Function Descriptions............................6

Typical Performance Characteristics..............................................7

PCB Design Guidelines for Chip Scale Package............................9

Outline Dimensions....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. A | Page 2 of 12

ADF4106-EP

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 1.

Parameter B Version1 Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN) 0.5/6.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/μs

RF Input Sensitivity −10/0 dBm min/max

Maximum Allowable Prescaler Output Frequency2 300 MHz max P = 8

325 MHz P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs

REFIN Input Sensitivity3 0.8/VDD V p-p min/max Biased at AVDD/24

REFIN Input Capacitance 10 pF max

REFIN Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency5 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP

ICP Sink/Source

High Value 5 mA typ With R
Low Value 625 μA typ
Absolute Accuracy 2.5 % typ With R
R

Range 3.0/11 kΩ typ

SET

ICP Three-State Leakage 2 nA max 1 nA typical; TA = 25°C

Sink and Source Current Matching 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 V min

VIL, Input Low Voltage 0.6 V max

I

, I

, Input Current ±1 μA max

INH

INL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V

V

− 0.4 V min CMOS output chosen

DD

IOH 100 μA max

VOL, Output Low Voltage 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 2.7/3.3 V min/V max

DVDD AVDD

VP AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5 V

6

I

(AIDD + DIDD) 11 mA max 9.0 mA typical

DD

7

I

(AIDD + DIDD) 11.5 mA max 9.5 mA typical

DD

8

I

(AIDD + DIDD) 13 mA max 10.5 mA typical

DD

IP 0.4 mA max TA = 25°C

Power-Down Mode9 (AIDD + DIDD) 10 μA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

Rev. A | Page 3 of 12

ADF4106-EP

Parameter B Version1 Unit Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN

)11 −122 dBc/Hz typ Measured at 10 kHz offset; normalized to 1 GHz

1_f

Phase Noise Performance12 VCO output

900 MHz13 −92.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz14 −76.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz15 −83.5 dBc/Hz typ 1 kHz offset and 1 MHz PFD frequency

Spurious Signals

900 MHz13 −90/−92 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz14 −65/−70 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz15 −70/−75 dBc typ 1 MHz/2 MHz and 1 MHz PFD frequency

1

Operating temperature range is −55°C to +125°C.

2

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

3

AVDD = DVDD = 3 V.

4

AC coupling ensures AVDD/2 bias.

5

Guaranteed by design. Sample tested to ensure compliance.

6

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.

8

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.

9

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.

10

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F

11

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a
frequency offset, f, is given by PN = P

12

The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

f

= 10 MHz; f

REFIN

. PN

= PN

PFD

SYNTH

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz.

PFD

= 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz.

PFD

− 10 log F

TOT

1_f

TIMING CHARACTERISITICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

)10 −223 dBc/Hz typ PLL loop BW = 500 kHz

SYNTH

− 20 log N.

PFD

+ 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MAX

to T

MIN

,

Table 2.

Parameter Limit1 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK Setup Time
t2 10 ns min DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulse Width

1

Operating temperature range (B Version) is –40°C to +85°C.

Timing Diagram

t

t

3

4

CLOCK

DB23 (MSB)

DATA

LE

LE

t

t

1

2

DB22

DB2

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

09272-002

Rev. A | Page 4 of 12

ADF4106-EP

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to + 3.6 V
AVDD to DVDD −0.3 V to + 0.3 V
VP to GND −0.3 V to + 5.8 V
VP to AVDD −0.3 V to + 5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C

Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
θJA Thermal Impedance

16-Lead TSSOP 112°C/W

20-Lead LFCSP (Paddle Soldered) 30.4°C/W

Reflow Soldering

Peak Temperature 260°C

Time at Peak Temperature 40 sec

Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

ESD CAUTION

Rev. A | Page 5 of 12

ADF4106-EP

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

DD

1

R

SET

2

CP

3

CPGND

AGND

RFINB
RF

REF

NOTES:

1. TRANSIS TOR COUNT 6425 ( C M OS),

ADF4106-EP

4

(Not to S cale)

5

6

A

IN

7

AV

DD

8

IN

303 (BIPOL AR).

TOP VIEW

Figure 3. 16-Lead TSSOP Pin Configuration

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
CE
DGND

CPGND 1

AGND 2
AGND 3
RFINB 4
RF

A 5

IN

NOTES

09272-003

1. TRANSISTOR COUNT 6425 ( C MOS),
303 (BIPOL AR) .

2. THE EXPOSED PAD MUST BE

CONNECTED TO AGND.

Figure 4. 20-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
TSSOP

1 19 R

2 20 CP

Pin No.
LFCSP Mnemonic Description

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R

I

So, with R

MAXCP

=

R

= 5.1 kΩ, I

SET

Charge Pump Output. When enabled, this provides ±I

SET

pin is 0.66 V. The relationship between ICP and R

SET

5.25

= 5 mA.

CP MAX

to the external loop filter, which in turn drives

CP

the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a

small bypass capacitor, typically 100 pF.
6 5 RFINA Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7 6, 7 AVDD

8 8 REFIN

Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV

must be the same value as DVDD.

DD

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into

three-state mode. Taking the pin high powers up the device, depending on the status of the power-

down bit, F2.
11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input

is a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

the four latches with the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to

be accessed externally.
15 16, 17 DVDD

16 18 VP

Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This should be greater than or equal to V

can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP Exposed Pad. The exposed pad must be connected to AGND.

SETVP

R

DV

DV

20 CP

191817

16

PIN 1
INDICATOR

ADF4106-EP

TOP VIEW

(Not to Scale)

6

7

DD

DD

AV

AV

/2 and a dc equivalent input

DD

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

8

IN

REF

DGND 9

DGND 10

SET

. In systems where VDD is 3 V, it

DD

is

09272-004

Rev. A | Page 6 of 12

ADF4106-EP

–

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ UNIT GHz KEYW ORD R
PARAM TYPE S IMPEDANCE 50Ω
DATA FORMAT MA

FREQ MAGS11 ANGS11

0.500 0.89148 –17.2820

0.600 0.88133 – 20.6919

0.700 0.87152 – 24.5386

0.800 0.85855 –27.3228

0.900 0.84911 –31.0698

1.000 0.83512 – 34.8623

1.100 0.82374 –38.5574

1.200 0.80871 –41.9093

1.300 0.79176 – 45.6990

1.400 0.77205 –49.4185

1.500 0.75696 –52.8898

1.600 0.74234 –56.2923

1.700 0.72239 –60.2584

1.800 0.69419 –63.1446

1.900 0.67288 –65.6464

2.000 0.66227 –68.0742

2.100 0.64758 –71.3530

2.200 0.62454 –75.5658

2.300 0.59466 –79.6404

2.400 0.55932 –82.8246

2.500 0.52256 –85.2795

2.600 0.48754 –85.6298

2.700 0.46411 –86.1854

2.800 0.45776 –86.4997

2.900 0.44859 –88.8080

3.000 0.44588 –91.9737

3.100 0.43810 –95.4087

3.200 0.43269 –99.1282

FREQ MAGS11 ANGS11

3.300 0.42777 –102.748

3.400 0.42859 –107.167

3.500 0.43365 –111.883

3.600 0.43849 –117.548

3.700 0.44475 –123.856

3.800 0.44800 –130.399

3.900 0.45223 –136.744

4.000 0.45555 –142.766

4.100 0.45313 –149.269

4.200 0.45622 –154.884

4.300 0.45555 –159.680

4.400 0.46108 –164.916

4.500 0.45325 –168.452

4.600 0.45054 –173.462

4.700 0.45200 –176.697

4.800 0.45043 178.824

4.900 0.45282 174.947

5.000 0.44287 170.237

5.100 0.44909 166.617

5.200 0.44294 162.786

5.300 0.44558 158.766

5.400 0.45417 153.195

5.500 0.46038 147.721

5.600 0.47128 139.760

5.700 0.47439 132.657

5.800 0.48604 125.782

5.900 0.50637 121.110

6.000 0.52172 115.400

Figure 5. S-Parameter Data for the RF Input

5

–55°C
+25°C

0

+125°C

–5

–10

–15

–20

LEVEL (dBm)

–25

–30

–35

–40

012345678910

FREQUENCY (GHz)

Figure 6. Input Sensitivity

0

REF LEVEL = –14.3d Bm

–10

–20

–30

–40

–50

–60

–70

OUTPUT PO WER (dB)

–80

–90

–100

–2kHz –1kHz 900MHz 1kHz 2kHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWI DTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

FREQUENCY

–93.0dBc/Hz

Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)

09272-005

09272-018

09272-007

40

–50

–60

–70

–80

–90

–100

–110

OUTPUT PO WER (dB)

–120

–130

–140

100Hz 1MHz

FREQUENCY O FFSET FROM 900MHz CARRIE R

10dB/DIV

= –40dBc/Hz

R

L

RMS NOISE = 0.36°

Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVE L = –14.0dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–400kHz –200kHz 900MHz 200kHz 400kHz

V

= 3V, VP = 5V

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDW IDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

FREQUENCY

–91.0dBc/Hz

Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2kHz –1kHz 5800MHz 1kHz 2kHz

V

= 3V, VP = 5V

DD

= 5mA

I

CP

PFD FREQUE NCY = 1M Hz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–83.5dBc/Hz

FREQUENCY

Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

09272-008

09272-009

09272-010

Rev. A | Page 7 of 12

ADF4106-EP

–

–

–

–

–

70

–80

–90

–100

–110

–120

–130

LEVEL (dBm)

–140

–150

–160

–170

1k 10k 100k 1M 10M 100M

FREQUENCY OFFSET (Hz)

–55°C
+25°C
+125°C

Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

0

REF LEVE L = –10dBm

–10

–20

–30

–40

–50

–66.0dBc

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2M –1M 5800 1M 2M

V

= 3V, VP = 5V

DD

I

= 5mA

CP

PFD FREQUENCY = 1M Hz
LOOP BANDW IDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWI DTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1

FREQUENCY (Hz)

–65.0dBc

Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)

–70

–80

PHASE NOISE ( dBc/Hz)

–90

–100

60

TEMPERATURE ( °C)

VDD = 3V

= 3V

V

P

100–40 –20 0 20 40 60 80

Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature

09272-017

09272-012

09272-013

5

–15

–25

–35

–45

–55

–65

–75

–85

FIRST REF ERENCE SPUR (dBc)

–95

–105

TUNNING VOLTAGE (V)

Figure 14. Reference Spurs vs. V

(5.8 GHz,1 MHz, and 100 kHz)

TUNE

VDD = 3V

= 5V

V

P

–130

–140

–150

–160

PHASE NOISE ( dBc/Hz)

–170

–180

120

PHASE DETECTO R FREQUENCY (Hz)

VDD = 3V
V

= 5V

P

100M10k 100k 1M 10M

Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency

6
–5
–4
–3
–2
–1

0

(mA)

CP

I

1

2

3

4

5

6

V

CP

(V)

VPP = 5V
I

SETTLING = 5mA

CP

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 16. Charge Pump Output Characteristics

501234

09272-014

09272-015

09272-016

Rev. A | Page 8 of 12

ADF4106-EP

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the 20-lead LFCSP (CP-20) are rectangular. The
printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized. The
bottom of the LFCSP has a central thermal pad.

The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.

Thermal vias may be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with 1 oz. copper to plug the via.

The user should connect the PCB thermal pad to AGND.

Rev. A | Page 9 of 12

ADF4106-EP

C

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65
BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40

BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 17. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.08

0.50

BSC

0.75

0.60

0.50

0.60 MAX

15

16

10

11

20

EXPOSED

PAD

(BOTTOM VIEW)

6

FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA SHEET.

1

P

N

I

R

C

I

A

O

T

N

I

1

D

2.25

2.10 SQ

1.95

5

0.25 MIN

012508-B

INDI

ATOR

1.00

0.85

0.80

SEATING

PLANE

PIN 1

4.00

12° MAX

BSC SQ

TOP VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT

BCS SQ

TO

0.60 MAX

3.75

0.05 MAX

0.02 NOM
COPLANARITY

0.20 REF

JEDEC STANDARDS MO-220- VG GD-1

Figure 18. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADF4106-SRU-EP −55°C to + 125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4106-SRU-EP-R7 −55°C to + 125°C 16-Lead Thin Shrink Small Outline Package [TSSOP] RU-16
ADF4106-SCPZ-EP −55°C to + 125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1
ADF4106-SCPZ-EP-R7 −55°C to + 125°C 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-20-1

1

Z = RoHS Compliant Part.

Rev. A | Page 10 of 12

ADF4106-EP

NOTES

Rev. A | Page 11 of 12

ADF4106-EP

NOTES

©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09272-0-11/10(A)

Rev. A | Page 12 of 12