ANALOG DEVICES ADF4106-EP Service Manual

V

PLL Frequency Synthesizer

FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended tuning

voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

Support defense and aerospace applications (AQEC)

Military temperature range (−55°C to +125°C)

Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available upon request

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios

ADF4106-EP

GENERAL DESCRIPTION

The ADF4106-EP frequency synthesizer can be used to
implement local oscillators in the up-conversion and down­conversion sections of wireless receivers and transmitters. It
consists of a low noise, digital phase frequency detector (PFD),
a precision charge pump, a programmable reference divider,
programmable A counter and B counter, and a dual-modulus
prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in
conjunction with the dual-modulus prescaler (P/P + 1), implement
an N divider (N = BP + A). In addition, the 14-bit reference
counter (R counter) allows selectable REF
PFD input. A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). Its very high
bandwidth means that frequency doublers can be eliminated in
many high frequency systems, simplifying system architecture
and reducing cost.

Additional application and technical information can be found
in the ADF4106 data sheet.

frequencies at the

IN

DV

AV

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

24-BIT INP UT

REGISTER

SD

OUT

FUNCTION

PRESCALER

DD

FROM

LATCH

P/P + 1

CE

DD

22

N = BP + A

AGND

DGND

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13

13-BIT

B COUNTER

LOAD

LOAD

6-BIT

A COUNTER

6

19

Figure 1.

CPGND

P

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

MUX

M3 M2 M1

REFERENCE

CHARGE

PUMP

R

SET

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4106-EP

09272-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADF4106-EP

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characterisitics ............................................................... 4

REVISION HISTORY

11/10—Rev. 0 to Rev. A

Changes to Figure 6.......................................................................... 7

Changes to Figure 11........................................................................ 8

Changes to Ordering Guide.......................................................... 10

8/10—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configurations and Function Descriptions............................6

Typical Performance Characteristics..............................................7

PCB Design Guidelines for Chip Scale Package............................9

Outline Dimensions....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. A | Page 2 of 12

ADF4106-EP

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 1.

Parameter B Version1 Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Frequency (RFIN) 0.5/6.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/μs

RF Input Sensitivity −10/0 dBm min/max

Maximum Allowable Prescaler Output Frequency2 300 MHz max P = 8

325 MHz P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs

REFIN Input Sensitivity3 0.8/VDD V p-p min/max Biased at AVDD/24

REFIN Input Capacitance 10 pF max

REFIN Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency5 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP

ICP Sink/Source

High Value 5 mA typ With R
Low Value 625 μA typ
Absolute Accuracy 2.5 % typ With R
R

Range 3.0/11 kΩ typ

SET

ICP Three-State Leakage 2 nA max 1 nA typical; TA = 25°C

Sink and Source Current Matching 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. VCP 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 V min

VIL, Input Low Voltage 0.6 V max

I

, I

, Input Current ±1 μA max

INH

INL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V min Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V

V

− 0.4 V min CMOS output chosen

DD

IOH 100 μA max

VOL, Output Low Voltage 0.4 V max IOL = 500 μA

POWER SUPPLIES

AVDD 2.7/3.3 V min/V max

DVDD AVDD

VP AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5 V

6

I

(AIDD + DIDD) 11 mA max 9.0 mA typical

DD

7

I

(AIDD + DIDD) 11.5 mA max 9.5 mA typical

DD

8

I

(AIDD + DIDD) 13 mA max 10.5 mA typical

DD

IP 0.4 mA max TA = 25°C

Power-Down Mode9 (AIDD + DIDD) 10 μA typ

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

Rev. A | Page 3 of 12

ADF4106-EP

Parameter B Version1 Unit Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor (PN
Normalized 1/f Noise (PN

)11 −122 dBc/Hz typ Measured at 10 kHz offset; normalized to 1 GHz

1_f

Phase Noise Performance12 VCO output

900 MHz13 −92.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz14 −76.5 dBc/Hz typ 1 kHz offset and 200 kHz PFD frequency
5800 MHz15 −83.5 dBc/Hz typ 1 kHz offset and 1 MHz PFD frequency

Spurious Signals

900 MHz13 −90/−92 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz14 −65/−70 dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz15 −70/−75 dBc typ 1 MHz/2 MHz and 1 MHz PFD frequency

1

Operating temperature range is −55°C to +125°C.

2

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

3

AVDD = DVDD = 3 V.

4

AC coupling ensures AVDD/2 bias.

5

Guaranteed by design. Sample tested to ensure compliance.

6

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.

8

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.

9

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.

10

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F

11

The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a
frequency offset, f, is given by PN = P

12

The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

f

= 10 MHz; f

REFIN

. PN

= PN

PFD

SYNTH

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.

PFD

= 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz.

PFD

= 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz.

PFD

− 10 log F

TOT

1_f

TIMING CHARACTERISITICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

)10 −223 dBc/Hz typ PLL loop BW = 500 kHz

SYNTH

− 20 log N.

PFD

+ 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MAX

to T

MIN

,

Table 2.

Parameter Limit1 (B Version) Unit Test Conditions/Comments

t1 10 ns min DATA to CLOCK Setup Time
t2 10 ns min DATA to CLOCK Hold Time
t3 25 ns min CLOCK High Duration
t4 25 ns min CLOCK Low Duration
t5 10 ns min CLOCK to LE Setup Time
t6 20 ns min LE Pulse Width

1

Operating temperature range (B Version) is –40°C to +85°C.

Timing Diagram

t

t

3

4

CLOCK

DB23 (MSB)

DATA

LE

LE

t

t

1

2

DB22

DB2

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

09272-002

Rev. A | Page 4 of 12