Datasheet ADF4106BRU, ADF4106BCP Datasheet (Analog Devices)

a

PLL Frequency Synthesizer

ADF4106

FEATURES

6.0 GHz Bandwidth

2.7 V to 3.3 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 3 V Systems

Programmable Dual Modulus Prescaler

8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
Programmable Anti-Backlash Pulsewidth
3-Wire Serial Interface
Analog and Digital Lock Detect
Hardware and Software Power-Down Mode

APPLICATIONS
Broadband Wireless Access
Instrumentation
Wireless LANS
Base Stations For Wireless Radio

FUNCTIONAL BLOCK DIAGRAM

AV

DV

DD

DD

REF

IN

14-BIT

R COUNTER

14

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low-noise digital PFD (Phase Frequency Detector), a precision
charge pump, a programmable reference divider, programmable
A and B counters and a dual-modulus prescaler (P/P + 1). The
A (6-bit) and B (13-bit) counters, in conjunction with the dual
modulus prescaler (P/P + 1), implement an N divider (N = BP + A).
In addition, the 14-bit reference counter (R Counter), allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthe­sizer is used with an external loop filter and VCO (Voltage
Controlled Oscillator). Its very high bandwidth means that
frequency doublers can be eliminated in many high-frequency
systems, simplifying system architecture and lowering cost.

V

P

PHASE

FREQUENCY

DETECTOR

CPGND

REFERENCE

CHARGE

PUMP

R

SET

CP

R COUNTER

LATCH

CLK

DATA

LE

RFINA

RF

B

IN

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

24-BIT INPUT

REGISTER

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

FUNCTION

LATCH

AB COUNTER

LATCH

B COUNTER

LOAD

LOAD

A COUNTER

DGND

13

13-BIT

6-BIT

LOCK

DETECT

19

CURRENT

SETTING 1

CPI3 CPI2 CPI1 CPI6 CPI5 CPI4

AV

SD

DD

OUT

MUX

M3 M2 M1

CURRENT

SETTING 2

HIGH Z

MUXOUT

ADF4106

6

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

ADF4106–SPECIFICATIONS

(AV

= DVDD = 3 V  10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V;

DD

1

R

= 5.1 k; dBm referred to 50 ; TA = T

SET

MIN

to T

unless otherwise noted.)

MAX

Parameter B Version

RF CHARACTERISTICS See Figure 3 for Input Circuit

RF Input Frequency (RF

3

)

IN

0.5/6.0 0.5/6.0 GHz min/max

1

BChips
(typ) Unit Test Conditions/Comments

2

RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable
Prescaler Output Frequency

4

300 300 MHz max

REFIN CHARACTERISTICS

REFIN Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, Use DC-Coupled

REFIN Input Sensitivity

5

0.8/AV

DD

0.8/AV

V p-p min/max AC-Coupled; When DC-Coupled,

DD

Square Wave, (0 to V

0 to V

max (CMOS Compatible)

DD

DD

)

REFIN Input Capacitance 10 10 pF max
REFIN Input Current ± 100 ±100 µA max

PHASE DETECTOR

Phase Detector Frequency

6

56 56 MHz max

CHARGE PUMP

ICP Sink/Source Programmable, See Table V

High Value 5 5 mA typ With R

= 5.1 kΩ

SET

Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With R

Range 2.7/10 2.7/10 kΩ typ See Table V

R

SET

I

Three-State Leakage Current 1 1 nA typ

CP

Sink and Source Current Matching 2 2 % typ 0.5 V ⱕ V
I

CP

vs. V

CP

1.5 1.5 % typ 0.5 V ⱕ VCP ⱕ VP – 0.5 V

= 5.1 kΩ

SET

ⱕ VP – 0.5 V

CP

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 1.4 1.4 V min

INH

, Input Low Voltage 0.6 0.6 V max

V

INL

I

, Input Current ± 1 ± 1 µA max

INH/IINL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min Open Drain Output Chosen 1 kΩ

Pull-up to 1.8 V

, Output High Voltage 1.4 1.4 V min CMOS Output Chosen

V

OH

I

OH

100 100 µA max

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV

DD

DV

DD

V

P

7

(AIDD + DIDD) 15 13 mA max 13 mA typ

I

DD

I

P

2.7/3.3 2.7/3.3 V min/V max
AV

DD

AV

DD

AVDD/5.5 AVDD/5.5 V min/V max AVDD ⱕ VP ⱕ 5.5 V

0.4 0.4 mA max TA = 25°C

Power-Down Mode8 (AIDD + DIDD)10 10 µA typ

–2–

REV. 0

ADF4106

BChips

2

Parameter B Version1(typ) Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Phase Noise Floor

9

–174 –174 dBc/Hz typ @ 25 kHz PFD Frequency
–166 –166 dBc/Hz typ @ 200 kHz PFD Frequency

Phase Noise Performance

900 MHz Output
5800 MHz Output
5800 MHz Output

Spurious Signals

900 MHz Output
5800 MHz Output
5800 MHz Output

NOTES

1

Operating temperature range (B Version) is –40°C to +85°C.

2

The BChip specifications are given as typical values.

3

Use a square wave for lower frequencies, below the mimimum stated.

4

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency

that is less than this value.

5

AVDD = DVDD = 3 V

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 6.0 GHz

8

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz

9

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).

10

The phase noise is measured with the EVAL-ADF4106EB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer (f

11

f

= 10 MHz; f

REFIN

12

f

= 10 MHz; f

REFIN

13

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz

PFD

= 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz

PFD

= 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz

PFD

10

11

12

13

11

12

13

= 10 MHz @ 0 dBm).

–159 –159 dBc/Hz typ @ 1 MHz PFD Frequency

@ VCO Output

–93 –93 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–74 –74 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency
–84 –84 dBc/Hz typ @ 1 kHz Offset and 1 MHz PFD Frequency

–90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
–65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency
–70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD Frequency

(AV

TIMING CHARACTERISTICS

= DVDD = 3 V  10%; AVDD ≤ VP ≤ 5.5 V; AGND = DGND = CPGND = 0 V; R

DD

TA = T

MIN

to T

unless otherwise noted.)

MAX

= 5.1 k;

SET

Limit at

to T

T

MIN

MAX

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

Guaranteed by design but not production tested.

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

t

t

3

4

CLOCK

DATA

LE

LE

DB23 (MSB)

t

t

2

1

DB22

DB2

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

REV. 0

Figure 1. Timing Diagram

–3–

ADF4106

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted.)

1, 2

AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +3.6 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.3 V

V

P

V

to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB to GND . . . . . . –0.3 V to VDD + 0.3 V

IN

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C

TSSOP ␪
CSP ␪

Thermal Impedance . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance . . . . . . . . . . . . . . . . . . 122°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

<2 kV and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.

3

GND = AGND = DGND = 0 V

ORDERING GUIDE

Model Temperature Range Package Option*

ADF4106BRU –40°C to +85°C RU-16
ADF4106BCP –40°C to +85°C CP-20

*RU = Thin Shrink Small Outline Package (TSSOP)

CP = Chip Scale Package
Contact the factory for chip availability.
Note that aluminum bond wire should not be used with the ADF4106 die.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADF4106 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–4–

REV. 0

PIN CONFIGURATIONS

ADF4106

R

SET

CP

CPGND

AGND

RF

IN

RF

IN

AV

REF

B

A

DD

IN

TSSOP

1

2

3

ADF4106

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

V

15

DV

14

MUXOUT

13

LE

12

DATA

11

CLK

10

CE

9

DGND

P

DD

NOTE: TRANSISTOR COUNT 6425 (CMOS), 303 (BIPOLAR)

Chip Scale Package

SET

20 CP

19 R

CPGND 1

AGND 2
AGND 3
RFINB 4

A 5

RF

IN

PIN 1
INDICATOR

ADF4106

TOP VIEW

6

7

DD

DD

AV

AV

18 VP17 DVDD16 DV

8

IN

REF

DGND 9

DD

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

DGND 10

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

R

SET

CP Charge Pump Output. When enabled this provides ±I

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal
voltage potential at the R

So, with R

= 5.1 kΩ, I

SET

pin is 0.6 V. The relationship between ICP and R

SET

25 5.

=

R

SET

to the external loop filter, which in turn drives the

CP

CPMAX

= 5 mA.

I

CP MAX

SET

is

external VCO.
CPGND Charge Pump Ground. This is the ground return path for the charge pump.
AGND Analog Ground. This is the ground return path of the prescaler.
RF

B Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with a small bypass

IN

capacitor, typically 100 pF. See Figure 3.
RF

A Input to the RF Prescaler. This small signal input is ac coupled to the external VCO.

IN

AV

REF

DD

IN

Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane

should be placed as close as possible to this pin. AV

must be the same value as DVDD.

DD

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of

100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac coupled.
DGND Digital Ground
CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state

mode. Taking the pin high will power up the device depending on the status of the power-down bit F2.
CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the

24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a

high impedance CMOS input.
LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, the latch being selected using the control bits.
MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF or the scaled Reference Frequency to be

accessed externally.
DV

V

P

DD

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be

set to 5 V and used to drive a VCO with a tuning range of up to 5 V.

REV. 0

–5–

ADF4106–Typical Performance Characteristics

FREQ UNIT – GHz
PARAM TYPE – S
DATA FORMAT – MA

FREQ MAGS11 ANGS11

0.500 0.89148 – 17.2820

0.600 0.88133 – 20.6919

0.700 0.87152 – 24.5386

0.800 0.85855 – 27.3228

0.900 0.84911 – 31.0698

1.000 0.83512 – 34.8623

1.100 0.82374 – 38.5574

1.200 0.80871 – 41.9093

1.300 0.79176 – 45.6990

1.400 0.77205 – 49.4185

1.500 0.75696 – 52.8898

1.600 0.74234 – 56.2923

1.700 0.72239 – 60.2584

1.800 0.69419 – 63.1446

1.900 0.67288 – 65.6464

2.000 0.66227 – 68.0742

2.100 0.64758 – 71.3530

2.200 0.62454 – 75.5658

2.300 0.59466 – 79.6404

2.400 0.55932 – 82.8246

2.500 0.52256 – 85.2795

2.600 0.48754 – 85.6298

2.700 0.46411 – 86.1854

2.800 0.45776 – 86.4997

2.900 0.44859 – 88.8080

3.000 0.44588 – 91.9737

3.100 0.43810 – 95.4087

3.200 0.43269 – 99.1282

KEYWORD – R
IMPEDANCE  – 50

FREQ MAGS11 ANGS11

3.300 0.42777 – 102.748

3.400 0.42859 – 107.167

3.500 0.43365 – 111.883

3.600 0.43849 – 117.548

3.700 0.44475 – 123.856

3.800 0.44800 – 130.399

3.900 0.45223 – 136.744

4.000 0.45555 – 142.766

4.100 0.45313 – 149.269

4.200 0.45622 – 154.884

4.300 0.45555 – 159.680

4.400 0.46108 – 164.916

4.500 0.45325 – 168.452

4.600 0.45054 – 173.462

4.700 0.45200 – 176.697

4.800 0.45043 178.824

4.900 0.45282 174.947

5.000 0.44287 170.237

5.100 0.44909 166.617

5.200 0.44294 162.786

5.300 0.44558 158.766

5.400 0.45417 153.195

5.500 0.46038 147.721

5.600 0.47128 139.760

5.700 0.47439 132.657

5.800 0.48604 125.782

5.900 0.50637 121.110

6.000 0.52172 115.400

TPC 1. S-Parameter Data for the RF Input

0

–5

–10

–15

OUTPUT POWER – dB

–20

–25

TA = +25C

TA = +85C

TA = –40C

–30

01

246

3

5

RF INPUT FREQUENCY – GHz

TPC 2. Input Sensitivity

VDD = 3V
V

= 3V

P

–40

–50

–60

10dB/DIV
RL = –40dBc/Hz

RMS NOISE = 0.36

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

TPC 4. Integrated Phase Noise (900 MHz,
200 kHz, and 20 kHz)

0

REF LEVEL = –14.0dBm

–10

–20

–30

–40

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

–50

–60

–70

OUTPUT POWER – dB

–80

–91.0dBc/Hz

–90

–100

–400kHz

400kHz900MHz–200kHz 200kHz

FREQUENCY

TPC 5. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –14.3dBm

–10

–20

–30

–40

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–50

–60

OUTPUT POWER – dB

–70

–93.0dBc/Hz

–80

–90

–100

–2kHz

2kHz900MHz–1kHz 1kHz

FREQUENCY

TPC 3. Phase Noise (900 MHz, 200 kHz, and 20 kHz)

–6–

0

REF LEVEL = –10dBm

–10

–20

–30

–40

VDD = 3V, VP = 5V
I

= 5mA

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–50

–60

–70

OUTPUT POWER – dB

–80

–84.0dBc/Hz

–90

–100

–2kHz

2kHz5800MHz–1kHz 1kHz

FREQUENCY

TPC 6. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz)

REV. 0

ADF4106

TUNING VOLTAGE – V

–5

–15

–105

051234

–45

–75

–85

–95

–25

–35

–65

–55

FIRST REFERENCE SPUR – dBc

VDD = 3V
V

P

= 5V

PHASE DETECTOR FREQUENCY – Hz

–120

–130

–180

10 100k100

OUTPUT POWER – dBc/Hz

1k 10k

–140

–150

–160

–170

V

DD

= 3V

V

P

= 5V

PRESCALER VALUE

10

9

0

8/9 64/6516/17

AI

DD

– mA

32/33

4

3

2

1

6

5

8

7

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 5800MHz CARRIER

10dB/DIV

= –40dBc/Hz

R

L

RMS NOISE = 1.8

TPC 7. Integrated Phase Noise (5.8 GHz, 1 MHz, and
100 kHz)

0

REF LEVEL = –10.0dBm

–10

–20

–30

–40

–50

–60

OUTPUT POWER – dB

–70

–80

–90

–100

–2MHz

–66.0dBc

–1MHz 5800MHz 1MHz 2MHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PDF FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1

FREQUENCY

–65.0dBc

TPC 8. Reference Spurs (5.8 GHz, 1 MHz, and 100 kHz)

TPC 10. Reference Spurs vs. V

(5.8 GHz, 1 MHz, and

TUNE

100 kHz)

TPC 11. Phase Noise (referred to CP output) vs.
PFD Frequency

–60

–70

–80

PHASE NOISE – dBc/Hz

TPC 9. Phase Noise (5.8 GHz, 1 MHz, and 100 kHz) vs.
Temperature

REV. 0

–90

–100

–40 100–20

020406080

TEMPERATURE – C

VDD = 3V
VP = 5V

TPC 12. AIDD vs. Prescaler Value

–7–

ADF4106

3.5
VDD = 3V

= 3V

V

P

3.0

2.5

2.0

– mA

DD

1.5

DI

1.0

0.5

0

50 300100

150 200 250

PRESCALER OUTPUT FREQUENCY

TPC 13. DIDD vs. Prescaler Output Frequency

CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION

The Reference Input stage is shown in Figure 2. SW1 and SW2
are normally-closed switches. SW3 is normally-open. When
Powerdown is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

100k

NC

REF

SW2

IN

NC

SW1

NO

SW3

BUFFER

NC = NO CONNECT

TO R COUNTER

Figure 2. Reference Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 3. It is followed by a 2-stage
limiting amplifier to generate the CML clock levels needed for the
prescaler.

500

1.6V

500

AV

DD

RF

RF

BIAS

GENERATOR

A

IN

B

IN

6

– mA

CP

I

–2

–4

–6

4

2

0

0 5.00.5

1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
VCP – V

VP = 5V
I

= 5mA

CP

TPC 14. Charge Pump Output Characteristics

PRESCALER (P/P + 1)

The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A and B
counters. The prescaler is programmable. It can be set in soft­ware to 8/9, 16/17, 32/33 or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value and is given by: (P

2

– P).

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL feed­back counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:

f

REFIN

R

f

VCO

fPBA

=×+×[( ) ]

VCO

Output Frequency of external voltage controlled
oscillator (VCO).

P Preset modulus of dual modulus prescaler

(8/9, 16/17, etc.,).

B Preset Divide Ratio of binary 13-bit counter

(3 to 8191).

A Preset Divide Ratio of binary 6-bit swallow

counter (0 to 63).

f

REFIN

External reference frequency oscillator.

Figure 3. RF Input Stage

AGND

–8–

REV. 0

ADF4106

N = BP + A

TO PFD

FROM RF

INPUT STAGE

PRESCALER

MODULUS
CONTROL

N DIVIDER

P/P + 1

13-BIT B

COUNTER

LOAD

LOAD

6-BIT A

COUNTER

Figure 4. A and B Counters

R COUNTER

The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP

The PFD takes inputs from the R counter and N counter (N =
BP + A) and produces an output proportional to the phase and
frequency difference between them. Figure 5 is a simplified
schematic. The PFD includes a programmable delay element
which controls the width of the anti-backlash pulse. This pulse
ensures that there is no deadzone in the PFD transfer function
and minimizes phase noise and reference spurs. Two bits in the
Reference Counter Latch, ABP2 and ABP1 control the width of
the pulse. See Table III.

V

P

CHARGE

PUMP

R DIVIDER

HIHID1

U1

CLR1

Q1

UP

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4110 family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than
15 ns. With LDP set to “1,” five consecutive cycles of less than
15 ns are required to set the lock detect. It will stay set high
until a phase error of greater than 25 ns is detected on any sub­sequent PD cycle.

The N-channel open-drain analog lock detect should be oper­ated with an external pull-up resistor of 10 k⍀ nominal. When
lock has been detected this output will be high with narrow low­going pulses.

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

CONTROL

MUXOUT

DGND

Figure 6. MUXOUT Circuit

N DIVIDER

R DIVIDER

N DIVIDER

CP OUTPUT

D2

CLR2

U2

Q2

PROGRAMMABLE

DELAY

ABP2

ABP1

DOWN

U3

CPGND

CP

Figure 5. PFD Simplified Schematic and Timing (In Lock)

REV. 0

INPUT SHIFT REGISTER

The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destina­tion latch is determined by the state of the two control bits
(C2, C1) in the shift register. These are the two LSBs, DB1 and
DB0, as shown in the timing diagram of Figure 1. The truth table
for these bits is shown in Table VI. Table I shows a summary
of how the latches are programmed.

Table I. C2, C1 Truth Table

Control Bits
C2 C1 Data Latch

0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch

–9–

ADF4106

Table II. Latch Summary

REFERENCE COUNTER LATCH

RESERVED

X

00

RESERVED

DB22DB23

PRESCALER

VALU E

DB22DB23

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CP GAIN

DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11

DB20

DB21

G1

CURRENT

SETTING

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21

DOWN 2

POWER-

ANTI-

BACKLASH

WIDTH

ABP1ABP2T1T2LDP

CURRENT

SETTING

CPI3CPI4

R14

13-BIT B COUNTER

1

N COUNTER LATCH

FUNCTION LATCH

TIMER COUNTER

CONTROL

TC3 TC2 TC1

14-BIT REFERENCE COUNTER

DB10 DB9 DB8

MODE

ENABLE

FASTLOCK

FASTLOCK

F4F5

DB7 DB6

PD

STATE

CP THREE-

POLARITY

6-BIT A COUNTER

DB5 DB4 DB3 DB2 DB1 DB0

MUXOUT

CONTROL

DOWN 1

POWER-

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13

C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

RESET

COUNTER

C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

CONTROL

BITS

CONTROL

BITS

PRESCALER

VALU E

DB22DB23

P1P2

INITIALIZATION LATCH

CURRENT

SETTING

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI5

CPI6

CPI4

DB21

DOWN 2

POWER-

CPI3

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

TC4PD2

CPI1CPI2

TC3 TC2 TC1

MODE

FASTLOCK

F5

ENABLE

FASTLOCK

F4

STATE

CP THREE-

F3

F2

PD

POLARITY

MUXOUT

CONTROL

M2M3

DOWN 1

POWER-

F1PD1M1

–10–

CONTROL

RESET

COUNTER

C2 (1) C1 (1)

BITS

REV. 0

Table III. Reference Counter Latch Map

ADF4106

RESERVED

X

X

= DON’T CARE

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

0

0

ANTI-

BACKLASH

WIDTH

ABP1

ABP2T1T2LDP

R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO

0 0 0 .......... 0011

0 0 0 .......... 0102

0 0 0 .......... 0113

0 0 0 .......... 1004

. . . .......... ....

. . . .......... ....

. . . .......... ....

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

ABP2 ABP1 ANTIBACKLASH PULSEWIDTH
0 0 2.9ns
0 1 1.3ns
1 0 6.0ns
1 1 2.9ns

14-BIT REFERENCE COUNTER

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14

LDP OPERATION
0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION

TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL

OPERATION

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

REV. 0

–11–

ADF4106

Table IV. AB Counter Latch Map

RESERVED

DB22DB23

XX

13-BIT B COUNTER

6-BIT A COUNTER

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21

G1

X = DON’T CARE

A6 A5 .......... A2 A1 DIVIDE RATIO

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

0 0 0 .......... 0 0 0 NOT ALLOWED

0 0 0 .......... 0 0 1 NOT ALLOWED

0 0 0 .......... 0 1 0 NOT ALLOWED

0 0 0 .......... 1 1 1 3

. . . .......... . . . .

. . . .......... . . . .

. . . .......... . . . .

1 1 1 .......... 1 0 0 8188

1 1 1 .......... 1 0 1 8189

1 1 1 .......... 1 1 0 8190

1 1 1 .......... 1 1 1 8191

A COUNTER

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

CONTROL

BITS

C2 (0) C1 (1)

F4 (FUNCTION LATCH)

FASTLOCK ENABLE CP GAIN OPERATION
0 0 CHARGE PUMP CURRENT SETTING

0 1 CHARGE PUMP CURRENT SETTING

1 0 CHARGE PUMP CURRENT SETTING

1 1 CHARGE PUMP CURRENT IS

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.

1 IS PERMANENTLY USED

2 IS PERMANENTLY USED

1 IS USED

SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION

–12–

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION LATCH.
B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY
ADJACENT VALUES OF (N  F

), AT THE OUTPUT, N

REF

IS (P2 - P)

MIN

REV. 0

Table V. Function Latch Map

ADF4106

PRESCALER

VALU E

DB22DB23

P1P2

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI5

CPI6

CPI4

CURRENT

SETTING

1

CPI3

CPI1CPI2

TC4 TC3 TC2 TC1 (PFD CYCLES)
00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2

MODE

FASTLOCK

F4

F5

F4

0
1
1

TIMEOUT

ENABLE

FASTLOCK

F3

0
1

F5
X
0
1

POLARITY

F3

F2

PHASE DETECTOR

F2

POLARITY

0

NEGATIVE

1

POSITIVE

CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE

FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2

M3 M2 M1
000
001

010
011DV

100
101

110
111

PD

CP

STATE

THREE-

MUXOUT

CONTROL

M2M3

DOWN 1

POWER-

F1
0
1

COUNTER

F1PD1M1

CONTROL

BITS

RESET

C2 (1) C1 (0)

COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET

OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV

DD

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND

CPI6 CPI5 CP14 I

CPI3 CPI2 CPI1 3k 5.1k 11k
0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN PD2 PD1 MODE
0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
101ASYNCHRONOUS POWER-DOWN
111SYNCHRONOUS POWER-DOWN

P2 P1 PRESCALER VALUE

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

REV. 0

(mA)

CP

–13–

ADF4106

Table VI. Initialization Latch Map

PRESCALER

VALU E

DB22DB23

P1P2

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI5

CPI6

CPI4

CURRENT

SETTING

1

CPI3

CPI1CPI2

TC4 TC3 TC2 TC1 (PFD CYCLES)
00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TC4PD2

MODE

FASTLOCK

F4

F5

F4
0
1
1

TIMEOUT

ENABLE

FASTLOCK

F3

0
1

F5
X
0
1

POLARITY

F3

F2

PHASE DETECTOR

F2

POLARITY

0

NEGATIVE

1

POSITIVE

CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE

FASTLOCK MODE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2

M3 M2 M1
000
001

010
011DV

100
101

110
111

PD

CP

STATE

THREE-

MUXOUT

CONTROL

M2M3

DOWN 1

POWER-

F1
0
1

COUNTER

F1PD1M1

CONTROL

BITS

RESET

C2 (1) C1 (1)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS
HELD IN RESET

OUTPUT
THREE-STATE OUTPUT

DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV

DD

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN

LOCK DETECT

SERIAL DATA OUTPUT
DGND

CPI6 CPI5 CP14 I

CPI3 CPI2 CPI1 3k 5.1k 11k

0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
101ASYNCHRONOUS POWER-DOWN
111SYNCHRONOUS POWER-DOWN

P2 P1 PRESCALER VALUE

0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65

(mA)

CP

–14–

REV. 0

ADF4106

THE FUNCTION LATCH

With C2, C1 set to 1,0, the on-chip function latch will be
programmed. Table V shows the input data format for program­ming the Function Latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A,B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled

(set to “0”). The N counter then resumes counting in “close” align­ment with the R counter. (The maximum error is one prescaler cycle).

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide
programmable power-down modes. They are enabled by the CE
pin. When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1. In the programmed asyn­chronous power-down, the device powers down immediately
after latching a “1” into bit PD1, with the condition that PD2
has been loaded with a “0.” In the programmed synchronous
power-down, the device power down is gated by the charge
pump to prevent unwanted frequency jumps. Once the power­down is enabled by writing a “1” into bit PD1 (on condition
that a “1” has also been loaded to PD2), then the device will go
into power-down on the occurrence of the next charge pump
event. When a power down is activated (either synchronous or
asynchronous mode including CE-pin-activated power down),
the following events occur:

All active dc current paths are removed.
The R, N, and timeout counters are forced to their load state
conditions.
The charge pump is forced into three-state mode.
The digital clock detect circuitry is reset.
The RF

input is debiased.

IN

The reference input buffer circuitry is disabled.
The input register remains active and capable of loading and
latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4110 Family. Table V shows the truth table.

Fastlock Enable Bit

DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.

Fastlock Mode Bit

DB10 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0,” Fastlock Mode 1 is
selected and if the Fastlock Mode bit is “1,” Fastlock Mode 2 is
selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock by having a “0” written to the CP Gain bit in the AB
counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current
Setting 2. The device enters Fastlock by having a “1” written to
the CP Gain bit in the AB counter latch. The device exits
Fastlock under the control of the Timer Counter. After the
timeout period determined by the value in TC4–TC1, the CP
Gain bit in the AB counter latch is automatically reset to “0”
and the device reverts to normal mode instead of Fastlock. See
Table V for the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump cur­rents. The intent is that the Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and in a
state of change (i.e., when a new output frequency is programmed).
The normal sequence of events is as follows:

Users initially decide what the preferred charge pump currents
are will be. For example, they may choose 2.5 mA as Current
Setting 1 and 5 mA as the Current Setting 2. At the same time
they must also decide how long they want the secondary cur­rent to stay active before reverting to the primary current. This
is controlled by the Timer Counter Control Bits DB14 to
DB11 (TC4–TC1) in the Function Latch. The truth table is
given in Table V.

Now, when users wish to program a new output frequency, they
can simply program the AB counter latch with new values for A
and B. At the same time they can set the CP Gain bit to a “1,”
which sets the charge pump with the value in CPI6–CPI4 for a
period of time determined by TC4–TC1. When this time is up,
the charge pump current reverts to the value set by CPI3–CPI1.
At the same time the CP Gain bit in the A, B Counter latch is
reset to 0 and is now ready for the next time that the user wishes
to change the frequency again.

Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”

Charge Pump Currents

CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.

Prescaler Value

P2 and P1 in the Function Latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 300 MHz. Thus, with
an RF frequency of 4 GHz, a prescaler value of 16/17 is valid
but a value of 8/9 is not valid.

PD Polarity

This bit sets the Phase Detector Polarity Bit. See Table V.

CP Three-State

This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.

REV. 0

–15–

ADF4106

THE INITIALIZATION LATCH

When C2, C1 = 1, 1, the Initialization Latch is programmed. This is
essentially the same as the Function Latch (programmed when
C2, C1 = 1, 0).

However, when the Initialization Latch is programmed there is
an additional internal reset pulse applied to the R and AB
counters. This pulse ensures that the AB counter is at load point
when the AB counter data is latched and the device will begin
counting in close phase alignment.

If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this powerdown. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse
and so close phase alignment is maintained when counting resumes.

When the first AB counter data is latched after initialization, the
internal reset pulse is again activated. However, successive AB
counter loads after this will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After initially powering up the device, there are three ways to
program the device.

Initialization Latch Method

• Apply VDD.

• Program the Initialization Latch (“11” in two LSBs of input

word). Make sure that F1 bit is programmed to “0.”

• Do a Function Latch load (“10” in two LSBs of the control
word), making sure that the F1 bit is programmed to a “0.”

• Do an R load (“00” in two LSBs).

• Do an AB load (“01” in two LSBs).

When the Initialization Latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, A, B and timeout counters to

load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allow­ing close phase alignment when counting resumes.

3. Latching the first AB counter data after the initialization

word will activate the same internal reset pulse. Successive
AB loads will not trigger the internal reset pulse unless there
is another initialization.

CE Pin Method

• Apply VDD.

• Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

• Program the Function Latch (10).

• Program the R Counter Latch (00).

• Program the AB Counter Latch (01).

• Bring CE high to take the device out of power-down.

The R and AB counters will now resume counting in close
alignment. Note that after CE goes high, a duration of 1 µs may
be required for the prescaler bandgap voltage and oscillator
input buffer bias to reach steady state.

CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V

DD

was

initially applied.

Counter Reset Method

• Apply VDD.

• Do a Function Latch Load (“10” in two LSBs). As part of

this, load “1” to the F1 bit. This enables the counter reset.

• Do an R Counter Load (“00” in two LSBs).

• Do an AB Counter Load (“01” in two LSBs).

• Do a Function Latch Load (“10” in two LSBs). As part of

this, load “0” to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initial­ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down.

APPLICATION SECTION
Local Oscillator for LMDS Base Station Transmitter

Figure 7 shows the ADF4106 being used with a VCO to pro­duce the LO for an LMDS base station operation in the

5.4 GHz to 5.8 GHz band.

The reference input signal is applied to the circuit at FREF

IN

and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
Reference Input without any 50 Ω termination.

In order to have a channel spacing of 1 MHz at the output, the
10 MHz reference input must be divided by 10, using the on-chip
reference divider of the ADF4106.

The charge pump output of the ADF4106 (Pin 2) drives the
loop filter. In calculating the loop filter component values, a
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for the
system would be 45 degrees. Other PLL system specifications
are given below:

K

= 2.5 mA

D

K

= 80 MHz/V

V

Loop Bandwidth = 50 kHz

= 1 MHz

F

REF

N = 5800
Extra Reference Spur Attenuation = 10 dB

All of these specifications are needed and used to come up with
the loop filter component values shown in Figure 7.

Figure 7 gives a typical phase noise performance of –83 dBc/Hz
at 1 kHz offset from the carrier. Spurs are better than –62 dBc.

The loop filter output drives the VCO, which, in turn, is fed
back to the RF input of the PLL synthesizer and also drives the
RF Output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output and the
RF

terminal of the synthesizer. Note that the ADF4106 RF

IN

input looks like 50 Ω at 5.8 GHz and so no terminating resistor
is needed. When operating at lower frequencies however, this is
not the case.

In a PLL system, it is important to know when the system is in
lock. In Figure 7, this is accomplished by using the MUXOUT
signal from the synthesizer. The MUXOUT pin can be pro­grammed to monitor various internal signals in the synthesizer.
One of these is the LD or lock-detect signal.

–16–

REV. 0

ADF4106

FREF

1000pF

IN

SPI COMPATIBLE SERIAL BUS

1000pF

51

5.1k

V

DD

AV

DD

REFIN

ADF4106

CE

CLK

DATA

LE

R

SET

CPGND

DV

DD

MUXOUT

RF

RF

AGND

DGND

V

P

RF

OUT

100pF

18

18

18

V

P

CP

100pF

LOCK
DETECT

100pF

A

IN

B

IN

100pF

6.2k

4.3k

1.5nF

NOTE
DECOUPLING CAPACITORS (0.1

VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE
BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

20pF

V

CC

V940ME03

1, 3, 4, 5, 7, 8,
9, 11, 12, 13



F/10pF) ON AVDD, DVDD,

100pF

Figure 7. Local Oscillator for LMDS Base Station

INTERFACING

The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. SCLK, SDATA and LE control the data
transfer. When LE (Latch Enable) goes high, the 24 bits which
have been clocked into the input register on each rising edge of
SCLK will get transferred to the appropriate latch. See Figure 1
for the Timing Diagram and Table I for the Latch Truth Table.

The maximum allowable serial clock rate is 20 MHz. This means
that the maximum update rate possible for the device is 833 kHz
or one update every 1.2 µs. This is certainly more than adequate
for systems which will have typical lock times in hundreds of
microseconds.

ADuC812 Interface

Figure 8 shows the interface between the ADF4106 and the
ADuC812 microconverter. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the microconverter to the device. When the third byte has
been written the LE input should be brought high to complete
the transfer.

REV. 0

–17–

ADF4106

On first applying power to the ADF4106, it needs at three writes
(one each to the R counter latch, the N counter latch and the
function latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control
power-down (CE input) and to detect lock (MUXOUT config­ured as lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maximum
rate at which the output frequency can be changed will be 166 kHz.

SCLOCK

MOSI

ADuC812

I/O PORTS

SCLK

SDATA

LE

ADF4106

CE

MUXOUT
(LOCK DETECT)

Figure 8. ADuC812 to ADF4106 Interface

ADSP-2181 Interface

Figure 9 shows the interface between the ADF4106 and the
ADSP-21xx Digital Signal Processor. The ADF4106 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate Framing.
This provides a means for transmitting an entire block of serial
data before an interrupt is generated. Set up the word length for
8 bits and use three memory locations for each 24-bit word. To
program each 24-bit latch, store the three 8-bit bytes, enable the
Autobuffered mode and then write to the transmit register of the
DSP. This last operation initiates the autobuffer transfer.

SCLK

SDATA

LE

ADF4106

CE

MUXOUT
(LOCK DETECT)

ADSP-21xx

I/O FLAGS

SCLOCK

MOSI

TFS

Figure 9. ADSP-21xx to ADF4106 Interface

–18–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Thin Shrink SO Package (TSSOP)

(RU-16)

0.201 (5.10)

0.193 (4.90)

ADF4106

SEATING

PIN 1

INDICATOR

0.035 (0.90) MAX

0.033 (0.85) NOM

SEATING

PLANE

PIN 1

0.006 (0.15)

0.002 (0.05)

PLANE

16

0.0256 (0.65)
BSC

9

0.177 (4.50)

0.169 (4.30)

81

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8
0

0.028 (0.70)

0.020 (0.50)

20-Leadless Frame Chip Scale Package (LFCSP)

(CP-20)

0.024 (0.60)

0.157 (4.0)
BSC SQ

TOP

VIEW

12 MAX

0.020 (0.50)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

0.148 (3.75)
BSC SQ

0.031 (0.80) MAX

0.026 (0.65) NOM

0.008 (0.20)
REF

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.030 (0.75)

0.022 (0.60)

0.014 (0.50)

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

0.017 (0.42)

0.009 (0.24)

16

15

BOTTOM

VIEW

11

10

0.080 (2.00)
REF

0.010 (0.25)
MIN

20

1

5

6

0.080 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

REV. 0

–19–

C02720–.8–10/01(0)

–20–

PRINTED IN U.S.A.