ANALOG DEVICES ADF4106 Service Manual

www.BDTIC.com/ADI

PLL Frequency Synthesizer

FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended

tuning voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios

FUNCTIONAL BLOCK DIAGRAM

DV

AV

DD

DD

ADF4106

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P +

1). The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REF
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.

V

CPGND

P

frequencies at the PFD

IN

R

SET

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

24-BIT INPUT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

A COUNTER

DGND

13

6-BIT

6

19

Figure 1.

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

AV

SD

CURRENT

SETTING 1

CPI3 CPI2 CPI1

DD

OUT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4106

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

02720-001

ADF4106

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Phase Frequency Detector (PFD) and Charge Pump............ 10

Timing Characterisitics ............................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

General Description......................................................................... 9

Reference Input Section............................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P +1)......................................................................... 9

A Counter and B Counter........................................................... 9

R Counter ...................................................................................... 9

REVISION HISTORY

6/05—Rev A to Rev. B

Updated Format..................................................................Universal

Changes to Figure 1.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Figure 3 and Figure 4................................................... 6

Changes to Figure 6.......................................................................... 7

Changes to Figure 10........................................................................ 7

Deleted TPC 13 and TPC 14 ........................................................... 8

Changes to Figure 15........................................................................ 8

Changes to Figure 20 Caption....................................................... 10

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 21

MUXOUT and Lock Detect...................................................... 10

Input Shift Register .................................................................... 10

The Function Latch.................................................................... 16

The Initialization Latch ............................................................. 17

Applications..................................................................................... 18

Local Oscillator for LMDS Base Station Transmitter............ 18

Interfacing ................................................................................... 19

PCB Design Guidelines for Chip Scale Package .................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 21

5/03—Rev 0 to Rev. A

dits to Specifications...................................................................... 2

E

Edits to TPC 11................................................................................. 7

Updated Outline Dimensions....................................................... 19

10/01—Revision 0: Initial Revision

Rev. B | Page 2 of 24

ADF4106

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 1.

Parameter B Version1B Chips2 (typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 18 for input circuit

RF Input Frequency (RFIN) 0.5/6.0 0.5/6.0 GHz min/max

RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable Prescaler

Output Frequency

3

300 300 MHz max P = 8

325 325 MHz P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/300 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

4

0.8/V

DD

0.8/V

DD

V p-p min/max Biased at AVDD/2 (see Note 55)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 μA max

PHASE DETECTOR

Phase Detector Frequency

6

104 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP Programmable, see Table 9

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 μA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Table 9

SET

ICP Three-State Leakage 2 2 nA max 1 nA typical; TA = 25°C
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

For lower frequencies, ensure
slew rate (SR) > 320 V/μs

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

ICP vs. V

CP

1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 μA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min

Open-drain output chosen, 1 kΩ pull-up

resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 VDD − 0.4 V min CMOS output chosen
I

OH

100 100 μA max

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

POWER SUPPLIES

AV

DD

DV

DD

V

P

7

I

(AI

DD

I

DD

I

DD

I

P

+ DI ) 11 9.0 mA max 9.0 mA typ

DD DD

8

(AI

+ DI ) 11.5 9.5 mA max 9.5 mA typ

DD DD

9

(AI

+ DI ) 13 10.5 mA max 10.5 mA typ

DD DD

Power-Down Mode10

+ DIDD)

(AI

DD

2.7/3.3 2.7/3.3 V min/V max
AV

DD

AV

DD

AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5V

0.4 0.4 mA max TA = 25°C
10 10 μA typ

Rev. B | Page 3 of 24

ADF4106

www.BDTIC.com/ADI

Parameter B Version1B Chips2 (typ) Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Normalized

Phase Noise Floor

Phase Noise Performance

900 MHz

13

5800 MHz
5800 MHz

11

12

14

15

Spurious Signals

900 MHz
5800 MHz
5800 MHz

1

Operating temperature range (B Version) is –40°C to +85°C.

2

The B chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

4

AVDD = DVDD = 3 V.

5

AC coupling ensures AVDD/2 bias.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.

8

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.

9

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.

10

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.

11

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F

12

The phase noise is measured with the EVAL-ADF4106EB1 evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

f

= 10 MHz; f

REFIN

13

14

15

. PN

= PN

PFD

SYNTH

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.

PFD

= 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.

PFD

− 10 log F

TOT

TIMING CHARACTERISITICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 2.

Parameter Limit1 (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

1

Operating temperature range (B Version) is –40°C to +85°C.

–219 –219 dBc/Hz typ

@ VCO output
–92.5 −92.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−76.5 −76.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−83.5 −83.5 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency

–90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency
–65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency
–70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency

− 20 log N.

PFD

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulse Width

t

t

3

4

MAX

to T

MIN

,

CLOCK

DATA

DB23 (MSB)

LE

LE

t

t

1

2

DB22

DB2

Figure 2. Timing Diagram

Rev. B | Page 4 of 24

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

02720-002

ADF4106

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 –0.3 V to + 3.6 V
AVDD to DVDD –0.3 V to + 0.3 V
VP to GND –0.3 V to + 5.8 V
VP to AVDD –0.3 V to + 5.8 V
Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) –40°C to +85°C

Storage Temperature Range –65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 112°C/W
LFCSP θJA Thermal Impedance

(Paddle Soldered)

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 40 sec

Transistor Count

CMOS 6425
Bipolar 303

1

GND = AGND = DGND = 0 V.

30.4°C/W

S

tresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ES

D rating of <2 kV, and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 5 of 24

ADF4106

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

P

1

R

SET

2

CP

AGND
RFINB
RF

IN

AV

DD

REF

3

4

5

6

A

7

8

IN

ADF4106

TOP VIEW

(Not to Scale)

CPGND

NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).

Figure 3. 16-Lead TSSOP Pin Configuration

16

V

15

DV

14

MUXOUT

13

LE

12

DATA

11

CLK

10

CE

9

DGND

P

DD

CPGND 1

AGND 2
AGND 3
RFINB 4
RF

A 5

IN

02720-003

NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).

Figure 4. 20-Lead LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
TSSOP

1 19 R

2 20 CP

Pin No.
LFCSP Mnemonic Function

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R

I

MAXCP

So, with R

SET

Charge Pump Output. When enabled, this provides ±I

5.25

=

R

SET

= 5.1 kΩ, I

CP MAX

= 5 mA.

pin is 0.66 V. The relationship between ICP and R

SET

to the external loop filter, which in turn

CP

drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND
5 4 RF

B

IN

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF. See Figure 18.
6 5 RF
7 6, 7 AV

8 8 REF

A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

IN

DD

IN

Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV

DD

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input

resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or

9 9, 10 DGND
10 11 CE

it can be ac-cou

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output

pled.

into three-state mode. Taking the pin high powers up the device, depending on the status of the

power-down bit, F2.
11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.

This input is a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches with the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency

to be accessed externally.
15 16, 17 DV

16 18 V

DD

P

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.

SET

V

DV

R
191817

20 CP

PIN 1
INDICATOR

ADF4106

TOP VIEW

6

7

8

IN

DD

DD

AV

AV

REF

DGND 9

must be the same value as DVDD.

must be the same value as AVDD.

DD

DV
16

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

DGND 10

SET

is

02720-004

Rev. B | Page 6 of 24

ADF4106

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ UNIT GHz KEYWORD R
PARAM TYPE S IMPEDANCE 50Ω
DATA FORMAT MA

FREQ MAGS11 ANGS11

0.500 0.89148 –17.2820

0.600 0.88133 – 20.6919

0.700 0.87152 – 24.5386

0.800 0.85855 –27.3228

0.900 0.84911 –31.0698

1.000 0.83512 – 34.8623

1.100 0.82374 –38.5574

1.200 0.80871 –41.9093

1.300 0.79176 – 45.6990

1.400 0.77205 –49.4185

1.500 0.75696 –52.8898

1.600 0.74234 –56.2923

1.700 0.72239 –60.2584

1.800 0.69419 –63.1446

1.900 0.67288 –65.6464

2.000 0.66227 –68.0742

2.100 0.64758 –71.3530

2.200 0.62454 –75.5658

2.300 0.59466 –79.6404

2.400 0.55932 –82.8246

2.500 0.52256 –85.2795

2.600 0.48754 –85.6298

2.700 0.46411 –86.1854

2.800 0.45776 –86.4997

2.900 0.44859 –88.8080

3.000 0.44588 –91.9737

3.100 0.43810 –95.4087

3.200 0.43269 –99.1282

FREQ MAGS11 ANGS11

3.300 0.42777 –102.748

3.400 0.42859 –107.167

3.500 0.43365 –111.883

3.600 0.43849 –117.548

3.700 0.44475 –123.856

3.800 0.44800 –130.399

3.900 0.45223 –136.744

4.000 0.45555 –142.766

4.100 0.45313 –149.269

4.200 0.45622 –154.884

4.300 0.45555 –159.680

4.400 0.46108 –164.916

4.500 0.45325 –168.452

4.600 0.45054 –173.462

4.700 0.45200 –176.697

4.800 0.45043 178.824

4.900 0.45282 174.947

5.000 0.44287 170.237

5.100 0.44909 166.617

5.200 0.44294 162.786

5.300 0.44558 158.766

5.400 0.45417 153.195

5.500 0.46038 147.721

5.600 0.47128 139.760

5.700 0.47439 132.657

5.800 0.48604 125.782

5.900 0.50637 121.110

6.000 0.52172 115.400

Figure 5. S-Parameter Data for the RF Input

0

–5

–10

–15

–20

RF INPUT POWER (dBm)

–25

–30

T

= +25°C

A

RF INPUT FREQUENCY (GHz)

T

= –40°C

A

TA = +85°C

Figure 6. Input Sensitivity

0

REF LEVEL = –14.3dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2kHz –1kHz 900MHz 1kHz 2kHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

FREQUENCY

–93.0dBc/Hz

Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)

VDD = 3V

= 3V

V

P

02720-005

02720-006

6543210

02720-007

–40

–50

–60

–70

–80

–90

–100

–110

OUTPUT POWER (dB)

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

10dB/DIV
R

= –40dBc/Hz

L

RMS NOISE = 0.36°

Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –14.0dBm

–10

–20

–30

–40

–50

–60

OUTPUT POWER (dB)

–70

–80

–90

–100

–400kHz –200kHz 900MHz 200kHz 400kHz

V

= 3V, VP = 5V

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

FREQUENCY

–91.0dBc/Hz

Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–60

OUTPUT POWER (dB)

–70

–80

–90

–100

–2kHz –1kHz 5800MHz 1kHz 2kHz

FREQUENCY

= 3V, VP = 5V

V

DD

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–83.5dBc/Hz

Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

02720-008

02720-009

02720-010

Rev. B | Page 7 of 24

ADF4106

www.BDTIC.com/ADI

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 5800MHz CARRIER

Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–66.0dBc

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2kHz –1kHz 5800MHz 1kHz 2kHz

FREQUENCY (MHz)

Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)

–60

–70

–80

PHASE NOISE (dBc/Hz)

–90

–100

TEMPERATURE (°C)

Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature

10dB/DIV

= –40dBc/Hz

R

L

RMS NOISE = 1.8°

= 3V, VP = 5V

V

DD

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1

–65.0dBc

VDD = 3V
V

P

= 3V

02720-011

–5

–15

–25

–35

–45

–55

–65

–75

–85

FIRST REFERENCE SPUR (dBc)

–95

–105

TUNNING VOLTAGE (V)

Figure 14. Reference Spurs vs. V

(5.8 GHz,1 MHz, and 100 kHz)

TUNE

VDD = 3V
V

= 5V

P

501234

02720-014

02720-012

PHASE NOISE (dBc/Hz)

–120

–130

–140

–150

–160

–170

–180

PHASE ETECTOR FREQUENCY (Hz)

VDD = 3V
V

= 5V

P

02720-015

100M10k 100k 1M 10M

Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency

–6
–5
–4
–3
–2
–1

0

(mA)

CP

I

1
2
3
4

02720-013

100–40–200 20406080

5
6

V

CP

(V)

VPP = 5V

SETTLING = 5mA

I

CP

02720-016

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 16. Charge Pump Output Characteristics

Rev. B | Page 8 of 24