Datasheet ADF4106 Datasheet (ANALOG DEVICES)

www.BDTIC.com/ADI

PLL Frequency Synthesizer

FEATURES

6.0 GHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (VP) allows extended

tuning voltage in 3 V systems

Programmable dual-modulus prescaler

8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
Programmable antibacklash pulse width
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode

APPLICATIONS

Broadband wireless access
Satellite systems
Instrumentation
Wireless LANS
Base stations for wireless radios

FUNCTIONAL BLOCK DIAGRAM

DV

AV

DD

DD

ADF4106

GENERAL DESCRIPTION

The ADF4106 frequency synthesizer can be used to implement
local oscillators in the up-conversion and down-conversion
sections of wireless receivers and transmitters. It consists of a
low noise, digital phase frequency detector (PFD), a precision
charge pump, a programmable reference divider, programmable
A counter and B counter, and a dual-modulus prescaler (P/P +

1). The A (6-bit) counter and B (13-bit) counter, in conjunction
with the dual-modulus prescaler (P/P + 1), implement an N
divider (N = BP + A). In addition, the 14-bit reference counter
(R Counter) allows selectable REF
input. A complete phase-locked loop (PLL) can be implemented
if the synthesizer is used with an external loop filter and voltage
controlled oscillator (VCO). Its very high bandwidth means
that frequency doublers can be eliminated in many high
frequency systems, simplifying system architecture and
reducing cost.

V

CPGND

P

frequencies at the PFD

IN

R

SET

REF

IN

CLK

DATA

LE

RFINA
RF

B

IN

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

24-BIT INPUT

REGISTER

SD

OUT

FUNCTION

PRESCALER

FROM

LATCH

P/P + 1

CE

22

N = BP + A

AGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

A, B COUNTER

LATCH

13-BIT

B COUNTER

LOAD

LOAD

A COUNTER

DGND

13

6-BIT

6

19

Figure 1.

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

AV

SD

CURRENT

SETTING 1

CPI3 CPI2 CPI1

DD

OUT

CHARGE

MUX

M3 M2 M1

PUMP

CURRENT

SETTING 2

CPI6 CPI5 CPI4

HIGH Z

CP

MUXOUT

ADF4106

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

02720-001

ADF4106

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Phase Frequency Detector (PFD) and Charge Pump............ 10

Timing Characterisitics ............................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

General Description......................................................................... 9

Reference Input Section............................................................... 9

RF Input Stage............................................................................... 9

Prescaler (P/P +1)......................................................................... 9

A Counter and B Counter........................................................... 9

R Counter ...................................................................................... 9

REVISION HISTORY

6/05—Rev A to Rev. B

Updated Format..................................................................Universal

Changes to Figure 1.......................................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Figure 3 and Figure 4................................................... 6

Changes to Figure 6.......................................................................... 7

Changes to Figure 10........................................................................ 7

Deleted TPC 13 and TPC 14 ........................................................... 8

Changes to Figure 15........................................................................ 8

Changes to Figure 20 Caption....................................................... 10

Updated Outline Dimensions....................................................... 20

Changes to Ordering Guide.......................................................... 21

MUXOUT and Lock Detect...................................................... 10

Input Shift Register .................................................................... 10

The Function Latch.................................................................... 16

The Initialization Latch ............................................................. 17

Applications..................................................................................... 18

Local Oscillator for LMDS Base Station Transmitter............ 18

Interfacing ................................................................................... 19

PCB Design Guidelines for Chip Scale Package .................... 19

Outline Dimensions ....................................................................... 20

Ordering Guide .......................................................................... 21

5/03—Rev 0 to Rev. A

dits to Specifications...................................................................... 2

E

Edits to TPC 11................................................................................. 7

Updated Outline Dimensions....................................................... 19

10/01—Revision 0: Initial Revision

Rev. B | Page 2 of 24

ADF4106

www.BDTIC.com/ADI

SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 1.

Parameter B Version1B Chips2 (typ) Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 18 for input circuit

RF Input Frequency (RFIN) 0.5/6.0 0.5/6.0 GHz min/max

RF Input Sensitivity –10/0 –10/0 dBm min/max
Maximum Allowable Prescaler

Output Frequency

3

300 300 MHz max P = 8

325 325 MHz P = 16

REFIN CHARACTERISTICS

REFIN Input Frequency 20/300 20/300 MHz min/max For f < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

4

0.8/V

DD

0.8/V

DD

V p-p min/max Biased at AVDD/2 (see Note 55)
REFIN Input Capacitance 10 10 pF max
REFIN Input Current ±100 ±100 μA max

PHASE DETECTOR

Phase Detector Frequency

6

104 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP Programmable, see Table 9

ICP Sink/Source

High Value 5 5 mA typ With R
Low Value 625 625 μA typ
Absolute Accuracy 2.5 2.5 % typ With R
R

Range 3.0/11 3.0/11 kΩ typ See Table 9

SET

ICP Three-State Leakage 2 2 nA max 1 nA typical; TA = 25°C
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

For lower frequencies, ensure
slew rate (SR) > 320 V/μs

= 5.1 kΩ

SET

= 5.1 kΩ

SET

MAX

to T

MIN

,

ICP vs. V

CP

1.5 1.5 % typ 0.5 V ≤ VCP ≤ VP − 0.5 V

ICP vs. Temperature 2 2 % typ VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 1.4 V min
VIL, Input Low Voltage 0.6 0.6 V max
I

, I

, Input Current ±1 ±1 μA max

INH

INL

CIN, Input Capacitance 10 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 1.4 V min

Open-drain output chosen, 1 kΩ pull-up

resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 VDD − 0.4 V min CMOS output chosen
I

OH

100 100 μA max

VOL, Output Low Voltage 0.4 0.4 V max IOL = 500 μA

POWER SUPPLIES

AV

DD

DV

DD

V

P

7

I

(AI

DD

I

DD

I

DD

I

P

+ DI ) 11 9.0 mA max 9.0 mA typ

DD DD

8

(AI

+ DI ) 11.5 9.5 mA max 9.5 mA typ

DD DD

9

(AI

+ DI ) 13 10.5 mA max 10.5 mA typ

DD DD

Power-Down Mode10

+ DIDD)

(AI

DD

2.7/3.3 2.7/3.3 V min/V max
AV

DD

AV

DD

AVDD/5.5 AVDD/5.5 V min/V max AVDD ≤ VP ≤ 5.5V

0.4 0.4 mA max TA = 25°C
10 10 μA typ

Rev. B | Page 3 of 24

ADF4106

www.BDTIC.com/ADI

Parameter B Version1B Chips2 (typ) Unit Test Conditions/Comments

NOISE CHARACTERISTICS

ADF4106 Normalized

Phase Noise Floor

Phase Noise Performance

900 MHz

13

5800 MHz
5800 MHz

11

12

14

15

Spurious Signals

900 MHz
5800 MHz
5800 MHz

1

Operating temperature range (B Version) is –40°C to +85°C.

2

The B chip specifications are given as typical values.

3

This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that

is less than this value.

4

AVDD = DVDD = 3 V.

5

AC coupling ensures AVDD/2 bias.

6

Guaranteed by design. Sample tested to ensure compliance.

7

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.

8

TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.

9

TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.

10

TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.

11

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F

12

The phase noise is measured with the EVAL-ADF4106EB1 evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for
the synthesizer (f

13

f

= 10 MHz; f

REFIN

14

f

= 10 MHz; f

REFIN

15

f

= 10 MHz; f

REFIN

13

14

15

. PN

= PN

PFD

SYNTH

= 10 MHz @ 0 dBm).

REFOUT

= 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz.

PFD

= 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz.

PFD

= 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz.

PFD

− 10 log F

TOT

TIMING CHARACTERISITICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

Table 2.

Parameter Limit1 (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

1

Operating temperature range (B Version) is –40°C to +85°C.

–219 –219 dBc/Hz typ

@ VCO output
–92.5 −92.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−76.5 −76.5 dBc/Hz typ @ 1 kHz offset and 200 kHz PFD frequency

−83.5 −83.5 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency

–90/–92 –90/–92 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency
–65/–70 –65/–70 dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency
–70/–75 –70/–75 dBc typ @ 1 MHz/2 MHz and 1 MHz PFD frequency

− 20 log N.

PFD

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulse Width

t

t

3

4

MAX

to T

MIN

,

CLOCK

DATA

DB23 (MSB)

LE

LE

t

t

1

2

DB22

DB2

Figure 2. Timing Diagram

Rev. B | Page 4 of 24

DB1 (CONTROL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

02720-002

ADF4106

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 –0.3 V to + 3.6 V
AVDD to DVDD –0.3 V to + 0.3 V
VP to GND –0.3 V to + 5.8 V
VP to AVDD –0.3 V to + 5.8 V
Digital I/O Voltage to GND –0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND –0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) –40°C to +85°C

Storage Temperature Range –65°C to +125°C
Maximum Junction Temperature 150°C
TSSOP θJA Thermal Impedance 112°C/W
LFCSP θJA Thermal Impedance

(Paddle Soldered)

Reflow Soldering

Peak Temperature 260°C
Time at Peak Temperature 40 sec

Transistor Count

CMOS 6425
Bipolar 303

1

GND = AGND = DGND = 0 V.

30.4°C/W

S

tresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ES

D rating of <2 kV, and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 5 of 24

ADF4106

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

P

1

R

SET

2

CP

AGND
RFINB
RF

IN

AV

DD

REF

3

4

5

6

A

7

8

IN

ADF4106

TOP VIEW

(Not to Scale)

CPGND

NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).

Figure 3. 16-Lead TSSOP Pin Configuration

16

V

15

DV

14

MUXOUT

13

LE

12

DATA

11

CLK

10

CE

9

DGND

P

DD

CPGND 1

AGND 2
AGND 3
RFINB 4
RF

A 5

IN

02720-003

NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).

Figure 4. 20-Lead LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.
TSSOP

1 19 R

2 20 CP

Pin No.
LFCSP Mnemonic Function

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the R

I

MAXCP

So, with R

SET

Charge Pump Output. When enabled, this provides ±I

5.25

=

R

SET

= 5.1 kΩ, I

CP MAX

= 5 mA.

pin is 0.66 V. The relationship between ICP and R

SET

to the external loop filter, which in turn

CP

drives the external VCO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND
5 4 RF

B

IN

Analog Ground. This is the ground return path of the prescaler.

Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with

a small bypass capacitor, typically 100 pF. See Figure 18.
6 5 RF
7 6, 7 AV

8 8 REF

A Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.

IN

DD

IN

Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to this pin. AV

DD

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input

resistance of 100 kΩ. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or

9 9, 10 DGND
10 11 CE

it can be ac-cou

Digital Ground.

Chip Enable. A logic low on this pin powers down the device and puts the charge pump output

pled.

into three-state mode. Taking the pin high powers up the device, depending on the status of the

power-down bit, F2.
11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched

into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.

This input is a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one

of the four latches with the latch being selected using the control bits.
14 15 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency

to be accessed externally.
15 16, 17 DV

16 18 V

DD

P

Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground

plane should be placed as close as possible to this pin. DV

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,

it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.

SET

V

DV

R
191817

20 CP

PIN 1
INDICATOR

ADF4106

TOP VIEW

6

7

8

IN

DD

DD

AV

AV

REF

DGND 9

must be the same value as DVDD.

must be the same value as AVDD.

DD

DV
16

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

DGND 10

SET

is

02720-004

Rev. B | Page 6 of 24

ADF4106

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

FREQ UNIT GHz KEYWORD R
PARAM TYPE S IMPEDANCE 50Ω
DATA FORMAT MA

FREQ MAGS11 ANGS11

0.500 0.89148 –17.2820

0.600 0.88133 – 20.6919

0.700 0.87152 – 24.5386

0.800 0.85855 –27.3228

0.900 0.84911 –31.0698

1.000 0.83512 – 34.8623

1.100 0.82374 –38.5574

1.200 0.80871 –41.9093

1.300 0.79176 – 45.6990

1.400 0.77205 –49.4185

1.500 0.75696 –52.8898

1.600 0.74234 –56.2923

1.700 0.72239 –60.2584

1.800 0.69419 –63.1446

1.900 0.67288 –65.6464

2.000 0.66227 –68.0742

2.100 0.64758 –71.3530

2.200 0.62454 –75.5658

2.300 0.59466 –79.6404

2.400 0.55932 –82.8246

2.500 0.52256 –85.2795

2.600 0.48754 –85.6298

2.700 0.46411 –86.1854

2.800 0.45776 –86.4997

2.900 0.44859 –88.8080

3.000 0.44588 –91.9737

3.100 0.43810 –95.4087

3.200 0.43269 –99.1282

FREQ MAGS11 ANGS11

3.300 0.42777 –102.748

3.400 0.42859 –107.167

3.500 0.43365 –111.883

3.600 0.43849 –117.548

3.700 0.44475 –123.856

3.800 0.44800 –130.399

3.900 0.45223 –136.744

4.000 0.45555 –142.766

4.100 0.45313 –149.269

4.200 0.45622 –154.884

4.300 0.45555 –159.680

4.400 0.46108 –164.916

4.500 0.45325 –168.452

4.600 0.45054 –173.462

4.700 0.45200 –176.697

4.800 0.45043 178.824

4.900 0.45282 174.947

5.000 0.44287 170.237

5.100 0.44909 166.617

5.200 0.44294 162.786

5.300 0.44558 158.766

5.400 0.45417 153.195

5.500 0.46038 147.721

5.600 0.47128 139.760

5.700 0.47439 132.657

5.800 0.48604 125.782

5.900 0.50637 121.110

6.000 0.52172 115.400

Figure 5. S-Parameter Data for the RF Input

0

–5

–10

–15

–20

RF INPUT POWER (dBm)

–25

–30

T

= +25°C

A

RF INPUT FREQUENCY (GHz)

T

= –40°C

A

TA = +85°C

Figure 6. Input Sensitivity

0

REF LEVEL = –14.3dBm

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2kHz –1kHz 900MHz 1kHz 2kHz

VDD = 3V, VP = 5V

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

FREQUENCY

–93.0dBc/Hz

Figure 7. Phase Noise (900 MHz, 200 kHz, and 20 kHz)

VDD = 3V

= 3V

V

P

02720-005

02720-006

6543210

02720-007

–40

–50

–60

–70

–80

–90

–100

–110

OUTPUT POWER (dB)

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 900MHz CARRIER

10dB/DIV
R

= –40dBc/Hz

L

RMS NOISE = 0.36°

Figure 8. Integrated Phase Noise (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –14.0dBm

–10

–20

–30

–40

–50

–60

OUTPUT POWER (dB)

–70

–80

–90

–100

–400kHz –200kHz 900MHz 200kHz 400kHz

V

= 3V, VP = 5V

DD

= 5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 2.5 SECONDS
AVERAGES = 30

FREQUENCY

–91.0dBc/Hz

Figure 9. Reference Spurs (900 MHz, 200 kHz, and 20 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–60

OUTPUT POWER (dB)

–70

–80

–90

–100

–2kHz –1kHz 5800MHz 1kHz 2kHz

FREQUENCY

= 3V, VP = 5V

V

DD

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 10

–83.5dBc/Hz

Figure 10. Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

02720-008

02720-009

02720-010

Rev. B | Page 7 of 24

ADF4106

www.BDTIC.com/ADI

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE (dBc/Hz)

–120

–130

–140

100Hz 1MHz

FREQUENCY OFFSET FROM 5800MHz CARRIER

Figure 11. Integrated Phase Noise (5.8 GHz,1 MHz, and 100 kHz)

0

REF LEVEL = –10dBm

–10

–20

–30

–40

–50

–66.0dBc

–60

–70

OUTPUT POWER (dB)

–80

–90

–100

–2kHz –1kHz 5800MHz 1kHz 2kHz

FREQUENCY (MHz)

Figure 12. Reference Spurs (5.8 GHz,1 MHz, and 100 kHz)

–60

–70

–80

PHASE NOISE (dBc/Hz)

–90

–100

TEMPERATURE (°C)

Figure 13. Phase Noise (5.8 GHz,1 MHz, and 100 kHz) vs. Temperature

10dB/DIV

= –40dBc/Hz

R

L

RMS NOISE = 1.8°

= 3V, VP = 5V

V

DD

= 5mA

I

CP

PFD FREQUENCY = 1MHz
LOOP BANDWIDTH = 100kHz
RES BANDWIDTH = 1kHz
VIDEO BANDWIDTH = 1kHz
SWEEP = 13 SECONDS
AVERAGES = 1

–65.0dBc

VDD = 3V
V

P

= 3V

02720-011

–5

–15

–25

–35

–45

–55

–65

–75

–85

FIRST REFERENCE SPUR (dBc)

–95

–105

TUNNING VOLTAGE (V)

Figure 14. Reference Spurs vs. V

(5.8 GHz,1 MHz, and 100 kHz)

TUNE

VDD = 3V
V

= 5V

P

501234

02720-014

02720-012

PHASE NOISE (dBc/Hz)

–120

–130

–140

–150

–160

–170

–180

PHASE ETECTOR FREQUENCY (Hz)

VDD = 3V
V

= 5V

P

02720-015

100M10k 100k 1M 10M

Figure 15. Phase Noise (Referred to CP Output) vs. PFD Frequency

–6
–5
–4
–3
–2
–1

0

(mA)

CP

I

1
2
3
4

02720-013

100–40–200 20406080

5
6

V

CP

(V)

VPP = 5V

SETTLING = 5mA

I

CP

02720-016

5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Figure 16. Charge Pump Output Characteristics

Rev. B | Page 8 of 24

ADF4106

www.BDTIC.com/ADI

GENERAL DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 17. SW1 and SW2
are normally closed switches. SW3 is a normally open switch.
When power-down is initiated, SW3 is closed and SW1 and
SW2 are opened. This ensures that there is no loading of the
REF

pin on power-down.

IN

POWER-DOWN

CONTROL

100kΩ

NC

REF

SW2

IN

NC

SW1

SW3

NO

Figure 17. Reference Input Stage

BUFFER

TO R COUNTER

RF INPUT STAGE

The RF input stage is shown in Figure 18. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.

02720-017

A COUNTER AND B COUNTER

The A counter and B CMOS counter combine with the dual
modulus prescaler to allow a wide ranging division ratio in the
PLL feedback counter. The counters are specified to work when
the prescaler output is 325 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid, but a
value of 8/9 is not valid.

Pulse Swallow Function

The A counter and B counter, in conjunction with the dual­modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is

f

REFIN

()

[]

f ×+×=

VCO

ABP

where:

is the output frequency of the external voltage controlled

f

VCO

oscillator (VCO).

P is t

he preset modulus of the dual-modulus prescaler

(8/9, 16/17, etc.).

R

500Ω

1.6V

500Ω

AV

DD

AGND

02720-018

RFINA

RF

IN

BIAS

GENERATOR

B

Figure 18. RF Input Stage

PRESCALER (P/P +1)

The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = BP + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF input stage and divides it
down to a manageable frequency for the CMOS A counter and
B counter. The prescaler is programmable. It can be set in soft­ware to 8/9, 16/17, 32/33, or 64/65. It is based on a synchronous
4/5 core. There is a minimum divide ratio possible for fully
contiguous output frequencies. This minimum is determined by
P, the prescaler value, and is given by (P

2

− P).

B is t

he preset divide ratio of the binary 13-bit counter

(3 to 8191).

A is t

he preset divide ratio of the binary 6-bit swallow

counter (0 to 63).

is the external reference frequency oscillator.

f

REFIN

N = BP + A

TO PFD

FROM RF

INPUT STAGE

PRESCALER

P/P + 1

MODULUS
CONTROL

N DIVIDER

Figure 19. A and B Counters

13-BIT B

COUNTER

LOAD

LOAD

6-BIT A

COUNTER

R COUNTER

The 14-bit R counter allows the input reference frequency to
be divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383
are allowed.

02720-019

Rev. B | Page 9 of 24

ADF4106

www.BDTIC.com/ADI

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter
(N = BP + A) and produces an output proportional to the
phase and frequency difference between them. Figure 20 is a
sim

plified schematic. The PFD includes a programmable delay
element that controls the width of the antibacklash pulse. This
pulse ensures that there is no dead zone in the PFD transfer
function and minimizes phase noise and reference spurs. Two
bits in the reference counter latch, ABP2 and ABP1, control the
width of the pulse. See

HI

R DIVIDER

HID1D2

N DIVIDER

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4106 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch. Tabl e 9 shows the full truth table. Figure 21 shows the
MUX

OUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter

tch is set to 0, digital lock detect is set high when the phase

la
error on three consecutive phase detector cycles is less than
15 ns. With LDP set to 1, five consecutive cycles of less than
15 ns are required to set the lock detect. It stays set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.

Table 7 .

UP

Q1

U1

CLR1

PROGRAMMABLE

DELAY

ABP2

ABP1

CLR2

DOWN

Q2

U2

Figure 20. PFD Simplified Schematic

U3

V

P

CPGND

CHARGE

PUMP

CP

02720-020

The N-channel, open-drain, analog lock detect should be
op

erated with an external pull-up resistor of 10 kΩ nominal.
When lock is detected, this output is high with narrow, low­going pulses.

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

Figure 21. MUXOUT Circuit

CONTROL

MUXOUT

DGND

INPUT SHIFT REGISTER

The ADF4106 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 19-bit N counter, comprising a
6-bit A counter and a 13-bit B counter. Data is clocked into the
24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram of

hese bits is shown in Tabl e 5. Ta b l e 6 shows a summary of how

t
t

he latches are programmed.

Table 5. C1, C2 Truth Table

Control Bits
C2 C1 Data Latch

0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch (Including Prescaler)
1 1 Initialization Latch

Figure 2. The truth table for

02720-021

Rev. B | Page 10 of 24

ADF4106

www.BDTIC.com/ADI

Table 6. Latch Summary

REFERENCE COUNTER LATCH

RESERVED

00X

RESERVED

PRESCALER

VALUE

DB22DB23

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

G1XX

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

CURRENT

SETTING

CPI3CPI4

13-BIT B COUNTER

1

N COUNTER LATCH

FUNCTION LATCH

TIMER COUNTER

CONTROL

TC3 TC2 TC1

14-BIT REFERENCE COUNTER

R6

R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

FASTLOCK

MODE

ENABLE

FASTLOCK

F4F5

STATE

CP THREE-

PD

POLARITY

6-BIT A COUNTER

MUXOUT

CONTROL

POWER-

DOWN 1

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

COUNTER

C2 (0) C1 (0)R1R2R3R4R5

C2 (0)

RESET

C2 (1) C1 (0)F1PD1M1M2M3F3P1P2 CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

CONTROL

BITS

C1 (1)

CONTROL

BITS

INITIALIZATION LATCH

PRESCALER

VALUE

DB21

DB22DB23

P1P2 CPI1CPI2

CURRENT

SETTING

POWER-

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

CPI5

CPI6 TC4PD2

CPI3CPI4

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

TC3 TC2 TC1

Rev. B | Page 11 of 24

FASTLOCK

MODE

POLARITY

MUXOUT

CONTROL

POWER-

DOWN 1

PD

STATE

ENABLE

FASTLOCK

CP THREE-

D

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

B

8

F3

F4F5

F2

COUNTER

F1PD1M1M2M3

RESET

CONTROL

BITS

C2 (1) C1 (1)

02720-022

ADF4106

www.BDTIC.com/ADI

Table 7. Reference Counter Latch Map

RESERVED

X

X

= DON’T CARE

DB21DB22DB23

00

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

ABP2 ABP1
0 0 2.9ns
0 1 1.3ns

1 0 6.0ns
1 1 2.9ns

ANTIBACKLASH PULSE WIDTH

14-BIT REFERENCE COUNTER

R14 R13 R12 .......... R3 R2 R1

0 0 0 .......... 0 0 1 1

0 0 0 .......... 0 1 0 2

0 0 0 .......... 0 1 1 3

0 0 0 .......... 1 0 0 4

. . . .......... . . . .

. . . .......... . . . .

. . . .......... . . . .

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

DIVIDE RATIO

BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.

TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.

LDP

OPERATION

0

THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

02720-023

Rev. B | Page 12 of 24

ADF4106

www.BDTIC.com/ADI

Table 8. N (A, B) Counter Latch Map

RESERVED

DB22DB23

XX

13-BIT B COUNTER

CP GAIN

DB21

G1

DB19

DB20

X = DON’T CARE

B13 B12 B11 B3 B2 B1

0 0 0 .......... 0 0 0

0 0 0 .......... 0 0 1

0 0 0 .......... 0 1 0

0 0 0 .......... 0 1 1

. . . .......... . . .

. . . .......... . . .

. . . .......... . . .

1 1 1 .......... 1 0 0

1 1 1 .......... 1 0 1

1 1 1 .......... 1 1 0

1 1 1 .......... 1 1 1

DB18 DB17

DB16 DB15 DB14

DB13 DB12 DB11

DB10 DB9

B COUNTER DIVIDE RATIO
NOT ALLOWED

NOT ALLOWED
NOT ALLOWED
3
.
.
.
8188
8189
8190

8191

DB8 DB7

A6 A5 .......... A2 A1

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

. . .......... . . .

. . .......... . . .

1 1 .......... 0 0 60

1 1 .......... 0 1 61

1 1 .......... 1 0 62

1 1 .......... 1 1 63

6-BIT A COUNTER

DB6 DB5

DB4 DB3

CONTROL

DB2 DB1

C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6

A COUNTER
DIVIDE RATIO

BITS

DB0

F4 (FUNCTION LATCH)
FASTLOCK ENABLE

00

0

1

11

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.

OPERATIONCP GAIN
CHARGE PUMP CURRENT

1

0

SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT

SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT

SETTING 1 IS USED.
CHARGE PUMP CURRENT IS

SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.

N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N × F
OUTPUT, N

IS (P2– P).

MIN

REF

), AT THE

02720-024

Rev. B | Page 13 of 24

ADF4106

www.BDTIC.com/ADI

Table 9. Function Latch Map

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1
00003

00017
001011
001115

010019
010123
011027
011131

100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC4PD2 F2

TC3 TC2 TC1

MODE

FASTLOCK

F5

F4
0

1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT

0

NORMAL
THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABLED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

PHASE DETECTOR

F2

POLARITY
NEGATIVE

0

POSITIVE

1

M3 M2 M1
000

001
010

011
100
101

110
111

POWER-

DOWN 1

M1M2M3F3P1P2 CPI1CPI2CPI5

PD1

F1
0

1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (0)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS

HELD IN RESET

OUTPUT
THREE-STATE OUTPUT

DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDER OUTPUT
DV

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN

LOCK DETECT
SERIAL DATA OUTPUT
DGND

I

CPI6 CPI5 CPI4
CPI3 CPI2 CPI1
0 0 0 1.06 0.625 0.289

0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160

1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020

1 1 1 8.50 5.0 2.320

CE PIN
0

1
101
111

P2 P1
0 0 8/9

0 1 16/17
1 0 32/33
1 1 64/65

PRESCALER VALUE

PD2 PD1 MODE
X

X0

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

3kΩ 5.1kΩ 11kΩ

CP

(mA)

Rev. B | Page 14 of 24

02720-025

ADF4106

www.BDTIC.com/ADI

Table 10. Initialization Latch Map

PRESCALER

VALUE

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1
00003

00017
001011
001115

010019
010123
011027
011131

100035
100139
101043
101147
110051
110155
111059
111163

TIMER COUNTER

CONTROL

TC4PD2 F2

TC3 TC2 TC1

MODE

FASTLOCK

F5

F4
0

1
1

TIMEOUT
(PFD CYCLES)

STATE

ENABLE

CP THREE-

FASTLOCK

F4

CHARGE PUMP

F3

OUTPUT
NORMAL

0

THREE-STATE

1

F5

FASTLOCK MODE

X

FASTLOCK DISABLED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

PHASE DETECTOR

F2

POLARITY

NEGATIVE

0

POSITIVE

1

M3 M2 M1
000

001
010

011
100
101

110
111

POWER-

DOWN 1

M1M2M3F3P1P2 CPI1CPI2CPI5

PD1

F1
0

1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (1)

COUNTER
OPERATION

NORMAL
R, A, B COUNTERS

HELD IN RESET

OUTPUT
THREE-STATE OUTPUT

DIGITAL LOCK DETECT
(ACTIVE HIGH)

N DIVIDER OUTPUT
DV

DD

R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN

LOCK DETECT
SERIAL DATA OUTPUT
DGND

I

CPI6 CPI5 CPI4
CPI3 CPI2 CPI1
0 0 0 1.06 0.625 0.289

0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160

1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020

1 1 1 8.50 5.0 2.320

CE PIN
0

1
101
111

P2 P1
0 0 8/9

0 1 16/17
1 0 32/33
1 1 64/65

PRESCALER VALUE

PD2 PD1 MODE
X

X0

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

3kΩ 5.1kΩ 11kΩ

CP

(mA)

Rev. B | Page 15 of 24

02720-026

ADF4106

www.BDTIC.com/ADI

THE FUNCTION LATCH

With C2 and C1 set to 1 and 0, respectively, the on-chip
function latch is programmed. Tabl e 9 shows the input data

rmat for programming the function latch.

fo

Counter Reset

DB2 (F1) is the counter reset bit. When this is 1, the R counter
and the N (A, B) counter are reset. For normal operation, this
bit should be 0. When powering up, disable the F1 bit (set to 0).
The N counter will then resume counting in close alignment
with the R counter. (The maximum error is one prescaler cycle).

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power­down modes. They are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled
re

gardless of the states of PD2, PD1.

In the programmed asynchronous power-down, the device
p

owers down immediately after latching 1 into the PD1 bit,

with the condition that PD2 is loaded with 0.

In the programmed synchronous power-down, the device
p

ower-down is gated by the charge pump to prevent unwanted
frequency jumps. Once the power-down is enabled by writing 1
into the PD1 bit (provided that 1 has also been loaded to PD2),
then the device goes into power-down during the next charge
pump event.

When a power-down is activated (either synchronous or
asy

nchronous mode, including CE pin activated power-down),

the following events occur:

ll active dc current paths are removed.

• A

• The R

, N, and timeout counters are forced to their load state

conditions.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines which fastlock mode is
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected; and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fastlock
when 0 is written to the CP gain bit in the N (A, B) counter
latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current
Setting 2. The device enters fastlock when 1 is written to the CP
gain bit in the N (A, B) counter latch. The device exits fastlock
under the control of the timer counter. After the timeout
period, which is determined by the value in TC4 to TC1, the CP
gain bit in the N (A, B) counter latch is automatically reset to 0,
and the device reverts to normal mode instead of fastlock. See
Tabl e 9 for the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump
currents. The intent is that Current Setting 1 is used when the
RF output is stable and the system is in a static state. Current
Setting 2 is used when the system is dynamic and in a state of
change (that is, when a new output frequency is programmed).
The normal sequence of events follows.

The user initially decides what the preferred charge pump
c

urrents are going to be. For example, the choice may be

2.5 mA as Current Setting 1 and 5 mA as the Current Setting 2.

• The cha

• T

• The RF

• T

• The i

latching data.

rge pump is forced into three-state mode.

he digital clock detect circuitry is reset.

input is debiased.

IN

he reference input buffer circuitry is disabled.

nput register remains active and capable of loading and

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4106 family. Ta b le 9 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. When this
bit is 1, fastlock is enabled.

Rev. B | Page 16 of 24

Simultaneously, the decision must be made as to how long the
s

econdary current stays active before reverting to the primary
current. This is controlled by the timer counter control bits,
DB14 to DB11 (TC4 to TC1), in the function latch. The truth
table is given in

To program a new output frequency, simply program the N (A,

unter latch with new values for A and B. Simultaneously,

B) co
the CP gain bit can be set to 1, which sets the charge pump with
the value in CPI6 to CPI4 for a period of time determined by
TC4 to TC1. When this time is up, the charge pump current
reverts to the value set by CPI3 to CPI1. At the same time, the
CP gain bit in the N (A, B) counter latch is reset to 0 and is now
ready for the next time the user wishes to change the frequency.

Note that there is an enable feature on the timer counter. It is
ena

bled when Fastlock Mode 2 is chosen by setting the fastlock

mode bit (DB10) in the function latch to 1.

Tabl e 9.

ADF4106

www.BDTIC.com/ADI

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. The truth table is given in

Tabl e 9.

Prescaler Value

P2 and P1 in the function latch set the prescaler values. The
prescaler value should be chosen so that the prescaler output
frequency is always less than or equal to 325 MHz. Therefore,
with an RF frequency of 4 GHz, a prescaler value of 16/17 is
valid, but a value of 8/9 is not valid.

PD Polarity

This bit sets the phase detector polarity bit. See Tab l e 9 .

CP Three-State

This bit controls the CP output pin. With the bit set high, the
CP output is put into three-state. With the bit set low, the CP
output is enabled.

THE INITIALIZATION LATCH

When C2 and C1 = 1 and 1, respectively, the initialization latch
is programmed. This is essentially the same as the function
latch (programmed when C2 and C1 = 1 and 0, respectively).

However, when the initialization latch is programmed, there is
a

n additional internal reset pulse applied to the R and N (A, B)
counters. This pulse ensures that the N (A, B) counter is at the
load point when the N (A, B) counter data is latched and the
device begins counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE

in is high, PD1 bit is high, and PD2 bit is low), the internal

p
pulse also triggers this power-down. The prescaler reference
and the oscillator input buffer are unaffected by the internal
reset pulse; therefore, close phase alignment is maintained when
counting resumes.

When the first N (A, B) counter data is latched after
ini

tialization, the internal reset pulse is again activated.
However, successive N (A, B) counter loads after this will not
trigger the internal reset pulse.

Device Programming After Initial Power-Up

After initial power up of the device, there are three methods for
programming the device: initialization latch, CE pin, and
counter reset.

Initialization Latch Method

• Apply V

ogram the initialization latch (11 in two LSBs of input

• Pr

word). Make sure that the F1 bit is programmed to 0.

• Do a f

word), making sure that the F1 bit is programmed to a 0.

• Do a

.

DD

unction latch load (10 in two LSBs of the control

n R load (00 in two LSBs).

• Do a

n N (A, B) load (01 in two LSBs).

When the initialization latch is loaded, the following occurs:

• The f

unction latch contents are loaded.

• An in

ternal pulse resets the R, N (A, B), and timeout counters
to load-state conditions and also three-states the charge
pump. Note that the prescaler band gap reference and the
oscillator input buffer are unaffected by the internal reset
pulse, allowing close phase alignment when counting
resumes.

atching the first N (A, B) counter data after the initialization

• L

word activates the same internal reset pulse. Successive N (A,
B) loads will not trigger the internal reset pulse, unless there
is another initialization.

CE PIN METHOD

• Apply V

ing CE low to put the device into power-down. This is an

• Br

asychronous power-down in that it happens immediately.

rogram the function latch (10).

• P

• P

rogram the R counter latch (00).

• P

rogram the N (A, B) counter latch (01).

• B

ring CE high to take the device out of power-down. The R
and N (A, B) counters now resume counting in close
alignment.

Note that after CE goes high, a 1 μs duration may be required
fo

r the prescaler band gap voltage and oscillator input buffer

bias to reach steady state.

CE can be used to power the device up and down to check for
cha

nnel activity. The input register does not need to be
reprogrammed each time the device is disabled and enabled as
long as it is programmed at least once after V
applied.

DD

.

is initially

DD

COUNTER RESET METHOD

• Apply V

• Do a f

load 1 to the F1 bit. This enables the counter reset.

• Do a

• Do a

• Do a f

load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the

nitialization method. It offers direct control over the internal

i
reset. Note that counter reset holds the counters at load point
and three-states the charge pump but does not trigger
synchronous power-down.

.

DD

unction latch load (10 in two LSBs). As part of this,

n R counter load (00 in two LSBs).

n N (A, B) counter load (01 in two LSBs).

unction latch load (10 in two LSBs). As part of this,

Rev. B | Page 17 of 24

ADF4106

www.BDTIC.com/ADI

APPLICATIONS

LOCAL OSCILLATOR FOR LMDS BASE STATION TRANSMITTER

Figure 22 shows the ADF4106 being used with a VCO to
produce the LO for an LMDS base station.

The reference input signal is applied to the circuit at FREF
and, in this case, is terminated in 50 Ω. A typical base station
system would have either a TCXO or an OCXO driving the
reference input without any 50 Ω termination.

To achieve a channel spacing of 1 MHz at the output, the
10 MH

z reference input must be divided by 10, using the

on-chip reference divider of the ADF4106.

The charge pump output of the ADF4106 (Pin 2) drives the

op filter. In calculating the loop filter component values, a

lo
number of items need to be considered. In this example, the
loop filter was designed so that the overall phase margin for
the system would be 45°.

Other PLL system specifications include:

K

= 2.5 mA

D

K

= 80 MHz/V

V

V

DD

IN

V

P

Loop Bandwidth = 50 kHz

F

= 1 MHz

PFD

N = 5800

Extra Reference Spur Attenuation = 10 dB

These specifications are needed and used to derive the loop
f

ilter component values shown in

Figure 22.

The circuit in Figure 22 shows a typical phase noise

erformance of −83.5 dBc/Hz at 1 kHz offset from the carrier.

p
Spurs are better than −62 dBc.

The loop filter output drives the VCO, which in turn is fed

ack to the RF input of the PLL synthesizer and also drives the

b
RF output terminal. A T-circuit configuration provides 50 Ω
matching between the VCO output, the RF output, and the RF

IN

terminal of the synthesizer.

In a PLL system, it is important to know when the system

ck. In Figure 22, this is accomplished by using the

is in lo

OUT signal from the synthesizer. The MUXOUT pin

MUX
can be programmed to monitor various internal signals in the
synthesizer. One of these is the LD or lock-detect signal.

RF

OUT

100pF

18Ω

18Ω

18Ω

FREF

7

AV

1000pF

IN

1000pF

51Ω

DD

8

REF

16

15

V

DV

P

DD

2

CP

IN

100pF

6.2kΩ

4.3kΩ

20pF

14

V

CC

2

V956ME03

100pF

10

ADF4106

1.5nF

CE

MUXOUT

CLK
DATA
LE

RFINA

R

1

SET

5.1kΩ

-COMPATIBLE SERIAL BUS

®

SPI

CPGND

43

B

RF

IN

AGND

DGND

9

Figure 22. Local Oscillator for LMDS Base Station

LOCK

14

DETECT

100pF

6

5

100pF

51Ω

NOTE
DECOUPLING CAPACITORS (0.1
V

OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE

P

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

1, 3, 4, 5, 7, 8,
9, 11, 12, 13

μ

F/10pF) ON AVDD, DVDD, AND

02720-027

Rev. B | Page 18 of 24

ADF4106

www.BDTIC.com/ADI

INTERFACING

The ADF4106 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 24 bits clocked into the input
register on each rising edge of CLK are transferred to the
appropriate latch. See
Tabl e 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

eans that the maximum update rate for the device is 833 kHz,

m
or one update every 1.2 μs. This is certainly more than adequate
for systems that have typical lock times in hundreds of
microseconds.

ADuC812 Interface

Figure 23 shows the interface between the ADF4106 and the
ADuC812 MicroConverter®. Since the ADuC812 is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4106 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
is written, the LE input should be brought high to complete
the transfer.

On first applying power to the ADF4106, it needs four writes
(o

ne each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control

ower-down (CE input) and to detect lock (MUXOUT

p
configured as lock detect and polled by the port input).

When operating in the mode described, the maximum

OCK rate of the ADuC812 is 4 MHz. This means that

SCL
the maximum rate at which the output frequency can be
changed is 166 kHz.

SCLOCK

ADuC812

I/O PORTS

Figure 2 for the timing diagram and

CLK

MOSI

Figure 23. ADuC812-to-ADF4106 Interface

DATA

LE

ADF4106

CE
MUXOUT

(LOCK DETECT)

02720-028

ADSP2181 Interface

Figure 24 shows the interface between the ADF4106 and the
ADSP21xx digital signal processor (DSP). The ADF4106
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.

ADSP-21xx

I/O FLAGS

SCLOCK

MOSI

TFS

Figure 24. ADSP-21xx-to-ADF4106 Interface

CLK

DATA

LE

ADF4106

CE
MUXOUT

(LOCK DETECT)

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the LFCSP (CP-20) are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the LFCSP has a central thermal pad.

The thermal pad on the PCB should be at least as large as this
exp

osed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.

Thermal vias may be used on the PCB thermal pad to improve
t

hermal performance of the package. If vias are used, they
should be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter should be between 0.3 mm and 0.33 mm, and
the via barrel should be plated with 1 oz. copper to plug the via.

The user should connect the PCB thermal pad to AGND.

02720-029

Rev. B | Page 19 of 24

ADF4106

R

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09

Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP]

-16)

(RU

Dimensions shown in millimeters

4.00

BSC SQ

0.60

MAX

12° MAX

0.50

BSC

TOP

VIEW

0.80 MAX

0.65 TYP

0.20

REF

3.75

BCS SQ

0.05 MAX

0.02 NOM

0.75

0.55

0.35

COPLANARITY

0.08

8°
0°

0.60

MAX

16

15

11

10

PIN 1

INDICATOR

20

5

6

0.30

0.23

0.18

0.75

0.60

0.45

1

2.25

2.10 SQ

1.95

0.25 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 26. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4

mm × 4 mm Body, Very Thin Quad

(CP-20-1)

Dimensions shown in millimeters

Rev. B | Page 20 of 24

ADF4106

www.BDTIC.com/ADI

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF4106BRU –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4106BRU-REEL –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4106BRU-REEL7 –40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4106BRUZ
ADF4106BRUZ-RL
ADF4106BRUZ-R7
ADF4106BCP –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20
ADF4106BCP-REEL –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20
ADF4106BCP-REEL7 –40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20
ADF4106BCPZ
ADF4106BCPZ-RL
ADF4106BCPZ-R7
EVAL-ADF4106EB1 Evaluation Board
EVAL-ADF411XEB1 Evaluation Board

1

Z = Pb-free part.

1

1

1

1

1

1

–40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
–40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
–40°C to + 85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

–40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20
–40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20
–40°C to + 85°C 20-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-20

Rev. B | Page 21 of 24

ADF4106

www.BDTIC.com/ADI

NOTES

Rev. B | Page 22 of 24

ADF4106

www.BDTIC.com/ADI

NOTES

Rev. B | Page 23 of 24

ADF4106

www.BDTIC.com/ADI

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C02720–0–6/05(B)

Rev. B | Page 24 of 24