Datasheet ADF4002 Datasheet (ANALOG DEVICES)

A

V

T

V

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Phase Detector/Frequency Synthesizer

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector

APPLICATIONS

Clock conditioning
Clock generation
IF LO generation

REF

IN

CLK

DATA

LE

24-BIT INP UT

REGISTER

SD

OUT

) allows extended

P

DV

DD

DD

22

GENERAL DESCRIPTION

The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the part can be used as a standalone PFD and charge pump.

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

P

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPGND

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

MUX

REFERENCE

CHARGE

PUMP

CPI6 CPI5 CPI 4

R

CURRENT

SETTING 2

HIGH Z

ADF4002

SET

CP

MUXOU

RFINA
RF

IN

B

CE

AGND

N COUNTER

DGND

13-BIT

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

M3 M2 M1

ADF4002

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

06052-001

ADF4002

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

N Counter...................................................................................... 8

R Counter ...................................................................................... 8

Phase Frequency Detector (PFD) and Charge Pump.............. 8

MUXOUT and Lock Detect.........................................................9

Input Shift Register .......................................................................9

Latch Maps and Descriptions ....................................................... 10

Latch Summary........................................................................... 10

Reference Counter Latch Map.................................................. 11

N Counter Latch Map................................................................ 12

Function Latch Map................................................................... 13

Initialization Latch Map ............................................................ 14

Function Latch............................................................................ 15

Initialization Latch..................................................................... 16

Applications..................................................................................... 17

Very Low Jitter Encode Clock for High Speed Converters... 17

PFD............................................................................................... 17

Interfacing ................................................................................... 17

PCB Design Guidelines for Chip Scale Package .................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

4/07—Rev. 0 to Rev. A

Changes to Features List.................................................................. 1

Changes to Table 1............................................................................ 3

Deleted Figure................................................................................... 7

Changes to Figure 16...................................................................... 11

4/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADF4002

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SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

= T

to T

A

MAX

, unless otherwise noted.

MIN

= 5.1 kΩ, dBm referred to 50 Ω,

SET

Table 1.

B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 11 for input circuit

RF Input Sensitivity −10 0 dBm
RF Input Frequency (RFIN) 5 400 MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs

REFIN CHARACTERISTICS

REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

2

0.8 VDD V p-p Biased at AVDD/2

3

REFIN Input Capacitance 10 pF
REFIN Input Current ±100 μA

PHASE DETECTOR

Phase Detector Frequency

4

104 MHz ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP Programmable, see Figure 18

ICP Sink/Source

High Value 5 mA With R

= 5.1 kΩ

SET

Low Value 625 μA
Absolute Accuracy 2.5 % With R
R

Range 3.0 11 kΩ See Figure 18

SET

= 5.1 kΩ

SET

ICP Three-State Leakage 1 nA TA = 25°C
ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ VP − 0.5 V
Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 V
VIL, Input Low Voltage 0.6 V
I

, I

, Input Current ±1 μA

INH

INL

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 V CMOS output chosen
IOH 100 μA
VOL, Output Low Voltage 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 2.7 3.3 V
DVDD AVDD
VP AVDD 5.5 V AVDD ≤ VP ≤ 5.5 V

5

I

(AIDD + DIDD) 5.0 6.0 mA

DD

IP 0.4 mA TA = 25°C
Power-Down Mode 1 μA AIDD + DIDD

NOISE CHARACTERISTICS

− 10logF

6

−222 dBc/Hz

− 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the

PFD

Normalized Phase Noise Floor

1

Operating temperature range (B version) is −40°C to +85°C.

2

AVDD = DVDD = 3 V.

3

AC coupling ensures AVDD/2 bias.

4

Guaranteed by design. Sample tested to ensure compliance.

5

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN

frequency in MHz.

6

The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)

and 10logF
EVAL-ADF4002EB1 and the HP8644B as the PLL reference.

. PN

SYNTH

= PN

TOT

PFD

Rev. A | Page 3 of 20

ADF4002

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TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

1

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MAX

to T

MIN

,

Table 2.

Parameter Limit (B Version)

2

Unit Test Conditions/Comments

t1 10 ns min DATA to CLK setup time
t2 10 ns min DATA to CLK hold time
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
t6 20 ns min LE pulse width

1

Guaranteed by design, but not production tested.

2

Operating temperature range (B version) is −40°C to +85°C.

Timing Diagram

t

t

3

4

CLK

DATA

LE

LE

DB23 (MSB)

t

t

1

2

DB22

DB2

DB1 (CONTR OL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

06052-022

Rev. A | Page 4 of 20

ADF4002

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.6 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

THERMAL CHARACTERISTICS

Table 4. Thermal Impedance

Package Type θJA Unit

TSSOP 150.4 °C/W
LFCSP 122 °C/W

ESD CAUTION

Rev. A | Page 5 of 20

ADF4002

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

DD

R

SET

CP

CPGND

AGND

RFINB

RF

IN

AV

REF

A

DD

IN

1

INDICATO R

2

3

4

ADF4002

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT

LE

DATA

CLK

CE

DGND

PIN 1

Figure 3. TSSOP Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 19 R

SET

Connecting a resistor between this pin and CPGND sets the max
nominal voltage potential at the R

I

MAXCP

2 20 CP

where R
Charge Pump Output. When enabled, this provides ±I

= 5.1 kΩ and I

SET

external VCO.
3 1 CPGND
4 2, 3 AGND
5 4 RF

B

IN

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the RF input.

Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 11.
6 5 RF
7 6, 7 AV

A Input to the RF Input. This small signal input is ac-coupled to the external VCO.

IN

DD

Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to the AV
8 8 REF

IN

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can

be ac

-coupled.
9 9, 10 DGND
10 11 CE

Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2.

11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.

13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches; the latch is selected using the control bits.

14 15 MUXOUT

Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.

15 16, 17 DV

DD

Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV

16 18 V

P

Charge Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.

CPGND 1

AGND 2
AGND 3
RFINB

4

RF

5

A

IN

06052-002

Figure 4. LFCSP Pin Configuration (Top View)

pin is 0.66 V. The relationship between ICP and R

SET

25.5

=

R

SET

= 5 mA.

CP MAX

to the external loop filter that, in turn, drives the

CP

pin. AVDD must be the same value as DVDD.

DD

must be the same value as AVDD.

DD

SETVP

DV

R

DV

20 CP

191817

16

PIN 1
INDICATOR

ADF4002

TOP VIEW

(Not to Scale)

6

7

DD

DD

AV

AV

8

REF

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

IN

6052-003

DGND 9

DGND 10

imum charge pump output current. The

is

SET

/2 and a dc equivalent input

DD

. In systems where VDD is 3 V, it can

DD

Rev. A | Page 6 of 20

ADF4002

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TYPICAL PERFORMANCE CHARACTERISTICS

0

–5

–10

–15

–20

POWER (dBm)

+85°C

–25

–30

–35

–40

0 100 200 300 400 500 600

+25°C

–40°C

FREQUENCY (MHz )

Figure 5. RF Input Sensitivity

06052-027

130

–135

–140

–145

–155

–160

–165

PHASE NOISE ( dBc/Hz)

–170

–175

–180

100k 1M 10M 100M 1G

PFD FREQUENCY (Hz)

Figure 8. Phase Noise (Referred to CP Output) vs. PFD Frequency

06052-033

0

–5

–10

–15

POWER (dBm)

–20

–25

012345 109687

–40°C

+25°C

+85°C

FREQUENCY (MHz)

Figure 6. RF Input Sensitivity, Low Frequency

70

–80

–90

–100

–110

–120

–130

PHASE NOISE (d Bc/Hz)

–140

–150

–160

1k 10k 100k 1M 10M

FREQUENCY OFFSET (Hz)

rms NOISE = 0. 07 DEGREES

Figure 7. Integrated Phase Noise (400 MHz, 1 MHz, 50 kHz)

REF –4dBm
SAMP LOG 10dB/

0

–10

–20

–30

–40

–50

–60

–70

–80

06052-026

–90

–100

–94.5dBc

1

CENTER 399.995MHz
RES BW 20kHz

ATTN 10dB

1R

VBW 20kHz

MKR1 1.000 MHz

–94.5dBc

SPAN 2.2MHz

SWEEP 21ms (601p ts)

06052-030

Figure 9. Reference Spurs (400 MHz, 1 MHz, 7 kHz)

06052-031

Rev. A | Page 7 of 20

ADF4002

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THEORY OF OPERATION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOW N

CONTROL

100kΩ

NC

REF

SW2

IN

NC

SW1

SW3

NO

Figure 10. Reference Input Stage

BUFFER

TO R COUNTER

RF INPUT STAGE

The RF input stage is shown in Figure 11. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the N counter.

RFINA

RF

IN

BIAS

GENERATOR

B

Figure 11. RF Input Stage

500Ω

1.6V

500Ω

AV

AGND

DD

06052-014

N COUNTER

The N CMOS counter allows a wide ranging division ratio in
the PLL feedback counter. Division ratios from 1 to 8191 are
allowed.

N and R Relationship

The N counter makes it possible to generate output frequencies
that are spaced only by the reference frequency divided by R.

06052-013

The equation for the VCO frequency is

VCO

×=

R

f

REFIN

Nf

where:

is the output frequency of external voltage controlled

f

VCO

oscillator (VCO).

N is the preset divide ratio of binary 13-bit counter (1 to 8191).
f

is the external reference frequency oscillator.

REFIN

FROM N

COUNTER LATCH

FROM RF

INPUT STAGE

13-BIT N

COUNTER

TO PFD

06052-021

Figure 12. N Counter

R COUNTER

The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 13 is a simplified schematic.
The P

FD includes a programmable delay element that controls
the width of the antibacklash pulse. This pulse ensures that
there is no dead zone in the PFD transfer function, and
minimizes phase noise and reference spurs. Two bits in the
reference counter latch (ABP2 and ABP1) control the width of
the pulse. See

ulse width is not recommended.

p

R DIVIDER

Figure 16 for details. The smallest antibacklash

UP

HI

Q1

U1

CLR1

PROGRAMMABLE

ABP2

DELAY

U3

ABP1

P

CHARGE

PUMP

CP

Rev. A | Page 8 of 20

CLR2

HID1D2

N DIVIDER

DOWN

Q2

U2

Figure 13. PFD Simplified Schematic and Timing (In Lock)

CPGND

06052-023

ADF4002

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MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4002 allows the user to
access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch.

Figure 18 shows the full truth table. Figure 14 shows the

OUT section in block diagram form.

MUX

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.

Digital lock detect is active high. When LDP in the R counter
la

tch is set to 0, digital lock detect is set high when the phase
error on three consecutive phase detector (PD) cycles is less
than 15 ns. With LDP set to 1, five consecutive cycles of less
than 15 ns are required to set the lock detect. It stays set at high
until a phase error of greater than 25 ns is detected on any
subsequent PD cycle. For PFD frequencies greater than 10 MHz,

MUX

Figure 14. MUXOUT Circuit

CONTROL

MUXOUT

DGND

06052-024

analog lock detect is more accurate because of the smaller pulse
widths.

The N-channel, open-drain, analog lock detect should be

erated with an external pull-up resistor of 10 kΩ nominal.

op
When lock has been detected, this output is high with narrow,
low going pulses.

INPUT SHIFT REGISTER

The ADF4002 digital section includes a 24-bit input shift
register, a 14-bit R counter, and a 13-bit N counter. Data is
clocked into the 24-bit shift register on each rising edge of CLK.
The data is clocked in MSB first. Data is transferred from the
shift register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs, DB1
and DB0, as shown in the timing diagram (see
p

rovides the truth table for these bits. Figure 15 shows a

summa

ry of how the latches are programmed.

Table 6. C2, C1 Truth Table

Control Bits

C2 C1

0 0 R Counter
0 1 N Counter
1 0 Function Latch
1 1 Initialization Latch

Data Latch

Figure 2). Tabl e 6

Rev. A | Page 9 of 20

ADF4002

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LATCH MAPS AND DESCRIPTIONS

LATCH SUMMARY

REFERENCE COUNTER LATCH

RESERVED

00X

RESERVED

RESERVED

DB22DB23

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB 11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21DB22DB23

XX

G1

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

CURRENT

SETTING

CPI3CPI4

13-BIT N COUNT ER

1

N COUNTER LATCH

FUNCTION LATCH

TIMER COUNT ER

CONTROL

TC3 TC2 TC1

14-BIT REFE RENCE COUNTER

R6

R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

B1B2B3B4B5B6B7B8B9B10B11B12B13 XXXXXX

MODE

ENABLE

FAST LOCK

FASTLOCK

F4F5

CP THREE-

PD

STATE

POLARITY

RESERVED

MUXOUT

CONTROL

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5

CONTROL

BITS

C2 (0)

C1 (1)

CONTROL

BITS

RESET

POWER-

DOWN 1

COUNTER

C2 (1) C1 (0)F1PD1M1M2M3F3XXCPI1CPI2CPI5CPI6 TC4PD2 F2

INITIALIZATION LATCH

RESERVED

DB21

DB22DB23

XXCPI1CPI2

CURRENT

SETTING

POWER-

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

CPI5

CPI6 TC4PD2

CPI3CPI4

CURRENT

SETTING

1

TIMER COUNTER

CONTROL

TC3 TC2 TC1

Figure 15. Latch Summary

Rev. A | Page 10 of 20

RESET

COUNTER

F1PD1M1M2M3

CONTROL

BITS

C2 (1) C1 (1)

06052-015

MODE

ENABLE

FAST LOCK

FAST LOCK

F4F5

PD

STATE

CP THREE-

D

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

B

8

F3

F2

MUXOUT

CONTROL

POLARITY

POWER-

DOWN 1

ADF4002

www.BDTIC.com/ADI

REFERENCE COUNTER LATCH MAP

RESERVED

X

X

= DON’T CARE

DB21DB22DB23

00

TEST

MODE BITS

LOCK

DETECT

PRECISION

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

R14 R13 R12 .......... R3 R2 R1

0 0 0 .......... 0 0 1 1

0 0 0 .......... 0 1 0 2

0 0 0 .......... 0 1 1 3

0 0 0 .......... 1 0 0 4

. . . .......... . . . .

. . . .......... . . . .

. . . .......... . . . .

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

ABP2 ABP1
0 0 2.9n s
0 1 NOT AL LOWED
1 0 6.0n s
1 1 2.9n s

ANTIBACKLASH PULSE WIDTH

14-BIT REFERE NCE COUNTER

CONTROL

BITS

C2 (0) C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1ABP2T1T2LDP

DIVIDE RATIO

LDP

0

1

BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.

TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.

OPERATION

THREE CONSECUT IVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LO CK DETECT IS SET.
FIVE CONSECUTIVE CYCL ES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LO CK DETECT IS SET.

Figure 16. Reference Counter Latch Map

06052-025

Rev. A | Page 11 of 20

ADF4002

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N COUNTER LATCH MAP

RESERVED

DB22DB23

XX

13-BIT N COUNTE R

CP GAIN

DB21

G1

DB19

DB20

X = DON’T CARE

N13 N12 N11 N3 N2 N1

0 0 0 .......... 0 0 0

0 0 0 .......... 0 0 1

0 0 0 .......... 0 1 0

0 0 0 .......... 0 1 1

. . . .......... . . .

. . . .......... . . .

. . . .......... . . .

1 1 1 .......... 1 0 0

1 1 1 .......... 1 0 1

1 1 1 .......... 1 1 0

1 1 1 .......... 1 1 1

DB18 DB17

DB16 DB15 DB14

DB13 DB12 DB 11

DB10 DB9

N COUNTER DIVIDE RATIO

NOT ALLOWED
1
2
3
.

.
.
8188
8189
8190

8191

DB8

DB7

DB6

RESERVED

DB5

DB4 DB3

CONTROL

DB2 DB1

C2 (0) C1 (1)B1B2B3B4B5B6B7B8B9B10B11B12B13 XXXXXX

BITS

DB0

F4 (FUNCTION LATCH)
FASTLOCK ENA BLE

00

0

1

11

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BI TS.

OPERATIONCP GAIN

CHARGE PUMP CURRENT

1

0

SETTING 1 IS PERMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.

CHARGE PUMP CURRENT
SETTING 1 IS USED.

CHARGE PUMP CURRENT IS
SWITCHED TO SETT ING 2. T HE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BI TS.

06052-016

Figure 17. N Counter Latch Map

Rev. A | Page 12 of 20

ADF4002

www.BDTIC.com/ADI

FUNCTION LATCH MAP

RESERVED

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1

00003
00017

001011
001115

010019
010123
011027
011131

100035
100139
101043

101147
110051
110155
111059

111163

TIMER COUNT ER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FAST LOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

ENABLE

CP THREE-

FAST LOC K

F4

CHARGE PUMP

F3

OUTPUT

NORMAL

0

THREE-STATE

1

FASTLOCK MODE

F5

X

FASTLOCK DISABL ED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

SEE PAGE 15

MUXOUT

PD

STAT E

F2

0
1

CONTROL

POLARITY

M2M3F3XX CPI1CPI2CPI5

PHASE DETECTOR
POLARITY

NEGATIVE
POSITIVE

M3 M2 M1

000
001

010
011
100
101

110
111

M1

POWER-

PD1

DOWN 1

COUNTER

F1

F1

0
1

CONTROL

BITS

RESET

C2 (1) C1 (0)

COUNTER
OPERATION

NORMAL
R COUNTER AND

N COUNTER
HELD IN RESET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HI GH)

N DIVIDER OUT PUT
DV

DD

R DIVIDER OUT PUT
N-CHANNEL O PEN-DRAIN
LOCK DETECT
SERIAL DATA O UTPUT

DGND

I

CPI6 CPI5 CP14

CPI3 CPI2 CPI1

000
001
010
011
100
101
110
111

CE PIN

0
1
101
111

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BIT S.

PD2 PD1 MODE

X
X0

3kΩ 5.1kΩ 11kΩ

1.088

2.176

3.264

4.352

5.440

6.528

7.616

8.704

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

CP

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

(mA)

Figure 18. Function Latch Map

Rev. A | Page 13 of 20

0.294

0.588

0.882

1.176

1.470

1.764

2.058

2.352

06052-017

ADF4002

www.BDTIC.com/ADI

INITIALIZATION LATCH MAP

RESERVED

DB22DB23

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CPI6

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1

00003
00017

001011
001115

010019
010123
011027
011131

100035
100139
101043

101147
110051
110155
111059

111163

TIMER COUNT ER

CONTROL

TC3 TC2 TC1

TC4PD2 F2

MODE

FAST LOCK

F5

F4

0
1
1

TIMEOUT
(PFD CYCLES)

SEE PAGE 16

STAT E

ENABLE

CP THREE-

FAST LOC K

F4

CHARGE PUMP

F3

OUTPUT

NORMAL

0

THREE-STATE

1

FASTLOCK MODE

F5

X

FASTLOCK DISABL ED

0

FASTLOCK MODE 1

1

FASTLOCK MODE 2

MUXOUT

PD

CONTROL

POLARITY

M2M3F3XXCPI1CPI2CPI5

PHASE DETECTOR

F2

POLARITY

0

NEGATIVE
POSITIVE

1

M3 M2 M1

000
001

010
011

100

101

110
111

M1

PD1

POWER-

DOWN 1

F1

0
1

COUNTER

F1

CONTROL

BITS

RESET

C2 (1) C1 (1)

COUNTER
OPERATION

NORMAL
R COUNTER AND

N COUNTER
HELD IN RESET

OUTPUT

THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HI GH)

N DIVIDER OUT PUT
DV

DD

R DIVIDER OUT PUT
N-CHANNEL O PEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT

DGND

I

CPI6 CPI5 CP14

CPI3 CPI2 CPI1

000
001
010
011
100
101
110
111

CE PIN

0
1
101
111

THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BIT S.

PD2 PD1 MODE

X
X0

3kΩ 5.1kΩ 11kΩ

1.088

2.176

3.264

4.352

5.440

6.528

7.616

8.704

ASYNCHRONOUS POWER-DOWN

X

NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN

CP

0.625

1.250

1.875

2.500

3.125

3.750

4.375

5.000

(mA)

0.294

0.588

0.882

1.176

1.470

1.764

2.058

2.352

Figure 19. Initialization Latch Map

Rev. A | Page 14 of 20

06052-036

ADF4002

www.BDTIC.com/ADI

FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch is
programmed. Figure 18 shows the input data format for

gramming the function latch.

pro

Counter Reset

DB2 (F1) is the counter reset bit. When this bit is set to 1, the
R counter and the N counter are reset. For normal operation,
set this bit to 0. Upon powering up, the F1 bit needs to be
disabled (set to 0). Then, the N counter resumes counting in
close alignment with the R counter (the maximum error is one
prescaler cycle).

Power-Down

DB3 (PD1) and DB21 (PD2) provide programmable power­down modes. These bits are enabled by the CE pin.

When the CE pin is low, the device is immediately disabled
r

egardless of the states of the PD2, PD1 bits.

In the programmed asynchronous power-down, the device
p

owers down immediately after latching a 1 into Bit PD1, with

the condition that Bit PD2 has been loaded with a 0.

In the programmed synchronous power-down, the device

ower-down is gated by the charge pump to prevent unwanted

p
frequency jumps. Once the power-down is enabled by writing
a 1 into Bit PD1 (on condition that a 1 has also been loaded to
Bit PD2), then the device enters power-down on the occurrence
of the next charge pump event.

When a power-down is activated (either in synchronous or
asy

nchronous mode, including a CE pin activated power-

down), the following events occur:

• A

ll active dc current paths are removed.

• The R

• The cha

• The dig

• The RFIN

• The r

• The i

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1 on
the ADF4002. Figure 18 shows the truth table.

Fastlock Enable Bit

DB9 of the function latch is the fastlock enable bit. Only when
this is 1 is fastlock enabled.

, N, and timeout counters are forced to their load

state conditions.

rge pump is forced into three-state mode.

ital lock detect circuitry is reset.

input is debiased.

eference input buffer circuitry is disabled.

nput register remains active and capable of loading

and latching data.

Fastlock Mode Bit

DB10 of the function latch is the fastlock mode bit. When
fastlock is enabled, this bit determines the fastlock mode to be
used. If the fastlock mode bit is 0, then Fastlock Mode 1 is
selected, and if the fastlock mode bit is 1, then Fastlock Mode 2
is selected.

Fastlock Mode 1

In this mode, the charge pump current is switched to the
contents of Current Setting 2. The device enters fastlock by
having a 1 written to the CP gain bit in the N counter latch. The
device exits fastlock by having a 0 written to the CP gain bit in
the AB counter latch.

Fastlock Mode 2

In this mode, the charge pump current is switched to the
contents of Current Setting 2. The device enters fastlock by
having a 1 written to the CP gain bit in the N counter latch. The
device exits fastlock under the control of the timer counter.
After the timeout period determined by the value in TC4 to
TC1, the CP gain bit in the N counter latch is automatically
reset to 0 and the device reverts to normal mode instead of
fastlock. See

Figure 18 for the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump
currents. The intent is to use the Current Setting 1 when the
RF output is stable and the system is in a static state. Current
Setting 2 is meant to be used when the system is dynamic and
in a state of change, that is, when a new output frequency is
programmed.

The normal sequence of events is as follows:

The user initially decides the referred charge pump currents.

or example, the choice can be 2.5 mA as Current Setting 1 and

F
5 mA as Current Setting 2.

At the same time, the decision must be made as to how long the

econdary current is to stay active before reverting to the

s
primary current. This is controlled by Timer Counter Control
Bit DB14 to Timer Counter Control Bit DB11 (TC4 to TC1) in
the function latch. See

To program a new output frequency, simply program the N

ounter latch with a new value for N. At the same time, the CP

c
gain bit can be set to 1. This sets the charge pump with the
value in CPI6 to CPI4 for a period of time determined by TC4
to TC1. When this time is up, the charge pump current reverts
to the value set by CPI3 to CPI1. At the same time, the CP gain
bit in the N counter latch is reset to 0 and is ready for the next
time that the user wishes to change the frequency.

Note that there is an enable feature on the timer counter. It is
ena

bled when Fastlock Mode 2 is chosen by setting the Fastlock

Mode Bit DB10 in the function latch to 1.

Figure 18 for the truth table.

Rev. A | Page 15 of 20

ADF4002

www.BDTIC.com/ADI

Charge Pump Currents

CPI3, CPI2, and CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the
charge pump. See

Figure 18 for the truth table.

PD Polarity

This bit sets the phase detector polarity bit (see Figure 18).

CP Three-State

This bit controls the CP output pin. Setting the bit high puts the
CP output into three-state. With the bit set low, the CP output
is enabled.

INITIALIZATION LATCH

The initialization latch is programmed when C2, C1 = 1, 1. This
is essentially the same as the function latch (programmed when
C2, C1 = 1, 0).

However, when the initialization latch is programmed there is

n additional internal reset pulse applied to the R and N

a
counters. This pulse ensures that the N counter is at load point
when the N counter data is latched and the device begins
counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE
p

in is high; PD1 bit is high; and PD2 bit is low), the internal
pulse also triggers this power-down. The prescaler reference
and the oscillator input buffer are unaffected by the internal
reset pulse, thereby maintaining close phase alignment when
counting resumes.

When the first N counter data is latched after initialization, the
in

ternal reset pulse is reactivated. However, successive AB

counter loads after this do not trigger the internal reset pulse.

Device Programming After Initial Power-Up

After initially powering up the device, there are three ways to
program the device.

Initialization Latch Method

1. Apply V

2. Pr

ogram the initialization latch (11 in two LSBs of input

word). Make sure that the F1 bit is programmed to 0.

3. C

onduct a function latch load (10 in two LSBs of the

control word). Make sure that the F1 bit is programmed to 0.

erform an R load (00 in two LSBs).

4. P

5. P

erform an N load (01 in two LSBs).

DD

.

When the initialization latch is loaded, the following occurs:

• The f

• A

• L

unction latch contents are loaded.

n internal pulse resets the R, N, and timeout counters to
load state conditions and three-states the charge pump.
Note that the prescaler band gap reference and the oscilla­tor input buffer are unaffected by the internal reset pulse,
allowing close phase alignment when counting resumes.

atching the first N counter data after the initialization
word activates the same internal reset pulse. Successive N
loads do not trigger the internal reset pulse unless there is
another initialization.

CE Pin Method

1. Apply V

2. Br

asynchronous power-down because it happens immediately.

rogram the function latch (10).

3. P

4. P

rogram the R counter latch (00).

5. Pr

6. B

ring CE high to take the device out of power-down. The
R and N counters resume counting in close alignment.
Note that after CE goes high, a duration of 1 μs can be
required for the prescaler band gap voltage and oscillator
input buffer bias to reach steady state.

CE can be used to power the device up and down to check for

nnel activity. The input register does not need to be

cha
reprogrammed each time the device is disabled and enabled, as
long as it has been programmed at least once after V
initially applied.

.

DD

ing CE low to put the device into power-down. This is an

ogram the N counter latch (01).

was

DD

Counter Reset Method

1. Apply V

2. Do a f

step, load 1 to the F1 bit. This enables the counter reset.

erform an R counter load (00 in two LSBs).

3. P

4. P

erform an N counter load (01 in two LSBs).

5. Do a f

step, load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the
i

nitialization method. It offers direct control over the internal
reset. Note that counter reset holds the counters at load point
and three-states the charge pump, but does not trigger
synchronous power-down.

.

DD

unction latch load (10 in two LSBs). As part of this

unction latch load (10 in two LSBs). As part of this

Rev. A | Page 16 of 20

ADF4002

V

www.BDTIC.com/ADI

APPLICATIONS

VERY LOW JITTER ENCODE CLOCK FOR HIGH SPEED CONVERTERS

Figure 20 shows the ADF4002 with a VCXO to provide the
encode clock for a high speed analog-to-digital converter (ADC).

The converter used in this application is an AD9215-80, a 12-bit
co

nverter that accepts up to an 80 MHz encode clock. To realize
a stable low jitter clock, use a 77.76 MHz, narrow band VCXO.
This example assumes a 19.44 MHz reference clock.

To minimize the phase noise contribution of the ADF4002, the

mallest multiplication factor of 4 is used. Thus, the R divider is

s
programmed to 1, and the N divider is programmed to 4.

The charge pump output of the ADF4002 (Pin 2) drives the

op filter. The loop filter bandwidth is optimized for the best

lo
possible rms jitter, a key factor in the signal-to-noise ratio
(SNR) of the ADC. Too narrow a bandwidth allows the VCXO
noise to dominate at small offsets from the carrier frequency.
Too wide a bandwidth allows the ADF4002 noise to dominate at
offsets where the VCXO noise is lower than the ADF4002 noise.
Thus, the intersection of the VCXO noise and the ADF4002 in­band noise is chosen as the optimum loop filter bandwidth.

The design of the loop filter uses the ADIsimPLL (Version 3.0)

nd is available as a free download from www.analog.com/pll.

a
The r

ms jitter is measured at <1.2 ps. This level is lower than
the maximum allowable 6 ps rms required to ensure the
theoretical SNR performance of 59 dB for this converter.

The setup shown in Figure 20 using the ADF4002, AD9215, and
HSC-A

DC-EVALA-SC allows the user to quickly and effectively
determine the suitability of the converter and encode clock. The
SPI® interface is used to control the ADF4002, and the USB inter­face helps control the operation of the AD9215-80. The controller
board sends back FFT information to the PC that, if using an
ADC analyzer, provides all conversion results from the ADC.

SPI

TCXO:

19.44MHz

AGILENT:

500kHz, 1.8V p -p

ADF4002

R = 1

PD

N = 4

Figure 20. ADF4002 as Encode Clock

VCXO: 77.76MHz

ENCODE

CLOCK

A

IN

AD9215-80

PC

USB

HC-ADC-EVALA-SC

06052-034

PFD

As the ADF4002 permits both R and N counters to be pro­grammed to 1, the part can effectively be used as a standalone
PFD and charge pump. This is particularly useful in either a
clock cleaning application or a high performance LO. Addi­tionally, the very low normalized phase noise floor (−222 dBc/Hz)
enables very low in-band phase noise levels. It is possible to
operate the PFD up to a maximum frequency of 104 MHz.

In Figure 21, the reference frequency equals the PFD; therefore,
R = 1. The c

harge pump output integrates into a stable control
voltage for the VCXO, and the output from the VCXO is divided
down to the desired PFD frequency using an external divider.

DD

16

157

DD

AVDDDV

IN

ADF4002

CPGND

AGND

DGND

943

P

2

P

V

R

SET

RFINA

RF

IN

CE

B

LOOP

FILTER

1

10kΩ

100pF

6

5

51Ω

100pF

DECOUPLING CAPACITORS AND
INTERFACE S IGNALS HAVE BE EN
OMITT ED FROM THE DIAGRAM IN
THE INTERESTS OF GREATER
CLARITY.

Figure 21. ADF4002 as a PFD

V

CC

GND

V

CC

V

CC

EXTERNAL PRES CALER

GND

VCO

OR

VCXO

100pF

100pF

18Ω

RF

OUT

18Ω

18Ω

06052-035

REF

V

8

REF

IN

INTERFACING

The ADF4002 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When the latch enable (Pin LE) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of CLK are transferred to the appropriate latch. For more
information, see
th

e latch truth table.

The maximum allowable serial clock rate is 20 MHz. This
m

eans that the maximum update rate possible for the device is
833 kHz, or one update every 1.2 μs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.

Figure 2 for the timing diagram and Table 6 for

Rev. A | Page 17 of 20

ADF4002

www.BDTIC.com/ADI

ADuC812 Interface

Figure 22 shows the interface between the ADF4002 and the

ADuC812 MicroConverter®. Because the ADuC812 is based on

a

n 8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4002 needs a
24-bit word. This is accomplished by writing three 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, bring the LE input high to complete the
transfer.

On first applying power to the ADF4002, it needs four writes
(o

ne each to the initialization latch, function latch, R counter

latch, and N counter latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power-

wn (CE input) and to detect lock (MUXOUT configured as

do
lock detect and polled by the port input).

When operating in the SPI master mode, the maximum SCLOCK

te of the

ra
ra

te at which the output frequency can be changed is 166 kHz.

ADuC812 is 4 MHz. This means that the maximum

SCLOCK

MOSI

ADuC812

I/O PORTS

Figure 22. ADuC812 to ADF4002 Interface

CLK

DATA

ADF4002

LE

CE

MUXOUT
(LOCK DETECT )

06052-019

ADSP21xx Interface

Figure 23 shows the interface between the ADF4002 and the
ADSP21xx digital signal processor. The ADF4002 needs a
24-bit serial word for each latch write. The easiest way to accom­plish this using the ADSP21xx family is to use the autobuffered
transmit mode of operation with alternate framing. This provides
a means for transmitting an entire block of serial data before an

interrupt is generated. Set up the word length for eight bits and
use three memory locations for each 24-bit word. To program
each 24-bit latch, store the three 8-bit bytes, enable the
autobuffered mode, and then write to the transmit register of
the DSP. This last operation initiates the autobuffer transfer.

SCLK

DT

ADSP21xx

TFS

I/O FLAGS

Figure 23. ADSP21xx to ADF4002 Interface

CLK

DATA

ADF4002

LE

CE

MUXOUT
(LOCK DETECT )

06052-020

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the lead frame chip scale package (CP-20-1) are
rectangular. The printed circuit board pad for these should be

0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The land should be centered on
the pad. This ensures that the solder joint size is maximized.
The bottom of the lead frame chip scale package has a central
thermal pad.

The thermal pad on the printed circuit board should be at least

rge as this exposed pad. On the printed circuit board, there

as la
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.

Thermal vias can be used on the printed circuit board thermal

ad to improve thermal performance of the package. If vias are

p
used, they should be incorporated into the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm and the via barrel should be plated with 1 oz
copper to plug the via.

The user should connect the printed circuit board thermal pad
to

AGND.

Rev. A | Page 18 of 20

ADF4002

R

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.10

5.00

4.90

16

4.50

4.40

4.30

PIN 1

0.15

0.05

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 24. 16-Lead Thin Shrink S

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

mall Outline Package [TSSOP]

0.75

0.60

0.45

(RU-16)

Dimensions shown in millimeters

0.60

MAX

0.60

MAX

0.75

0.55

0.35

COPLANARITY

0.08

16

15

11

10

PIN 1

INDICATOR

20

5

6

0.30

0.23

0.18

1

2.25

2.10 SQ

1.95

0.25 MIN

PIN 1

INDICATO

1.00

0.85

0.80

SEATING

PLANE

12° MAX

4.00

BSC SQ

VIEW

0.50
BSC

TOP

0.80 MAX

0.65 TYP

0.20
REF

3.75

BCS SQ

0.05 MAX

0.02 NOM

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1

Figure 25. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

(CP-20-1)

Dim

ensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF4002BRUZ
ADF4002BRUZ-RL
ADF4002BRUZ-RL7
ADF4002BCPZ
ADF4002BCPZ-RL
ADF4002BCPZ-RL7
EVAL-ADF4002EBZ1
EVAL-ADF411XEBZ1

1

Z = RoHS Compliant Part.

1

1

1

1

1

1

1

1

−40°C to +85°C 16-Lead TSSOP RU-16

−40°C to +85°C 16-Lead TSSOP RU-16

−40°C to +85°C 16-Lead TSSOP RU-16

−40°C to +85°C 20-Lead LFCSP_VQ CP-20-1

−40°C to +85°C 20-Lead LFCSP_VQ CP-20-1

−40°C to +85°C 20-Lead LFCSP_VQ CP-20-1
Evaluation Board
Evaluation Board

Rev. A | Page 19 of 20

ADF4002

www.BDTIC.com/ADI

NOTES

©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06052-0-4/07(A)

Rev. A | Page 20 of 20