ANALOG DEVICES ADF4002 Service Manual

A

V

T

V

www.BDTIC.com/ADI

Phase Detector/Frequency Synthesizer

FEATURES

400 MHz bandwidth

2.7 V to 3.3 V power supply
Separate charge pump supply (V

tuning voltage in 3 V systems
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
104 MHz phase detector

APPLICATIONS

Clock conditioning
Clock generation
IF LO generation

REF

IN

CLK

DATA

LE

24-BIT INP UT

REGISTER

SD

OUT

) allows extended

P

DV

DD

DD

22

GENERAL DESCRIPTION

The ADF4002 frequency synthesizer is used to implement local
oscillators in the upconversion and downconversion sections of
wireless receivers and transmitters. It consists of a low noise
digital phase frequency detector (PFD), a precision charge
pump, a programmable reference divider, and programmable
N divider. The 14-bit reference counter (R counter) allows
selectable REFIN frequencies at the PFD input. A complete
phase-locked loop (PLL) can be implemented if the synthesizer
is used with an external loop filter and voltage controlled
oscillator (VCO). In addition, by programming R and N to 1,
the part can be used as a standalone PFD and charge pump.

FUNCTIONAL BLOCK DIAGRAM

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

P

PHASE

FREQUENCY

DETECTOR

LOCK

DETECT

CPGND

CPI3 CPI2 CPI1

AV

DD

SD

OUT

CURRENT

SETTING 1

MUX

REFERENCE

CHARGE

PUMP

CPI6 CPI5 CPI 4

R

CURRENT

SETTING 2

HIGH Z

ADF4002

SET

CP

MUXOU

RFINA
RF

IN

B

CE

AGND

N COUNTER

DGND

13-BIT

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

M3 M2 M1

ADF4002

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

06052-001

ADF4002

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ........................................................................ 8

Reference Input Section............................................................... 8

RF Input Stage............................................................................... 8

N Counter...................................................................................... 8

R Counter ...................................................................................... 8

Phase Frequency Detector (PFD) and Charge Pump.............. 8

MUXOUT and Lock Detect.........................................................9

Input Shift Register .......................................................................9

Latch Maps and Descriptions ....................................................... 10

Latch Summary........................................................................... 10

Reference Counter Latch Map.................................................. 11

N Counter Latch Map................................................................ 12

Function Latch Map................................................................... 13

Initialization Latch Map ............................................................ 14

Function Latch............................................................................ 15

Initialization Latch..................................................................... 16

Applications..................................................................................... 17

Very Low Jitter Encode Clock for High Speed Converters... 17

PFD............................................................................................... 17

Interfacing ................................................................................... 17

PCB Design Guidelines for Chip Scale Package .................... 18

Outline Dimensions....................................................................... 19

Ordering Guide .......................................................................... 19

REVISION HISTORY

4/07—Rev. 0 to Rev. A

Changes to Features List.................................................................. 1

Changes to Table 1............................................................................ 3

Deleted Figure................................................................................... 7

Changes to Figure 16...................................................................... 11

4/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADF4002

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SPECIFICATIONS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
T

= T

to T

A

MAX

, unless otherwise noted.

MIN

= 5.1 kΩ, dBm referred to 50 Ω,

SET

Table 1.

B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

RF CHARACTERISTICS See Figure 11 for input circuit

RF Input Sensitivity −10 0 dBm
RF Input Frequency (RFIN) 5 400 MHz For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/μs

REFIN CHARACTERISTICS

REFIN Input Frequency 20 300 MHz For REFIN < 20 MHz, ensure SR > 50 V/μs
REFIN Input Sensitivity

2

0.8 VDD V p-p Biased at AVDD/2

3

REFIN Input Capacitance 10 pF
REFIN Input Current ±100 μA

PHASE DETECTOR

Phase Detector Frequency

4

104 MHz ABP = 0, 0 (2.9 ns antibacklash pulse width)

CHARGE PUMP Programmable, see Figure 18

ICP Sink/Source

High Value 5 mA With R

= 5.1 kΩ

SET

Low Value 625 μA
Absolute Accuracy 2.5 % With R
R

Range 3.0 11 kΩ See Figure 18

SET

= 5.1 kΩ

SET

ICP Three-State Leakage 1 nA TA = 25°C
ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ VP − 0.5 V
Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ VP − 0.5 V
ICP vs. Temperature 2 % VCP = VP/2

LOGIC INPUTS

VIH, Input High Voltage 1.4 V
VIL, Input Low Voltage 0.6 V
I

, I

, Input Current ±1 μA

INH

INL

CIN, Input Capacitance 10 pF

LOGIC OUTPUTS

VOH, Output High Voltage 1.4 V Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V
VOH, Output High Voltage VDD − 0.4 V CMOS output chosen
IOH 100 μA
VOL, Output Low Voltage 0.4 V IOL = 500 μA

POWER SUPPLIES

AVDD 2.7 3.3 V
DVDD AVDD
VP AVDD 5.5 V AVDD ≤ VP ≤ 5.5 V

5

I

(AIDD + DIDD) 5.0 6.0 mA

DD

IP 0.4 mA TA = 25°C
Power-Down Mode 1 μA AIDD + DIDD

NOISE CHARACTERISTICS

− 10logF

6

−222 dBc/Hz

− 20logN. All phase noise measurements were performed with an Agilent E5500 phase noise test system, using the

PFD

Normalized Phase Noise Floor

1

Operating temperature range (B version) is −40°C to +85°C.

2

AVDD = DVDD = 3 V.

3

AC coupling ensures AVDD/2 bias.

4

Guaranteed by design. Sample tested to ensure compliance.

5

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25°C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN

frequency in MHz.

6

The normalized phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value)

and 10logF
EVAL-ADF4002EB1 and the HP8644B as the PLL reference.

. PN

SYNTH

= PN

TOT

PFD

Rev. A | Page 3 of 20

ADF4002

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TIMING CHARACTERISTICS

AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
unless otherwise noted.

1

= 5.1 kΩ, dBm referred to 50 Ω, TA = T

SET

MAX

to T

MIN

,

Table 2.

Parameter Limit (B Version)

2

Unit Test Conditions/Comments

t1 10 ns min DATA to CLK setup time
t2 10 ns min DATA to CLK hold time
t3 25 ns min CLK high duration
t4 25 ns min CLK low duration
t5 10 ns min CLK to LE setup time
t6 20 ns min LE pulse width

1

Guaranteed by design, but not production tested.

2

Operating temperature range (B version) is −40°C to +85°C.

Timing Diagram

t

t

3

4

CLK

DATA

LE

LE

DB23 (MSB)

t

t

1

2

DB22

DB2

DB1 (CONTR OL

BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Figure 2. Timing Diagram

06052-022

Rev. A | Page 4 of 20

ADF4002

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.6 V
AVDD to DVDD −0.3 V to +0.3 V
VP to GND −0.3 V to +5.8 V
VP to AVDD −0.3 V to +5.8 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VP + 0.3 V
REFIN, RFINA, RFINB to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C
Transistor Count

CMOS 6425

Bipolar 303

1

GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

This device is a high performance RF integrated circuit with an
ESD rating of <2 kV, and it is ESD sensitive. Proper precautions
should be taken for handling and assembly.

THERMAL CHARACTERISTICS

Table 4. Thermal Impedance

Package Type θJA Unit

TSSOP 150.4 °C/W
LFCSP 122 °C/W

ESD CAUTION

Rev. A | Page 5 of 20

ADF4002

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DD

DD

R

SET

CP

CPGND

AGND

RFINB

RF

IN

AV

REF

A

DD

IN

1

INDICATO R

2

3

4

ADF4002

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT

LE

DATA

CLK

CE

DGND

PIN 1

Figure 3. TSSOP Pin Configuration (Top View)

Table 5. Pin Function Descriptions

Pin No.

TSSOP LFCSP Mnemonic Description

1 19 R

SET

Connecting a resistor between this pin and CPGND sets the max
nominal voltage potential at the R

I

MAXCP

2 20 CP

where R
Charge Pump Output. When enabled, this provides ±I

= 5.1 kΩ and I

SET

external VCO.
3 1 CPGND
4 2, 3 AGND
5 4 RF

B

IN

Charge Pump Ground. This is the ground return path for the charge pump.

Analog Ground. This is the ground return path of the RF input.

Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small

bypass capacitor, typically 100 pF. See Figure 11.
6 5 RF
7 6, 7 AV

A Input to the RF Input. This small signal input is ac-coupled to the external VCO.

IN

DD

Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground

plane should be placed as close as possible to the AV
8 8 REF

IN

Reference Input. This is a CMOS input with a nominal threshold of V

resistance of 100 kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can

be ac

-coupled.
9 9, 10 DGND
10 11 CE

Digital Ground.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

state mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2.

11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into
the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a
high impedance CMOS input.

13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of
the four latches; the latch is selected using the control bits.

14 15 MUXOUT

Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to
be accessed externally.

15 16, 17 DV

DD

Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane
should be placed as close as possible to this pin. DV

16 18 V

P

Charge Pump Power Supply. This should be greater than or equal to V
be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.

CPGND 1

AGND 2
AGND 3
RFINB

4

RF

5

A

IN

06052-002

Figure 4. LFCSP Pin Configuration (Top View)

pin is 0.66 V. The relationship between ICP and R

SET

25.5

=

R

SET

= 5 mA.

CP MAX

to the external loop filter that, in turn, drives the

CP

pin. AVDD must be the same value as DVDD.

DD

must be the same value as AVDD.

DD

SETVP

DV

R

DV

20 CP

191817

16

PIN 1
INDICATOR

ADF4002

TOP VIEW

(Not to Scale)

6

7

DD

DD

AV

AV

8

REF

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

IN

6052-003

DGND 9

DGND 10

imum charge pump output current. The

is

SET

/2 and a dc equivalent input

DD

. In systems where VDD is 3 V, it can

DD

Rev. A | Page 6 of 20