ANALOG DEVICES ADF 4001 BRUZ Datasheet

a

2013

781/461-3113

B

200 MHz Clock Generator PLL

ADF4001

FEATURES
200 MHz Bandwidth

2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/

ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM

FUNCTIONAL BLOCK DIAGRAM

AV

DV

DD

DD

GENERAL DESCRIPTION

The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REF

IN

frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an exter­nal loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.

V

CPGND

P

R

SET

ADF4001

REF

IN

CLK

DATA

LE

RFINA

RF

B

IN

REV.

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

24-BIT

INPUT REGISTER

SD

OUT

22

CE AGND DGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

13

13-BIT

N COUNTER

REFERENCE

PHASE

FREQUENCY

DETECTOR

LOCK DETECT

CPI3

AV

DD

SD

OUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: © Analog Devices, Inc. All rights reserved.

CURRENT
SETTING 1

CPI2

MUX

M3

CHARGE

PUMP

CPI1

M2

M1

CURRENT
SETTING 2

CPI6

CPI5

HIGH Z

CP

CPI4

MUXOUT

ADF4001* Product Page Quick Links

Comparable Parts

View a parametric search of comparable parts

Evaluation Kits

• ADF4001 Evaluation Board

Documentation

Application Notes

• AN-30: Ask the Applications Engineer - PLL Synthesizers

• AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers

Data Sheet

• ADF4001: 200 MHz Clock Generator PLL Data Sheet

User Guides

• UG-092: The PLL Frequency Synthesizer Evaluation Board
for the ADF4001

• UG-476: PLL Software Installation Guide

Software and Systems Requirements

• Integer-N Software

• ADF4001 FMC-SDP Interposer & Evaluation Board /
Xilinx KC705 Reference Design

• BeMicro FPGA Project for ADF4001 with Nios driver

Tools and Simulations

• ADIsimPLL™

• ADIsimRF

Last Content Update: 08/30/2016

Reference Materials

Analog Dialogue

• Ask the Applications Engineer—30: PLL SYNTHESIZERS

• Phase-locked loops for high-frequency receivers and
transmitters

Technical Articles

• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1

• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3

• Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2

Design Resources

• ADF4001 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Discussions

View all ADF4001 EngineerZone Discussions

Sample and Buy

Visit the product page to see pricing options

Technical Support

Submit a technical question or find your regional support
number

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.

ADF4001–SPECIFICATIONS

B

CPGND = 0 V; R

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit

RF Input Frequency 5/165 MHz min/max
RF Input Sensitivity –10/0 dBm min/max

RF CHARACTERISTICS (5 V)

RF Input Frequency 10/200 MHz min/max –5/0 dBm min/max

REF

CHARACTERISTICS See Figure 2 for Input Circuit

IN

REF

IN

REF

IN

REF

IN

REFIN Input Current ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

I

Sink/Source Programmable: See Table V

CP

High Value 5 mA typ With R
Low Value 625 µA typ
Absolute Accuracy 2.5 % typ With R
R

SET

I

Three-State Leakage Current 1 nA typ

CP

Sink and Source Current Matching 2 % typ 0.5 V ≤ V
I

vs. V

CP

ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 0.8 × DV

INH

V

, Input Low Voltage 0.2 × DV

INL

I

INH/IINL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min IOH = 500 µA
VOL, Output Low Voltage 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV

DD

DV

DD

V

P

4

I

(AIDD + DIDD)

DD

ADF4001 5.5 mA max 4.5 mA typical

I

P

Low Power Sleep Mode 1 µA typ

NOISE CHARACTERISTICS

ADF4001 Phase Noise Floor

Phase Noise Performance

200 MHz Output

Spurious Signals

200 MHz Output

NOTES

1

Operating temperature range (B Version) is –40°C to +85°C.

2

AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels.

3

Guaranteed by design. Sample tested to ensure compliance.

4

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

6

The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer.

7

f

= 10 MHz; f

REF

IN

Specifications subject to change without notice.

= 4.7 k; TA = T

SET

MIN

to T

, unless otherwise noted; dBm referred to 50 .)

MAX

20/200 MHz min/max –10/0 dBm min/max

Input Frequency 5/104 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave

Input Sensitivity

2

–5 dBm min AC-Coupled. When DC-Coupled:

Input Capacitance 10 pF max

3

55 MHz max

Range 2.7/10 kΩ typ See Table V

CP

1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5

, Input Current ±1 µA max

2.7/5.5 V min/V max
AV

DD

AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V

0.4 mA max TA = 25°C

5

6

7

7

= 200 kHz; Offset Frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.

PFD

–161 dBc/Hz typ @ 200 kHz PFD Frequency
–153 dBc/Hz typ @ 1 MHz PFD Frequency

–99 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

–90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

DD

DD

(AV

= DVDD = 3 V  10%, 5 V  10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =

DD

(0 to V

0 to V

)

DD

Max (CMOS Compatible)

DD

= 4.7 kΩ

SET

= 4.7 kΩ

SET

≤ VP – 0.5

CP

V min
V max

@ VCXO Output

1

–2–

REV.

ADF4001

WARNING!

ESD SENSITIVE DEVICE

B

600

(AV

TIMING CHARACTERISTICS

R

= 4.7 k; TA = T

SET

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

Guaranteed by design but not production tested.
Specifications subject to change without notice.

MIN

to T

, unless otherwise noted; dBm referred to 50 .)

MAX

Limit at
T

to T

MIN

10 ns min DATA to CLOCK Setup Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Setup Time
20 ns min LE Pulsewidth

CLOCK

DATA

DB20

(MSB )

= DVDD = 3 V  10%, 5 V  10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V;

DD

MAX

t

t

3

4

t

t

1

2

DB19

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

t

6

LE

LE

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(

TA = 25°C, unless otherwise noted.)

1, 2

AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

P

V

to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V

IN

A to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± mV

RF

IN

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . .150°C

t

5

TSSOP θ
LFCSP θ
LFCSP θ

Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance (Paddle Soldered) . . 122°C/W

JA

Thermal Impedance (Paddle Not Soldered) 216°C/W

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high performance RF integrated circuit with an ESD rating of

<2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling and
assembly.

3

GND = AGND = DGND = 0 V.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV.

–3–

ADF4001

PIN CONFIGURATIONS

DD

1
2
3
4
5

SET

VPDVDDDV

CP

R

20

19

18

ADF4001

TOP VIEW

(Not to Scale)

8

6

7

IN

DD

AVDDAV

REF

LFCSP

DD

16

17

MUXOUT

15
14

LE

13

DATA

12

CLK
CE

11

9

10

DGND

DGND

/2 and a dc

. In systems

DD

02569-004

1

R

SET

2

CP

3

CPGND

4

IN

IN

B
A

DD

IN

ADF4001

TOP VIEW

5

(Not to S cale)

6

7

8

AGND

RF
RF

AV

REF

NOTES

1. TRANSIS TO R COUNT 6425 (CMOS)
AND 50 (BIPOL AR).

16

15

14

13

12

11

10

9

V

P

DV

DD

MUXOUT
LE
DATA
CLK
CE
DGND

CPGND

AGND
AGND

B

RF

IN

A

RF

IN

02569-003

NOTES

1. TRANSISTO R COUNT 6425 (CMOS) AND 50 (BIPOLAR).

2. CONNECT EX POSED PAD TO AGND.

TSSOP

Table 1. Pin Function Descriptions

TSSOP
Pin No.

1 19 R

2 20 CP

LFCSP
Pin No. Mnemonic Description

SET

Connecting a resistor between this pin and CPGND sets the maximum charge pump
output current. The nominal voltage potential at the R
between I

So, with R

CP

I

MAXCP

SET

Charge Pump Output. When enabled, this provides ±I

and R

SET

5.23



R

SET

= 4.7 kΩ, I

is

CP MAX

= 5 mA.

pin is 0.66 V. The relationship

SET

to the external loop filter which,

CP

in turn, drives the external VCO or VCXO.
3 1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler.
5 4 RFINB

Complementary Input to the N counter. This point must be decoupled to the ground

plane with a small bypass capacitor, typically 100 pF. See Figure 3.
6 5 RFINA Input to the N counter. This small signal input is ac-coupled to the external VCO or VCXO.
7 6, 7 AVDD

Analog Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the

analog ground plane should be placed as close as possible to this pin. AVDD must have the

.

DD

8 8 REFIN

same value as DV

Reference Input. This is a CMOS input with a nominal threshold of V

equivalent input resistance of 100 kΩ. See Figure 2. This input can be driven from a TTL

or CMOS crystal oscillator or can be ac-coupled.
9 9, 10 DGND Digital Ground.
10 11 CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump

output into three-state mode. Taking the pin high will power up the device, depending on

the status of the power-down bit F2.
11 12 CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The

data is latched into the 24-bit shift register on the CLK rising edge. This input is a high

impedance CMOS input.
12 13 DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control

bits. This input is a high impedance CMOS input.
13 14 LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is

loaded into one of the four latches, the latch being selected by using the control bits.
14 15 MUXOUT

This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference

frequency to be accessed externally.
15 16, 17 DVDD

Digital Power Supply. This ranges from 2.7 V to 5.5 V. Decoupling capacitors to the

digital ground plane should be placed as close as possible to this pin. DVDD must be the

.

DD

16 18 VP

same value as AV

Charge Pump Power Supply. This should be greater than or equal to V

where V

is 3 V, it can be set to 5 V and used to drive a VCO or VCXO with a tuning

DD

range of up to 5 V.
N/A EP EPAD Exposed Pad. The exposed pad should be connected to AGND.

Rev. B | Page 4

Typical Performance Characteristics–ADF4001

B

0

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

–35

0

TA = +25C

50 100 150 200 250

FREQUENCY – MHz

TPC 1. Input Sensitivity, V

0

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

0

510152025

FREQUENCY – MHz

TPC 2. Input Sensitivity, V

TA = +85C

TA = –40C

= 3.3 V, 100 pF on RF

DD

= 3.3 V, 100 pF on RF

DD

10dB/DIVISION R

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100

FREQUENCY OFFSET FROM 200MHz CARRIER – Hz

IN

IN

TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL =

–200kHz –100kHz 0200MHz 100kHz 200kHz

TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)

= –40dBc/Hz rms NOISE = 0.229 DEGREES

L

0.229 rms

1k 10k 100k 1M

VDD = 3V, VP = 5V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz

–5.7dBm

LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 300Hz
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2 SECONDS
AVERAGES = 20

–92.3dBc

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL =

–5.7dBm

–2kHz –1kHz 200MHz 1kHz 2kHz 0

VDD = 3V, VP = 5V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 26

–99.2dBc/Hz

TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)

REV.

–5–