Datasheet ADF4001BRU, ADF4001BCP Datasheet (Analog Devices)

a

200 MHz Clock Generator PLL

ADF4001

FEATURES
200 MHz Bandwidth

2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (V

) Allows Extended

P

Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware-Compatible to the ADF4110/ADF4111/

ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead Chip Scale Package

APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM

FUNCTIONAL BLOCK DIAGRAM

AV

ADF4001

DV

DD

DD

GENERAL DESCRIPTION

The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable refer­ence signals. It consists of a low-noise digital PFD (Phase
Frequency Detector), a precision charge pump, a programmable
reference divider, and a programmable 13-bit N counter. In
addition, the 14-bit reference counter (R Counter) allows
selectable REFIN frequencies at the PFD input. A complete
PLL (Phase-Locked Loop) can be implemented if the synthesizer
is used with an external loop filter and VCO (Voltage Controlled
Oscillator) or VCXO (Voltage Controlled Crystal Oscillator).
The N min value of 1 allows flexibility in clock generation.

V

CPGND

P

REFERENCE

R

SET

REF

CLK

DATA

RFINA

RF

IN

IN

24-BIT

INPUT REGISTER

LE

SD

OUT

B

22

CE AGND DGND

14-BIT

R COUNTER

14

R COUNTER

LATCH

FUNCTION

LATCH

N COUNTER

LATCH

13

13-BIT

N COUNTER

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

PHASE

FREQUENCY

DETECTOR

LOCK DETECT

CPI3

AV

DD

SD

OUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

CURRENT
SETTING 1

CPI2

MUX

M3

CHARGE

PUMP

CPI1

M2

M1

CURRENT
SETTING 2

CPI6

CPI5

HIGH Z

CP

CPI4

MUXOUT

ADF4001–SPECIFICATIONS

CPGND = 0 V; R

Parameter B Version Unit Test Conditions/Comments

RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit

RF Input Frequency 5/165 MHz min/max
RF Input Sensitivity –10/0 dBm min/max

RF CHARACTERISTICS (5 V)

RF Input Frequency 10/200 MHz min/max –5/0 dBm min/max

REFIN CHARACTERISTICS See Figure 2 for Input Circuit

REFIN Input Frequency 5/100 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave

REFIN Input Sensitivity

REFIN Input Capacitance 10 pF max
REFIN Input Current ± 100 µA max

PHASE DETECTOR

Phase Detector Frequency

CHARGE PUMP

Sink/Source Programmable: See Table V

I

CP

High Value 5 mA typ With R

Low Value 625 µA typ

Absolute Accuracy 2.5 % typ With R
R

SET

I

Three-State Leakage Current 1 nA typ

CP

Sink and Source Current Matching 2 % typ 0.5 V ≤ V
I

vs. V

CP

ICP vs. Temperature 2 % typ VCP = VP/2

LOGIC INPUTS

V

, Input High Voltage 0.8 × DV

INH

, Input Low Voltage 0.2 × DV

V

INL

I

INH/IINL

CIN, Input Capacitance 10 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min IOH = 500 µA
VOL, Output Low Voltage 0.4 V max IOL = 500 µA

POWER SUPPLIES

AV

DD

DV

DD

V

P

4

I

(AIDD + DIDD)

DD

ADF4001 5.5 mA max 4.5 mA typical

I

P

Low Power Sleep Mode 1 µA typ

NOISE CHARACTERISTICS

ADF4001 Phase Noise Floor

Phase Noise Performance

200 MHz Output

Spurious Signals

200 MHz Output

NOTES

1

Operating temperature range is as follows: B Version: –40°C to +85°C.

2

AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS-compatible levels.

3

Guaranteed by design. Sample tested to ensure compliance.

4

TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).

6

The phase noise is measured with the EVAL-ADF4001EB1 Evaluation Board and the HP8562E Spectrum Analyzer.

7

f

= 10 MHz; f

REFIN

Specifications subject to change without notice.

= 4.7 k; TA = T

SET

MIN

to T

unless otherwise noted; dBm referred to 50 )

MAX

20/200 MHz min/max –10/0 dBm min/max

2

3

–5 dBm min AC-Coupled. When DC-Coupled:

55 MHz max

Range 2.7/10 kΩ typ See Table V

CP

1.5 % typ 0.5 V ≤ VCP ≤ VP – 0.5

, Input Current ± 1 µA max

2.7/5.5 V min/V max
AV

DD

AVDD/6.0 V min/V max AVDD ≤ VP ≤ 6.0 V

0.4 mA max TA = 25°C

5

6

7

7

= 200 kHz; Offset frequency = 1 kHz; fRF = 200 MHz; N = 1000; Loop B/W = 20 kHz.

PFD

–161 dBc/Hz typ @ 200 kHz PFD Frequency
–153 dBc/Hz typ @ 1 MHz PFD Frequency

–99 dBc/Hz typ @ 1 kHz Offset and 200 kHz PFD Frequency

–90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency

DD

DD

(AV

= DVDD = 3 V  10%, 5 V  10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND =

DD

(0 to V

0 to V

)

DD

max (CMOS-Compatible)

DD

= 4.7 kΩ

SET

= 4.7 kΩ

SET

≤ VP – 0.5

CP

V min
V max

@ VCXO Output

1

–2–

REV. 0

ADF4001

WARNING!

ESD SENSITIVE DEVICE

(AV

TIMING CHARACTERISTICS

4.7 k; TA = T

Parameter (B Version) Unit Test Conditions/Comments

t

1

t

2

t

3

t

4

t

5

t

6

NOTES
Guaranteed by design but not production tested.
Specifications subject to change without notice.

MIN

to T

unless otherwise noted; dBm referred to 50 .)

MAX

Limit at
T

to T

MIN

10 ns min DATA to CLOCK Set Up Time
10 ns min DATA to CLOCK Hold Time
25 ns min CLOCK High Duration
25 ns min CLOCK Low Duration
10 ns min CLOCK to LE Set Up Time
20 ns min LE Pulsewidth

CLOCK

= DVDD = 3 V  10%, 5 V  10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V; R

DD

MAX

t

t

3

4

SET

=

DATA

t

DB20

(MSB)

LE

LE

t

1

2

DB19

Figure 1. Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(

TA = 25°C unless otherwise noted)

1, 2

AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to + 0.3 V

DD

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

P

V

to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V

P

Digital I/O Voltage to GND . . . . . . . . . –0.3 V to V

Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to V

REF

, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V

IN

RF

INA

to RF

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 320 mV

INB

+ 0.3 V

DD

+ 0.3 V

P

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . .150°C

DB2

(CONTROL BIT C2)

TSSOP θ
CSP θ

JA

CSP θ

JA

DB1

Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W

JA

Thermal Impedance (Paddle Soldered) . . . . 122°C/W

Thermal Impedance (Paddle Not Soldered) . . 216°C/W

DB0 (LSB)

(CONTROL BIT C1)

t

5

t

6

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

This device is a high-performance RF integrated circuit with an ESD rating of

< 2 kΩ and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.

3

GND = AGND = DGND = 0 V.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADF4001BRU –40°C to +85°C Thin Shrink Small Outline Package (TSSOP) RU-16
ADF4001BCP –40°C to +85°C Chip Scale Package* CP-20

*Contact factory for chip availability.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4001 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

ADF4001

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1R

SET

2 CP Charge Pump Output. When enabled, this provides ±I

3 CPGND Charge Pump Ground. This is the ground return path for the charge pump.
4 AGND Analog Ground. This is the ground return path of the prescaler.
5RF

6RF
7AV

8 REF

B Complementary Input to the N Counter. This point must be decoupled to the ground plane with a small

IN

A Input to the N Counter. This small signal input is ac-coupled to the external VCO or VCXO.

IN

DD

IN

9 DGND Digital Ground
10 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-

11 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into

12 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is

13 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of

14 MUXOUT This multiplexer output allows either the Lock Detect, the scaled RF, or the scaled Reference Frequency to

15 DV

16 V

DD

P

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The
nominal voltage potential at the R

So, with R

= 4.7 kΩ, I

SET

CP MAX

SET

= 5 mA.

pin is 0.66 V. The relationship between ICP and R

I

CP AX

23 5.

=

M

R

SET

to the external loop filter which, in turn, drives the

CP

SET

is

external VCO or VCXO.

bypass capacitor, typically 100 pF. See Figure 3.

Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AV

must be the same value as DV

DD

DD.

Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resis­tance of 100 kΩ. See Figure 2. This input can be driven from a TTL or CMOS crystal oscillator or can be
ac-coupled.

state mode. Taking the pin high will power up the device, depending on the status of the power-down bit F2.

the 24-bit shift register on the CLK rising edge. This input is a high-impedance CMOS input.

a high-impedance CMOS input.

the four latches, the latch being selected using the control bits.

be accessed externally.
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane

should be placed as close as possible to this pin. DV

must be the same value as AVDD.

DD

Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it
can be set to 5 V and used to drive a VCO or VCXO with a tuning range of up to 5 V.

TRANSISTOR COUNT

6425 (CMOS) and 50 (Bipolar).

R

SET

CP

CPGND

AGND

RF

IN

RF

IN

AV

REF

B

A

DD

IN

1

2

ADF4001

3

4

TOP VIEW

5

(Not to Scale)

6

7

8

PIN CONFIGURATIONS

V

16

P

DV

15

DD

MUXOUT

14

13

12

11

10

9

LE

DATA

CLK

CE

DGND

CPGND 1

AGND 2
AGND 3
RFINB 4

A 5

RF

IN

–4–

SET

20 CP

19 R

18 VP17 DVDD16 DV

PIN 1
INDICATOR

ADF4001

TOP VIEW

6

7

8

IN

DD

DD

AV

AV

REF

DD

DGND 9

DGND 10

15 MUXOUT
14 LE
13 DATA
12 CLK
11 CE

REV. 0

Typical Performance Characteristics–ADF4001

0

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

–35

0

TA = +25C

50 100 150 200 250

FREQUENCY – MHz

TPC 1. Input Sensitivity. V

0

–5

–10

–15

–20

AMPLITUDE – dBm

–25

–30

0

5 10152025

FREQUENCY – MHz

TPC 2. Input Sensitivity. V

TA = +85C

TA = –40C

= 3.3 V; 100 pF on RF

DD

= 3.3 V; 100 pF on RF

DD

10dB/DIVISION R

–40

–50

–60

–70

–80

–90

–100

–110

PHASE NOISE – dBc/Hz

–120

–130

–140

100

FREQUENCY OFFSET FROM 200MHz CARRIER – Hz

IN

IN

TPC 4. Integrated Phase Noise (200 MHz, 200 kHz, 20 kHz)

0

–10

REFERENCE LEVEL =

–200kHz –100kHz 0200MHz 100kHz 200kHz

OUTPUT POWER – dB

–100

–20

–30

–40

–50

–60

–70

–80

–90

TPC 5. Reference Spurs (200 MHz, 200 kHz, 20 kHz)

= –40dBc/Hz rms NOISE = 0.229 DEGREES

L

0.229 rms

1k 10k 100k 1M

VDD = 3V, VP = 5V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz

–5.7dBm

LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 300Hz
VIDEO BANDWIDTH = 300Hz
SWEEP = 4.2 SECONDS
AVERAGES = 20

–92.3dBc

0

–10

–20

–30

–40

–50

–60

–70

OUTPUT POWER – dB

–80

–90

–100

REFERENCE LEVEL =

–5.7dBm

–2kHz –1kHz 200MHz 1kHz 2kHz 0

VDD = 3V, VP = 5V

= 2.5mA

I

CP

PFD FREQUENCY = 200kHz
LOOP BANDWIDTH = 20kHz
RES. BANDWIDTH = 10Hz
VIDEO BANDWIDTH = 10Hz
SWEEP = 1.9 SECONDS
AVERAGES = 26

TPC 3. Phase Noise (200 MHz, 200 kHz, 20 kHz)

REV. 0

–99.2dBc/Hz

–5–

ADF4001

CIRCUIT DESCRIPTION
Reference Input Section

The reference input stage is shown in Figure 2. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF

IN

pin

on power-down.

POWER-DOWN

CONTROL

NC

100k

SW2

REF

NC

IN

SW1

SW3

NO

BUFFER

TO
R COUNTER

Figure 2. Reference Input Stage

RF Input Stage

The RF input stage is shown in Figure 3. It is followed by a
two-stage limiting amplifier to generate the CML clock levels
needed for the N Counter buffer.

2k

1.6V

2k

AV

DD

BIAS

GENERATOR

FROM

N COUNTER LATCH

FROM RF

INPUT STAGE

13-BIT N

COUNTER

TO PFD

Figure 4. N Counter

R Counter

The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE
PUMP

The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 5 is a simplified schematic. The
PFD includes a programmable delay element which controls the
width of the antibacklash pulse. This pulse ensures that there is
no deadzone in the PFD transfer function and minimizes phase
noise and reference spurs. Two bits in the Reference Counter
Latch, ABP2 and ABP1 control the width of the pulse. See
Table III.

V

P

CHARGE
PUMP

UP

D1

CLR1

Q1

U1

DELAY

U3

CP

HI

R DIVIDER

RF

A

IN

RFINB

AGND

Figure 3. RF Input Stage

N Counter

The N CMOS counter allows a wide ranging division ratio
in the PLL feedback counter. Division ratios of 1 to 8191
are allowed.

N and R Relationship

The N counter, in conjunction with the R Counter make it
possible to generate output frequencies that are spaced only by
the Reference Frequency divided by R. The equation for the
VCO frequency is as follows:

f

= N/R × f

f

VCO

VCO

Output Frequency of external voltage-controlled oscil-

REFIN

lator (VCO).

N Preset Divide Ratio of binary 13-bit counter (1 to 8,191).

f

External reference frequency oscillator.

REFIN

R Preset divide ratio of binary 14-bit programmable refer-

ence counter (1 to 16,383).

CLR2

DOWN

D2

HI

N DIVIDER

R DIVIDER

N DIVIDER

CP OUTPUT

Q2

U2

CPGND

Figure 5. PFD Simplified Schematic and Timing (In Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the Function
Latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.

–6–

REV. 0

DV

DD

ANALOG LOCK DETECT

DIGITAL LOCK DETECT

R COUNTER OUTPUT

N COUNTER OUTPUT

SDOUT

MUX

CONTROL MUXOUT

DGND

Figure 6. MUXOUT Circuit

Lock Detect

MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect. Digital lock detect is
active high. When LDP in the R counter latch is set to “0,” digital
lock detect is set high when the phase error on three consecutive
Phase Detector cycles is less than 15 ns. With LDP set to “1,” five
consecutive cycles of less than 15 ns are required to set the lock
detect. It will stay set high until a phase error of greater than

ADF4001

25 ns is detected on any subsequent PD cycle. The N-channel
open-drain analog lock detect should be operated with an external
pull-up resistor of 10 kΩ nominal. When lock has been detected,
this output will be high with narrow low-going pulses.

INPUT SHIFT REGISTER

The ADF4001 digital section includes a 24-bit input shift regis­ter, a 14-bit R counter, and a 13-bit N counter. Data is clocked
into the 24-bit shift register on each rising edge of CLK. The
data is clocked in MSB first. Data is transferred from the shift
register to one of four latches on the rising edge of LE. The
destination latch is determined by the state of the two control
bits (C2, C1) in the shift register. These are the two LSBs DB1,
DB0 as shown in the timing diagram of Figure 1. The truth
table for these bits is shown in Table I. Table II shows a sum­mary of how the latches are programmed.

Table I. C2, C1 Truth Table

Control Bits
C2 C1 Data Latch

0 0 R Counter
0 1 N Counter
1 0 Function Latch
1 1 Initialization Latch

RESERVED

DB21

DB22DB23

XXX

RESERVED

XX

RESERVED

XX

CP

GAIN

DB21

DB22DB23

POWER-

DB21

DB22DB23

Table II. ADF4001 Family Latch Summary

REFERENCE COUNTER LATCH

TEST

DETECT

PRECISION

MODE

BITS

T1

LOCK

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

ANTI-

BACKLASH

WIDTH

ABP2

R12 R11 R10

14-BIT REFERENCE COUNTER

R8R9

CONTROL

C2 (0) C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6

N -COUNTER

13-BIT N COUNTER

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

N10N11

N6 N5 N4

N2N3

RESERVED

CONTROL

C2 (0) C1 (1)N1N8N9N12N13 N7G1

FUNCTION LATCH

CPI3CPI4

CURRENT

SETTING

1

CURRENT

SETTING

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TIMER COUNTER

CONTROL

TC3 TC2 TC1

MODE

FASTLOCK

ENABLE

FASTLOCK

F4F5

CP

THREE-

STATE

PHASE

POLARITY

DETECTOR

MUXOUT

CONTROL

DOWN 1

POWER-

RESET

COUNTER

C2 (1) C1 (0)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

BITS

BITS

RESERVED

XX

X = DON’T CARE

REV. 0

INITIALIZATION LATCH

CPI3CPI4

CURRENT

SETTING

1

CURRENT

SETTING

DOWN 2

POWER-

DB21

DB22DB23

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

TIMER COUNTER

CONTROL

TC3 TC2 TC1

MODE

FASTLOCK

ENABLE

FASTLOCK

F4F5

CP

THREE-

STATE

PHASE

POLARITY

DETECTOR

MUXOUT

CONTROL

DOWN 1

POWER-

RESET

COUNTER

C2 (1) C1 (1)F1PD1M1M2M3F3CPI1CPI2CPI5CPI6 TC4PD2 F2

CONTROL

BITS

–7–

ADF4001

Table III. Reference Counter Latch Map

RESERVED

DB21

DB22DB23

XXX

X = DON’T CARE

TEST

MODE

LOCK

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DETECT

PRECISION

BITS

T1

ANTI-

BACKLASH

WIDTH

ABP2

ABP2 ABP1 ANTIBACKLASH PULSEWIDTH

002.9ns

011.3ns

106.0ns
1 1 2.9ns

R12 R11 R10

R14 R13 R12 .......... R3 R2 R1 DIVIDE RATIO

0 0 0 .......... 0011

0 0 0 .......... 0102

0 0 0 .......... 0113

0 0 0 .......... 1004

. . . .......... ....

. . . .......... ....

. . . .......... ....

1 1 1 .......... 1 0 0 16380

1 1 1 .......... 1 0 1 16381

1 1 1 .......... 1 1 0 16382

1 1 1 .......... 1 1 1 16383

14-BIT REFERENCE COUNTER

R8R9

CONTROL

BITS

C2 (0)

C1 (0)R1R2R3R4R5R7R14ABP1T2LDP R13 R6

TEST MODE BITS SHOULD

BE SET TO 00 FOR NORMAL

OPERATION

LDP OPERATION

0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

–8–

REV. 0

Table IV. N Counter Latch Map

ADF4001

RESERVED

CP GAIN

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DB21

DB22DB23

X

G1

X X

N13 N12 N11 N3 N2 N1 N COUNTER DIVIDE RATIO

0 0 0 .......... 0011

0 0 0 .......... 0102

0 0 0 .......... 0113

0 0 0 .......... 1004

. . . .......... ....

. . . .......... ....

. . . .......... ....

1 1 1 .......... 1 0 0 8188

1 1 1 .......... 1 0 1 8189

1 1 1 .......... 1 1 0 8190

1 1 1 .......... 1 1 1 8191

F4 (FUNCTION LATCH)
FASTLOCK ENABLE CP GAIN OPERATION

0 0 CHARGE PUMP CURRENT SETTING

0 1 CHARGE PUMP CURRENT SETTING

1 0 CHARGE PUMP CURRENT SETTING

1 1 CHARGE PUMP CURRENT IS

LATCH DESCRIPTION.

13-BIT N COUNTER

1 IS PERMANENTLY USED

2 IS PERMANENTLY USED

1 IS USED

SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK

MODE IS USED. SEE FUNCTION

N1N2N3N4N5N6N7N8N9N10N11N12N13

RESERVED

XXX X

X = DON’T CARE

C2 (0) C1 (1)

X

CONTROL

BITS

THESE BITS ARE NOT USED

BY THE DEVICE AND ARE

DON’T CARE BITS.

REV. 0

–9–

ADF4001

Table V. Function Latch Map

RESERVED

DB22DB23

X

X

X = DON’T CARE

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1 (PFD CYCLES)

00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

CPI1CPI2CPI5CPI6 TC4PD2

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TIMEOUT

MODE

FASTLOCK

F4 F5 FASTLOCK MODE

0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2

CP

STATE

THREE-

ENABLE

FASTLOCK

F4F5

F3 CHARGE PUMP OUTPUT

0 NORMAL

1 THREE-STATE

M3 M2 M1 OUTPUT

0 0 0 THREE-STATE OUTPUT
001DIGITAL LOCK DETECT
0 1 0 N DIVIDER OUTPUT
0 1 1 AVDD
1 0 0 R DIVIDER OUTPUT
1 0 1 N-CHANNEL OPEN-DRAIN

110SERIAL DATA OUTPUT
1 1 1 DGND

PHASE

POLARITY

DETECTOR

F2

PHASE DETECTOR
F2 POLARITY
0 NEGATIVE
1 POSITIVE

MUXOUT

CONTROL

DOWN 1

POWER-

PD1

M1M2M3F3

COUNTER
F1 OPERATION

0 NORMAL
1 R, N COUNTER

LOCK DETECT

CONTROL

RESET

COUNTER

C2 (1) C1 (0)

F1

HELD IN RESET

BITS

CPI6 CPI5 CP14 ICP (mA)

CPI3 CPI2 CPI1 2.7k 4.7k 10k

0 0 0 1.088 0.625 0.294
0 0 1 2.176 1.25 0.588
0 1 0 3.264 1.875 0.882
0 1 1 4.352 2.5 1.176
1 0 0 5.44 3.125 1.47
1 0 1 6.528 3.75 1.764
1 1 0 7.616 4.375 2.058
1 1 1 8.704 5.0 2.352

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
101ASYNCHRONOUS POWER-DOWN
111SYNCHRONOUS POWER-DOWN

–10–

REV. 0

Table VI. Initialization Latch Map

ADF4001

RESERVED

DB22DB23

XX

X = DON’T CARE

CURRENT

SETTING

POWER-

DB21

DOWN 2

2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

CURRENT

SETTING

1

CPI3CPI4

TC4 TC3 TC2 TC1 (PFD CYCLES)

00003
00017
001011
001115
010019
010123
011027
011131
100035
100139
101043
101147
110051
110155
111059
111163

CPI1CPI2CPI5CPI6 TC4PD2

TIMER COUNTER

CONTROL

TC3 TC2 TC1

TIMEOUT

MODE

FASTLOCK

F4 F5 FASTLOCK MODE

0 X FASTLOCK DISABLED
1 0 FASTLOCK MODE 1
1 1 FASTLOCK MODE 2

CP

STATE

THREE-

ENABLE

FASTLOCK

F4F5

F3 CHARGE PUMP OUTPUT

0 NORMAL

1 THREE-STATE

M3 M2 M1 OUTPUT

0 0 0 THREE-STATE OUTPUT
001DIGITAL LOCK DETECT
0 1 0 N DIVIDER OUTPUT
0 1 1 AVDD
1 0 0 R DIVIDER OUTPUT
1 0 1 N-CHANNEL OPEN-DRAIN

110SERIAL DATA OUTPUT
1 1 1 DGND

PHASE

POLARITY

DETECTOR

F2

PHASE DETECTOR
F2 POLARITY
0 NEGATIVE
1 POSITIVE

MUXOUT

CONTROL

DOWN 1

POWER-

PD1

M1M2M3F3

COUNTER
F1 OPERATION

0 NORMAL
1 R, N COUNTER

LOCK DETECT

CONTROL

RESET

COUNTER

F1

C2 (1) C1 (0)

HELD IN RESET

BITS

REV. 0

CPI6 CPI5 CP14 ICP (mA)

CPI3 CPI2 CPI1 2.7k 4.7k 10k

0 0 0 1.088 0.625 0.294
0 0 1 2.176 1.25 0.588
0 1 0 3.264 1.875 0.882
0 1 1 4.352 2.5 1.176
1 0 0 5.44 3.125 1.47
1 0 1 6.528 3.75 1.764
1 1 0 7.616 4.375 2.058
1 1 1 8.704 5.0 2.352

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN
1 X 0 NORMAL OPERATION
101ASYNCHRONOUS POWER-DOWN
111SYNCHRONOUS POWER-DOWN

–11–

ADF4001

THE FUNCTION LATCH

With C2, C1 set to 1, 0, the on-chip function latch will be pro­grammed. Table V shows the input data format for programming
the Function Latch.

Counter Reset

DB2 (F1) is the counter reset bit. When this is “1,” the R counter
and the A, B counters are reset. For normal operation this bit
should be “0.” Upon powering up, the F1 bit needs to be disabled,

the N counter resumes counting in “close” alignment with the R counter.
(The maximum error is one prescaler cycle.)

Power-Down

DB3 (PD1) and DB21 (PD2) on the ADF4110 Family, provide
programmable power-down modes. They are enabled by the
CE pin.

When the CE pin is low, the device is immediately disabled
regardless of the states of PD2, PD1.

In the programmed asynchronous power-down, the device pow­ers down immediately after latching a “1” into bit PD1, with the
condition that PD2 has been loaded with a “0.”

In the programmed synchronous power-down, the device power­down is gated by the charge pump to prevent unwanted frequency
jumps. Once the power-down is enabled by writing a “1” into bit
PD1 (on condition that a “1” has also been loaded to PD2), the
device will go into power-down on the occurrence of the next
charge pump event.

When a power-down is activated (either synchronous or
asynchronous mode, including CE-pin-activated power-down),
the following events occur:

All active dc current paths are removed.

The R, N, and timeout counters are forced to their load state
conditions.

The charge pump is forced into three-state mode.

The digital clock detect circuitry is reset.

The RF

input is debiased.

IN

The reference input buffer circuitry is disabled.

The input register remains active and capable of loading and
latching data.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, M1 on the
ADF4001. Table V shows the truth table.

Fastlock Enable Bit

DB9 of the Function Latch is the Fastlock Enable Bit. Only
when this is “1” is Fastlock enabled.

Fastlock Mode Bit

DB10 of the Function Latch is the Fastlock Mode bit. When
Fastlock is enabled, this bit determines which Fastlock Mode is
used. If the Fastlock Mode bit is “0,” Fastlock Mode 1 is selected;
if the Fastlock Mode bit is “1, ”Fastlock Mode 2 is selected.

Fastlock Mode 1

The charge pump current is switched to the contents of Current
Setting 2.

The device enters Fastlock by having a “1” written to the CP
Gain bit in the N counter latch. The device exits Fastlock by
having a “0” written to the CP Gain bit in the AB counter latch.

Fastlock Mode 2

The charge pump current is switched to the contents of Current
Setting 2.

The device enters Fastlock by having a “1” written to the CP
Gain bit in the N counter latch. The device exits Fastlock under
the control of the Timer Counter. After the timeout period
determined by the value in TC4–TC1, the CP Gain bit in the
N counter latch is automatically reset to “0” and the device
reverts to normal mode instead of Fastlock. See Table V for
the timeout periods.

Timer Counter Control

The user has the option of programming two charge pump
currents. The intent is that the Current Setting 1 is used when
the RF output is stable and the system is in a static state. Cur­rent Setting 2 is meant to be used when the system is dynamic
and in a state of change (i.e., when a new output frequency is
programmed).

The normal sequence of events is as follows:

The user initially decides what the preferred charge pump cur­rents are going to be. For example, they may choose 2.5 mA as
Current Setting 1 and 5 mA as Current Setting 2.

At the same time they must also decide how long they want the
secondary current to stay active before reverting to the primary
current. This is controlled by the Timer Counter Control Bits
DB14 to DB11 (TC4–TC1) in the Function Latch. The truth
table is given in Table V.

Now, when the user wishes to program a new output frequency,
they can simply program the N counter latch with new value for N.
At the same time they can set the CP Gain bit to a “1,” which sets
the charge pump with the value in CPI6–CPI4 for a period of
time determined by TC4–TC1. When this time is up, the charge
pump current reverts to the value set by CPI3–CPI1. At the
same time the CP Gain bit in the N Counter latch is reset to 0
and is now ready for the next time that the user wishes to change
the frequency.

Note that there is an enable feature on the Timer Counter. It is
enabled when Fastlock Mode 2 is chosen by setting the Fastlock
Mode bit (DB10) in the Function Latch to “1.”

Charge Pump Currents

CPI3, CPI2, CPI1 program Current Setting 1 for the charge
pump. CPI6, CPI5, CPI4 program Current Setting 2 for the
charge pump. The truth table is given in Table V.

PD Polarity

This bit sets the PD Polarity Bit. See Table V.

CP 3-State

This bit sets the CP output pin. With the bit set high, the CP
output is put into three-state. With the bit set low, the CP
output is enabled.

–12–

REV. 0

ADF4001

R DIVIDER

RF

IN

PFD

CHARGE

PUMP

N DIVIDER

1

1

LOOP

FILTER

CP

VCXO

13MHz

SYSTEM

CLOCK

ADF4110
ADF4111
ADF4112
ADF4113

REF

IN

CP

RF

IN

A

LOOP

FILTER

VCO

ADF4001

13MHz

RF

IN

THE INITIALIZATION LATCH

When C2, C1 = 1, 1, the Initialization Latch is programmed.
This is essentially the same as the Function Latch (programmed
when C2, C1 = 1, 0).

However, when the Initialization Latch is programmed, there is
an additional internal reset pulse applied to the R and N counters.
This pulse ensures that the N counter is at load point when the
N counter data is latched, and the device will begin counting in
close phase alignment.

If the Latch is programmed for synchronous power-down (CE
pin is High; PD1 bit is High; PD2 bit is Low), the internal pulse
also triggers this power-down. The oscillator input buffer is
unaffected by the internal reset pulse, and so close phase align­ment is maintained when counting resumes.

When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive N
counter loads after this will not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER INITIAL POWER-UP

After initially powering up the device, there are three ways to
program the device.

Initialization Latch Method

Apply VDD.

Program the Initialization Latch (“11” in 2 LSBs of input word).
Make sure that F1 bit is programmed to “0.”

Then do an R load (“00” in 2 LSBs).

Then do an N load (“01” in 2 LSBs).

When the Initialization Latch is loaded, the following occurs:

1. The function latch contents are loaded.

2. An internal pulse resets the R, N, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler bandgap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allow­ing close phase alignment when counting resumes.

3. Latching the first N counter data after the initialization word
will activate the same internal reset pulse. Successive N loads
will not trigger the internal reset pulse unless there is another
initialization.

The CE Pin Method

Apply VDD.

Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.

Program the Function Latch (10).
Program the R Counter Latch (00).
Program the N Counter Latch (01).

Bring CE high to take the device out of power-down. The R and
AB counters will now resume counting in close alignment.

Note that after CE goes high, a duration of 1 µs may be required
for the prescaler bandgap voltage and oscillator input buffer bias
to reach steady state.

CE can be used to power the device up and down in order to
check for channel activity. The input register does not need to
be reprogrammed each time the device is disabled and enabled
as long as it has been programmed at least once after V
initially applied.

REV. 0

DD

was

The Counter Reset Method

Apply VDD.

Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “1” to the F1 bit. This enables the counter reset.

Do an R Counter Load (“00” in 2 LSBs).

Do an N Counter Load (“01” in 2 LSBs).

Do a Function Latch Load (“10” in 2 LSBs). As part of this,
load “0” to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initial­ization method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but does not trigger synchronous
power-down. The counter reset method requires an extra func­tion latch load compared to the initialization latch method.

APPLICATIONS SECTION
Extremely Stable, Low Jitter Reference Clock for GSM Base
Station Transmitter

Figure 7 shows the ADF4001 being used with a VCXO to pro­duce an extremely stable, low jitter reference clock for a GSM
base station Local Oscillator (LO).

Figure 7. Low Jitter, Stable Clock Source for GSM Base
Station Local Oscillator cct

The system reference signal is applied to the circuit at REFIN.
Typical GSM systems would have a very stable OCXO as the
clock source for the entire base station. However, distribution of
this signal around the base station makes it susceptible to
noise and spurious pickup. It is also open to pulling from the
various loads it may need to drive.

The charge pump output of the ADF4001 (Pin 2) drives the
loop filter and the 13 MHz VCXO. The VCXO output is fed
back to the RF input of the ADF4001 and also drives the refer­ence (REFIN) for the LO. A T-circuit configuration provides
50 Ω matching between the VCXO output, the LO REFIN, and
the RF

terminal of the ADF4001.

IN

COHERENT CLOCK GENERATION

When testing A/D converters, it is often advantageous to use a
coherent test system, that is a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting

–13–

ADF4001

function. Figure 8 shows how the ADF4001 can be used to
handle all the possible combinations of input signal frequency
and sampling rate. The first ADF4001 is phase locked to a
VCO. The output of the VCO is also fed into the N divider of
the second ADF4001. This results in both ADF4001’s
being coherent with the REF

. Since the REFIN comes from

IN

the signal generator, the MUXOUT signal of the second
ADF4001 is coherent with the F
used as F

MODEL 1051

, the sampling clock.

S

SINE

OUTPUT

BRUEL &

KJAER

SQUARE

OUTPUT

REF

FS = (FIN  N1)/(R1  N2)

IN

R1

ADF4001

ADF4001

frequency to the ADC. This is

IN

F

IN

A

IN

SAMPLING

CP

N1

N2

RF

RF

IN

RF

IN

MUXOUT

LOOP

FILTER

NC7S04

VCO

100MHz

A/D

CONVERTER

UNDER

TEST

CLOCK

F

S

REF

R1

IN

4

1

N1

CP

RF

RF

LOOP

FILTER

IN

ADF4001

R2

REF

IN

52MHz

MASTER

CLOCK

1300

486

N2

CP

RF

RF

LOOP

FILTER

IN

ADF4001

R3

REF

IN

65

24

N3

CP

RF

RF

LOOP

FILTER

IN

ADF4001

Figure 9. Tri-Band System Clock Generation

V

P

VCXO
13MHz

VCXO

19.44MHz

VCXO

19.2MHz

13MHz SYSTEM

CLOCK FOR GSM

19.44MHz SYSTEM

CLOCK FOR WCDMA

19.2MHz SYSTEM

CLOCK FOR CDMA

Figure 8. Coherent Clock Generator

TRI-BAND CLOCK GENERATION CIRCUIT

In multi-band applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz Master Clock. The low RF
Fmin spec and the ability to program R and N values as low as
 1 makes the ADF4001 suitable for this. Other F

OUT

clock

frequencies can be realized using the formula:

F REF N R

=∗÷

OUT IN

()

SHUTDOWN CIRCUIT

The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic “1” is applied to the IN input.
The low-cost switch is available in both SOT-23 and micro
SO packages.

FREF

POWER-DOWN CONTROL

V

S

V

DD

15

7

AV

IN

16

10

DV

DD

CE

V

DD

P

2

LOOP

CP

FILTER

1

R

SET

10k

IN

ADG702

D

V

CC

VCO

OR

VCXO

GND

DD

GND

100pF

100pF

18

RF

18

18

OUT

ADF4001

100pF

6

RFINA

51

CPGND

3

RF

AGND4DGND

5

B

IN

100pF

DECOUPLING CAPACITORS AND INTERFACE

9

SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.

–14–

Figure 10. Local Oscillator Shutdown Circuit

REV. 0

ADF4001

INTERFACING

The ADF4001 family has a simple SPI-compatible serial inter­face for writing to the device. SCLK, SDATA, and LE control
the data transfer. When LE (Latch Enable) goes high, the 24
bits that have been clocked into the input register on each rising
edge of SCLK will be transferred to the appropriate latch. See
Figure 1 for the Timing Diagram and Table I for the Latch
Truth Table.

The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device
is 833 kHz or one update every 1.2 ms. This is certainly more
than adequate for systems with typical lock times in hundreds
of microseconds.

ADuC812 Interface

Figure 11 shows the interface between the ADF4001 family and
the ADuC812 microconverter. Since the ADuC812 is based on
an 8051 core, this interface can be used with any 8051-based
microcontroller. The microconverter is set up for SPI Master
Mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4001 family
needs a 24-bit word. This is accomplished by writing three 8-bit
bytes from the microconverter to the device. When the third
byte has been written, the LE input should be brought high to
complete the transfer.

On first applying power to the ADF4001 family, it needs three
writes (one each to the R counter latch, the N counter latch and
the initialization latch) for the output to become active.

I/O port lines on the ADuC812 are also used to control power­down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).

When operating in the mode described, the maximum SCLOCK
rate of the ADuC812 is 4 MHz. This means that the maxi­mum rate at which the output frequency can be changed will
be 166 kHz.

ADuC812

SCLOCK

MOSI

I/O PORTS

ADF4001

SCLK

SDATA

LE

CE

MUXOUT
(LOCK DETECT)

Figure 11. ADuC812 to ADF4001 Family Interface

ADSP-2181 Interface

Figure 12 shows the interface between the ADF4001 family and
the ADSP-21xx Digital Signal Processor. The ADF4001 family
needs a 24-bit serial word for each latch write. The easiest way
to accomplish this using the ADSP-21xx family is to use the
Autobuffered Transmit Mode of operation with Alternate
Framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the Autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the auto­buffer transfer.

ADSP-21xx

SCLK

DT

TFS

I/O FLAGS

ADF4001

SCLK

SDATA

LE

CE

MUXOUT
(LOCK DETECT)

Figure 12. ADSP-21xx to ADF4001 Family Interface

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The lands on the chip package (CP-20) are rectangular. The
printed circuit board pad for these should be 0.1 mm longer
than the package land length and 0.05 mm wider than the
package land width. The land should be centered on the pad.
This will ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edge of the pad pattern. This will ensure that
shorting is avoided.

Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at 1.2 mm
pitch grid. The via diameter should be between 0.3 mm and

0.33 mm and the via barrel should be plated with 1 oz. copper
to plug the via.

The user should connect the printed circuit board thermal pad
to AGND.

REV. 0

–15–

ADF4001

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

16-Lead Thin Shrink SO Package (TSSOP)

(RU-16)

0.201 (5.10)

0.193 (4.90)

PIN 1

INDICATOR

0.035 (0.90) MAX

0.033 (0.85) NOM

SEATING

PLANE

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

PLANE

16

0.0256 (0.65)
BSC

9

0.177 (4.50)

0.169 (4.30)

81

0.0433 (1.10)
MAX

0.0118 (0.30)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8
0

0.028 (0.70)

0.020 (0.50)

20-Leadless Frame Chip Scale Package (LFCSP)

(CP-20)

0.024 (0.60)

0.157 (4.0)
BSC SQ

TOP

VIEW

12 MAX

0.020 (0.50)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS

0.148 (3.75)
BSC SQ

0.031 (0.80) MAX

0.026 (0.65) NOM

0.008 (0.20)
REF

0.024 (0.60)

0.017 (0.42)

0.009 (0.24)

0.012 (0.30)

0.009 (0.23)

0.007 (0.18)

0.030 (0.75)

0.022 (0.60)

0.014 (0.50)

0.002 (0.05)

0.0004 (0.01)

0.0 (0.0)

0.017 (0.42)

0.009 (0.24)

16

15

BOTTOM

VIEW

11

10

0.080 (2.00)
REF

0.010 (0.25)
MIN

20

6

1

0.080 (2.25)

0.083 (2.10) SQ

0.077 (1.95)

5

C02569–1–7/01(0)

–16–

PRINTED IN U.S.A.

REV. 0