ANALOG DEVICES ADE7769 Service Manual

Energy Metering IC with Integrated

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FEATURES

On-chip oscillator as clock source
High accuracy, supports 50 Hz/60 Hz IEC62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Supplies average real power on frequency outputs F1 and F2
High frequency output CF calibrates and supplies

instantaneous real

CF output remains logic high when ADE7769 is under

no-load threshold

Logic output REVP indicates a potential miswiring or

negative power

Direct drive for electromechanical counters and 2-phase

stepper motor

Proprietary ADCs and DSPs provide high accuracy over

large vari

ations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no-load threshold)
On-chip reference 2.45 V (20 ppm/°C typical) with external

ov

erdrive capability
Single 5 V supply, low power (20 mW typical)
Low cost CMOS process

GENERAL DESCRIPTION

The ADE77691 is a high accuracy electrical energy metering IC.
It is a pin reduction version of the ADE7755 with an enhanced,
precise oscillator circuit that serves as a clock source to the chip.
The ADE7769 eliminates the cost of an external crystal or
resonator, thus reducing the overall cost of a meter built with
this IC. The chip directly interfaces with the shunt resistor.

power

s (F1 and F2)

Oscillator and No-Load Indication

ADE7769

The ADE7769 specifications surpass the accuracy require­ments of the IEC62053-21 standard. The AN-679 Application

Note can be used as a basis for a description of an IEC61036

(equivalent to IEC62053-21) low cost, watt-hour meter
reference design.

The only analog circuitry used in the ADE7769 is in the Σ-Δ

DCs and reference circuit. All other signal processing, such as

A
multiplication and filtering, is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.

The ADE7769 supplies average real power information on the

ow frequency outputs, F1 and F2. These outputs can be used to

l
directly drive an electromechanical counter or interface with an
MCU. The high frequency CF logic output, ideal for calibration
purposes, provides instantaneous real power information.

The ADE7769 includes a power supply monitoring circuit on

supply pin. The ADE7769 remains inactive until the

e V

th

DD

supply voltage on V
falls below 4 V, the ADE7769 also remains inactive and the F1,
F2, and CF outputs are in their nonactive modes.

Internal phase matching circuitry ensures that the voltage and

urrent channels are phase matched, while the HPF in the

c
current channel eliminates dc offsets. An internal no-load
threshold ensures that the ADE7769 does not exhibit creep
when no load is present. During a no-load condition, the CF
pin stays logic high.

reaches approximately 4 V. If the supply

DD

1

U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

1 6 13

POWER

SUPPLY MONITOR

V2P

2

+

3

V2N

4

V1N

5

+

V1P

2.5V

REFERENCE

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

...110101...

Σ-Δ

ADC

...11011001...

Σ-Δ

ADC

INTERNAL

OSCILLATOR

4kΩ

7 11 8 10 12 14 16 159

IN/OUT

RCLKIN

REF

PHASE

CORRECTION

Figure 1.

The ADE7769 has a 16-lead, narrow body SOIC package.

DGND

ADE7769

SIGNAL

PROCESSING

BLOCK

MULTIPLIER

LPF

Φ

HPF

DIGITAL-TO-FREQUENCY

CONVERTER

REVP

CF

SCFS0S1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

F1

05332-001

F2

ADE7769

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Internal Oscillator (OSC).......................................................... 14

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Functional Description.................................................................. 10

Theory of Operation ..................................................................10

Analog Inputs..............................................................................11

Power Supply Monitor............................................................... 12

REVISION HISTORY

8/05—Sp0 to Rev. A

Transfer Function....................................................................... 14

Selecting a Frequency for an Energy Meter Application ...... 15

No-Load Threshold.................................................................... 16

Negative Power Information..................................................... 16

Evaluation Board and Reference Design Board..................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. A | Page 2 of 20

ADE7769

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SPECIFICATIONS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T
unless otherwise noted.

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Measurement Error1 on Channel V1 0.1 % reading typ

1, 2

Channel V2 with full-scale signal (±165 mV),
25°C over a dyn
line frequency = 45 Hz to 65 Hz

Phase Error1 Between Channels

V1 Phase Lead 37° (PF = 0.8 Capacitive) ±0.1 Degrees (°) max
V1 Phase Lag 60° (PF = 0.5 Inductive) ±0.1 Degrees (°) max

AC Power Supply Rejection

Output Frequency Variation (CF) 0.2 % reading typ

1

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @
50 Hz, ripple on

DC Power Supply Rejection

Output Frequency Variation (CF) ±0.3 % reading typ

1

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms,

= 5 V ± 250 mV

V

DD

ANALOG INPUTS See the Analog Inputs section

Channel V1 Maximum Signal Level ±30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level ±165 mV max V2P and V2N to AGND
Input Impedance (DC) 320 kΩ min OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C
Bandwidth (–3 dB) 7 kHz nominal OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C
ADC Offset Error

1, 2

±18 mV max

See the Terminology and Typical Performance
Characteristic

Gain Error

1

±4 % ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV r

OSCILLATOR FREQUENCY (OSC) 450 kHz nominal RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C

Oscillator Frequency Tolerance
Oscillator Frequency Stability

1

1

±12 % reading typ
±30 ppm/°C typ

REFERENCE INPUT

REF

Input Voltage Range 2.65 V max 2.45 V nominal

IN/OUT

2.25 V min 2.45 V nominal
Input Capacitance 10 pF max

ON-CHIP REFERENCE 2.45 V nominal

Reference Error ±200 mV max
Temperature Coefficient ±20 ppm/°C typ

LOGIC INPUTS3

SCF, S0, S1

Input High Voltage, V
Input Low Voltage, V

INH

0.8 V max VDD = 5 V ± 5%

INL

2.4 V min VDD = 5 V ± 5%

Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max

LOGIC OUTPUTS3

F1 and F2

Output High Voltage, VOH 4.5 V min I

= 10 mA, VDD = 5 V, I

SOURCE

Output Low Voltage, VOL 0.5 V max

CF

Output High Voltage, VOH 4 V min I

= 5 mA, VDD = 5 V, I

SOURCE

Output Low Voltage, VOL 0.5 V max

Frequency Output Error

1, 2

(CF) ±10 % ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV r

MIN

to T

= −40°C to +85°C,

MAX

amic range 500 to 1,

V

of 200 mV rms @ 100 Hz

DD

s sections

ms

= 10 mA, VDD = 5 V

SINK

= 5 mA, VDD = 5 V

SINK

ms

Rev. A | Page 3 of 20

ADE7769

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Parameter Value Unit Test Conditions/Comments

POWER SUPPLY For specified performance

VDD 4.75 V min 5 V – 5%

5.25 V max

I

5 mA max Typically 4 mA

DD

1

See the Terminology section for an explanation of specifications.

2

See the figures in the Typical Performance Characteristics section.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T
unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See

Figure 2.

Table 2.

Parameter Specifications Unit Test Conditions/Comments

1

t

1

t2 See Table 6 sec Output pulse period. See the Transfer Function section.
t

1/2 t2 sec Time between the F1 and F2 falling edges.

3

1, 2

t

4

t

See Table 7 sec CF pulse period. See the Transfer Function section.

5

t

6

1

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

2

The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7.

120

ms

F1 and F2 pulse width (logic low).

90 ms CF pulse width (logic high).

2

μs

Minimum time between the F1 and F2 pulses.

5 V + 5%

MIN

to T

= −40°C to +85°C,

MAX

t

1

F1

t

6

t

2

F2

CF

t

3

t

4

t

5

05332-002

Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 4 of 20

ADE7769

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD to AGND −0.3 V to +7 V
VDD to DGND –0.3 V to +7 V
Analog Input Voltage to AGND,

V1P, V1N, V2P, and V2N –6 V to +6 V
Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to VDD + 0.3 V
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
16-Lead Plastic SOIC, Power Dissipation 350 mW

θJA Thermal Impedance

Package Temperature Soldering See J-STD-20

1

JEDEC 1S standard (2-layer) board data.

1

124.9°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. A | Page 5 of 20

ADE7769

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TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7769 is defined by the following formula:

EnergyTrueADE7769byRegisteredEnergy

%Error ×

Phase Error Between Channels
The high-pass filter (HPF) in the current channel (Channel V1)
has a phase-lead response. To offset this phase response and
equalize the phase response between channels, a phase­correction network is also placed in Channel V1. The phase­correction network matches the phase to within 0.1° over a
range of 45 Hz to 65 Hz, and 0.2° over a range 40 Hz to 1 kHz
(see

Power Supply Rejection (PSR)

This
percentage of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is tak
onto the supplies, and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is t
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.

=

Figure 23 and Figure 24).

quantifies the ADE7769 measurement error as a

en. A 200 mV rms/100 Hz signal is then introduced

aken. The supplies are then varied 5% and a second

EnergyTrue

−

100%

ADC Offset Error

This r

efers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power
calculation is not affected by this offset.

Frequency Output Error (CF)

requency output error of the ADE7769 is defined as the

The f
difference between the measured output frequency (minus the
offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7769 transfer function.

Gain Error

The ga

in error of the ADE7769 is defined as the difference
between the measured output of the ADCs (minus the offset)
and the ideal output of the ADCs. The difference is expressed as
a percentage of the ideal of the ADCs.

Oscillator Frequency Tolerance

cillator frequency tolerance of the ADE7769 is defined as

The os
the part-to-part frequency variation in terms of percentage
at room temperature (25°C). It is measured by taking the
difference between the measured oscillator frequency and the
nominal frequency defined in the

Oscillator Frequency Stability

scillator frequency stability is defined as frequency variation

O
in terms of the parts-per-million drift over the operating
temperature range. In a metering application, the temperature
range is −40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at −40°C and +85°C and the measured
oscillator frequency at +25°C.

Specifications section.

Rev. A | Page 6 of 20