Datasheet ADE7768 Datasheet (ANALOG DEVICES)

Energy Metering IC with Integrated

www.BDTIC.com/ADI

Oscillator and Positive Power Accumulation

FEATURES

On-chip oscillator as clock source
High accuracy, supports 50 Hz/60 Hz IEC62053-21
Less than 0.1% error over a dynamic range of 500 to 1
Supplies positive-only average real power on frequency

outputs F1 an

High frequency output CF calibrates and supplies

instantaneous,

Logic output REVP indicates potential miswiring or negative

power

Direct drive for electromechanical counters and 2-phase

stepper motor

Proprietary ADCs and DSPs provide high accuracy over

large variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no-load threshold)
On-chip reference 2.45 V (20 ppm/°C typical) with

external over
Single 5 V supply, low power (20 mW typical)
Low cost CMOS process

GENERAL DESCRIPTION

The ADE77681 is a high accuracy, electrical energy metering IC.
It is a pin reduction version of the ADE7755, enhanced with a
precise oscillator circuit that serves as a clock source to the chip.
The ADE7768 eliminates the cost of an external crystal or
resonator, thus reducing the overall cost of a meter built with
this IC. The chip directly interfaces with the shunt resistor.

1

U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

d F2

positive-only real power

s (F1 and F2)

drive capability

ADE7768

The ADE7768 specifications surpass the accuracy require­ments of the IEC62053-21 standard. The AN-679 Application

Note can be used as a basis for a description of an IEC61036

(equivalent to IEC62053-21) low cost, watt-hour meter
reference design.

The only analog circuitry used in the ADE7768 is in the Σ-Δ

DCs and reference circuit. All other signal processing, such as

A
multiplication and filtering, is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.

The ADE7768 supplies positive-only average real power

rmation on the low frequency outputs, F1 and F2. These

info
outputs can be used to directly drive an electromechanical
counter or interface with an MCU. The high frequency CF logic
output, ideal for calibration purposes, provides instantaneous
positive-only, real power information.

The ADE7768 includes a power supply monitoring circuit on
th

supply pin. The ADE7768 remains inactive until the

e V

DD

supply voltage on V
falls below 4 V, the ADE7768 also remains inactive and the F1,
F2, and CF outputs are in their nonactive modes.

Internal phase matching circuitry ensures that the voltage and
c

urrent channels are phase matched, while the HPF in the
current channel eliminates dc offsets. An internal no-load
threshold ensures that the ADE7768 does not exhibit creep
when no load is present. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.

The ADE7768 comes in a 16-lead, narrow body SOIC package.

reaches approximately 4 V. If the supply

DD

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

1 6 13

POWER

SUPPLY MONITOR

2

V2P

+

3

V2N

4

V1N

+

5

V1P

2.5V

REFERENCE

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

...110101...

Σ-Δ

ADC

...11011001...

Σ-Δ

ADC

INTERNAL

OSCILLATOR

4kΩ

7 11 8 10 12 14 16 159

IN/OUT

RCLKIN

REF

PHASE

CORRECTION

Figure 1.

DGND

ADE7768

SIGNAL

PROCESSING

BLOCK

MULTIPLIER

LPF

Φ

HPF

DIGITAL-TO-FREQUENCY

CONVERTER

CF

SCFS0S1

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

REVP

F1

05331-001

F2

ADE7768

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Power Supply Monitor............................................................... 12

Timing Characteristics ................................................................ 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Functional Description.................................................................. 10

Theory of Operation ..................................................................10

Analog Inputs..............................................................................11

Revision History

8/05—Sp0 to Rev. A

Internal Oscillator (OSC).......................................................... 14

Transfer Function....................................................................... 14

Selecting a Frequency for an Energy Meter Application ......15

No-Load Threshold.................................................................... 16

Negative Power Information..................................................... 16

Evaluation Board and Reference Design Board..................... 16

Outline Dimensions....................................................................... 17

Ordering Guide .......................................................................... 17

Rev. A | Page 2 of 20

ADE7768

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SPECIFICATIONS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T
unless otherwise noted.

Table 1.

Parameter Value Unit Test Conditions/Comments

ACCURACY

Measurement Error on Channel V1 0.1 % reading typ

1, 2

Channel V2 with full-scale signal (±165 mV),
25°C over a dyn
line frequency = 45 Hz to 65 Hz

Phase Error1 Between Channels

V1 Phase Lead 37° (PF = 0.8 Capacitive) ±0.1 Degrees (°) max
V1 Phase Lag 60° (PF = 0.5 Inductive) ±0.1 Degrees (°) max

AC Power Supply Rejection1

Output Frequency Variation (CF) 0.2 % reading typ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms @
50 Hz, ripple on

DC Power Supply Rejection1

Output Frequency Variation (CF) ±0.3 % reading typ

S0 = S1 = 1, V1 = 21.2 mV rms, V2 = 116.7 mV rms,

= 5 V ± 250 mV

V

DD

ANALOG INPUTS See the Analog Inputs section

Channel V1 Maximum Signal Level ±30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level ±165 mV max V2P and V2N to AGND
Input Impedance (DC) 320 kΩ min OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C
Bandwidth (–3 dB) 7 kHz nominal OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C
ADC Offset Error

1, 2

±18 mV max

See the Terminology and the Typical Performance
Characteristic

Gain Error

1

±4 % ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV r

OSCILLATOR FREQUENCY (OSC) 450 kHz nominal RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C

Oscillator Frequency Tolerance
Oscillator Frequency Stability

1

1

±12 % reading typ
±30 ppm/°C typ

REFERENCE INPUT

REF

Input Voltage Range 2.65 V max 2.45 V nominal

IN/OUT

2.25 V min 2.45 V nominal
Input Capacitance 10 pF max

ON-CHIP REFERENCE 2.45 V nominal

Reference Error ±200 mV max
Temperature Coefficient ±20 ppm/°C typ

LOGIC INPUTS3

SCF, S0, S1

Input High Voltage, V
Input Low Voltage, V

INH

0.8 V max VDD = 5 V ± 5%

INL

2.4 V min VDD = 5 V ± 5%

Input Current, IIN ±1 μA max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max

LOGIC OUTPUTS3

F1 and F2

Output High Voltage, VOH 4.5 V min I

= 10 mA, VDD = 5 V, I

SOURCE

Output Low Voltage, VOL 0.5 V max

CF

Output High Voltage, VOH 4 V min I

= 5 mA, VDD = 5 V, I

SOURCE

Output Low Voltage, VOL 0.5 V max

Frequency Output Error

1, 2

(CF) ±10 % ideal typ

External 2.5 V reference, V1 = 21.2 mV rms,
V2 = 116.7 mV r

MIN

to T

= −40°C to +85°C,

MAX

amic range 500 to 1,

V

of 200 mV rms @ 100 Hz

DD

s sections

ms

= 10 mA, VDD = 5 V

SINK

= 5 mA, VDD = 5 V

SINK

ms

Rev. A | Page 3 of 20

ADE7768

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Parameter Value Unit Test Conditions/Comments

POWER SUPPLY For specified performance

VDD 4.75 V min 5 V – 5%

5.25 V max

I

5 mA max Typically 4 mA

DD

1

See the Terminology section for an explanation of specifications.

2

See the figures in the Typical Performance Characteristics section.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C, T
unless otherwise noted. Sample tested during initial release and after any redesign or process change that may affect this parameter.
See

Figure 2.

Table 2.

Parameter Specifications Unit Test Conditions/Comments

1

t

1

t2 See Table 6 sec Output pulse period. See the Transfer Function section.
t

1/2 t2 sec Time between the F1 and F2 falling edges.

3

1, 2

t

4

t

See Table 7 sec CF pulse period. See the Transfer Function section.

5

t

6

1

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

2

The CF pulse is always 35 μs in high frequency mode. See the Frequency Outputs section and Table 7.

120

ms

F1 and F2 pulse width (logic low)

90 ms CF pulse width (logic high).

2

μs

Minimum time between the F1 and F2 pulses.

5 V + 5%

MIN

to T

= –40°C to +85°C,

MAX

t

1

F1

t

6

t

2

F2

CF

t

3

t

4

t

5

05331-002

Figure 2. Timing Diagram for Frequency Outputs

Rev. A | Page 4 of 20

ADE7768

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD to AGND −0.3 V to +7 V
VDD to DGND −0.3 V to +7 V
Analog Input Voltage to AGND,

V1P, V1N, V2P, and V2N −6 V to +6 V
Reference Input Voltage to AGND −0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND −0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
16-Lead Plastic SOIC, Power Dissipation 350 mW

θJA Thermal Impedance
Package Temperature Soldering See J-STD-20

1

JEDEC 1S standard (2-layer) board data.

1

124.9°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. A | Page 5 of 20

ADE7768

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TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7768 is defined by the following formula:

7768

−

% ×

Phase Error Between Channels

The high-pass filter (HPF) in the current channel (Channel V1)
has a phase-lead response. To offset this phase response and
equalize the phase response between channels, a phase­correction network is also placed in Channel V1. The phase­correction network matches the phase to within 0.1° over a
range of 45 Hz to 65 Hz, and 0.2° over a range 40 Hz to 1 kHz
(see

Power Supply Rejection (PSR)

This
percentage of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is tak
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is t
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.

=

Error

Figure 24 and Figure 25).

quantifies the ADE7768 measurement error as a

en. A 200 mV rms/100 Hz signal is then introduced

aken. The supplies are then varied 5% and a second

EnergyTrue

EnergyTrueADEbyRegisteredEnergy

%100

ADC Offset Error

This r

efers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power
calculation is not affected by this offset.

Frequency Output Error (CF)

requency output error of the ADE7768 is defined as the

The f
difference between the measured output frequency (minus the
offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7768 transfer function.

Gain Error

The ga

in error of the ADE7768 is defined as the difference
between the measured output of the ADCs (minus the offset)
and the ideal output of the ADCs. The difference is expressed
as a percentage of the ideal of the ADCs.

Oscillator Frequency Tolerance

cillator frequency tolerance of the ADE7768 is defined as

The os
the part-to-part frequency variation in terms of percentage at
room temperature (25°C). It is measured by taking the differ­ence between the measured oscillator frequency and the
nominal frequency defined in the

Oscillator Frequency Stability

scillator frequency stability is defined as frequency variation

O
in terms of the parts-per-million drift over the operating
temperature range. In a metering application, the temperature
range is −40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at −40°C and +85°C and the measured
oscillator frequency at +25°C.

Specifications section.

Rev. A | Page 6 of 20

ADE7768

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD

Power Supply. This pin provides the supply voltage for the circuitry in the ADE7
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 μF
capacitor in parallel with a 100 nF ceramic capacitor.

2, 3 V2P, V2N

Analog Inputs for Channel V2 (Voltage Channel). These inputs provide a fully differential input pair. The
maximum differential input voltage is ±165 mV for specified operation. Both inputs have internal ESD
protection circuitry; an overvoltage of ±6 V can be sustained on these inputs without risk of permanent
damage.

4, 5 V1N, V1P

Analog Inputs for Channel V1 (Current Channel). These inputs are fully differential voltage inputs with a
maximum signal level of ±30 mV with respect to the V1N pin for specified operation. Both inputs have
internal ESD protection circuitry and, in addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.

6 AGND

This pin provides the ground reference for the analog circuitry in the ADE7768, that is, the ADCs and
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, such as antialiasing filters, current and voltage sensors, and so forth.
For accurate noise suppression, the analog ground plane should be connected to the digital ground plane at
only one point. A star ground configuration helps to keep noisy digital currents away from the analog
circuits.

7 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.45 V
and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at
this pin. In either case, this pin should be decoupled to AGND with a 1 μF tantalum capacitor and a 100 nF
ceramic capacitor. The internal reference cannot be used to drive an external load.

8 SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF.
See Table 7.

9, 10 S1, S0

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
With this logic input, designers have greater flexibility when designing an energy meter. See the Selecting a
Frequency for an Energy Meter Application section.

11 RCLKIN

To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a
nominal value of 6.2 kΩ must be connected from this pin to DGND.

12 REVP

This logic output goes high when negative power is detected, that is, when the phase angle between the
voltage and current signals is greater than 90°. This output is not latched and is reset when positive power is
once again detected. The output goes high or low at the same time that a pulse is issued on CF.

13 DGND

This pin provides the ground reference for the digital circuitry in the ADE7768, that is, the multiplier, filters,
and digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital
ground plane is the ground reference for all digital circuitry, such as counters (mechanical and digital), MCUs,
and indicator LEDs. For accurate noise suppression, the analog ground plane should be connected to the
digital ground plane at one point only—a star ground.

14 CF

Calibration Frequency Logic Output. The CF logic output provides instantaneous, positive-only real power
information. This output is intended for calibration purposes. See the SCF pin description.

15, 16 F2, F1

Low Frequency Logic Outputs. F1 and F2 supply average positiv
outputs can be used to directly drive electromechanical counters and 2-phase stepper motors. See the
Transfer Function section.

V

1

DD

V2P

2
3

V2N

ADE7768

V1N

4

TOP VIEW

(Not to Scale)

V1P

5
6

AGND

REF

7

IN/OUT

SCF

8

Figure 3. Pin Configuration

16
15
14
13
12
11
10

9

F1
F2
CF
DGND
REVP
RCLKIN
S0
S1

05331-003

768. The supply voltage

e-only real power information. The logic

Rev. A | Page 7 of 20

ADE7768

2

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TYPICAL PERFORMANCE CHARACTERISTICS

V

DD

1

V

602kΩ

20V

200Ω

40A TO

40mA

+

350μΩ

+

1μF

1.0
PF = 1

0.8

ON-CHIP REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 101 100
CURRENT CHANNEL (% of Full Scale)

+85°C

Figure 5. Error as a % of Reading over Temperature

with O

n-Chip Reference (PF = 1)

1.0
PF = 0.5 IND

0.8

ON-CHIP REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

+85°C, PF = 0.5 IND

0.1 101 100
CURRENT CHANNEL (% of Full Scale)

–40°C, PF = 0.5 IND

+25°C, PF = 1

+25°C, PF = 0.5 IND

2

150nF

200Ω

3

150nF

200Ω

5

150nF

200Ω

4

150nF

7

100nF

Figure 4. Test Circuit for Performance Curves

–40°C

+25°C

V2P

ADE7768

V2N

V1P

V1N

REF

IN/OUT

AGND

6

05331-019

05331-020

DD

U1

DGND

REVP

RCLKIN

13

SCF

F1
F2

CF

S0
S1

100nF

16
15
14

12

11

10

9
8

820Ω

6.2kΩ

+

10μF

U3

1

2 3

10nF 10nF 10nF

1.0
PF = 1

0.8

EXTERNAL REFERENCE

0.6

0.4

0.2

+85°C

0

–0.2

–0.4

ERROR (% of Reading)

–40°C

–0.6

–0.8

–1.0

0.1 101 100

K7

4

K8

PS2501-1

V

DD

10kΩ

05331-004

+25°C

CURRENT CHANNEL (% of Full Scale)

Figure 7. Error as a % of Reading over Temperature

with E

xternal Reference (PF = 1)

1.0

PF = 0.5 IND

0.8

EXTERNAL REFERENCE

0.6

0.4

0.2

+85°C, PF = 0.5 IND

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 101 100

+25°C, PF = 0.5 IND

CURRENT CHANNEL (% of Full Scale)

+25°C, PF = 1

–40°C, PF = 0.5 IND

05331-021

05331-022

Figure 6. Error as a % of Reading over Temperature

n-Chip Reference (PF = 0.5 IND)

with O

Rev. A | Page 8 of 20

Figure 8. Error as a % of Reading over Temperature

with E

xternal Reference (PF = 0.5 IND)

ADE7768

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0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

PF = 0.5 IND

5045 55 60 65

FREQUENCY (Hz)

PF = 1

PF = 0.5 CAP

Figure 9. Error as a % of Reading over Input Frequency

1.0
PF = 1

0.8

ON-CHIP REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 101 100

5.25V

5V

4.75V

CURRENT CHANNEL (% of Full Scale)

Figure 10. PSR with On-Chip Reference, PF = 1

1.0

PF = 1

0.8

EXTERNAL REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 101 100
CURRENT CHANNEL (% of Full Scale)

5.25V

5V

4.75V

Figure 11. PSR with External Reference, PF = 1

05331-018

05331-023

05331-024

40

DISTRIBUTION CHARACTERISTICS
MEAN = 2.247828
SDs = 1.367176
MIN = –2.09932
MAX = +5.28288

30

NO. OF POINTS = 100

20

FREQUENCY

10

0

–5–4–3–2–10123456789

CHANNEL V1 OFFSET (mV)

EXTERNAL REFERENCE

TEMPERATURE = 25°C

Figure 12. Channel V1 Offset Distribution

50

DISTRIBUTION CHARACTERISTICS
MEAN = –1.563484
SDs = 2.040699
MIN = –6.82969

40

MAX = +2.6119
NO. OF POINTS = 100

30

20

FREQUENCY

10

0

–12–10–8–6–4–2024681012

CHANNEL V2 OFFSET (mV)

EXTERNAL REFERENCE

TEMPERATURE = 25°C

Figure 13. Channel V2 Offset Distribution

1000

DISTRIBUTION CHARACTERISTICS
MEAN = 0%
SDs = 1.55%
MIN = –11.79%

800

MAX = +6.08%
NO. OF POINTS = 3387

600

400

FREQUENCY

200

0

–10–8–6–4–2024681012

DEVIATION FROM MEAN (%)

EXTERNAL REFERENCE

TEMPERATURE = 25°C

Figure 14. Part-to-Part CF Deviation from Mean

05331-025

05331-026

05331-027

Rev. A | Page 9 of 20

ADE7768

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FUNCTIONAL DESCRIPTION

THEORY OF OPERATION

The two ADCs in the ADE7768 digitize the voltage signals from
the current and voltage sensors. These ADCs are 16-bit Σ-Δs
with an oversampling rate of 450 kHz. This analog input
structure greatly simplifies sensor interfacing by providing a
wide dynamic range for direct connection to the sensor and
by simplifying the antialiasing filter design. A high-pass filter
in the current channel removes any dc component from the
current signal. This eliminates any inaccuracies in the real
power calculation due to offsets in the voltage or current
signals.

MAGNITUDEMAGNITUDE

ACTIVE ENERGY

0Wh

INSTANTANEOUS
POWER

0W

The real power calculation is derived from the instantaneous
p

ower signal. The instantaneous power signal is generated by
a direct multiplication of the current and voltage signals. To
extract the real power component (the dc component), the
instantaneous power signal is low-pass filtered.
il

lustrates the instantaneous real power signal and shows how

Figure 15

the real power information can be extracted by low-pass
filtering the instantaneous power signal. In the ADE7768,
this signal is compared to 0 and only positive real power is
accumulated for F1, F2, and CF pulse outputs. This scheme
correctly calculates real power for sinusoidal current and
voltage waveforms at all power factors. All signal processing
is carried out in the digital domain for superior stability over
temperature and time.

DIGITAL-TO-

FREQUENCY

CH1

CH2

ADC

HPF

MULTIPLIER

ADC

INSTANTANEOUS

POWER SIGNAL – p(t)

LPF

≥0

INSTANTANEOUS REAL

POWER SIGNAL

DIGITAL-TO-

FREQUENCY

05331-028

Figure 16. Positive-Only Energy Accumulation

Power Factor Considerations

The method used to extract the real power information from
the instantaneous power signal (that is, by low-pass filtering) is
still valid even when the voltage and current signals are not in
phase. Figure 17 displays the unity power factor condition and a
dis

placement power factor (DPF) = 0.5 (a current signal lagging
the voltage by 60°). Assuming that the voltage and current
waveforms are sinusoidal, the real power component of the
instantaneous power signal (that is, the dc term) is given by

×

IV

⎞

⎛
⎜

2

F1
F2

CF

⎝

This is the correct real power calculation.

POWER

V × I

2

0V

(

60cos

⎟
⎠

INSTANTANEOUS

POWER SIGNAL

)

°×

(1)

INSTANTANEOUS REAL

POWER SIGNAL

TIME

TIME TIME

Figure 15. Signal Processing Block Diagram

05331-005

The low frequency outputs (F1 and F2) are generated by
accumulating positive-only real power information. This low
frequency inherently means a long accumulation time between
output pulses. Consequently, the resulting output frequency is
proportional to the average positive-only real power. This
average positive-only real power information is then accumu­lated (by a counter) to generate real energy information (see
Figure 16). Conversely, due to its high output frequency and
shor

ter integration time, the CF output frequency is propor­tional to the instantaneous positive-only real power. This is
useful for system calibration, which can be done faster under
steady load conditions.

Rev. A | Page 10 of 20

CURRENT
VOLTAGE

POWER

INSTANTANEOUS

POWER SIGNAL

V × I

COS (60°)

2

0V

VOLTAGE CURRENT

Figure 17. DC Component of Instantaneous Power Signal Conveys

eal Power Information, PF < 1

R

INSTANTANEOUS REAL

POWER SIGNAL

60°

TIME

05331-006

ADE7768

+

–

www.BDTIC.com/ADI

Nonsinusoidal Voltage and Current

The real power calculation method also holds true for non­sinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications have some
harmonic content. Using the Fourier transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content.

∞

0

∑

≠

0h

(

sin2)(

h

)

αthωVVtv +××+=

(2)

h

where:

v(t) is the instantaneous voltage.
V

is the average value.

0

Vh is the rms value of voltage harmonic h.

α

is the phase angle of the voltage harmonic.

h

∑

∞

≠

oh

(

+××+=

ω

sin2)(

βthIIti

)

(3)

hhO

where:

i(t) is the instantaneous current.
I

is the dc component.

0

Ih is the rms value of current harmonic h.

β

is the phase angle of the current harmonic.

h

Using Equations 2 and 3, the real power (P
terms of its fundamental real power (P
power (P

) as P = P1 + P

H

H

) can be expressed in

) and harmonic real

1

where:

cos

φ

IVP ×=

111

βαφ

−=

(4)

1

111

and

∞

IVP

φ

cos×=

∑

hH

≠

1h

βαφ

−=

hhh

(5)

hh

In Equation 5, a harmonic real power component is generated
fo

r every harmonic, provided that harmonic is present in both
the voltage and current waveforms. The power factor calcul­ation has previously been shown to be accurate in a pure
sinusoid. Therefore, the harmonic real power must also
correctly account for the power factor, because it is made up
of a series of pure sinusoids.

Note that the input bandwidth of the analog inputs is 7 kHz at

he nominal internal oscillator frequency of 450 kHz.

t

ANALOG INPUTS

Channel V1 (Current Channel)

The voltage output from the current sensor is connected to the
ADE7768 here. Channel V1 is a fully differential voltage input.
V1P is the positive input with respect to V1N.

The maximum peak differential signal on Channel V1 should

s than ±30 mV (21 mV rms for a pure sinusoidal signal)

be les
for specified operation.

V1

30mV

DIFFERENTIAL INPUT

V

CM

30mV

Figure 18. Maximum Signal Levels, Channel V1

±30mV MAX PEAK

COMMON-MODE

±6.25mV MAX

AGND

Figure 18 shows the maximum signal levels on V1P and V1N.
The maximum differential voltage is ±30 mV. The differential
voltage signal on the inputs must be referenced to a common
mode, such as AGND. The maximum common-mode signal is
±6.25 mV.

Channel V2 (Voltage Channel)

The output of the line voltage sensor is connected to the device
at this analog input. Channel V2 is a fully differential voltage
input with a maximum peak differential signal of ±165 mV.
Figure 19 shows the maximum signal levels that can be
co

nnected to the ADE7768 Channel V2.

V2

+165mV

DIFFERENTIAL INPUT

V

CM

–165mV

Figure 19. Maximum Signal Levels, Channel V2

±165mV MAX PEAK

COMMON-MODE

±25mV MAX

Channel V2 is usually driven from a common-mode voltage,
that is, the differential voltage signal on the input is referenced
to a common mode (usually AGND). The analog inputs of the
ADE7768 can be driven with common-mode voltages of up to
25 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.

AGND

V1P

V1

V1N

V

CM

05331-007

V2P

V2

V2N

V

CM

05331-008

Rev. A | Page 11 of 20

ADE7768

A

(

×+ω

×

×

V

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Typical Connection Diagrams

Figure 20 shows a typical connection diagram for Channel V1.
A shunt is the current sensor selected for this example because
of its low cost compared to other current sensors, such as the
current transformer (CT). This IC is ideal for low current
meters.

SHUNT

AGND

PHASE NEUTRAL

Figure 20. Typical Connection for Channel V1

Figure 21 shows a typical connection for Channel V2. Typically,
the ADE7768 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of R
convenient way of carrying out a gain calibration on a meter.

PHASENEUTRAL

Figure 21. Typical Connections for Channel V2

POWER SUPPLY MONITOR

The ADE7768 contains an on-chip power supply monitor.
The power supply (V
ADE7768. If the supply is less than 4 V, the ADE7768 becomes
inactive. This is useful to ensure proper device operation at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering, which provide a high degree
of immunity to false triggering from noisy supplies.

In Figure 22, the trigger level is nominally set at 4 V. The toler­a

nce on this trigger level is within ±5%. The power supply and
decoupling for the part should be such that the ripple at V
does not exceed 5 V ± 5%, as specified for normal operation.

V

DD

5V
4V

0V

INTERNAL

CTIVATION

INACTIVE ACTIVE INACTIVE

Figure 22. On-Chip Power Supply Monitor

R

F

±30mV

R

F

R

B

RA*

R

F

*RA>> RB + R

) is continuously monitored by the

DD

TIME

V1P

C

F

V1N

C

F

, RB, and RB

A

V2P

±165mV

C

F

F

V2N

C

R

F

F

05331-009

is also a

F

05331-010

DD

05331-011

HPF and Offset Effects

Figure 23 shows the effect of offsets on the real power calcula­tion. As can be seen, offsets on Channel V1 and Channel V2
contribute a dc component after multiplication. Because this dc
component is extracted by the LPF and used to generate the real
power information, the offsets contribute a constant error to the
real power calculation. This problem is easily avoided by the
built-in HPF in Channel V1. By removing the offsets from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at the line frequency (ω) are
removed by the LPF and the digital-to-frequency conversion
(see the

Digital-to-Frequency Conversion section).

Equation 6 shows how the power calculation is affected by the

ffsets in the current and voltage channels.

dc o

)()

IV

= coscos

2

()

+ 2cos

2

× I

OS

OS

V × I

2

0

tIVω×

DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION

IOS× V

× I

V

OS

FREQUENCY (RAD/s)

}cos{}cos{

ItIVtV +ω

(6)

OSOS

() ()

OSOSOSOS

tVItIVIV

ω×+ω×+×+

05331-012

Figure 23. Effect of Channel Offset on the Real Power Calculation

The HPF in Channel V1 has an associated phase response that
is compensated for on chip.

e error between channels with the compensation network

phas

Figure 24 and Figure 25 show the

activated. The ADE7768 is phase compensated up to 1 kHz as
shown. This ensures correct active harmonic power calculation
even at low power factors.

0.30

0.25

0.20

0.15

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY (Hz)

Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)

05331-013

Rev. A | Page 12 of 20

ADE7768

www.BDTIC.com/ADI

0.30

0.25

0.20

0.15

0.10

0.05

PHASE (Degrees)

0

–0.05

–0.10

40 45 50 55 60 65 70

Figure 25. Phase Error Between Channels (40 Hz to 70 Hz)

FREQUENCY (Hz)

05331-014

Digital-to-Frequency Conversion

As previously described, the digital output of the low-pass filter
after multiplication contains the positive-only real power
information. However, because this LPF is not an ideal brick
wall filter implementation, the output signal also contains
attenuated components at the line frequency and its harmonics,
that is, cos(hωt) where h = 1, 2, 3, ... and so on.

The magnitude response of the filter is given by

()

fH+=

1

(7)

2

f

1

2

45.4

For a line frequency of 50 Hz, this gives an attenuation of
th

e 2ω (100 Hz) component of approximately 22 dB. The
dominating harmonic is twice the line frequency (2ω) due to
the instantaneous power calculation.

F1

DIGITAL-TO-

FREQUENCY

V

MULTIPLIER

I

V × I

2

0

INSTANTANEOUS REAL POWER SIGNAL

Figure 26. Positive-Only, Real Power-to-Frequency Conversion

≥0

LPF

LPF TO EXTRACT

REAL POWER

(DC TERM)

COS (2ω)

ATTENUATED BY LPF

ω

2ω

FREQUENCY (RAD/s)

(FREQUENCY DOMAIN)

DIGITAL-TO­FREQUENCY

F1
F2

CF

CF

FREQUENCY FREQUENCY

TIME

TIME

In Figure 26, the frequency output CF varies over time, even
under steady load conditions. This frequency variation is
primarily due to the cos(2ωt) component in the instantaneous
positive-only real power signal. The output frequency on CF
can be up to 2048 times higher than the frequency on F1 and
F2. This higher output frequency is generated by accumulating
the instantaneous positive-only real power signal over a much
shorter time while converting it to a frequency. This shorter
accumulation period means less averaging of the cos(2ωt)
component. Consequently, some of this instantaneous power
signal passes through the digital-to-frequency conversion. This
is not a problem in the application. Where CF is used for
calibration purposes, the frequency should be averaged by the
frequency counter, which removes any ripple. If CF is used to
measure energy, such as in a microprocessor-based application,
the CF output should also be averaged to calculate power.

05331-015

Figure 26 shows the instantaneous positive-only real power

nal at the output of the LPF that still contains a significant

sig
amount of instantaneous power information, that is, cos(2ωt).
This signal is then passed to the digital-to-frequency converter
where it is compared to 0 and only positive real power is inte­grated (accumulated) over time to produce an output frequency.
The accumulation of the signal suppresses or averages out any
non-dc components in the instantaneous positive-only real
power signal. The average value of a sinusoidal signal is 0. Thus,
the frequency generated by the ADE7768 is proportional to the
average positive-only real power.

requency conversion for steady load conditions, that is, the

f

Figure 26 shows the digital-to-

constant voltage and current.

Rev. A | Page 13 of 20

Because the F1 and F2 outputs operate at a much lower

requency, much more averaging of the instantaneous positive-

f
only real power signal is carried out. The result is a greatly
attenuated sinusoidal content and a virtually ripple-free
frequency output.

Connecting to a Microcontroller for Energy Measurement

The easiest way to interface the ADE7768 to a microcontroller
is to use the CF high frequency output with the output
frequency scaling set to 2048 × F1, F2. This is done by setting
SCF = 0 and S0 = S1 = 1 (see Table 7). With full-scale ac

nals on the analog inputs, the output frequency on CF is

sig
approximately 2.867 kHz. Figure 27 illustrates one scheme that

uld be used to digitize the output frequency and carry out the

co
necessary averaging mentioned in the previous section.

ADE7768

×

×

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FREQUENCY

CF

FREQUENCY

RIPPLE

AVERAGE

TIME

ADE7768

CF

Figure 27. Interfacing the ADE7768 to an MCU

MCU

COUNTER

TIMER

±10%

05331-016

As shown in Figure 27, the frequency output CF is connected
to an MCU counter or port. This counts the number of pulses
in a given integration time, which is determined by an MCU
internal timer. The average power proportional to the average
frequency is given by

PowerAverageFrequencyAverage ==

Counter

(8)

Time

The energy consumed during an integration period is given by

TimePowerAverageEnergy =×=×=

Counter

Time

For the purpose of calibration, this integration time could be
10 seconds to 20 seconds, to accumulate enough pulses to
ensure correct averaging of the frequency. In normal operation,
the integration time could be reduced to 1 second or 2 seconds,
depending, for example, on the required update rate of a
display. With shorter integration times on the MCU, the
amount of energy in each update may still have some small
amount of ripple, even under steady load conditions. However,
over a minute or more the measured energy has no ripple.

Power Measurement Considerations

Calculating and displaying power information always has some
associated ripple, which depends on the integration period used
in the MCU to determine average power and also on the load.
For example, at light loads, the output frequency may be 10 Hz.
With an integration period of 2 seconds, only about 20 pulses
are counted. The possibility of missing one pulse always exists,
because the ADE7768 output frequency is running asynchro­nously to the MCU timer. This results in a 1-in-20 or 5% error
in the power measurement. When REVP is logic high, the
ADE7768 does not generate any pulse on F1, F2, and CF.

INTERNAL OSCILLATOR (OSC)

The nominal internal oscillator frequency is 450 kHz when
used with RCLKIN, with a nominal value of 6.2 kΩ. The
frequency outputs are directly proportional to the oscillator
frequency, thus RCLKIN must have low tolerance and low

temperature drift to ensure stability and linearity of the chip.
The oscillator frequency is inversely proportional to the
RCLKIN, as shown in
os

cillator operates when used with RCLKIN values between

Figure 28. Although the internal

5.5 kΩ and 20 kΩ, choosing a value within the range of the
nominal value, as shown in

490

480

470

460

450

440

430

FREQUENCY (kHz)

420

410

400

5.8 5.9 6.1 6.3 6.7

Figure 28. Effect of RCLKIN on Internal Oscillator Frequency (OSC)

Figure 28, is recommended.

6.0 6.2 6.4 6.5 6.6
RESISTANCE (kΩ)

05331-017

TRANSFER FUNCTION

Frequency Outputs F1 and F2

The ADE7768 calculates the product of two voltage signals

)9(CounterTime

(on Channel V1 and Channel V2) and then low-pass filters this
product to extract positive-only real power information. This
positive-only real power information is then converted to a
frequency. The frequency information is output on F1 and F2
in the form of active low pulses. The pulse rate at these outputs
is relatively low—for example, 0.175 Hz maximum for ac signals
with S0 = S1 = 0 (see
t

hese outputs is generated from positive-only real power

Table 6). This means that the frequency at

information accumulated over a relatively long period of time.
The result is an output frequency that is proportional to the
average positive-only real power. The averaging of the positive­only real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:

Freq

75.494

=

2

V

REF

FV2V1

×

41rmsrms

−

(10)

where:

Fr

eq is the output frequency on F1 and F2 (Hz).

V1

is the differential rms voltage signal on Channel V1 (V).

rms

is the differential rms voltage signal on Channel V2 (V).

V2

rms

V

is the reference voltage (2.45 V ± 200 mV) (V).

REF

are one of four possible frequencies selected by using the

F

1–4

S0 and S1 logic inputs (see Tabl e 5).

Rev. A | Page 14 of 20

ADE7768

www.BDTIC.com/ADI

Table 5. F

S1 S0 OSC Relation1F

0 0 OSC/219 0.86
0 1 OSC/218 1.72
1 0 OSC/217 3.43
1 1 OSC/216 6.86

1

F

is a binary fraction of the internal oscillator frequency.

1–4

2

Values are generated using the nominal frequency of 450 kHz.

Example

In this example, with ac voltages of ±30 mV peak applied to
V1 and ±165 mV peak applied to V2, the expected output
frequency is calculated as follows:

= OSC/219 Hz, S0 = S1 = 0

F

1–4

V1

rms

V2

rms

= 2.45 V (nominal reference value)

V

REF

Note that if the on-chip reference is used, actual output

requencies may vary from device to device due to the

f
reference tolerance of ±200 mV.

Freq

Table 6. Maximum Output Frequency on F1 and F2

S1 S0 OSC Relation Max Frequency1 or AC Inputs (Hz)

0 0 0.204 × F1 0.175
0 1 0.204 × F2 0.35
1 0 0.204 × F3 0.70
1 1 0.204 × F4 1.40

1

Values are generated using the nominal frequency of 450 kHz.

Frequency Output CF

The pulse output CF (calibration frequency) is intended for
calibration purposes. The output pulse rate on CF can be up
to 2048 times the pulse rate on F1 and F2. The lower the F
frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table 7 shows

ow the two frequencies are related, depending on the states

h
of the logic inputs S0, S1, and SCF. Due to its relatively high
pulse rate, the frequency at the CF logic output is proportional
to the instantaneous positive-only real power. As with F1 and
F2, CF is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is
high, this positive-only real power information is accumulated
over a much shorter time. Therefore, less averaging is carried
out in the digital-to-frequency conversion. With much less
averaging of the positive-only real power signal, the CF output
is much more responsive to power fluctuations (see the signal
processing block diagram in

Frequency Selection

1–4

= 0.03/√2 V
= 0.165/√2 V

=

××

165.003.075.494

×××

2

45.222

Figure 15).

at Nominal OSC (Hz)

1–4

F

1

F

2

SCF S1 S0 CF Max for AC Signals (Hz)

1

1 0 0 128 × F1, F2 = 22.4
0 0 0 64 × F1, F2 = 11.2
1 0 1 64 × F1, F2 = 22.4
0 0 1 32 × F1, F2 = 11.2
1 1 0 32 × F1, F2 = 22.4
0 1 0 16 × F1, F2 = 11.2
1 1 1 16 × F1, F2 = 22.4
0 1 1 2048 × F1, F2 = 2.867 kHz

Table 7. Maximum Output Frequency on CF

1

Values are generated using the nominal frequency of 450 kHz.

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Ta ble 5, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended for driving an energy
register (electromechanical or other). Because only four
different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant
of 100 imp/kWh with a maximum current of between 10 A

(11)

175.0204.0

=×=

1

and 120 A.
max
cases, the meter constant is 100 imp/kWh.

Table 8. F1 and F2 Frequency at 100 imp/kWh

I

MAX

12.5 0.076

25.0 0.153

40.0 0.244

60.0 0.367

80.0 0.489

120.0 0.733

The F
output frequencies (F1, F2). When designing an energy meter,

1–4

the nominal design voltage on Channel V2 (voltage) should be
set to half-scale to allow calibration of the meter constant. The
current channel should also be no more than half scale when
the meter sees maximum load. This allows overcurrent signals
and signals with high crest factors to be accommodated.
s

hows the output frequency on F1 and F2 when both analog

inputs are half scale. The frequencies in Tabl e 9 align very well

th those in

wi

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

S1 S0 F

0 0 0.86
0 1 1.72 0.051 × F2 0.088 Hz

1 0 3.43 0.051 × F3 0.176 Hz
1 1 6.86 0.051 × F

1

Values are generated using the nominal frequency of 450 kHz.

Tabl e 8 shows the output frequency for several

imum currents (I

) with a line voltage of 220 V. In all

MAX

(A) F1 and F2 (Hz)

frequencies allow complete coverage of this range of

1–4

Table 8 for maximum load.

Frequency on F1 and F2—

1–4

(Hz)

CH1 an

d CH2 Half-Scale AC Input

0.051 × F

1

4

0.044 Hz

0.352 Hz

Table 9

1

Rev. A | Page 15 of 20

ADE7768

www.BDTIC.com/ADI

When selecting a suitable F
frequency output at I

MAX

of 100 imp/kWh should be compared with Column 4 of
Table 9. The closest frequency in Table 9 determines the best

ce of frequency (F

choi
imum current of 25 A is being designed, the output frequency
on F1 and F2 with a meter constant of 100 imp/kWh is 0.153 Hz
at 25 A and 220 V (from Tab le 8 ). In Table 9, the closest fre-

uency to 0.153 Hz in Column 4 is 0.176 Hz. Therefore, as

q
shown in

Table 5, F3 (3.43 Hz) is selected for this design.

frequency for a meter design, the

1–4

(maximum load) with a meter constant

). For example, if a meter with a max-

1–4

For example, for an energy meter with a meter constant of

p/kWh on F1, F2 using F

100 im

(3.43 Hz), the minimum

3

output frequency at F1 or F2 would be 0.00244% of 3.43 Hz or

–5

8.38 × 10

Hz. This would be 2.68 × 10–3 Hz at CF (32 × F1 Hz)
when SCF = S0 = 1, S1 = 0. In this example, the no-load
threshold would be equivalent to 3 W of load or a start-up
current of 13.72 mA at 220 V. Compare this value to the
IEC62053-21 specification which states that the meter must
start up with a load equal to or less than 0.4% Ib. For a 5 A (Ib)
meter, 0.4% of Ib is equivalent to 20 mA.

Frequency Outputs

Figure 2 shows a timing diagram for the various frequency
outputs. The F1 and F2 outputs are the low frequency outputs
that can be used to directly drive a stepper motor or electro­mechanical impulse counter. The F1 and F2 outputs provide
two alternating low frequency pulses. The F1 and F2 pulse
widths (t

) are set such that if they fall below 240 ms (0.24 Hz),

1

they are set to half of their period. The maximum output
frequencies for F1 and F2 are shown in Tabl e 6.

The high frequency CF output is intended for communications

nd calibration purposes. CF produces a 90-ms-wide active

a
high pulse (t

) at a frequency proportional to active power. The

4

CF output frequencies are given in Table 7. As with F1 and F2,
if t

he period of CF (t

) falls below 180 ms, the CF pulse width is

5

set to half the period. For example, if the CF frequency is 20 Hz,
the CF pulse width is 25 ms.

When high frequency mode is selected (SCF = 0, S1 = S0 = 1),
t

he CF pulse width is fixed at 35 μs. Therefore, t

is always 35 μs,

4

regardless of output frequency on CF.

NO-LOAD THRESHOLD

The ADE7768 includes a no-load threshold and start-up
current feature that eliminates any creep effects in the meter.
The ADE7768 is designed to issue a minimum output
frequency. Any load generating a frequency lower than this
minimum frequency does not cause a pulse to be issued on F1,
F2, or CF. The minimum output frequency is given as 0.00244%
for each of the F

frequency selections (see Tabl e 5).

1–4

NEGATIVE POWER INFORMATION

The ADE7768 detects when the current and voltage channels
have a phase shift greater than 90°. This mechanism can detect
an incorrect meter connection or the generation of negative
power. The REVP pin output goes active high when negative
power is detected and active low if positive power is detected.
The REVP pin output changes state as a pulse is issued on CF.

EVALUATION BOARD AND REFERENCE DESIGN BOARD

An evaluation board can be used to verify the functionality and
the performance of the ADE7768. Download documentation
for the board from http://www.analog.com/ADE7768.

In addition, the reference design board ADE7768ARN-REF

nd Application Note AN-679 can be used in the design

a
of a low cost watt-hour meter that surpasses IEC62053-21
accuracy specifications. Download the application note from

http://www.analog.com/ADE7768.

Rev. A | Page 16 of 20

ADE7768

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OUTLINE DIMENSIONS

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

16

1

9

6.20 (0.2441)

5.80 (0.2283)

8

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

0.10

COMPLIANT TO JEDEC STANDARDS MS-012-AC

1.75 (0.0689)

1.35 (0.0531)

0.51 (0.0201)

0.31 (0.0122)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8°
0°

1.27 (0.0500)

0.40 (0.0157)

× 45°

Figure 29. 16-Lead Standard Small Outline Package [SOIC_N]

w Body (R-16)

Narro

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADE7768AR −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16
ADE7768AR-RL −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] REEL R-16
ADE7768ARZ
ADE7768ARZ-RL1 −40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] REEL R-16
ADE7768AR-REF Reference Board
EVAL-ADE7768EB Evaluation Board

1

Z = Pb-free part.

1

−40°C to +85°C 16-Lead Standard Small Outline Package [SOIC_N] R-16

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ADE7768

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NOTES

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ADE7768

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NOTES

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ADE7768

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NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
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D05331–0–8/05(A)

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