Datasheet ADE7757 Datasheet (Analog Devices)

Energy Metering IC

with Integrated Oscillator

FEATURES
On-Chip Oscillator as Clock Source
High Accuracy, Supposes 50 Hz/60 Hz IEC 521/IEC 61036
Less than 0.1% Error over a Dynamic Range of 500 to 1
The ADE7757 Supplies Average Real Power on the

Frequency Outputs F1 and F2

The High Frequency Output CF Is Intended for

Calibration and Supplies Instantaneous Real Power

The Logic Output REVP Can Be Used to Indicate a

Potential Miswiring or Negative Power

Direct Drive for Electromechanical Counters and

2-Phase Stepper Motors (F1 and F2)

Proprietary ADCs and DSP Provide High Accuracy over

Large Variations in Environmental Conditions and

Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V (20 ppm/C Typical)

with External Overdrive Capability
Single 5 V Supply, Low Power (20 mW Typical)
Low Cost CMOS Process
AC Input Only

GENERAL DESCRIPTION

The ADE7757 is a high accuracy electrical energy measurement
IC. It is a pin reduction version of the ADE7755 with an enhance­ment of a precise oscillator circuit that serves as a clock source
to the chip. The ADE7757 eliminates the cost of an external
crystal or resonator, thus reducing the overall cost of a meter

ADE7757

*

built with this IC. The chip directly interfaces with the shunt
resistor and operates only with ac input.

The ADE7757 specifications surpass the accuracy requirements
as quoted in the IEC 61036 standard. The AN-679 Application
Note can be used as a basis for a description of an IEC 61036
low cost watt-hour meter reference design.

The only analog circuitry used in the ADE7757 is in the ⌺-⌬
ADCs and reference circuit. All other signal processing (e.g.,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
time and extreme environmental conditions.

The ADE7757 supplies average real power information on the
low frequency outputs F1 and F2. These outputs may be used
to directly drive an electromechanical counter or interface with
an MCU. The high frequency CF logic output, ideal for calibra­tion purposes, provides instantaneous real power information.

The ADE7757 includes a power supply monitoring circuit on
the V
the supply voltage on V

supply pin. The ADE7757 will remain inactive until

DD

reaches approximately 4 V. If the

DD

supply falls below 4 V, the ADE7757 will also remain inactive
and the F1, F2, and CF outputs will be in their nonactive modes.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched while the HPF in the cur­rent channel eliminates dc offsets. An internal no-load threshold
ensures that the ADE7757 does not exhibit creep when no load
is present.

The ADE7757 is available in a 16-lead SOIC narrow-body package.

FUNCTIONAL BLOCK DIAGRAM

V

AGND

DD

POWER

SUPPLY MONITOR

V2P

V2N

V1N

V1P

2.5V

REFERENCE

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others pending.

4k

REF

-

ADC

-

ADC

IN/OUT

...110101...

...11011001...

INTERNAL

OSCILLATOR

RCLKIN

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DGND

ADE7757

SIGNAL

PROCESSING

BLOCK

MULTIPLIER

PHASE

CORRECTION

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

HPF



DIGITAL-TO-FREQUENCY

S0

SCF

LPF

CONVERTER

REVP

S1

CF

F1

F2

(VDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 k,

ADE7757–SPECIFICATIONS

Parameter Value Unit Test Conditions/Comments

ACCURACY

Measurement Error1 on Channel V1 Channel V2 with Full-Scale Signal (± 165 mV), 25°C

Phase Error

V1 Phase Lead 37°
(PF = 0.8 Capacitive) ± 0.1 Degrees (°) max
V1 Phase Lag 60°
(PF = 0.5 Inductive) ± 0.1 Degrees (°) max

AC Power Supply Rejection

Output Frequency Variation (CF) 0.2 % Reading typ V1 = 21.2 mV rms, V2 = 116.7 mV rms @ 50 Hz

DC Power Supply Rejection

Output Frequency Variation (CF) ± 0.3 % Reading typ V1 = 21.2 mV rms, V2 = 116.7 mV rms,

ANALOG INPUTS See Analog Inputs section

Channel V1 Maximum Signal Level ± 30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level ± 165 mV max V2P and V2N to AGND
Input Impedance (DC) 320 kΩ min OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 5
Bandwidth (–3 dB) 7 kHz nominal OSC = 450 kHz, RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C
ADC Offset Error
Gain Error

OSCILLATOR FREQUENCY (OSC) 450 kHz nominal RCLKIN = 6.2 kΩ, 0.5% ± 50 ppm/°C

Oscillator Frequency Tolerance
Oscillator Frequency Stability

REFERENCE INPUT

REF

Input Capacitance 10 pF max

ON-CHIP REFERENCE Nominal 2.5 V

Reference Error ± 200 mV max
Temperature Coefficient ± 20 ppm/°C typ

LOGIC INPUTS

SCF, S0, S1,

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

LOGIC OUTPUTS

F1 and F2

Output High Voltage, V

Output Low Voltage, V

CF

Output High Voltage, V

Output Low Voltage, VOL I

Frequency Output Error

POWER SUPPLY For Specified Performance

V

DD

I

DD

NOTES

1

See Terminology section for explanation of specifications.

2

See plots in Typical Performance Characteristics.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

Specifications subject to change without notice.

1, 2

1

between Channels Line Frequency = 45 Hz to 65 Hz

1

1

1, 2

1

1

1

Input Voltage Range 2.7 V max 2.5 V + 8%

IN/OUT

0.1 % Reading typ Over a Dynamic Range 500 to 1

± 18 mV max See Terminology Section and Typical Performance Characteristics
± 4% Ideal typ External 2.5 V Reference

± 12 % Reading typ
± 30 ppm/°C typ

2.3 V min 2.5 V – 8%

3

INH

INL

IN

IN

3

OH

2.4 V min VDD = 5 V ± 5%

0.8 V max VDD = 5 V ± 5%
± 1 µA max Typically 10 nA, VIN = 0 V to V
10 pF max

4.5 V min VDD = 5 V

OL

0.5 V max V

OH

4V min V

1, 2

(CF) ± 10 % Ideal typ External 2.5 V Reference,

0.5 V max V

4.75 V min 5 V – 5%

5.25 V max 5 V + 5%
5 mA max Typically 4 mA

0.5%  50 ppm/C, T

S0 = S1 = 1,

Ripple on V
S0 = S1 = 1,

VDD = 5 V ± 250 mV

V1 = 21.2 mV rms, V2 = 116.7 mV rms

I

SOURCE

I

SINK

= 5 V

DD

I

SOURCE

= 5 V

DD

SINK

= 5 V

DD

V1 = 21.2 mV rms, V2 = 116.7 mV rms

to T

MIN

DD

= 10 mA

= 10 mA

= 5 mA

= 5 mA

= –40C to +85C, unless otherwise noted.)

MAX

of 200 mV rms @ 100 Hz

0

ppm/°C

DD

REV. A–2–

(VDD = 5 V  5%, AGND = DGND = 0 V, On-Chip Reference, RCLKIN = 6.2 kΩ,

1, 2

TIMING CHARACTERISTICS

0.5%  50 ppm/C, T

MIN

to T

= –40C to +85C, unless otherwise noted.)

MAX

Parameter A, B Versions Unit Test Conditions/Comments

3

t

1

t

2

t

3

3, 4

t

4

t

5

t

6

NOTES

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See Figure 1.

3

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section.

4

The CF pulse is always 35 µs in the high frequency mode. See Frequency Outputs section and Table III.

Specifications subject to change without notice.

244 ms F1 and F2 Pulse Width (Logic Low).
See Table II sec Output Pulse Period. See Transfer Function section.
1/2 t

2

sec Time between F1 Falling Edge and F2 Falling Edge.
173 ms CF Pulse Width (Logic High).
See Table III sec CF Pulse Period. See Transfer Function section.
2 µs Minimum Time between F1 and F2 Pulses.

t

1

F1

t

6

t

2

ADE7757

F2

CF

t

3

t

4

t

5

Figure 1. Timing Diagram for Frequency Outputs

REV. A

–3–

ADE7757

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

DD

Analog Input Voltage to AGND

V1P, V1N, V2P, and V2N . . . . . . . . . . . . . . . . –6 V to +6 V

Reference Input Voltage to AGND . . . –0.3 V to V

Digital Input Voltage to DGND . . . . . –0.3 V to V

Digital Output Voltage to DGND . . . . –0.3 V to V

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350 mW

Thermal Impedance2 . . . . . . . . . . . . . . . . . . .124.9°C/W

␪

JA

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

JEDEC 1S Standard (2-layer) Board Data.

ORDERING GUIDE

Model Package Description Package Options

ADE7757ARN SOIC Narrow-Body RN-16
ADE7757ARNRL SOIC Narrow-Body RN-16

in Reel
EVAL-ADE7757EB Evaluation Board Evaluation Board
ADE7757ARN-REF Reference Design Reference Design

TERMINOLOGY
Measurement Error

The error associated with the energy measurement made by the
ADE7757 is defined by the following formula

%–Error

Phase Error between Channels

Energy Registered by ADE True Energy

=

True Energy

7757

¥ 100%

The HPF (high-pass filter) in the current channel (Channel V1)
has a phase lead response. To offset this phase response and
equalize the phase response between channels, a phase correc­tion network is also placed in Channel V1. The phase correction
network matches the phase to within ± 0.1° over a range of 45 Hz
to 65 Hz, and ± 0.2° over a range 40 Hz to 1 kHz (see Figures
11 and 12).

Power Supply Rejection

This quantifies the ADE7757 measurement error as a percent­age of reading when the power supplies are varied.

For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see the Measurement Error definition.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied ± 5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

ADC Offset Error

This refers to the small dc signal (offset) associated with the
analog inputs to the ADCs. However, the HPF in Channel V1
eliminates the offset in the circuitry. Therefore, the power cal­culation is not affected by this offset.

Frequency Output Error (CF)

The frequency output error of the ADE7757 is defined as the
difference between the measured output frequency (minus
the offset) and the ideal output frequency. The difference is
expressed as a percentage of the ideal frequency. The ideal
frequency is obtained from the ADE7757 transfer function
(see the Transfer Function section).

Gain Error

The gain error of the ADE7757 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is obtained
from the ADE7757 transfer function (see the Transfer Function
section).

Oscillator Frequency Tolerance

The oscillator frequency tolerance of the ADE7757 is defined as
part-to-part frequency variation in terms of percentage at room
temperature (25°C). It is measured by taking the difference
between the measured oscillator frequency and the nominal
frequency defined in the Specifications section.

Oscillator Frequency Stability

Oscillator frequency stability is defined as frequency variation
in terms of parts-per-million drift over the operating tem­perature range. In a metering application, the temperature
range is –40°C to +85°C. Oscillator frequency stability is
measured by taking the difference between the measured
oscillator frequency at –40°C and +85°C and the measured
oscillator frequency at +25°C.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADE7757 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. A–4–

PIN CONFIGURATION

ADE7757

REF

V

V2P

V2N

V1N

V1P

AGND

IN/OUT

SCF

DD

1

2

3

ADE7757

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

F1

F2

CF

DGND

REVP

RCLKIN

S0

S1

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1V

DD

Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The supply voltage
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 µF
capacitor in parallel with a ceramic 100 nF capacitor.

2, 3 V2P, V2N Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential input pair. The

maximum differential input voltage is ± 165 mV for specified operation. Both inputs have internal ESD
protection circuitry; an overvoltage of ± 6 V can be sustained on these inputs without risk of permanent
damage.

4, 5 V1N, V1P Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage inputs with a

maximum signal level of ± 30 mV with respect to the V1N pin for specified operation. Both inputs have
internal ESD protection circuitry and, in addition, an overvoltage of ±6 V can be sustained on these
inputs without risk of permanent damage.

6 AGND This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and reference.

This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage sensors, and so forth. For
accurate noise suppression, the analog ground plane should be connected to the digital ground plane at
only one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.

7 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V and a typical temperature coefficient of 20 ppm/°C. An external reference source may also
be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF tanta-
lum capacitor and a 100 nF ceramic capacitor. The internal reference cannot be used to drive an
external load.

8 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibration output

CF. Table III shows calibration frequencies selection.

9, 10 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conver-

sion. With this logic input, designers have greater flexibility when designing an energy meter. See the
Selecting a Frequency for an Energy Meter Application section.

11 RCLKIN To enable the internal oscillator as a clock source to the chip, a precise low temperature drift resistor at a

nominal value of 6.2 kΩ must be connected from this pin to DGND.

12 REVP This logic output will go high when negative power is detected, i.e., when the phase angle between the

voltage and current signals is greater than 90°. This output is not latched and will be reset when positive
power is once again detected. The output will go high or low at the same time that a pulse is issued on CF.

13 DGND This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier, filters, and

digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digi­tal ground plane is the ground reference for all digital circuitry, e.g., counters (mechanical and digital),
MCUs, and indicator LEDs. For accurate noise suppression, the analog ground plane should be con­nected to the digital ground plane at one point only, i.e., a star ground.

14 CF Calibration Frequency Logic Output. The CF logic output provides instantaneous real power informa-

tion. This output is intended for calibration purposes. Also see SCF pin description.

15, 16 F2, F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can

be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Func­tion section.

REV. A

–5–

ADE7757–Typical Performance Characteristics

V

DD

602k

1F

200

150nF

200

150nF

200

150nF

200

150nF

100nF

220V

40A TO

350

40mA

Figure 2. Test Circuit for Performance Curves

0.5
PF = 1

ON-CHIP REFERENCE

0.4

0.3

0.2

0.1

0

% ERROR

–0.1

–0.2

–0.3

–0.4

–0.5

0.01 0.1 1 10 100

+25C

CURRENT – A

+85C

–40C

V2P

ADE7757

V2N

V1P

V1N

REF

IN/OUT

AGND

V

DD

U1

DGND

CF

REVP

RCLKIN

S0

SCF

100nF

F1

F2

6.2k

S1

10nF 10nF 10nF

% ERROR

–0.2

–0.4

–0.6

–0.8

–1.0

10F

PS2501-1

V

DD

10k

+85C

K7

K8

+25C

–40C

CURRENT – A

U3

1.0
PF = 1

EXTERNAL REFERENCE

0.8

0.6

0.4

0.2

0

0.01 0.1 1 10 100

TPC 1. Error as a % of Reading over Temperature
with On-Chip Reference (PF = 1)

0.9
PF = 0.5

ON-CHIP REFERENCE

0.7

0.5

0.3

0.1

% ERROR

+25C, PF = 1.0

–0.1

–0.3

–0.5

0.01 0.1 1 10 100

–40C, PF = 0.5

+85C, PF = 0.5

–25C, PF = 0.5

CURRENT – A

TPC 2. Error as a % of Reading over Temperature
with On-Chip Reference (PF = 0.5)

TPC 3. Error as a % of Reading over Temperature
with External Reference (PF = 1)

1.0
PF = 0.5

EXTERNAL REFERENCE

0.8

0.6

0.4

0.2

0

% ERROR

–0.2

–0.4

–0.6

–0.8

–1.0

0.01 0.1 1 10 100

+25C, PF = 1.0

CURRENT – A

+85C, PF = 0.5

+25C, PF = 0.5

–40C, PF = 0.5

TPC 4. Error as a % of Reading over Temperature
with External Reference (PF = 0.5)

REV. A–6–

ADE7757

0.5

0.4

0.3

0.2

0.1

0

% ERROR

–0.1

–0.2

–0.3

–0.4

–0.5

45

PF = +0.5

PF = –0.5

PF = +1.0

50 55 60 65

FREQUENCY – Hz

TPC 5. Error as a % of Reading over Input Frequency

1.0
PF = 1

ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

% ERROR

–0.2

–0.4

–0.6

–0.8

–1.0

0.01

0.1 1 10 100

5.25V

5.0V

4.75V

CURRENT – A

TPC 6. PSR with Internal Reference

45

DISTRIBUTION CHARACTERISTICS

40

NUMBER POINTS: 100
MINIMUM: –4.319mV
MAXIMUM: 2.2828mV

35

MEAN: –1.04576552mV
STD. DEV: 1.300956604mV

30

25

20

15

10

0.5

0

–8

–7 –6 –5 –4 –3 –2 –1 876543210

INTERNAL REFERENCE

TEMPERATURE = 25C

mV

TPC 8. Channel V1 Offset Distribution

45

DISTRIBUTION CHARACTERISTICS

40

NUMBER POINTS: 100
MINIMUM: –9.82923mV
MAXIMUM: 0.472126mV

35

MEAN: 4.54036589mV
STD. DEV: 1.89694475mV

30

25

20

15

10

0.5

0

–8

INTERNAL REFERENCE

TEMPERATURE = 25C

–6 –4 –2 86420–10–12–14–16–18–20 10

mV

TPC 9. Channel V2 Offset Distribution

% ERROR

REV. A

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0.01 0.1 1 10 100
CURRENT – A

PF = 1
EXTERNAL REFERENCE

5.25V

5.0V

4.75V

TPC 7. PSR with External Reference

–7–

40

DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 100

35

MINIMUM: –6.15%
MAXIMUM: 9.96%
MEAN: 0%

30

STD. DEV: 2.84%

25

20

15

10

0.5

0

–18

–20

–16

–14

–12

–10

–8

–6–4–2

EXTERNAL REFERENCE

TEMPERATURE = 25C

8

6

4

2

0

%

1012141618

20

TPC 10. Part-to-Part CF Distribution from Mean

ADE7757

THEORY OF OPERATION

The two ADCs digitize the voltage signals from the current
and voltage sensors. These ADCs are 16-bit ⌺-⌬ with an
oversampling rate of 450 kHz. This analog input structure
greatly simplifies sensor interfacing by providing a wide dynamic
range for direct connection to the sensor and also simplifies the
antialiasing filter design. A high-pass filter in the current chan­nel removes any dc component from the current signal. This
eliminates any inaccuracies in the real power calculation due to
offsets in the voltage or current signals. Because the HPF is
always enabled, the IC will operate only with ac input (see HPF
and Offset Effects section).

The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. In order
to extract the real power component (i.e., the dc component),
the instantaneous power signal is low-pass filtered. Figure 3
illustrates the instantaneous real power signal and shows how
the real power information can be extracted by low-pass filtering
the instantaneous power signal. This scheme correctly calculates
real power for sinusoidal current and voltage waveforms at all
power factors. All signal processing is carried out in the digital
domain for superior stability over temperature and time.

DIGITAL-TO­FREQUENCY

DIGITAL-TO­FREQUENCY

INSTANTANEOUS REAL

POWER SIGNAL

F1

F2

CF

CH1

CH2

HPF

ADC

MULTIPLIER

ADC

INSTANTANEOUS

POWER SIGNAL – p(t)

LPF

The low frequency outputs (F1, F2) of the ADE7757 are gener­ated by accumulating this real power information. This low
frequency inherently means a long accumulation time between
output pulses. Consequently, the resulting output frequency is
proportional to the average real power. This average real power
information is then accumulated (e.g., by a counter) to generate
real energy information. Conversely, due to its high output
frequency and hence shorter integration time, the CF output
frequency is proportional to the instantaneous real power. This
is useful for system calibration, which can be done faster under
steady load conditions.

Power Factor Considerations

The method used to extract the real power information from the
instantaneous power signal (i.e., by low-pass filtering) is still
valid even when the voltage and current signals are not in phase.
Figure 4 displays the unity power factor condition and a DPF
(displacement power factor) = 0.5, i.e., current signal lagging the
voltage by 60°. If we assume the voltage and current waveforms
are sinusoidal, the real power component of the instantaneous
power signal (i.e., the dc term) is given by





V ×

1

×°

60cos




()




2

This is the correct real power calculation.

V  I

2

POWER

0V

INSTANTANEOUS

POWER SIGNAL

INSTANTANEOUS REAL

POWER SIGNAL

TIME

TIME TIME

Figure 3. Signal Processing Block Diagram

CURRENT

V  I

2

POWER

COS (60)

VOLTAGE

INSTANTANEOUS

POWER SIGNAL

0V

VOLTAGE CURRENT

INSTANTANEOUS REAL

POWER SIGNAL

60

Figure 4. DC Component of Instantaneous Power
Signal Conveys Real Power Information, PF < 1

TIME

REV. A–8–

ADE7757

Nonsinusoidal Voltage and Current

The real power calculation method also holds true for
nonsinusoidal current and voltage waveforms. All voltage and
current waveforms in practical applications will have some har­monic content. Using the Fourier Transform, instantaneous
voltage and current waveforms can be expressed in terms of
their harmonic content.

vt V 2

=+ × × +

()

0

∞

Σ

Vhtsin

hh

≠

ho

ωα

()

(1)

where:

v(t) is the instantaneous voltage.
V

is the average value.

0

Vhis the rms value of voltage harmonic h.

is the phase angle of the voltage harmonic.

␣

h

it I

=+ × × +

()

0

2 Σ

ho

∞

Ihtsin

hh

≠

ωβ

()

(2)

where:

i(t) is the instantaneous current.
I

is the dc component.

0

is the rms value of current harmonic h.

I

h

is the phase angle of the current harmonic.

␤

h

Using Equations 1 and 2, the real power P can be expressed in
terms of its fundamental real power (P
power (P

).

H

PPP

=+

) and harmonic real

1

H

1

where

PV I

=×=cos–φ

111 1

φαβ

111

(3)

and

PVI

=∑ ×

H

h

≠∞1

=

φαβ

hhh

cos–φ

hh h

(4)

As can be seen from Equation 4, a harmonic real power compo­nent is generated for every harmonic, provided that harmonic is
present in both the voltage and current waveforms. The power
factor calculation has previously been shown to be accurate in
the case of a pure sinusoid. Therefore, the harmonic real power
must also correctly account for power factor since it is made up
of a series of pure sinusoids.

Note that the input bandwidth of the analog inputs is 7 kHz at
the nominal internal oscillator frequency of 450 kHz.

ANALOG INPUTS
Channel V1 (Current Channel)

The voltage output from the current sensor is connected to the
ADE7757 here. Channel V1 is a fully differential voltage input.
V1P is the positive input with respect to V1N.

The maximum peak differential signal on Channel V1 should be
less than ±30 mV (21 mV rms for a pure sinusoidal signal) for
specified operation.

V1

+30mV

V

CM

–30mV

DIFFERENTIAL INPUT

ⴞ30mV MAX PEAK

COMMON-MODE

ⴞ6.25mV MAX

AGND

V1P

+

V1

–

V1N

+

V

–

CM

Figure 5. Maximum Signal Levels, Channel V1

The diagram in Figure 5 illustrates the maximum signal levels
on V1P and V1N. The maximum differential voltage is ±30 mV.
The differential voltage signal on the inputs must be referenced
to a common mode, e.g., AGND. The maximum common­mode signal is ±6.25 mV, as shown in Figure 5.

Channel V2 (Voltage Channel)

The output of the line voltage sensor is connected to the
ADE7757 at this analog input. Channel V2 is a fully differen­tial voltage input with a maximum peak differential signal of
± 165 mV. Figure 6 illustrates the maximum signal levels that
can be connected to the ADE7757 Channel V2.

V2

+165mV

V

–165mV

DIFFERENTIAL INPUT

CM

ⴞ165mV MAX PEAK

COMMON-MODE

ⴞ25mV MAX

+
–

+
–

AGND

V2P

V2

V2N

V

CM

Figure 6. Maximum Signal Levels, Channel V2

Channel V2 is usually driven from a common-mode voltage,
i.e., the differential voltage signal on the input is referenced to a
common mode (usually AGND). The analog inputs of the
ADE7757 can be driven with common-mode voltages of up to
25 mV with respect to AGND. However, best results are achieved
using a common mode equal to AGND.

REV. A

–9–

ADE7757

Typical Connection Diagrams

Figure 7 shows a typical connection diagram for Channel V1. A
shunt is the current sensor selected for this example because of
its low cost compared to other current sensors such as the CT
(current transformer). This IC is ideal for low current meters.

SHUNT

AGND

PHASE NEUTRAL

R

F

30mV

R

F

V1P

C

F

V1N

C

F

Figure 7. Typical Connection for Channel V1

Figure 8 shows a typical connection for Channel V2. Typically,
the ADE7757 is biased around the phase wire, and a resistor
divider is used to provide a voltage signal that is proportional to
the line voltage. Adjusting the ratio of R

, RB, and RF is also a

A

convenient way of carrying out a gain calibration on a meter.

R

B

RA*

C

R

F

F

PHASENEUTRAL

*RA >> RB + R

F

165mV

R

F

V2P

V2N

C

F

Figure 8. Typical Connections for Channel V2

V

DD

5V
4V

0V

TIME

INTERNAL

ACTIVATION

INACTIVE ACTIVE INACTIVE

Figure 9. On-Chip Power Supply Monitor

HPF and Offset Effects

Figure 10 illustrates the effect of offsets on the real power calcu­lation. As can be seen, offsets on Channel V1 and Channel V2
will contribute a dc component after multiplication. Since this
dc component is extracted by the LPF and used to generate the
real power information, the offsets will contribute a constant
error to the real power calculation. This problem is easily avoided
by the built-in HPF in Channel V1. By removing the offsets
from at least one channel, no error component can be generated
at dc by the multiplication. Error terms at the line frequency (␻)
are removed by the LPF and the digital-to-frequency conversion
(see Digital-to-Frequency Conversion section).

The equation below shows how the power calculation is affected
by the dc offsets in the current and voltage channels.

POWER SUPPLY MONITOR

The ADE7757 contains an on-chip power supply monitor. The
power supply (V

) is continuously monitored by the ADE7757.

DD

If the supply is less than 4 V, the ADE7757 becomes inactive.
This is useful to ensure proper device operation at power-up
and power-down. The power supply monitor has built in hyster­esis and filtering that provide a high degree of immunity to false
triggering from noisy supplies.

As can be seen from Figure 9, the trigger level is nominally set
at 4 V. The tolerance on this trigger level is within ± 5%. The
power supply and decoupling for the part should be such that
the ripple at V

does not exceed 5 V ± 5% as specified for

DD

normal operation.

VtVItI

cos cos

ωω

+

()

{}

VI

×

=

VI

+

VIVI tIV t

+×+×

2

×

cos

×

2

V

 I

OS

OS

V  I

2

×

{}

OS OS

OS OS OS OS

ω

2

t

()

DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR REAL
POWER CALCULATION

IOS  V

V

0

FREQUENCY – RAD/s

+

()

cos cos

ωω

()

 I

OS

+×

()

Figure 10. Effect of Channel Offset on the Real
Power Calculation

REV. A–10–

ADE7757

LPF

F1

F2

DIGITAL-TO­FREQUENCY

CF

DIGITAL-TO­FREQUENCY

MULTIPLIER

F1

TIME

CF

TIME

FREQUENCY FREQUENCY

V

I

0

FREQUENCY (RAD/s)



2

COS (2)

ATTENUATED BY LPF

V I

2

LPF TO EXTRACT

REAL POWER

(DC TERM)

INSTANTANEOUS REAL POWER SIGNAL

(FREQUENCY DOMAIN)

The HPF in Channel V1 has an associated phase response that
is compensated for on-chip. Figures 11 and 12 show the phase
error between channels with the compensation network acti­vated. The ADE7757 is phase compensated up to 1 kHz as
shown. This will ensure correct active harmonic power calcula­tion even at low power factors.

0.30

0.25

0.20

0.15

0.10

0.05

PHASE – Degrees

0

–0.05

–0.10

0 100 200 300 400 500 600 700 800 900 1000

FREQUENCY – Hz

Figure 11. Phase Error between Channels (0 Hz to 1 kHz)

0.30

0.25

For a line frequency of 50 Hz, this would give an attenuation
of the 2␻ (100 Hz) component of approximately 22 dB. The
dominating harmonic will be at twice the line frequency (2␻)
due to the instantaneous power calculation.

Figure 13 shows the instantaneous real power signal at the output
of the LPF that still contains a significant amount of instanta­neous power information, i.e., cos(2␻t). This signal is then passed
to the digital-to-frequency converter where it is integrated
(accumulated) over time in order to produce an output frequency.
The accumulation of the signal will suppress or average out any
non-dc components in the instantaneous real power signal. The
average value of a sinusoidal signal is zero. Thus, the frequency
generated by the ADE7757 is proportional to the average real
power. Figure 13 shows the digital-to-frequency conversion for
steady load conditions, i.e., constant voltage and current.

0.20

0.15

0.10

0.05

PHASE – Degrees

0

–0.05

–0.10

40 45 50 55 60 65 70

FREQUENCY – Hz

Figure 12. Phase Error between Channels (40 Hz to 70 Hz)

Digital-to-Frequency Conversion

As previously described, the digital output of the low-pass filter
after multiplication contains the real power information. However,
since this LPF is not an ideal “brick wall” filter implementation,
the output signal also contains attenuated components at the
line frequency and its harmonics, i.e., cos(h␻t) where h = 1, 2,
3, . . . and so on.

The magnitude response of the filter is given by

|H f

()

=+|

1

1

2

f

.

445

2

(5)

Figure 13. Real Power-to-Frequency Conversion

As can be seen in the diagram, the frequency output CF is seen
to vary over time, even under steady load conditions. This fre­quency variation is primarily due to the cos(2␻t) component in
the instantaneous real power signal. The output frequency on
CF can be up to 2048 times higher than the frequency on F1
and F2. This higher output frequency is generated by accumu­lating the instantaneous real power signal over a much shorter
time while converting it to a frequency. This shorter accumula­tion period means less averaging of the cos(2␻t) component.
Consequently, some of this instantaneous power signal passes
through the digital-to-frequency conversion. This will not be a
problem in the application. Where CF is used for calibration
purposes, the frequency should be averaged by the frequency
counter, which will remove any ripple. If CF is being used to
measure energy, for example in a microprocessor based applica­tion, the CF output should also be averaged to calculate power.

Because the outputs F1 and F2 operate at a much lower fre­quency, a lot more averaging of the instantaneous real power
signal is carried out. The result is a greatly attenuated sinusoidal
content and a virtually ripple-free frequency output.

REV. A

–11–

ADE7757

Interfacing the ADE7757 to a Microcontroller for Energy Measurement

The easiest way to interface the ADE7757 to a microcontroller
is to use the CF high frequency output with the output frequency
scaling set to 2048 × F1, F2. This is done by setting SCF = 0
and S0 = S1 = 1 (see Table III). With full-scale ac signals on
the analog inputs, the output frequency on CF will be approxi­mately 2.867 kHz. Figure 14 illustrates one scheme that could
be used to digitize the output frequency and carry out the neces­sary averaging mentioned in the previous section.

CF

FREQUENCY

RIPPLE

AVERAGE

FREQUENCY

ADE7757

TIME

COUNTER

CF

10%

MCU

TIMER

Figure 14. Interfacing the ADE7757 to an MCU

As shown, the frequency output CF is connected to an MCU
counter or port. This will count the number of pulses in a given
integration time, which is determined by an MCU internal timer.
The average power proportional to the average frequency is
given by

Average Frequency Average Power

==

Counter

Time

The energy consumed during an integration period is given by

Energy Average Power Time

Counter

Time

Time Counter=×=×=

For the purpose of calibration, this integration time could be
10 seconds to 20 seconds in order to accumulate enough pulses to
ensure correct averaging of the frequency. In normal opera­tion, the integration time could be reduced to one or two seconds,
depending, for example, on the required update rate of a dis­play. With shorter integration times on the MCU, the amount
of energy in each update may still have some small amount of
ripple, even under steady load conditions. However, over a
minute or more the measured energy will have no ripple.

Power Measurement Considerations

Calculating and displaying power information will always have
some associated ripple that will depend on the integration period
used in the MCU to determine average power and also on the
load. For example, at light loads, the output frequency may be
10 Hz. With an integration period of two seconds, only about
20 pulses will be counted. The possibility of missing one pulse
always exists as the ADE7757 output frequency is running
asynchronously to the MCU timer. This would result in a one­in-twenty or 5% error in the power measurement.

INTERNAL OSCILLATOR (OSC)

The nominal internal oscillator frequency is 450 kHz when used
with RCLKIN with a nominal value of 6.2 kΩ. The frequency
outputs are directly proportional to the oscillator frequency,
thus RCLKIN must have low tolerance and low temperature
drift to ensure stability and linearity of the chip. The oscillator
frequency is inversely proportional to the RCLKIN as shown in
Figure 15. Although the internal oscillator operates when used
with RCLKIN values between 5.5 kΩ and 20 kΩ, choosing a
value within the range of the nominal value, as shown in Figure 15,
is recommended.

490

480

470

460

450

440

430

FREQUENCY – kHz

420

410

400

5.8 5.9 6.1 6.3 6.7

6.0 6.2 6.4 6.5 6.6

RESISTANCE – k

Figure 15. Effect of RCLKIN on Internal Oscillator
Frequency (OSC)

TRANSFER FUNCTION
Frequency Outputs F1 and F2

The ADE7757 calculates the product of two voltage signals (on
Channel V1 and Channel V2) and then low-pass filters this
product to extract real power information. This real power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active low
pulses. The pulse rate at these outputs is relatively low, e.g.,

0.175 Hz maximum for ac signals with S0 = S1 = 0 (see Table II).
This means that the frequency at these outputs is generated
from real power information accumulated over a relatively long
period of time. The result is an output frequency that is propor­tional to the average real power. The averaging of the real power
signal is implicit to the digital-to-frequency conversion. The
output frequency or pulse rate is related to the input voltage
signals by the following equation

Freq

=

rms rms

2

V

REF

14

–

.

VV F

×××515 84 1 2

where

Freq =Output frequency on F1 and F2 (Hz).
V1

=Differential rms voltage signal on Channel V1 (V).

rms

V2

=Differential rms voltage signal on Channel V2 (V).

rms

=The reference voltage (2.5 V ± 8%) (V).

V

REF

=One of four possible frequencies selected by using the

F

1-4

logic inputs S0 and S1—see Table I.

REV. A–12–

ADE7757

Table I. F

S1 S0 OSC Relation

00 OSC/2
01 OSC/2
10 OSC/2
11 OSC/2

NOTES

1

F

is a binary fraction of the internal oscillator frequency (OSC).

1–4

2

Values are generated using the nominal frequency of 450 kHz.

Frequency Selection

1–4

1

19

18

17

16

F

at Nominal

1–4

OSC (Hz)

0.86

1.72

3.44

6.86

2

Example

In this example, with ac voltages of ± 30 mV peak applied to V1
and ± 165 mV peak applied to V2, the expected output frequency
is calculated as follows:

F

= OSC/219 Hz, S0 = S1 = 0

1–4

V1

= 0.03/√2 V

rms

= 0.165/√2 V

V2

rms

= 2.5 V (nominal reference value)

V

REF

NOTE: If the on-chip reference is used, actual output frequencies may vary
from device to device due to reference tolerance of ± 8%.

Freq

515 85 0 03 0 165

×× ×

...

××

2225

F

1

=×=

2

.

0 204 0 175

F=

..

1

Table II. Maximum Output Frequency on F1 and F2

Max Frequency*

S1 S0 OSC Relation for AC Inputs (Hz)

0 0 0.204 × F
0 1 0.204 × F
1 0 0.204 × F
1 1 0.204 × F

*Values are generated using the nominal frequency of 450 kHz

1

2

3

4

0.175

0.35

0.70

1.40

Frequency Output CF

The pulse output CF (calibration frequency) is intended for
calibration purposes. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F

1–4

frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table III shows
how the two frequencies are related, depending on the states of
the logic inputs S0, S1, and SCF. Due to its relatively high
pulse rate, the frequency at CF logic output is proportional to
the instantaneous real power. As with F1 and F2, CF is derived
from the output of the low-pass filter after multiplication. How­ever, because the output frequency is high, this real power
information is accumulated over a much shorter time. There­fore, less averaging is carried out in the digital-to-frequency
conversion. With much less averaging of the real power signal,
the CF output is much more responsive to power fluctuations
(see the Signal Processing Block in Figure 3).

Table III. Maximum Output Frequency on CF

SCF S1 S0 CF Max for AC Signals (Hz)*

100128 × F1, F2 = 22.4
00064 × F1, F2 = 11.2
10164 × F1, F2 = 22.4
00132 × F1, F2 = 11.2
11032 × F1, F2 = 22.4
01016 × F1, F2 = 11.2
11116 × F1, F2 = 22.4
0112048 × F1, F2 = 2.867 kHz

*Values are generated using the nominal frequency of 450 kHz.

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Table I, the user can select one of four frequencies.
This frequency selection determines the maximum frequency on
F1 and F2. These outputs are intended for driving an energy
register (electromechanical or others). Since only four different
output frequencies can be selected, the available frequency
selection has been optimized for a meter constant of 100 imp/kWh
with a maximum current of between 10 A and 120 A. Table IV
shows the output frequency for several maximum currents (I

MAX

)
with a line voltage of 220 V. In all cases, the meter constant is
100 imp/kWh.

Table IV. F1 and F2 Frequency at 100 imp/kWh

I

(A) F1 and F2 (Hz)

MAX

12.5 0.076

25.0 0.153

40.0 0.244

60.0 0.367

80.0 0.489

120.0 0.733

The F

frequencies allow complete coverage of this range of

1–4

output frequencies (F1, F2). When designing an energy meter,
the nominal design voltage on Channel V2 (voltage) should be
set to half-scale to allow for calibration of the meter constant.
The current channel should also be no more than half-scale
when the meter sees maximum load. This will allow overcurrent
signals and signals with high crest factors to be accommodated.
Table V shows the output frequency on F1 and F2 when both
analog inputs are half-scale. The frequencies listed in Table V
align very well with those listed in Table IV for maximum load.

REV. A

–13–

ADE7757

Table V. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2–

S1 S0 F

000.86 0.051 × F

011.72 0.051 × F

103.44 0.051 × F

(Hz)* CH1 and CH2 Half-Scale AC Input*

1–4

0.044 Hz

1

0.088 Hz

2

0.176 Hz

3

116.86 0.051 × F4 0.352 Hz

*Values are generated using the nominal frequency of 450 kHz.

When selecting a suitable F
the frequency output at I

frequency for a meter design,

1–4

(maximum load) with a meter con-

MAX

stant of 100 imp/kWh should be compared with column four of
Table V. The closest frequency in Table V will determine the
best choice of frequency (F

). For example, if a meter with a

1–4

maximum current of 25 A is being designed, the output fre­quency on F1 and F2 with a meter constant of 100 imp/kWh is

0.153 Hz at 25 A and 220 V (from Table IV). Looking at Table V,
the closest frequency to 0.153 Hz in column four is 0.176 Hz.
Therefore, F3 (3.44 Hz—see Table I) is selected for this design.

Frequency Outputs

Figure 1 shows a timing diagram for the various frequency out­puts. The outputs F1 and F2 are the low frequency outputs that
can be used to directly drive a stepper motor or electromechanical
impulse counter. The F1 and F2 outputs provide two alter­nating low frequency pulses. The F1 and F2 pulse widths (t

)

1

are set such that if they fall below 1062 ms (0.942 Hz) they are
set to half of their period. The maximum output frequencies for
F1 and F2 are shown in Table II.

The high frequency CF output is intended to be used for com­munications and calibration purposes. CF produces a 173 ms wide
active high pulse (t

) at a frequency proportional to active power.

4

The CF output frequencies are given in Table III. As in the case
of F1 and F2, if the period of CF (t

) falls below 346 ms, the

5

CF pulse width is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulse width is 25 ms.

NOTE: When the high frequency mode is selected (i.e., SCF =
0, S1 = S0 = 1), the CF pulse width is fixed at 35 µs. Therefore,
t

will always be 35 µs, regardless of output frequency on CF.

4

NO LOAD THRESHOLD

The ADE7757 also includes a no-load threshold and start-up
current feature that will eliminate any creep effects in the meter.
The ADE7757 is designed to issue a minimum output frequency.
Any load generating a frequency lower than this minimum fre­quency will not cause a pulse to be issued on F1, F2, or CF.
The minimum output frequency is given as 0.0014% for each of
the F

frequency selections (see Table I). For example, for an

1–4

energy meter with a meter constant of 100 imp/kWh on F1, F2
using F
would be 0.0014% of 3.44 Hz or 4.81 × 10

3.08 × 10

(3.44 Hz), the minimum output frequency at F1 or F2

3

–3

Hz at CF (64 × F1 Hz) when SCF = S0 = 1, S1 = 0.

–5

Hz. This would be

In this example, the no-load threshold would be equivalent to

1.7 W of load or a start-up current of 8 mA at 220 V. Compare
this value to the IEC 1036 specification which states that the
meter must start up with a load equal to or less than 0.4% Ib.
For a 5 A (Ib) meter, 0.4% of Ib is equivalent to 20 mA.

Negative Power Information

The ADE7757 detects when the current and voltage channels
have a phase shift greater than 90°. This mechanism can detect
wrong connection of the meter or generation of negative power.
The REVP pin output will go active high when negative power
is detected and active low if positive power is detected. The
REVP pin output changes state as a pulse is issued on CF. The
REVP pin is not functional in the current version and will only
work in the A version (ADE7757A).

REV. A–14–

OUTLINE DIMENSIONS

16-Lead Standard Small Outline Package [SOIC]

Narrow Body

(RN-16)

Dimensions shown in millimeters and (inches)

10.00 (0.3937)

9.80 (0.3858)

4.00 (0.1575)

3.80 (0.1496)

16

1

9

6.20 (0.2441)

5.80 (0.2283)

8

ADE7757

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

COMPLIANT TO JEDEC STANDARDS MS-012AC

1.75 (0.0689)

1.35 (0.0531)

0.51 (0.0201)

0.31 (0.0122)

SEATING
PLANE

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

8
0

1.27 (0.0500)

0.40 (0.0157)

 45

REV. A

–15–

ADE7757

Revision History

Location Page

10/03—Data Sheet changed from REV. 0 to REV. A.

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Change to Typical Connection Diagrams section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

C02898–0–10/03(A)

–16–

REV. A