Analog Devices ADE7753 User Manual

PRELIMINARY TECHNICAL DA TA

Active and Apparent Energy Metering IC

with di/dt sensor interface

Preliminary Technical Data

FEATURES High Accuracy, supports IEC 61036 and IEC61268 On-Chip Digital Integrator enables direct interface with

current sensors with di/dt output

The ADE7753 supplies Active, Reactive and Apparent

Energy, Sampled Waveform, Current and Voltage RMS Less than 0.1% error over a dynamic range of 1000 to 1 Positive only energy accumulation mode available An On-Chip user Programmable threshold for line

voltage surge and SAG, and PSU supervisory Digital Power, Phase & Input Offset Calibration An On-Chip temperature sensor (±3°C typical) A SPI compatible Serial Interface A pulse output with programmable frequency An Interrupt Request pin (IRQ) and Status register Proprietary ADCs and DSP provide high accuracy data over

large variations in environmental conditions and time Reference 2.4V±8% (20 ppm/°C typical)

with external overdrive capability Single 5V Supply, Low power (25mW typical)

GENERAL DESCRIPTIONGENERAL DESCRIPTION

GENERAL DESCRIPTION

GENERAL DESCRIPTIONGENERAL DESCRIPTION

The ADE7753 is an accurate active and apparent energy measurements IC with a serial interface and a pulse output. The ADE7753 incorporates two second order sigma delta ADCs, a digital integrator (on CH1), reference circuitry, temperature sensor, and all the signal processing required to perform RMS calculation on the voltage and current, active, reactive, and apparent energy measurement.

An on-chip digital integrator provides direct interface to di/ dt current sensors such as Rogowski coils. The digital integrator eliminates the need for external analog integrator, and this solution provides excellent long-term stability and

FUNCTIONAL BLOCK DIAGRAMFUNCTIONAL BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAM

FUNCTIONAL BLOCK DIAGRAMFUNCTIONAL BLOCK DIAGRAM

HPF

PHCAL[5:0]

RESET

INTEGRATOR

冮

LPF1

MULTIPLIER

IRMSOS[11:0]

VRMSOS[11:0]

V1P

V1N

V2P

V2N

PGA

TEMP

SENSOR

PGA

2.4V

REFERENCE

AVDD

ADC

4kΩ

ADE7753*

precise phase matching between the current and voltage channels. The integrator can be switched on and off based on the current sensor selected. The ADE7753 contains an Active Energy register, an Apparent Energy register capable of holding at least TBD seconds of accumulated power at full load and rms calculation for both inputs. Data is read from the ADE7753 via the serial interface. The ADE7753 also provides a pulse output (CF) with output frequency is proportional to the active power. In addition to rms calculation and active and apparent power information, the ADE7753 also accumulates the signed reactive energy. The ADE7753 also provides various system calibration features, i.e., channel offset correction, phase calibration and power calibration. The part also incorporates a detection circuit for short duration low or high voltage variations. The ADE7753 has a positive only accumulation mode which gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit any creep when there is no load. A zero crossing output (ZX) produces an output which is synchronized to the zero crossing point of the line voltage. This information is used in the ADE7753 to measure the line's period. The signal is also used internally to the chip in the line cycle Active and Apparent energy accumulation mode. This enables a faster and more precise energy accumulation and is useful during calibration. This signal is also useful for synchronization of relay switching with a voltage zero crossing. The interrupt request output is an open drain, active low logic output. The Interrupt Status Register indicates the nature of the interrupt, and the Interrupt Enable Register controls which event produces an output on the The ADE7753 is available in 20-lead SSOP package.

DVDD

DGND

ADE7753

CFNUM[11:0]

DFC

CFDEN[11:0]

WDIV[7:0]

SAG

LPF2

WGAIN[11:0]

APOS[15:0]

VAGAIN[11:0]

VADIV[7:0]

ADE7753 REGISTERS & SERIAL INTERFACE

IRQ pin.

REF

AGND

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others Pending.

IN/OUT

CLKIN

CLKOUT

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DIN DOUT SCLK CS

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

IRQ

PRELIMINARY TECHNICAL DA TA

ADE7753–SPECIFICA TIONS

1,3

Parameter Spec Units Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth 14 kHz CLKIN = 3.579545 MHz Measurement Error

Channel 1 Range = 0.5V full-scale

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1

Gain = 2 0.1 % typ Over a dynamic range 1000 to 1

Gain = 4 0.1 % typ Over a dynamic range 1000 to 1

Gain = 8 0.1 % typ Over a dynamic range 1000 to 1

Gain = 16 0.2 % typ Over a dynamic range 1000 to 1

Channel 1 Range = 0.25V full-scale

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1

Gain = 2 0.1 % typ Over a dynamic range 1000 to 1

Gain = 4 0.1 % typ Over a dynamic range 1000 to 1

Gain = 8 0.2 % typ Over a dynamic range 1000 to 1

Gain = 16 0.2 % typ Over a dynamic range 1000 to 1

Channel 1 Range = 0.125V full-scale

Gain = 1 0.1 % typ Over a dynamic range 1000 to 1

Gain = 2 0.1 % typ Over a dynamic range 1000 to 1

Gain = 4 0.2 % typ Over a dynamic range 1000 to 1

Gain = 8 0.2 % typ Over a dynamic range 1000 to 1

Gain = 16 0.4 % typ Over a dynamic range 1000 to 1

Phase Error

AC Power Supply Rejection

Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20mV rms, Gain = 16, Range = 0.5V

DC Power Supply Rejection

Output Frequency Variation (CF) ±0.3 % typ Channel 1 = 20mV rms/60Hz, Gain = 16, Range = 0.5V

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels ±0.5 V max V1P, V1N, V2N and V2P to AGND Input Impedance (dc) 390 kΩ min Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545MHz Gain Error

Channel 1

Channel 2 ±4 % typ V2 = 0.5V dc

Gain Error Match

Channel 1

Channel 2 ±0.3 % typ Gain = 1, 2, 4, 8, 16

Offset Error

Channel 1 ±10 mV max Channel 1 Range = 0.5V Channel 2 ±10 mV max Channel 2 Range = 0.5V

WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545MHz/128 = 27.9kSPS

Channel 1 See Channel 1 Sampling

Signal-to-Noise plus distortion 62 dB typ 150mV rms/60Hz, Range = 0.5V, Gain = 2 Bandwidth (-3dB) 14 kHz CLKIN = 3.579545MHz

Channel 2 See Channel 2 Sampling

Signal-to-Noise plus distortion 52 dB typ 150mV rms/60Hz, Gain = 2 Bandwidth (-3dB) 140 Hz CLKIN = 3.579545MHz

1,4

Range = 0.5V full-scale ±4 % typ V1 = 0.5V dc

Range = 0.25V full-scale ±4 % typ V1 = 0.25V dc

Range = 0.125V full-scale ±4 % typ V1 = 0.125V dc

Range = 0.5V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16

Range = 0.25V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16

Range = 0.125V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16

on Channel 1 Channel 2 = 300mV rms/60Hz, Gain = 2

Between Channels ±0.05 ° max Line Frequency = 45Hz to 65Hz, HPF on

(AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)

AVDD = DVDD = 5V+175mV rms/ 120Hz Channel 2 = 300mV rms/60Hz, Gain = 1

AVDD = DVDD = 5V ± 250mV dc Channel 2 = 300mV rms/60Hz, Gain = 1

External 2.5V reference, Gain = 1 on Channel 1 & 2

External 2.5V reference

-2-

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PRELIMINARY TECHNICAL DA TA

ADE7753

Parameter Spec Units Test Conditions/Comments

REFERENCE INPUT

REF

Input Capacitance 10 pF max

ON-CHIP REFERENCE Nominal 2.4V at REF

Reference Error ±200 mV max

Current source 10 µA max

Output Impedance 4 kΩ min

Temperature Coefficient 20 ppm/°C typ

CLKIN Note all specifications CLKIN of 3.579545MHz

Input Clock Frequency 4 MHz max

LOGIC INPUTS

RESET, DIN, SCLK, CLKIN and CS

Input High Voltage, V Input Low Voltage, V Input Current, I Input Capacitance, C

LOGIC OUTPUTS

SAG & IRQ Open Drain outputs, 10kΩ pull up resistor

Output High Voltage, V Output Low Voltage, V

ZX & DOUT

Output High Voltage, V Output Low Voltage, V

POWER SUPPLY For specified Performance

NOTES:

See Terminology Section for explanation of Specifications

See Plots in Typical Performance Graphs

Specifications subject to change without notice

See Analog Inputs Section

Input Voltage Range 2.6 V max 2.4 V +8%

IN/OUT

2.2 V min 2.4V -8%

1 MHz min

INH

INL

2.4 V min DVDD = 5 V ± 10%

0.8 V max DVDD = 5 V ± 10% ±3 µA max Typically 10nA, VIN = 0V to DV 10 pF max

4 V min I

0.4 V max I 4 V min I

1 V max I

4.75 V min 5V - 5 %

5.25 V max 5V +5%

4.75 V min 5V - 5 %

5.25 V max 5V + 5% 3 mA max Typically 2.0 mA 4 mA max Typically 3.0 mA

SOURCE

= 0.8mA

SINK

SOURCE

= 0.8mA

SINK

SOURCE

= 7mA

SINK

= 5mA

IN/OUT

TO OUTPUT PIN

Load Circuit for Timing Specifications

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50pF

ORDERING GUIDEORDERING GUIDE

ORDERING GUIDE

ORDERING GUIDEORDERING GUIDE

MODEL Package Option* ADE7753ARS RS-20

200 µA

ADE7753ARSRL RS-20

+2.1V

1.6 mA

EVAL-ADE7753EB ADE7753 evaluation board

* RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline Package in reel.

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PRELIMINARY TECHNICAL DA TA

ADE7753 ADE7753 TIMING CHARACTERISTICS

1,2

Parameter A,B Versions Units Test Conditions/Comments

Write timing

20 ns (min) CS falling edge to first SCLK falling edge 150 ns (min) SCLK logic high pulse width 150 ns (min) SCLK logic low pulse width 10 ns (min) Valid Data Set up time before falling edge of SCLK 5 ns (min) Data Hold time after SCLK falling edge TBD ns (min) Minimum time between the end of data byte transfers. TBD ns (min) Minimum time between byte transfers during a serial write. 100 ns (min) CS Hold time after SCLK falling edge.

Read timing

TBD ns (min) Minimum time between read command (i.e. a write to Communication

Reigster) and data read.

TBD ns (min) Minimum time between data byte transfers during a multibyte read. 30 ns (min) Data access time after SCLK rising edge following a write to the

Communications Register 100 ns (max) Bus relinquish time after falling edge of SCLK. 10 ns (min) 100 ns (max) Bus relinquish time after rising edge of CS. 10 ns (min)

(AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference, CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)

NOTES

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%) and timed from a voltage level of 1.6V.

See timing diagram below and Serial Interface section of this data sheet.

Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.

Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.

Serial Write TimingSerial Write Timing

Serial Write Timing

Serial Write TimingSerial Write Timing

SCLK

DIN

t2t

Command Byte

A4 A3 A2 A1 A0

Serial Read TimingSerial Read Timing

Serial Read Timing

Serial Read TimingSerial Read Timing

DB7

Most Significant Byte

DB0 DB7

Least Significant Byte

DB0

SCLK

DIN

DOUT

000

A4 A3 A2

Command Byte

–4–

DB7

Most Significant Byte

DB0

DB7

Least Significant Byte

DB0

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PRELIMINARY TECHNICAL DA TA

ABSOLUTE MAXIMUM RATINGS*ABSOLUTE MAXIMUM RATINGS*

ABSOLUTE MAXIMUM RATINGS*

ABSOLUTE MAXIMUM RATINGS*ABSOLUTE MAXIMUM RATINGS*

(TA = +25°C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

toAVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Analog Input Voltage to AGND

V1P, V1N, V

Reference Input Voltage to AGND . . . . –0.3 V to AV

and V

. . . . . . . . . . . . . . . . . .

-6V to +6V

0.3 V Digital Input Voltage to DGND –0.3 V to DV Digital Output Voltage to DGND –0.3 V to DV

+ 0.3 V

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7753 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Storage Temperature Range . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150°C

20 Pin SSOP, Power Dissipation . . . . . . . . . . . . 450 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . 112°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ADE7753

WARNING!

ESD SENSITIVE DEVICE

T erminology

MEASUREMENT ERRORMEASUREMENT ERROR

MEASUREMENT ERROR

MEASUREMENT ERRORMEASUREMENT ERROR

The error associated with the energy measurement made by the ADE7753 is defined by the following formula:

ErrorPercentage

æ ç

ç è

PHASE ERROR BETWEEN CHANNELSPHASE ERROR BETWEEN CHANNELS

PHASE ERROR BETWEEN CHANNELS

PHASE ERROR BETWEEN CHANNELSPHASE ERROR BETWEEN CHANNELS

7753

EnergyTrue

The digital integrator and the HPF (High Pass Filter) in Channel 1 have non-ideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction network is placed in Channel 1: one for the digital integrator and the other for the HPF. Each phase correction network corrects the phase response of the corresponding component and ensures a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45Hz to 65Hz and ±0.2° over a range 40Hz to 1kHz.

POWER SUPPLY REJECTIONPOWER SUPPLY REJECTION

POWER SUPPLY REJECTION

POWER SUPPLY REJECTIONPOWER SUPPLY REJECTION

This quantifies the ADE7753 measurement error as a percentage of reading when the power supplies are varied. For the AC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the same input signal levels when an ac (175mV rms/120Hz) signal is introduced onto the supplies. Any error introduced by this AC signal is expressed as a percentage of reading—see Measurement Error definition above. For the DC PSR measurement a reading at nominal supplies (5V) is taken. A second reading is obtained with the same

EnergyTrueADEbyregisteredEnergy

100

÷ ø

input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of reading.

ADC OFFSET ERRORADC OFFSET ERROR

ADC OFFSET ERROR

ADC OFFSET ERRORADC OFFSET ERROR

This refers to the DC offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection - see characteristic curves. However, when HPF1 is switched on the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets may be removed by performing an offset calibration see Analog Inputs.

GAIN ERRORGAIN ERROR

GAIN ERROR

GAIN ERRORGAIN ERROR

The gain error in the ADE7753 ADCs is defined as the difference between the measured ADC output code (minus the offset) and the ideal output code - see Channel 1 ADC & Channel 2 ADC. It is measured for each of the input ranges on Channel 1 (0.5V, 0.25V and 0.125V). The difference is expressed as a percentage of the ideal code.

GAIN ERROR MATCHGAIN ERROR MATCH

GAIN ERROR MATCH

GAIN ERROR MATCHGAIN ERROR MATCH

The Gain Error Match is defined as the gain error (minus the offset) obtained when switching between a gain of 1 (for each of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed as a percentage of the output ADC code obtained under a gain of 1. This gives the gain error observed when the gain selection is changed from 1 to 2, 4, 8 or 16.

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ADE7753

PRELIMINARY TECHNICAL DA TA

PIN FUNCTION DESCRIPTIONPIN FUNCTION DESCRIPTION

PIN FUNCTION DESCRIPTION

PIN FUNCTION DESCRIPTIONPIN FUNCTION DESCRIPTION

Pin No.Pin No.

Pin No.

Pin No.Pin No.

2DV

3AV

4,5 V1P, V1N Analog inputs for Channel 1. This channel is intended for use with the di/dt current

6,7 V2N, V2P Analog inputs for Channel 2. This channel is intended for use with the voltage trans-

8 AGND This pin provides the ground reference for the analog circuitry in the ADE7753, i.e.

9 REF

10 DGND This provides the ground reference for the digital circuitry in the ADE7753, i.e. multi-

11 CF Calibration Frequency logic output. The CF logic output gives Active Power informa-

12 ZX Voltage waveform (Channel 2) zero crossing output. This output toggles logic high and

MNEMONICMNEMONIC

MNEMONIC

MNEMONICMNEMONIC

RESET Reset pin for the ADE7753. A logic low on this pin will hold the ADCs and digital

circuitry (including the Serial Interface) in a reset condition.

IN/OUT

SAG This open drain logic output goes active low when either no zero crossings are detected

IRQ Interrupt Request Output. This is an active low open drain logic output. Maskable

Digital power supply. This pin provides the supply voltage for the digital circuitry in the ADE7753. The supply voltage should be maintained at 5V ± 5% for specified operation. This pin should be decoupled to DGND with a 10µF capacitor in parallel with a ceramic 100nF capacitor.

Analog power supply. This pin provides the supply voltage for the analog circuitry in the ADE7753. The supply should be maintained at 5V ± 5% for specified operation. Every effort should be made to minimize power supply ripple and noise at this pin by the use of proper decoupling. The typical performance graphs in this data sheet show the power supply rejection performance. This pin should be decoupled to AGND with a 10µF capacitor in parallel with a ceramic 100nF capacitor.

transducer such as Rogowski coil or other current sensor such as shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5V, ±0.25V and ±0.125V, depending on the full scale selection - See Analog Inputs. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8 or 16. The maximum signal level at these pins with respect to AGND is ±0.5V. Both inputs have internal ESD protection circuitry and in addition an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage.

ducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8 or

16. The maximum signal level at these pins with respect to AGND is ±0.5V. Both inputs have internal ESD protection circuitry, and an overvoltage of ±6V can be sustained on these inputs without risk of permanent damage.

ADCs and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g. anti-aliasing filters, current and voltage transducers etc. In order to keep ground noise around the ADE7753 to a minimum, the quiet ground plane should only connected to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane - see Applications Information.

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4V ± 8% and a typical temperature coefficient of 20ppm/°C. An external reference source may also be connected at this pin. In either case this pin should be decoupled to AGND with a 1µF ceramic capacitor.

plier, filters and digital-to-frequency converter. Because the digital return currents in the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane of the system - see Applications Information. However, high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance.

tion. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM Register—see Energy To Frequency Conversion.

low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection.

or a low voltage threshold (Channel 2) is crossed for a specified duration. See Line Volt-

age Sag Detection.

interrupts include: Active Energy Register roll-over, Active Energy Register at half level, and arrivals of new waveform samples. See ADE7753 Interrupts.

DESCRIPTIONDESCRIPTION

DESCRIPTION

DESCRIPTIONDESCRIPTION

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PRELIMINARY TECHNICAL DA TA

ADE7753

Pin No.Pin No.

Pin No.

Pin No.Pin No.

MNEMONICMNEMONIC

MNEMONIC

MNEMONICMNEMONIC

DESCRIPTIONDESCRIPTION

DESCRIPTION

DESCRIPTIONDESCRIPTION

15 CLKIN Master clock for ADCs and digital signal processing. An external clock can be pro-

vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock frequency for specified operation is 3.579545MHz. Ceramic load capacitors of between 22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manufacturers data sheet for load capacitance requirements.

16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a

clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used.

CS Chip Select. Part of the four wire SPI Serial Interface. This active low logic input al-

lows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial Interface.

18 SCLK Serial Clock Input for the synchronous serial interface. All Serial data transfers are

synchronized to this clock—see ADE7753 Serial Interface. The SCLK has a schmitt-trigger input for use with a clock source which has a slow edge transition time, e.g., optoisolator outputs.

19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of

SCLK. This logic output is normally in a high impedance state unless it is driving data onto the serial data bus—see ADE7753 Serial Interface..

20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of

SCLK—see ADE7753 Serial Interface..

REF

RESET

DVDD AVDD

V1P

V1N

V2N V2P

AGND

IN/OUT

DGND

PIN CONFIGURATIONPIN CONFIGURATION

PIN CONFIGURATION

PIN CONFIGURATIONPIN CONFIGURATION

SSOP Packages

20 19 18 17

15 14 13 12

DIN DOUT SCLK CS CLKOU CLKIN IRQ

SAG ZX CF

1 2 3 4 5 6 7 8 9

ADE7753

TOP VIEW

(Not to Scale)

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PRELIMINARY TECHNICAL DA TA

ADE7753

Typical Performance Characteristics-ADE7753

–8–

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PRELIMINARY TECHNICAL DA TA

V.I

frequency (rad/s)

ω 2ω

VOS.I

IOS.V

DC component (including error term) is extracted by the LPF for real power calculation

ANALOG INPUTSANALOG INPUTS

ANALOG INPUTS

ANALOG INPUTSANALOG INPUTS

The ADE7753 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N are ±0.5V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/ V2N are ±0.5V with respect to AGND. Each analog input channel has a PGA (Programmable Gain Amplifier) with possible gain selections of 1, 2, 4, 8 and 16. The gain selections are made by writing to the Gain register—see Figure 2. Bits 0 to 2 select the gain for the PGA in Channel 1 and the gain selection for the PGA in Channel 2 is made via bits 5 to 7. Figure 1 shows how a gain selection for Channel 1 is made using the Gain register.

GAIN[7:0]

Gain (k)

k.V

selection

Offset Adjust (±50mV)

V1P

V1N

CH1OS[7:0] Bit 0 to 5: Sign magnitude coded offset correction Bit 6: Not used Bit 7: Digital Integrator (On=1, Off=0; default ON)

Figure 1— PGA in Channel 1

In addition to the PGA, Channel 1 also has a full scale input range selection for the ADC. The ADC analog input range selection is also made using the Gain register—see Figure 2. As mentioned previously the maximum differential input voltage is 1V. However, by using bits 3 and 4 in the Gain register, the maximum ADC input voltage can be set to 0.5V,

0.25V or 0.125V. This is achieved by adjusting the ADC reference—see ADE7753 Reference Circuit. Table I below sum- marizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections.

ADE7753

GAIN REGISTER*

Channel 1 and Channel 2 PGA Control

PGA 2 Gain Select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16

*Register contents show power on defaults

Figure 2— ADE7753 Analog Gain register

It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the Offset Correction Registers (CH1OS and CH2OS respectively). These registers allow channel offsets in the range ±20mV to ±50mV (depending on the gain setting) to be removed. Note that it is not necessary to perform an offset correction in an Energy measurement application if HPF in Channel 1 is switched on. Figure 3 shows the effect of offsets on the real power calculation. As can be seen from Figure 3, an offset on Channel 1 and Channel 2 will contribute a dc component after multiplication. Since this dc component is extracted by LPF2 to generate the Active (Real) Power information, the offsets will have contributed an error to the Active Power calculation. This problem is easily avoided by enabling HPF in Channel

1. By removing the offset from at least one channel, no error component is generated at dc by the multiplication. Error terms at Cos(w.t) are removed by LPF2 and by integration of the Active Power signal in the Active Energy register (AENERGY[23:0]) – see Energy Calculation.

01234

ADDR: 0FH

00000000

PGA 1 Gain Select 000 = x1 001 = x2 010 = x4 011 = x8 100 = x16

Channel 1 Full Scale Select 00 = 0.5V 01 = 0.25V 10 = 0.125V

Table ITable I

Table I

Table ITable I

Maximum input signal levels for Channel 1

Max SignalMax Signal

Max Signal

Max SignalMax Signal Channel 1Channel 1

Channel 1

Channel 1Channel 1

0.5V Gain = 1 ——

0.25V Gain = 2 Gain = 1 —

0.125V Gain = 4 Gain = 2 Gain = 1

ADC Input Range SelectionADC Input Range Selection

ADC Input Range Selection

ADC Input Range SelectionADC Input Range Selection

0.5V0.5V

0.5V

0.5V0.5V

0.25V0.25V

0.25V

0.25V0.25V

0.125V0.125V

0.125V

0.125V0.125V

0.0625V Gain = 8 Gain = 4 Gain = 2

0.0313V Gain = 16 Gain = 8 Gain = 4

0.0156V — Gain = 16 Gain = 8

0.00781V ——Gain = 16

REV. PrC 01/02

Figure 3— Effect of channel offsets on the real power cal-

culation

The contents of the Offset Correction registers are 6-Bit, sign and magnitude coded. The weighting of the LSB size depends on the gain setting, i.e., 1, 2, 4, 8 or 16. Table II below shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the Offset Correction registers. The maximum value which can be written to the offset correction registers is ±31 decimal —see Figure 4. Figure 4 shows the relationship between the Offset Correction register contents and the offset (mV) on the analog inputs for a gain setting of one. In order to perform an offset adjustment, The analog inputs should be first connected to AGND, and there should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the

–9–

ADE7753

PRELIMINARY TECHNICAL DA TA

Table IITable II

Table II

Table IITable II

Offset Correction range

GainGain

Gain

GainGain

Correctable SpanCorrectable Span

Correctable Span

Correctable SpanCorrectable Span

LSB SizeLSB Size

LSB Size

LSB SizeLSB Size

1 ±50mV 1.61mV/LSB 2 ±37mV 1.19mV/LSB 4 ±30mV 0.97mV/LSB 8 ±26mV 0.84mV/LSB 16 ±24mV 0.77mV/LSB

Waveform register will give an indication of the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the relevant offset register. The offset correction can be confirmed by performing another read. Note when adjusting the offset of Channel 1, one should disable the digital integrator and the HPF.

CH1OS[5:0]

Sign + 5 Bits

01, 1111b

1Fh

00h

3Fh

0mV

11, 1111b

+50mV

Offset Adjust

Sign + 5 Bits

-50mV

Figure 4– Channel Offset Correction Range (Gain = 1)

di/dtdi/dt

CURRENT SENSOR AND DIGITAL INTEGRATOR CURRENT SENSOR AND DIGITAL INTEGRATOR

di/dt

CURRENT SENSOR AND DIGITAL INTEGRATOR

di/dtdi/dt

CURRENT SENSOR AND DIGITAL INTEGRATOR CURRENT SENSOR AND DIGITAL INTEGRATOR

di/dt sensor detects changes in magetic field caused by ac current. Figure 5 shows the principle of a di/dt current sensor.

The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7753 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched on by default when the ADE7753 is powered up. Setting the MSB of CH1OS register will turn on the integrator. Figures 6 to 9 show the magnitude and phase response of the digital integrator.

-10

GAIN-dB

-20

-30

-40

-50

-60

FREQUENCY-Hz

Figure 6– Combined gain response of the digital integrator

and phase compensator

-88

-88.5

-89

-89.5

-90

PHASE-DEGREES

-90.5

-91

-91.5

-92

FREQUENCY-Hz

Magnetic field created by current (directly proportional to current)

EMF (electromotive force) induced by changes in

magnetic flux density (d/dt)

Figure 5– Principle of a di/dt current sensor

The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generates an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal which is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current carrying conductor and the di/dt sensor.

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Figure 7– Combined phase response of the digital integra-

tor and phase compensator

-1

-2

-3

GAIN-dB

-4

-5

-6 40 45 50 55 60 65 70

FREQUENCY-Hz

Figure 8– Combined gain response of the digital integrator

and phase compensator (40Hz to 70Hz)

REV. PrC 01/02

PRELIMINARY TECHNICAL DA TA

-89.985

-89.99

-89.995

-90

PHASE-DEGREES

-90.005

-90.01

-90.015

-90.02 40 45 50 55 60 65 70

Figure 9– Combined phase response of the digital integra-

tor and phase compensator (40Hz to 70Hz)

Note that the integrator has a -20dB/dec attenuation and approximately -90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. However, the di/dt sensor has a 20dB/dec gain associated with it, and generates significant high frequency noise, a more effective anti-aliasing filter is needed to avoid noise due to aliasing— see Antialias Filter.

When the digital integrator is switched off, the ADE7753 can be used directly with a conventional current sensor such as current transformer (CT) or a low resistance current shunt.

ZERO CROSSING DETECTIONZERO CROSSING DETECTION

ZERO CROSSING DETECTION

ZERO CROSSING DETECTIONZERO CROSSING DETECTION

The ADE7753 has a zero crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero cross signal (ZX) and it is also used in the calibration mode - see Energy Calibration. The zero crossing signal is also used to initiate a temperature measurement on the ADE7753

- see Temperature Measurement. Figure 10 shows how the zero cross signal is generated from the output of LPF1.

FREQUENCY-Hz

ADE7753

The phase response of this filter is shown in the Channel 2 Sampling section of this data sheet. The phase lag response of

LPF1 results in a time delay of approximately 0.97ms (@ 60Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX. The zero-crossing detection also drives one flag bit in the interrupt status register. An active low in the IRQ output will also appear if the corresponding bit in the Interrupt Enable register is set to logic one. The flag in the Interrupt status register as well as the IRQ output are reset to their default value when the Interrupt Status register with reset (RSTSTATUS) is read.

Zero crossing Time outZero crossing Time out

Zero crossing Time out

Zero crossing Time outZero crossing Time out

The zero crossing detection also has an associated time-out register ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) every 128/CLKIN seconds. The register is reset to its user programmed full scale value every time a zero crossing on Channel 2 is detected. The default power on value in this register is FFFh. If the register decrements to zero before a zero crossing is detected and the DISSAG bit in the Mode register is logic zero, the 5)/ pin will go active low. The absence of a zero crossing is also indicated on the 143 pin if the SAG enable bit in the Interrupt Enable register is set to logic one. Irrespective of the enable bit setting, the SAG flag in the Interrupt Status register is always set when the ZXTOUT register is decremented to zero - see ADE7753 Interrupts.

The Zerocross Time-out register can be written/read by the user and has an address of 1Dh - see Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB. Thus the maximum delay for an interrupt is 0.15 second (128/CLKIN × 2

Figure 11 shows the mechanism of the zero crossing time out detection when the line voltage stays at a fixed DC level for more than CLKIN/128 x ZXTOUT seconds.

16-bit internal register value

ZXTOUT

LPF1

REFERENCE

ADC 2

LPF1

= 140Hz

-3dB

MULTIPLIER

-63% to + 63% FS

ZERO

CROSS

0.92

x1, x2, x4, x8, x16

V2P

GAIN[7:5]

PGA2

V2N

1.0

23.2 ⬚ @ 60Hz

Figure 10– Zero cross detection on Channel 2

The ZX signal will go logic high on a positive going zero crossing and logic low on a negative going zero crossing on Channel 2. The zero crossing signal ZX is generated from the output of LPF1. LPF1 has a single pole at 156Hz (at CLKIN = 3.579545MHz). As a result there will be a phase lag between the analog input signal V2 and the output of LPF1.

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–11–

Channel 2

ZXTO detection bit

Figure 11 - Zero crossing Time out detection

PERIOD MEASUREMENTPERIOD MEASUREMENT

PERIOD MEASUREMENT

PERIOD MEASUREMENTPERIOD MEASUREMENT

The ADE7753 provides also the period measurement of the line. The period register is an unsigned 15-bit register and is updated every period of the selected phase.

The resolution of this register is 2.2ms/LSB when CLKIN=3.579545MHz, which represents 0.013% when the line frequency is 60Hz. When the line frequency is 60Hz, the value of the Period register is approximately 7576d. The length of the register enables the measurement of line frequencies as low as 13.9Hz.

PRELIMINARY TECHNICAL DA TA

ADE7753

POWER SUPPLY MONITORPOWER SUPPLY MONITOR

POWER SUPPLY MONITOR

POWER SUPPLY MONITORPOWER SUPPLY MONITOR

The ADE7753 also contains an on-chip power supply monitor. The Analog Supply (AV by the ADE7753. If the supply is less than 4V ± 5% then the ADE7753 will go into an inactive state, i.e. no energy will be accumulated when the supply voltage is below 4V. This is useful to ensure correct device operation at power up and during power down. The power supply monitor has built-in hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies.

5V 4V

ADE7753

Power-on

Reset

SAG

Inactive

) is continuously monitored

Time

Active

Inactive

half cycle for which the line voltage falls below the threshold, if the DISSAG bit in the Mode register is logic zero. As is the case when zero-crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the Interrupt Status register. If the SAG enable bit is set to logic one, the

IRQ logic output will go active low - see ADE7753 Interrupts.

SAG pin will go logic high again when the absolute value

The of the signal on Channel 2 exceeds the sag level set in the Sag Level register. This is shown in Figure 13 when the

SAG pin goes high during the tenth half cycle from the time when the signal on Channel 2 first dropped below the threshold level.

Sag Level SetSag Level Set

Sag Level Set

Sag Level SetSag Level Set

The contents of the Sag Level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1, after it is shifted left by one bit. Thus for example the nominal maximum code from LPF1 with a full scale signal on Channel 2 is 1C396h or (0001, 1100, 0011, 1001, 0110b)—see Channel 2 sampling. Shifting one bit left will give 0011,1000,0111,0010,1100b or 3872Ch. Therefore writing 38h to the Sag Level register will put the sag detection level at full scale. Writing 00h will put the sag detection level at zero. The Sag Level register is compared to the most significant byte of a waveform sample after the shift left and detection is made when the contents of the sag level register are greater.

Figure 12 - On-Chip power supply monitor

As can be seen from Figure 12 the trigger level is nominally set at 4V. The tolerance on this trigger level is about ±5%. The

SAG pin can also be used as a power supply monitor

input to the MCU. The

SAG pin will go logic low when the ADE7753 is reset. The power supply and decoupling for the part should be such that the ripple at AV

does not exceed

5V±5% as specified for normal operation.

LINE VOLTAGE SAG DETECTIONLINE VOLTAGE SAG DETECTION

LINE VOLTAGE SAG DETECTION

LINE VOLTAGE SAG DETECTIONLINE VOLTAGE SAG DETECTION

In addition to the detection of the loss of the line voltage signal (zero crossing), the ADE7753 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value, for a number of half cycles. This condition is illustrated in Figure 13 below.

Full Scale

SAGLVL[7:0]

SAG

Channel 2

SAGCYC[7:0] = 06H

6 half cycles

SAG reset high when Channel 2 exceeds SAGLVL[7:0]

Figure 13– ADE7753 Sag detection

Figure 13 shows the line voltage fall below a threshold which is set in the Sag Level register (SAGLVL[7:0]) for nine half cycles. Since the Sag Cycle register (SAGCYC[7:0]) contains 06h the

SAG pin will go active low at the end of the sixth

–12–

PEAK DETECTIONPEAK DETECTION

PEAK DETECTION

PEAK DETECTIONPEAK DETECTION

The ADE7753 can also be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value. Figure 14 illustrates the behavior of the peak detection for the voltage channel.

VPKLVL[7:0]

PKV reset low when RSTSTATUS register is read

PKV Interrupt Flag

(Bit C of STATUS register)

Read RSTSTATUS register

Figure 14 - ADE7753 Peak detection

Both channel 1 and channel 2 can be monitored at the same time. Figure 14 shows a line voltage exceeding a threshold which is set in the Voltage peak register (VPKLVL[7:0]). The Voltage Peak event is recorded by setting the PKV flag in the Interrupt Status register. If the PKV enable bit is set to logic one in the Interrupt Mask register, the

IRQ logic output

will go active low - see ADE7753 Interrupts.

Peak Level SetPeak Level Set

Peak Level Set

Peak Level SetPeak Level Set

The contents of the VPKLVL and IPKLVL registers are respectively compared to the absolute value of channel 1 and channel 2, after they are multiplied by 2. Thus, for example, the nominal maximum code from the channel 1 ADC with a full scale signal is 1C396h —see Channel 1 Sampling. Multiplying by 2 will give 3872Ch.

REV. PrC 01/02

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