Datasheet ADE7752A Datasheet (ANALOG DEVICES)

Polyphase Energy Metering IC

www.BDTIC.com/ADI

FEATURES

High accuracy, supports 50 Hz/60 Hz IEC62053-2x
Less than 0.1% error over a dynamic range of 500 to 1
Compatible with 3-phase/3-wire delta and 3-phase/4-wire

Wye configurations

The ADE7752

outputs F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous real power

Logic output REVP indicates a potential miswiring or

nega

Direct drive for electromechanical counters and 2-phase

epper motors (F1 and F2)

st

Proprietary ADCs and DSP provide high accuracy over large

ariations in environmental conditions and time

v
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.4 V ±8% (20 ppm/°C typical) with

external overdrive capability
Single 5 V supply, low power

60 mW t

30 mW typical: ADE7752A
Low cost CMOS process

GENERAL DESCRIPTION

The ADE7752 is a high accuracy polyphase electrical energy
measurement IC. The ADE7752A is a pin-to-pin compatible
low power version of ADE7752. The functions of ADE7752 and

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.

1

supplies average real power on frequency

tive power for each phase

ypical: ADE7752

5

IAP
IAN

6

16

VAP

IBP

7
8

IBN

15

VBP

9

ICP

10

ICN

VCP

14
13

VN

Ω

2.4V REF

4k

11 12 4 18 21 22 23 24 1

AGND

FUNCTIONAL BLOCK DIAGRAM

ADC

ADC

ADC

ADC

ADC

ADC

REF

IN/OUT

Figure 1. 24-Lead Standard Small Outline Package [SOIC]

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

with Pulse Output

ADE7752/ADE7752A

ADE7752A are the same. Both products are referred to in the
text of this data sheet as ADE7752.

The part specifications surpass the accuracy requirements as

uoted in the IEC62053-2x standard. The only analog circuitry

q
used in the ADE7752 is in the analog-to-digital converters (ADCs)
and reference circuit. All other signal processing (such as multi­plication, filtering, and summation) is carried out in the digital
domain. This approach provides superior stability and accuracy
over extremes in environmental conditions and over time.

The ADE7752 supplies average real power information on the
lo

w frequency outputs, F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or to
interface with an MCU. The CF logic output gives instanta­neous real power information. This output is intended to be
used for calibration purposes.

The ADE7752 includes a power supply monitoring circuit on

pin. The ADE7752 remains inactive until the supply

the V

DD

voltage on V
pulses are issued on F1, F2, and CF. Internal phase matching
circuitry ensures that the voltage and current channels are
phase matched. An internal no load threshold ensures the part
does not exhibit any creep when there is no load. The ADE7752
is available in a 24-lead SOIC package.

1

Patent pending.

LPF

LPF

LPF

DIGITAL-TO-FREQUENCY CONVERTER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

reaches 4 V. If the supply falls below 4 V, no

DD

POWER
SUPPLY

MONITOR

ADE7752/
ADE7752A

Σ

V

DD

3

2

DGND

19

CLKIN

CLKOUT

20

CFS1 F1F2S0SCFREVP

02676-A-001

ABS

17

X

X

X

ADE7752/ADE7752A

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Voltage Channels Connection .................................................. 15

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Test C irc uit ...................................................................................... 10

Te r mi n ol o g y .................................................................................... 11

Theory of Operation ...................................................................... 12

Power Factor Considerations.................................................... 12

Nonsinusoidal Voltage and Current ........................................ 13

Analog Inputs.................................................................................. 14

Current Channels ....................................................................... 14

Voltage Channels ........................................................................14

Typical Con ne c tion Diagrams ...................................................... 15

Current Channel Connection ...................................................15

Meter Connections..................................................................... 15

Power Supply Monitor ................................................................... 17

HPF and Offset Effects .............................................................. 17

Digital-to-Frequency Conversion ................................................ 18

Mode Selection of the Sum of the Three Active Energies..... 19

Power Measurement Considerations....................................... 19

Transfer F u n c tion ........................................................................... 20

Frequency Outputs F1 and F2 .................................................. 20

Frequency Output CF ................................................................ 21

Selecting a Frequency for an Energy Meter Application........... 22

Frequency Outputs..................................................................... 22

No Load Threshold .................................................................... 22

Negative Power Information..................................................... 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

7/05—Rev. B to Rev. C

Added ADE7752A.............................................................. Universal

Changed NEGP Pin Name to REVP................................ Universal

Changes to Table 1.............................................................................3

Changes to Table 6, Table 7 ............................................................21

Changes to Table 8, Table 9, Table 10............................................22

Updated Outline Dimensions........................................................24

Changes to Ordering Guide...........................................................24

9/03—Rev. A to Rev. B

U

pdated Format.................................................................. Universal

Change to Figure 19 ........................................................................15

5/03—Rev. 0 to Rev. A

to F

anged F

Ch

Change to Figure 6 .......................................................................... 10

Changes to Frequency Outputs F1 and F2 section .....................13

Replaced Table II .............................................................................13

Changes to Examples 1, 2, and 3 ...................................................14

Replaced Table III............................................................................14

Replaced Tables IV, V, and VI ........................................................15

Changes to SELECTING A FREQUENCY FOR AN ENERGY

METER APPLICATION section...................................................15

Changes to NO LOAD THRESHOLD section............................16

Replaced Table VII ..........................................................................16

1–5

............................................................ Universal

1–7

Rev. C | Page 2 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

SPECIFICATIONS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, T

Table 1.

ADE7752 ADE7752A

Parameter

ACCURACY

1, 2

Measurement Error on Current

Min Typ Max Min Typ Max

0.1 0.1 % Reading

Channel

Phase Error Between Channels

PF = 0.8 Capacitive ±0.1 ±0.1 Degrees
PF = 0.5 Inductive ±0.1 ±0.1 Degrees

AC Power Supply Rejection SCF = 0; S0 = S1 = 1

Output Frequency Variation

0.01 0.01 % Reading

(CF)

DC Power Supply Rejection S1 = 1; S0 = SCF = 0

Output Frequency Variation

0.1 0.1 % Reading

(CF)

ANALOG INPUTS See the Analog Inputs section.

Maximum Signal Levels ±0.5 ±0.5

Input Impedance (DC) 370 410 370 450 kΩ CLKIN = 10 MHz
Bandwidth (–3 dB) 14 14 kHz CLKIN/256, CLKIN = 10 MHz
ADC Offset Error

1, 2

±25 ±25 mV

Gain Error ±9 ±9 % Ideal

REFERENCE INPUT

REF

Input Voltage Range 2.6 2.6 V 2.4 V + 8%

IN/OUT

2.2 2.2 V 2.4 V – 8%
Input Impedance 3.3 3.3 kΩ
Input Capacitance 10 10 pF

ON-CHIP REFERENCE Nominal 2.4 V

Reference Error ±200 ±200 mV
Temperature Coefficient 25 25 ppm/°C

CLKIN All specifications for CLKIN of 10 MHz

Input Clock Frequency 10 10 MHz

LOGIC INPUTS

3

ACF, S0, S1, and ABS

Input High Voltage, V
Input Low Voltage, V
Input Current, I
Input Capacitance, C

LOGIC OUTPUTS

INH

INL

IN

IN

3

2.4 2.4 V VDD = 5 V ±5%

0.8 0.8 V VDD = 5 V ±5%
±3 ±3 A Typically 10 nA, VIN = 0 V to V
10 10 pF

F1 and F2

Output High Voltage, V
Output Low Voltage, V

OH

OL

4.5 4.5 V I

0.5 0.5 V I

CF and REVP

Output High Voltage, V
Output Low Voltage, V

OH

OL

4 4 V VDD = 5 V, I

0.5 0.5 V VDD = 5 V, I

POWER SUPPLY For specified performance

V

DD

I

DD

1

See the Terminology section for explanation of specifications.

2

See the plots in the Typical Performance Characteristics section.

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

4.75 5.25 4.75 5.25 V 5 V ±5%
12 16 6 9 mA

MIN

to T

= –40°C to +85°C, unless otherwise noted.

MAX

Unit Conditions

Voltage channel with full-scale signal
(±500 mV), 25

°C, over a dynamic range

of 500 to 1

IA = IB = IC = 100 mV rms,
VA = VB = VC =
ripple on V

100 mV rms, @ 50 Hz,

of 175 mV rms @ 100 Hz

DD

IA = IB = IC = 100 mV rms,

100 mV rms,

CN

Vpeak
differential

VA = VB = VC =
V

= 5 V ±250 mV

DD

V

to VN, VBP to VN, VCP to VN, IAP to IAN,

AP

I

to IBN, ICP to I

BP

External 2.5 V reference,
IA = IB = IC = 50

= 10 mA, V

SOURCE

= 10 mA, VDD = 5 V

SINK

SOURCE

= 5 mA

SINK

0 mV dc

= 5 V

DD

= 5 mA

DD

Rev. C | Page 3 of 24

ADE7752/ADE7752A

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TIMING CHARACTERISTICS

VDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 10 MHz, T

to T = –40°C to +85°C, unless otherwise noted .

MAX

MIN

Table 2.

Parameter Conditions Spec Unit

3

t F1 and F2 Pulse Width (Logic High). 275 ms

1

t Output Pulse Period. See the Transfer Function section. See Table 6. sec

2

t Time between F1 Falling Edge and F2 Falling Edge. 1/2 t

3 2

3, 4

t CF Pulse Width (Logic High). 96

4

5

t CF Pulse Period. See the Transfer Function and the Frequency Outputs sections. See Table 7. sec

5

t Minimum Time Between the F1 and F2 Pulse. CLKIN/4 sec

6

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See Figure 2.

3

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.

4

CF is not synchronous to F1 or F2 frequency outputs.

5

The CF pulse is always 1 µs in the high frequency mode.

t

1

1, 2

sec
ms

F1

F2

t

4

CF

t

6

t

2

t

3

t

5

02676-A-002

Figure 2. Timing Diagram for Frequency Outputs

Rev. C | Page 4 of 24

ADE7752/ADE7752A

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ABSOLUTE MAXIMUM RATINGS

T = 25°C, unless otherwise noted.

A

Table 3.

Parameter Rating

V to AGND −0.3 V to +7 V

DD

V to DGND −0.3 V to +7 V

DD

Analog Input Voltage to AGND

VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN,

ICP, and ICN −6 V to +6 V
Reference Input Voltage to AGND −0.3 V to V + 0.3 V
Digital Input Voltage to DGND −0.3 V to V + 0.3 V
Digital Output Voltage to DGND −0.3 V to V + 0.3 V
Operating Temperature Range

Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
24-Lead SOIC, Power Dissipation 88 mW
θJA Thermal Impedance 250°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−40°C to +85°C Industrial

DD

DD

DD

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 5 of 24

ADE7752/ADE7752A

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

24
23
22
21
20
19
18
17
16
15
14
13

F1
F2
S1
S0
CLKOUT
CLKIN
SCF
ABS
VAP
VBP
VCP
VN

02676-A-003

REF

CF

DGND

V

REVP

IAP
IAN
IBP
IBN
ICP
ICN

AGND

IN/OUT

DD

10
11
12

1
2
3
4

ADE7752/

5

ADE7752A

6

TOP VIEW

(Not to Scale)

7
8
9

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CF Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information.

This output is intended to be used for calibration purposes. See the SCF pin description.

2 DGND This provides the ground reference for the digital circuitry in the ADE7752: the multiplier, filters, and

digital-to-frequency converter. Because the digital return currents in the ADE7752 are small, it is
acceptable to connect this pin to the analog ground plane of the whole system.

3 V

DD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply
voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to
DGND with a 10 µF capacitor in parallel with a 100 nF ceramic capacitor.

4 REVP

This logic output goes logic high when negative power is detected on any of the three phase inputs,
that is, when the phase angle between the voltage and the current signals is greater than 90°. This
output is not latched and is reset when positive power is once again detected. See the Negative Power
Information section.

5, 6;
7, 8;
9, 10

IAP, IAN;
IBP, IBN;
ICP, ICN

Analog Inputs for Current Channel. This channel is intended for use with the current transducer and is
referenced in this document as the current channel. These inputs are fully differential voltage inputs
with maximum differential input signal levels of ±0.5 V. See the Analog Inputs section. Both inputs have
internal ESD protection circuitry. In addition, an overvoltage of ±6 V can be sustained on these inputs
without risk of permanent damage.

11 AGND

This pin provides the ground reference for the analog circuitry in the ADE7752: the ADCs, temperature
sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground
reference in the system. This quiet ground reference should be used for all analog circuitry, such as
antialiasing filters, current and voltage transducers, and so on. To keep ground noise around the
ADE7752 to a minimum, the quiet ground plane should connect to the digital ground plane at only
one point. It is acceptable to place the entire device on the analog ground plane.

12 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

2.4 V ± 8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor.

13–16 VN, VCP, VBP,

VAP

Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer and
is referenced in this document as the voltage channel. These inputs are single-ended voltage inputs with
a maximum signal level of ±0.5 V with respect to VN for specified operation. All inputs have internal ESD
protection circuitry. In addition, an overvoltage of ± 6 V can be sustained on these inputs without risk of
permanent damage.

17

ABS

This logic input is used to select the way the three active energies from the three phases are summed.
This offers the designer the capability to do the arithmetical sum of the three energies (ABS

or the sum of the absolute values (ABS

logic low). See the Mode Selection of the Sum of the Three Active

logic high)

Energies section.

18 SCF Select Calibration Frequency. This logic input is used to select the freq

uency on the calibration output

CF. Table 7 shows how the calibration frequencies are selected.

Rev. C | Page 6 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

Pin No. Mnemonic Description

19 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.

Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a
clock source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load
capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal
manufacturer’s data sheet for load capacitance requirements.

20 CLKOUT A crystal can be connected across this pin and CLKIN as described previously to provide a clock source

for the ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN
or when a crystal is being used.

21, 22 S0, S1 These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conver-

sion. This offers the designer greater flexibility when designing the energy meter. See the Selecting a
Frequency for an Energy Meter

24, 23 F1, F2 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can

be used to drive electromechanical counters and two-phase stepper motors directly. See the Transfer
Function section.

Application section.

Rev. C | Page 7 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

0.5

WYE CONNECTION
ON-CHIP REFERENCE

0.4

0.3

0.2

0.1

PHASE B

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

1.0

WYE CONNECTION
ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1

Figure 5. Error as a Percent of Reading over Power Factor

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

Figure 6. Error as a Percent of Reading over Power Factor

PHASE C

S

A

E

P

A

H

CURRENT CHANNEL (% of Full Scale)

PHASE A + B + C

Figure 4. Error as a Percent of Reading

with Internal Reference (Wye Connection)

+85°C PF = +0.5

+25°C PF = –0.5

–40°C PF = +0.5

with Inte

+25°C PF = +1

CURRENT CHANNEL (% of Full Scale)

rnal Reference (Wye Connection)

+85°C PF = +0.5

+25°C PF = +1

–40°C PF = +0.5

+25°C PF = –0.5

CURRENT CHANNEL (% of Full Scale)

with Extern

al Reference (Wye Connection)

02676-A-004

10010

02676-A-005

10010

02676-A-006

10010

1.0

WYE CONNECTION
ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1

+85°C PF = 1

–40°C PF = 1

CURRENT CHANNEL (% of Full Scale)

+25°C PF = 1

Figure 7. Error as a Percent of Reading over Temperature

rnal Reference (Wye Connection)

with Inte

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

DELTA CONNECTION
ON-CHIP REFERENCE

PF = –0.5

PF = +1

PF = +0.5

CURRENT CHANNEL (% of Full Scale)

Figure 8. Error as a Percent of Reading over Power Factor

th Internal Reference (Delta Connection)

wi

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

+85°C PF = 1

+25°C PF = 1

–40°C PF = 1

CURRENT CHANNEL (% of Full Scale)

Figure 9. Error as a Percent of Reading over Temperature

with Extern

al Reference (Wye Connection)

02676-A-007

10010

02676-A-008

10010

02676-A-009

10010

Rev. C | Page 8 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0

45

WYE CONNECTION
ON-CHIP REFERENCE

PF = 1

PF = 0.5

FREQUENCY (Hz)

60 655550

Figure 10. Error as a Percent of Reading over Frequency

an Internal Reference (Wye Connection)

with

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

4.75V

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

5V

5.25V

CURRENT CHANNEL (% of Full Scale)

Figure 11. Error as a Percent of Reading over Power Supply

with Extern

al Reference (Wye Connection)

02676-A-010

02676-A-011

10010

N: 88

18

MEAN: 4.48045
SD: 3.23101
MIN: –2.47468 MAX: 12.9385
RANGE: 15.4132

15

12

9

6

3

0

–20 –10–15

CH_I PhA OFFSET (mV)

Figure 12. Channel 1 Offset Distribution

0.5

WYE CONNECTION
ON-CHIP REFERENCE

0.4

0.3

0.2

0.1

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

4.75V

5V

0

5.25V

0.1 1
CURRENT CHANNEL (% of Full Scale)

Figure 13. Error as a Percent of Reading over Power Supply

rnal Reference (Wye Connection)

with Inte

02676-A-012

2015105–5 0

02676-A-013

10010

Rev. C | Page 9 of 24

ADE7752/ADE7752A

2

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TEST CIRCUIT

V

DD

1kΩ

33nF

1kΩ

33nF

100nF

V

DD

5

IAP

ADE7752/
ADE7752A

6

IAN

7

IBP

8

IBN
ICP

9

10

ICN

16

VAP

15

VBP
VCP

14

VN AGND DGND

13 11

1kΩ

33nF

3

17

ABS

CLKOUT

CLKIN

REF

IN/OUT

REVP

F1
F2

CF

S0
S1

SCF

2

24

23

825Ω

1

20

10MHz

19

21
22
18

12

100nF 10μF

4

NOT
CONNECTED

22pF

22pF

1kΩ

PS2501-1

V

DD

K7

TO FREQ.
COUNTER

K8

02676-A-014

20V

1MΩ

1kΩ

I

LOAD

33nF

10μF

RB

SAME AS
IAP, IAN

SAME AS
IAP, IAN

SAME AS VAP
SAME AS VAP

Figure 14. Test Circuit for Performance Curves

Rev. C | Page 10 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7752 is defined by the following formula:

⎧

=

ErrorPercentage 100

⎨
⎩

Error Between Channels
The hi

gh-pass filter (HPF) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
also placed in the current channel. The phase correction net­work ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range of 40 Hz to 1 kHz. See
Figure 26.

Power Supply Rejection (PSR)

quantifies the ADE7752 measurement error as a

This
percentage of reading when the power supplies are varied.

7752

EnergyTrue

Figure 24 and

⎫

EnergyTrue–ADE by Registered Energy

%

×

⎬
⎭

ADC Offset Error

This r

efers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see an analog input signal offset.
However, because the HPF is always present, the offset is
removed from the current channel, and the power calculation is
not affected by this offset.

Gain Error
The ga

in error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function. See the

nction

Fu

section.

Tr an sf er

For the ac PSR measurement, a reading at a nominal supply
(5 V) is tak
onto the supply and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading. See definition for Measurement Error.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is t
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

en. A 200 mV rms/100 Hz signal is then introduced

aken. The supply is then varied ±5% and a second

Rev. C | Page 11 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

THEORY OF OPERATION

The six voltage signals from the current and voltage transducers
are digitized with ADCs. These ADCs are 16-bit second-order
∑-Δ with an oversampling rate of 833 kHz. This analog input
structure greatly simplifies transducer interface by providing a
wide dynamic range for direct connection to the transducer and
also by simplifying the antialiasing filter design. A high-pass
filter in the current channel removes the dc component from
the current signal. This eliminates any inaccuracies in the real
power calculation due to offsets in the voltage or current
signals. See the

The real power calculation is derived from the instantaneous
p

ower signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals of each
phase. In order to extract the real power component (the dc
component), the instantaneous power signal is low-pass filtered
on each phase.
p

ower signal and shows how the real power information can be
extracted by low-pass filtering the instantaneous power signal.
This method is used to extract the real power information on
each phase of the polyphase system. The total real power
information is then obtained by adding the individual phase
real power. This scheme correctly calculates real power for
nonsinusoidal current and voltage waveforms at all power
factors. All signal processing is carried out in the digital domain
for superior stability over temperature and time.

HPF and Offset Effects section.

Figure 15 illustrates the instantaneous real

The low frequency output of the ADE7752 is generated by
acc

umulating the total real power information. This low
frequency inherently means a long accumulation time between
output pulses. The output frequency is therefore proportional to
the average real power. This average real power information
can, in turn, be accumulated (by a counter, for example) to
generate real energy information. Because of its high output
frequency and therefore shorter integration time, the CF output
is proportional to the instantaneous real power. This pulse is
useful for system calibration purposes that would take place
under steady load conditions.

POWER FACTOR CONSIDERATIONS

Low-pass filtering, the method used to extract the real power
information from the individual instantaneous power signal, is
still valid when the voltage and current signals of each phase are
not in phase.
co

ndition and a DPF (displacement power factor) = 0.5, or
current signal lagging the voltage by 60°, for one phase of the
polyphase. Assuming that the voltage and current waveforms
are sinusoidal, the real power component of the instantaneous
power signal, or the dc term, is given by

⎛
⎜
⎝

Figure 16 displays the unity power factor

×

1V

⎞

()

60cos

°×

⎟

2

⎠

p(t) = i(t) × v(t)

V × I

V × I

2

TIME

IAP

IAN

VAP

IBP

IBN

VBP

ICP

ICN

VCP

VN

WHERE:

v(t) =V × cos (ωt)
i(t) = I × cos (ωt)
p(t) =

V × I

{1+ cos (2ωt)}

2

INSTANTANEOUS

POWER SIGNAL - p(t)

HPF

ADC

MULTIPLIER

ADC

HPF

ADC

MULTIPLIER

ADC

HPF

ADC

MULTIPLIER

ADC

V × I

2

INSTANTANEOUS

REAL POWER SIGNAL

ABS

LPF

|X|

LPF

|X|

LPF

|X|

Figure 15. Signal Processing Block Diagram

VA × IA + VB × IB +

Σ

VC×IC

2

INSTANTANEOUS

TOTAL

POWER SIGNAL

DIGITAL-TO-

FREQUENCY

Σ

DIGITAL-TO-

FREQUENCY

Σ

F1
F2

CF

02676-A-015

Rev. C | Page 12 of 24

ADE7752/ADE7752A

IVP

×

=

www.BDTIC.com/ADI

This is the correct real power calculation.

INSTANTANEOUS
POWER SIGNAL

V× I

2

0V

CURRENT

VOLTAGE

INSTANTANEOUS
POWER SIGNAL

V× I

× cos(60°)

2

0V

VO LTA GE

Figure 16. DC Component of Instantaneous Power Signal

Conveys Real

60°

Power Information PF < 1

INSTANTANEOUS
REAL POWER SIGNAL

INSTANTANEOUS REAL
POWER SIGNAL

CURRENT

NONSINUSOIDAL VOLTAGE AND CURRENT

The real power calculation method also holds true for nonsin­usoidal current and voltage waveforms. All voltage and current
waveforms in practical applications have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content:

where:

()

∞

∑

n

0

=

sin2

no

(

(1)

)

αtωnVVtv +××+=

n

()

O

where:

s the instantaneous current.

i(t) i
I

is the dc component.

O

is the rms value of current harmonic n.

I

n

β is the phase angle of the current harmonic.

n

Using Equations 1 and 2, the real power, P, can be expressed in
terms of its fundamental real power (P
power (P

).

H

+ PP = P

1 H

where:

02676-A-016

−=

∞

∑

H

1

=

−=

As can be seen from Equation 4, a harmonic real power compo­nent is generated for every harmonic, provided that harmonic is
present in both the voltage and current waveforms. The power
factor calculation has been shown to be accurate in the case of a
pure sinusoid. Therefore, the harmonic real power must also
correctly account for power factor since it is made up of a series
of pure sinusoids.

Note that the input bandwidth of the analog inputs is 14 kHz

th a master clock frequency of 10 MHz.

wi

∞

∑

n

0

=

cos

φ

1111

(3)

βαφ

111

φIVP

×=

cos

nnnn

βαnφ

nn

(

)

(2)

××+=

n

βtωnIVIti sin2

n

) and harmonic real

1

(4)

he instantaneous voltage.

v(t) is t
V

is the average value.

O

is the rms value of voltage harmonic n.

V

n

α

is the phase angle of the voltage harmonic.

n

Rev. C | Page 13 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

ANALOG INPUTS

CURRENT CHANNELS VOLTAGE CHANNELS

The voltage outputs from the current transducers are connected
to the ADE7752 current channels, which are fully differential
voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN,
IBN, and ICN, respectively.

The output of the line voltage transducer is connected to the
ADE7752 at this analog input. Voltage channels are a pseudo­differential voltage input. VAP, VBP, and VCP are the positive
inputs with respect to VN.

The maximum peak differential signal on the current channel
s

hould be less than ±500 mV (353 mV rms for a pure sinusoidal

signal) for the specified operation.

Figure 17 illustrates the maximum signal levels on IAP and
I

AN. The maximum differential voltage between IAP and IAN
is ±500 mV. The differential voltage signal on the inputs must
be referenced to a common mode, such as AGND. The maxi­mum common-mode signal shown in

IAP–IAN

+500mV

DIFFERENTIAL INPUT

V

CM

–500mV

Figure 17. Maximum Signal Levels, Current Channel

±500mV MAX PEAK

COMMON-MODE

±25mV MAX

Figure 17 is ±25 mV.

IAP

IA

IAN

V

CM

AGND

The maximum peak differential signal on the voltage channel
is ±500 mV (353 mV rms for a pure sinusoidal signal) for
specified operation.

Figure 18 illustrates the maximum signal levels that can be
connected to the voltage channels of the ADE7752.

Voltage channels must be driven from a common-mode voltage.

n other words, the differential voltage signal on the input must

I
be referenced to a common mode (usually AGND). The analog
inputs of the ADE7752 can be driven with common-mode
voltages of up to 25 mV with respect to AGND. However, best
results are achieved using a common mode equal to AGND.

VAP–VN

+500mV

DIFFERENTIAL INPUT

02676-A-017

V

CM

–500mV

Figure 18. Maximum Signal Levels, Voltage Channel

±500mV MAX PEAK

COMMON-MODE

±25mV MAX

AGND

VA

VCM

VAP

VN

02676-A-018

Rev. C | Page 14 of 24

ADE7752/ADE7752A

(

(

(

)

+

××=

www.BDTIC.com/ADI

TYPICAL CONNECTION DIAGRAMS

CURRENT CHANNEL CONNECTION METER CONNECTIONS

Figure 19 shows a typical connection diagram for the current
channel (IA). A current transformer (CT) is the current trans­ducer selected for this example. Notice the common-mode
voltage for the current channel is AGND and is derived by
center tapping the burden resistor to AGND. This provides the
complementary analog input signals for IAP and IAN. The CT
turns ratio and burden resistor Rb are selected to give a peak
differential voltage of ±500 mV at maximum load.

CT

Rf

R

±500mV

b

IAP

Cf

IAN

In 3-phase service, two main power distribution services exist:
3-phase 4-wire or 3-phase 3-wire. The additional wire in the
3-phase 4-wire arrangement is the neutral wire. The voltage
lines have a phase difference of ±120° (±2π/3 radians) between
each other. See Equation 5.

()

()

()

AA

BB

CC

cos2

××=

cos2

cos2

tωVtV

()

l

⎛
⎜
⎝

π2

tωVtV

+××=

l

3

⎛

tωVtV

+××=

⎜

l

3

⎝

⎞

(5)

⎟
⎠

π4

⎞
⎟
⎠

IP

NEUTRALPHASE

Figure 19. Typical Connection for Current Channels

Rf

Cf

VOLTAGE CHANNELS CONNECTION

Figure 20 shows two typical connections for the voltage
channel. The first option uses a potential transformer (PT) to
provide complete isolation from the main voltage. In the second
option, the ADE7752 is biased around the neutral wire, and a
resistor divider is used to provide a voltage signal proportional
to the line voltage. Adjusting the ratio of Ra, Rb, and VR is also
a convenient way of carrying out a gain calibration on the meter.

PT

±500mV

AGND

NEUTRALPHASE

Ra

NEUTRALPHASE

Figure 20. Typical Connections for Voltage Channels

Cf

*

Rb

*

±500mV

VR

*

Ra >> Rf + VR;*Rb + VR = Rf

*

Rf

Rf

Rf

VAP

Cf

VN

Cf

VAP

VN

Cf

where V

02676-A-019

different phases.

, VB, and V

B represent the voltage rms values of the

A

C

The current inputs are represented by Equation 6.

()

()

()

where I
each phase and ϕ

, IB, and I

B represent the rms value of the current of

A

AA

BB

CC

A

C

, ϕ

cos2

cos2

cos2

B, and ϕ

B

⎧
⎨
⎩

⎧
⎨
⎩

)

+×=

φtωItI

A

l

π2

⎫

(6)

++×=

φtωItI

⎬

l

l

represent the phase difference of

C

B

3

⎭

π4

⎫

φtωItI

++×=

⎬

C

3

⎭

the current and voltage channel of each phase.

The instantaneous powers can then be calculated as follows:

(t) = VA(t) × IA(t)

P

A

P

(t) = V

B(t) × IB

(t)

B

(t) = VC(t) × IC(t)

P

C

B

B

B

Then:

)

()

02676-A-018

()

()

()

()

××−

AAAAAA

⎛
⎜

BBBBBB

⎝

CCCCCC

φtωIVφIVtP

2coscos

2coscos

⎛

2coscos

⎜
⎝

A

l

π4

⎞

φtωIVφIVtP

++××−××=

(7)

⎟

l

l

B

3

⎠

π8

⎞

φtωIVφIVtP

++××−××=

⎟

C

3

⎠

As shown in Equation 7, in the ADE7752, the real power calcu-

tion per phase is made when current and voltage inputs of one

la
phase are connected to the same channel (A, B, or C). Then the
summation of each individual real power calculation gives the
total real power information, P(t) = P

(t) + PB(t) + PC(t).B

A

Rev. C | Page 15 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

Figure 21 shows the connections of the analog inputs of the
ADE7752 with the power lines in a 3-phase 3-wire delta service.
Note that only two current inputs and two voltage inputs of the
ADE7752 are used in this case. The real power calculated by the
ADE7752 does not depend on the selected channels.

Cf

Ra*
Rb*

VR*

PHASE A

SOURCE

PHASE B

Ra*

Rb*
VR*

Rb*

CT

PHASE C

Cf

Ra >> Rf + VR*Rb + VR = Rf

*

CT

Rb*

ANTIALIASING

FILTERS

Rf

ANTIALIASING

FILTERS

Figure 21. 3-Phase 3-Wire Meter Connection with ADE7752

VAP
IAP
IAN

VN

Cf

IBP
IBN

VBP

LOAD

Figure 22 shows the connections of the analog inputs of the
ADE7752 with the power lines in a 3-phase 4-wire Wye service.

Cf

Ra*
Rb*

CT

Rb*

VAP
IAP

IAN

ANTIALIASING

FILTERS

ICP

LOAD

ICN
VCP

IBP
IBN

VBP

02676-A-022

VR*

Rb*

CT

PHASE A
SOURCE

02676-A-021

PHASE B

PHASE C

Cf

Ra*
Rb*

VR*

Rf

VN

CF

*

Figure 22. 3-Phase 4-Wire Meter Connection with ADE7752

ANTIALIASING

FILTERS

Cf

Ra*

Rb*

VR*
CT

ANTIALIASING

FILTERS

Rb*

Ra >> Rf + VR;*Rb + VR = Rf

Rev. C | Page 16 of 24

ADE7752/ADE7752A

V

www.BDTIC.com/ADI

POWER SUPPLY MONITOR

The ADE7752 contains an on-chip power supply monitor. The
power supply (V

) is continuously monitored by the ADE7752.

DD

If the supply is less than 4 V ± 5%, the outputs of the ADE7752
are inactive. This is useful to ensure correct device startup at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.

As can be seen from Figure 23, the trigger level is nominally set
a

t 4 V. The tolerance on this trigger level is about ±5%. The
power supply and decoupling for the part should be such that
the ripple at V

does not exceed 5 V ± 5% as specified for

DD

normal operation.

This problem is easily avoided by the HPF in the current
channels. By removing the offset from at least one channel, no
error component can be generated at dc by the multiplication.
Error terms at cos(ωt) are removed by the LPF and the digital­to-frequency conversion. See the
Co

nversion section.

()

{}

×

IV

{}

2

×

IV

()

+

×

2

tω

2cos

Digital-to-Frequency

()

coscos

ItωIVtωV

OSOS

() ()

=+×+

coscos

×+×+×+

OSOSOSOS

tωVItωIVIV

HPF AND OFFSET EFFECTS

Figure 25 shows the effect of offsets on the real power calcula­tion. As can be seen, an offset on the current channel and
voltage channel contribute a dc component after multiplication.
Since this dc component is extracted by the LPF and is used to
generate the real power information for each phase, the offsets
contribute a constant error to the total real power calculation.

V

DD

5V
4V

0V

TIME

INTERNAL

RESET

INACTIVE

Figure 23. On-Chip Power Supply Monitor

0.07

0.06

0.05

0.04

0.03

0.02

PHASE (Degrees)

0.01

0

–0.01

100 300 500 700 900

0 1000200 400 600 800

Figure 24. Phase Error Between Channels (0 Hz to 1 kHz)

ACTIVE INACTIVE

FREQUENCY (Hz)

02676-A-023

02676-A-025

The HPFs in the current channels have an associated phase
r

esponse that is compensated for on-chip.

Figure 24 and

Figure 26 show the phase error between channels with the

mpensation network. The ADE7752 is phase compensated

co
up to 1 kHz as shown. This ensures correct active harmonic
power calculation even at low power factors.

DC COMPONENT (INCLUDING ERRORTERM)

× I

OS

OS

V × I

2

Figure 25. Effect of Channel Offset on the Real Power Calculation

0.010

0.008

0.006

0.004

0.002

PHASE (Degrees)

0

–0.002

–0.004

40 7045 50

Figure 26. Phase Error Between Channels (40 Hz to 70 Hz)

IS EXTRACTED BYTHE LPF FOR REAL
POWER CALCULATION

IOS× V
V

× I

OS

0

ω

FREQUENCY – RAD/S

FREQUENCY (Hz)

2ω

55 60 65

02676-A-024

02676-A-026

Rev. C | Page 17 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

DIGITAL-TO-FREQUENCY CONVERSION

After multiplication, the digital output of the low-pass filter
contains the real power information of each phase. Because this
LPF is not an ideal brick wall filter implementation, however,
the output signal also contains attenuated components at the
line frequency and its harmonics (cos(hωt), where h = 1, 2, 3,
and so on).

The magnitude response of the filter is given by

()

||

where the −3 dB cutoff frequency of the low-pass filter is 8 Hz.

or a line frequency of 50 Hz, this would give an attenuation of

F
the 2ω(100 Hz) component of approximately –22 dB. The
dominating harmonic is twice the line frequency, cos(2ωt), due
to the instantaneous power signal.
i

nstantaneous real power signal at the output of the CF, which
still contains a significant amount of instantaneous power
information, cos (2ωt).

This signal is then passed to the digital-to-frequency converter

here it is integrated (accumulated) over time to produce an

w
output frequency. This accumulation of the signal suppresses or
averages out any non-dc component in the instantaneous real

1

=ffH

+

1

(8)

2

⎫

⎧

⎬

⎨

8

⎭

⎩

Figure 27 shows the

power signal. The average value of a sinusoidal signal is zero.
T

hus, the frequency generated by the ADE7752 is proportional
to the average real power. Figure 27 shows the digital-to­f

requency conversion for steady load conditions, constant

voltage, and current.

Figure 27As can be seen in

ver time, even under steady load conditions. This frequency

o

, the frequency output CF varies

variation is primarily due to the cos(2ωt) components in the
instantaneous real power signal. The output frequency on CF
can be up to 160 times higher than the frequency on F1 and F2.
The higher output frequency is generated by accumulating the
instantaneous real power signal over a much shorter time, while
converting it to a frequency. This shorter accumulation period
means less averaging of the cos(2ωt) component. As a conse­quence, some of this instantaneous power signal passes through
the digital-to-frequency conversion. This is not a problem in
the application. Where CF is used for calibration purposes, the
frequency should be averaged by the frequency counter. This
removes any ripple. If CF is being used to measure energy, such
as in a microprocessor-based application, the CF output should
also be averaged to calculate power. Because the outputs F1 and
F2 operate at a much lower frequency, much more averaging of
the instantaneous real power signal is carried out. The result is a
greatly attenuated sinusoidal content and a virtually ripple-free
frequency output.

MULTIPLIER

MULTIPLIER

MULTIPLIER

VA

VB

VC

ABS

LPF

|X|

IA

LPF

|X|

IB

LPF

|X|

IC

Figure 27. Real Power-to-Frequency Conversion

Σ

LPF TO EXTRACT

REAL POWER

(DC TERM)

DIGITAL-TO-

FREQUENCY

Σ

DIGITAL-TO-

FREQUENCY

Σ

V× I

2

0

INSTANTANEOUS REAL POWER SIGNAL

F1

F1
F2

FREQUENCY

TIME

CF

CF

FREQUENCY

TIME

cos(2ωt)

ATTENUATED BY LPF

ω

FREQUENCY – RAD/S

(FREQUENCY DOMAIN)

2ω

02676-A-027

Rev. C | Page 18 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES

The ADE7752 can be configured to execute the arithmetic sum
of the three active energies, Wh = Wh
sum of the absolute value of these energies, Wh = |Wh
|Wh

| + |WhϕC|. The selection between the two modes can be

ϕB

made by setting the
on the
of absolute values, respectively.

When the sum of the absolute values is selected, the active

ergy from each phase is always counted positive in the total

en
active energy. It is particularly useful in 3-phase 4-wire installa­tion where the sign of the active power should always be the
same. If the meter is misconnected to the power lines, (for
instance, if CT is connected in the wrong direction), the total
active energy recorded without this solution can be reduced by
two-thirds.

pin correspond to the arithmetic sum and the sum

ABS

pin. Logic high and logic low applied

ABS

+ WhϕB + WhϕC, or the

ϕA

| +

ϕA

The sum of the absolute values assures that the active energy

ecorded represents the actual active energy delivered. In this

r
mode, the reverse power pin still detects when negative power is
present on any of the three phase inputs.

POWER MEASUREMENT CONSIDERATIONS

Calculating and displaying power information always has some
associated ripple that depends on the integration period used in
the MCU to determine average power as well as the load. For
example, at light loads, the output frequency may be 10 Hz.
With an integration period of 2 seconds, only about 20 pulses
are counted. The possibility of missing one pulse always exists
since the ADE7752 output frequency is running asynchro­nously to the MCU timer. This would result in a 1-in-20 or
5% error in the power measurement.

Rev. C | Page 19 of 24

ADE7752/ADE7752A

(

)

×

×

===

×

×

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TRANSFER FUNCTION

FREQUENCY OUTPUTS F1 AND F2

The ADE7752 calculates the product of six voltage signals (on
c

urrent channel and voltage channel) and then low-pass filters
this product to extract real power information. This real power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, such as

29.32 Hz maximum for ac signals with SCF = 1; S0 = S1 = 1 (see
Tabl e 6). This means that the frequency at these outputs is
g

enerated from real power information accumulated over a
relatively long period of time. The result is an output frequency
that is proportional to the average real power. The averaging of
the real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:

181.6

=

Freq

AAN

BBN

2

V

REF

where:

Freq =

the output frequency on F1 and F2 (Hz).

V

and VCN = the differential rms voltage signal on voltage

AN, VBN,

channels (V).

I

and IC = the differential rms voltage signal on current

A, IB,

channels (V).

V

= the reference voltage (2.4 V ± 8%) (V).

REF

F

= one of seven possible frequencies selected by using the

1–7

logic inputs SCF, S0, and S1 (see Ta b l e 5 ).

Table 5. F

Frequency Selection

1–7

SCF S1 S0 F

1

(Hz)

1–7

0 0 0 1.27
1 0 0 1.19
0 0 1 5.09
1 0 1 4.77
0 1 0 19.07
1 1 0 19.07
0 1 1 76.29
1 1 1 0.60

1

F

is a fraction of the master clock and therefore varies if the specified

1–7

CLKIN frequency is altered.

Example 1

Thus, if full-scale differential dc voltages of +500 mV are
applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is
the maximum differential voltage that can be connected to
current and voltage channels), the expected output frequency is
calculated as follows:

××+×+××

FIVIVIV

−

CCN

71

F

= 0.60 Hz, SCF = S0 = S1 = 1

1–7

V

= V = V

AN

BN CN

= IA = IB = IC = 500 mV dc =

0.5 V(rms of dc = dc)

V

= 2.4 V (nominal reference value)

REF

Note that if the on-chip reference is used, actual output fre­q

uencies may vary from device to device due to reference

tolerance of ±8%.

60.05.05.0181.6

3

×=Freq

×

2

4.2

Hz483.0

=

Example 2

In this example, with ac voltages of ±500 mV peak applied to
the voltage channels and current channels, the expected output
frequency is calculated as follows:

SSSCFF

110,Hz60.0

−

AN

REF

71

BN

CN

AC

peakmV500

()

V4.2

=

=

ICIBIAVVV

=====

Vrms

5.0

==

2

valuereferencenominalV

Note that if the on-chip reference is used, actual output fre­q

uencies may vary from device to device due to reference

tolerance of ±8%.

×

3

×=Freq

6.05.05.0181.6

=

2

4.222

××

Hz24.0

As can be seen from these two example calculations, the

aximum output frequency for ac inputs is always half of that

m
for dc input signals. The maximum frequency also depends on
the number of phases connected to the ADE7752. In a 3-phase
3-wire delta service, the maximum output frequency is different
from the maximum output frequency in a 3-phase
4-wire Wye service. The reason is that there are only two phases
connected to the analog inputs, but also that in a delta service,
the current channel input and voltage channel input of the same
phase are not in phase in normal operation.

Example 3

In this example, the ADE7752 is connected to a 3-phase 3-wire
delta service as shown in Figure 21. The total real energy
calc

ulation processed in the ADE7752 can be expressed as

Total R eal P o we r = (V

where VA, VB, and V
C, respectively. I

B represent the voltage on Phase A, B, and

and I

A

− VC) × IA + (VB − VC) × I

A

C

B represent the current on Phase A and

B

B B

B

B, respectively.

Rev. C | Page 20 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

As the voltage and current inputs respect Equations 5 and 6, the
total real power (P) is

()( )()( )

⎛
⎜

⎜
⎝

⎛
⎜

⎜
⎝

()

()

×××

ω

cos2

⎛

cos2

⎜
⎝

⎛

ω

cos2

⎜
⎝

cos2cos2

tI

lA

π

2

⎞

+××+

ω

lB

⎟

3

⎠

π

2

⎞

+×××

tI

⎟

3

⎠

IIVVIIVVP

−×−+−−=

BNBPCBANAPCA

⎞

π

4

⎛

ωω

⎜
⎝

⎞

⎟

tVtVP

+××−××=

⎟

lClA

⎟

3

⎠

⎠

π

4

⎛

+××−

ω

tVvtV

cos2

⎜

lClB

3

⎝

For simplification, assume that ϕA = ϕB = ϕBC = 0 and

= V

B = V

V

A

= V. The preceding equation becomes:

B

C

2

π

⎛

⎞

⎛

×××=

sin2

IVP

A

×××+

sin2

IV

B

sin

tω

⎜

⎟

⎜

3

⎝

π

⎛
⎜

3

⎝

⎝

⎠

⎞

()

⎟
⎠

2

π

⎞

()

×

+×

cos

⎟

3

⎠

cossin

tω

ll

(9)

2

π

⎛
⎜
⎝

⎞

+×+×

tωπtω

⎟

ll

3

⎠

P then becomes:

⎛

2

where V

π

⎛

sin

⎜

××=

⎜

⎜

3

⎝

⎝

⎛

π

⎛

××+

sin

⎜

⎜

⎜

3

⎝

⎝

= V × sin(2π/3) and VBN = V × sin(π/3).

AN

⎛

⎞
⎟

⎠

⎞
⎟

⎠

ω

2sin

⎜

lAAN

⎝

⎛

ω

tIV

2sin

⎜

lBBN

⎝

As the LPF on each channel eliminates the 2ωl co

⎞

π

2

⎞

tIVP

++

⎟

⎟

⎟

3

(10)

⎠

⎠

⎞

π

⎞

++

⎟

⎟

⎟

3

⎠

⎠

mponent of

the equation, the real power measured by the ADE7752 is

3

2

3

IVIVP

××+××=

BBNAAN

2

If full-scale ac voltage of ±500 mV peak is applied to the voltage
cha

nnels and current channels, the expected output frequency

is calculated as follows:

110,60.0

====

71

−

V

REF

Hz

0

==

IV

CCN

=

SSSCFF

500

CBABNAN

value referencenominal V4.2

5.0

======

2

rmsacpeakIIIVV

VVm

Note that if the on-chip reference is used, actual output fre­q

uencies may vary from device to device due to reference

tolerance of ±8%.

⎞

⎞

⎟

⎟

⎟

⎠

⎠

Tabl e 6 shows a complete listing of all maximum output
frequencies when using all three channel inputs.

Table 6. Maximum Output Frequency on F1 and F2

Max Frequency for

SCF S1 S0

1 0 0 0.48 0.96
0 0 1 2.04
1 0 1 1.91
0 1 0 7.67
1 1 0 7.67
0 1 1 30.70

AC Inputs (

Hz)

Max Frequency for
DC Inputs (Hz)

1.02 0 0 0 0.51

4.09

3.84

15.35

15.35

61.4

0.48 1 1 1 0.24

FREQUENCY OUTPUT CF

The pulse output calibration frequency (CF) is intended for use
during calibration. The output pulse rate on CF can be up to
160 times the pulse rate on F1 and F2. The lower the F
frequency selected, the higher the CF scaling. Tab l e 7 shows

ow the two frequencies are related, depending on the states of

h
the logic inputs S0, S1, and SCF. Because of its relatively high
pulse rate, the frequency at this logic output is proportional to
the instantaneous real power. As with F1 and F2, the frequency
is derived from the output of the low-pass filter after multiplica­tion. However, because the output frequency is high, this real
power information is accumulated over a much shorter time.
Thus, less averaging is carried out in the digital-to-frequency
conversion. With much less averaging of the real power signal,
the CF output is much more responsive to power fluctuations.

Figure 15.

See

Table 7. Maximum Output Frequency on CF

SCF S1 S0 F

0 0 0 1.27 160 × F1, F2 = 81.87
1 0 0 1.19 8 × F1, F2 = 3.83
0 0 1 5.09
1 0 1 4.77
0 1 0 19.07
1 1 0 19.07
0 1 1 76.29
1 1 1 0.60 16 × F1, F2 = 3.84

(Hz) CF Max for AC Signals (Hz)

1–7

160 × F1, F2 = 327.46
16 × F1, F2 = 30.70
16 × F1, F2 = 122.81
8 × F1, F2 = 61.40
8 × F1, F2 = 245.61

1–7

2

×=Freq

×××

2

4.222

××

3

60.05.05.0181.6

=×

2

Hz139.0

Rev. C | Page 21 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in Ta ble 5, the user can select one of seven frequen­cies. This frequency selection determines the maximum
frequency on F1 and F2. These outputs are intended to be
used to drive the energy register (electromechanical or other).
Since only seven different output frequencies can be selected,
the available frequency selection has been optimized for a 3­phase 4-wire service with a meter constant of 100 imp/kWhr
and a maximum current between 10 A and 100 A.

ws the output frequency for several maximum currents

sho

) with a line voltage of 220 V (phase neutral). In all cases,

(I

MAX

Table 8

the meter constant is 100 imp/kWhr.

Table 8. V. F1 and F2 Frequency at 100 imp/kWhr

I

(A) F1 and F2 (Hz)

MAX

10 0.18
25 0.46
40 0.73
60 1.10
80 1.47
100 1.83

The F

frequencies allow complete coverage of this range of

1–7

output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on the voltage channels
should be set to half scale to allow for calibration of the meter
constant. The current channel should also be no more than
half scale when the meter sees maximum load. This allows
overcurrent signals and signals with high crest factors to be
accommodated.

en all six analog inputs are half scale.

F2 wh

Tabl e 9 shows the output frequency on F1 and

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2

SCF S1 S0 F

1–7

(Half-Scale AC Inputs)

0 0 0 1.27 0.26
1 0 0 1.19 0.24
0 0 1 5.09 1.02
1 0 1 4.77 0.96
0 1 0 19.07 3.84
1 1 0 19.07 3.84
0 1 1 76.29 15.35
1 1 1 0.60 0.12

When selecting a suitable F
frequency output at I

MAX

frequency for a meter design, the

1–7

(maximum load) with a 100 imp/kWhr

meter constant should be compared with column 5 of Tabl e 9.

requency closest to that listed in Table 9 is the best choice

The f

frequency (F

of

). For example, if a 3-phase 4-wire Wye meter

1–7

with a 25 A maximum current is being designed, the output
frequency on F1 and F2 with a 100 imp/kWhr meter constant is

0.15 Hz at 25 A and 220 V (from

e closest frequency to 0.15 Hz in column 5 is 0.12 Hz.

th
Therefore, F

= 0.6 Hz is selected for this design.

1–7

Tabl e 8). Looking at Tabl e 9,

FREQUENCY OUTPUTS

Figure 2 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electro­mechanical impulse counter. The F1 and F2 outputs provide
two alternating high going pulses. The pulse width (t
275 ms, and the time between the rising edges of F1 and F2 (t
is approximately half the period of F1 (t
period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse
width of F1 and F2 is set to half of their period. The maximum
output frequencies for F1 and F2 are shown in

The high frequency CF output is intended to be used for
co

mmunications and calibration purposes. CF produces a
96 ms-wide active high pulse (t
active power. The CF output frequencies are given in Tab le 7 . As

the case of F1 and F2, if the period of CF (t

in
192 ms, the CF pulse width is set to half the period. For
example, if the CF frequency is 20 Hz, the CF pulse width is
25 ms. One exception to this is when the mode is S0 = 1,
SCF = S1 = 0. In this case, the CF pulse width is 66% of the period.

NO LOAD THRESHOLD

The ADE7752 also includes no load threshold and start-up cur­rent features that eliminate any creep effects in the meter. The
ADE7752 is designed to issue a minimum output frequency.
Any load generating a frequency lower than this minimum fre­quency does not cause a pulse to be issued on F1, F2, or CF. The
minimum output frequency is given as 0.005% of the full-scale
output frequency for each of the F
approximately 0.00204% of the F
For example, for an energy meter with a 100 imp/kWhr meter
constant using F
F1 or F2 would be 9.59 × 10
at CF (16 × F1 Hz). In this example, the no load threshold
would be equivalent to 3.45 W of load or a start-up current of

15.70 mA at 240 V.

Table 10. CF, F1, and F2 Minimum Frequency at No Load
Threshold

SCF S1 S0 F1, F2 Min (Hz) CF Min (Hz)

0 0 0 2.56 x 10
1 0 0 2.40 x 10
0 0 1 1.02 x 10
1 0 1 9.59 x 10
0 1 0 3.84 x 10
1 1 0 3.84 x 10
0 1 1 1.54 x 10
1 1 1 1.20 x 10

(4.77 Hz), the minimum output frequency at

1–7

) is set at

1

). If, however, the

2

Tabl e 6.

) at a frequency proportional to

4

) falls below

5

frequency selections or

1–7

frequency (see Tab le 1 0).

1–7

–5

Hz. This would be 1. 54× 10–3 Hz

−05

−05

−04

−05

−04

−04

−03

−05

4.09 x 10

1.92 x 10

1.64 x 10

1.54 x 10

6.14 x 10

3.07 x 10

1.23 x 10

1.92 x 10

−03

−04

−02

−03

−03

−03

−02

−04

)

3

Rev. C | Page 22 of 24

ADE7752/ADE7752A

www.BDTIC.com/ADI

NEGATIVE POWER INFORMATION

The ADE7752 detects when the current and voltage channels of
any of the three phase inputs have a phase difference greater
than 90°: ϕ
wrong connection of the meter or generation of active energy.
The REVP pin output goes active high when negative power is
detected on any of the three phase inputs. If positive active
energy is detected on all the three phases, REVP pin output is low.

or ϕB or ϕB

A

> 90°. This mechanism can detect

C

The REVP pin output changes state at the same time a pulse is

sued on CF. If several phases measure negative power, the

is
REVP pin output stays high until all the phases measure
positive power. If a phase has gone below the no load threshold,
REVP detection on this phase is disabled. REVP detection on
this phase resumes when the power returns out of no load
condition. See the

No Load Threshold section.

Rev. C | Page 23 of 24

ADE7752/ADE7752A

Y

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

15.60 (0.6142)

15.20 (0.5984)

24 13

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARIT

0.10

1.27 (0.0500)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.020)

0.31 (0.012)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

7.60 (0.2992)

7.40 (0.2913)

12

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 28. 24-Lead Standard Small Outline Package [SOIC]

Wide Body (RW-24 )

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADE7752AR -40°C to + 85°C 24- Lead SOIC Package RW-24 in Tubes
ADE7752ARRL -40°C to + 85°C 24- Lead SOIC Package RW-24 on 13" Reels
ADE7752ARZ -40°C to + 85°C 24- Lead SOIC Package
ADE7752ARZ-RL -40°C to + 85°C 24- Lead SOIC Package RW-24 on 13" Reels
ADE7752AAR -40°C to + 85°C 24- Lead SOIC Package RW-24 in Tubes
ADE7752AAR-RL -40°C to + 85°C 24- Lead SOIC Package
ADE7752AARZ -40°C to + 85°C 24- Lead SOIC Package
ADE7752AARZ-RL -40°C to + 85°C 24- Lead SOIC Package RW-24 on 13" Reels
EVAL-ADE7752EB Evaluation Board
EVAL-ADE7752AEB Evaluation Board

1

Z = Pb-free part.

1

1

RW-24 in Tubes

RW-24 on 13" Reels

1

1

RW-24 in Tubes

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C02676-0-7/05(C)

Rev. C | Page 24 of 24