Datasheet ADE7752 Datasheet (Analog Devices)

Polyphase Energy Metering IC

FEATURES

High accuracy, supports 50 Hz/60 Hz IEC 687/61036
Less than 0.1% error over a dynamic range of 500 to 1
Compatible with 3-phase/3-wire delta and 3-phase/4-wire Wye

configurations

The ADE7752* supplies average real power on the frequency

outputs F1 and F2

High frequency output CF is intended for calibration and

supplies instantaneous real power

Logic output NEGP indicates a potential miswiring or negative

power for each phase

Direct drive for electromechanical counters and 2-phase stepper

motors (F1 and F2)

Proprietary ADCs and DSP provide high accuracy over large

variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.4 V ±8% (20 ppm/°C typical) with external

overdrive capability
Single 5 V supply, low power (60 mW typical)
Low cost CMOS process

*Patent pending.

with Pulse Output

ADE7752

GENERAL DESCRIPTION

The ADE7752 is a high accuracy polyphase electrical energy
measurement IC. The part specifications surpass the accuracy
requirements as quoted in the IEC61036 standard. The only analog
circuitry used in the ADE7752 is in the ADCs and reference circuit.
All other signal processing (e.g., multiplication, filtering, and sum­mation) is carried out in the digital domain. This approach
provides superior stability and accuracy over extremes in environ­mental conditions and over time.

The ADE7752 supplies average real power information on the low
frequency outputs, F1 and F2. These logic outputs may be used to
directly drive an electromechanical counter or to interface with an
MCU. The CF logic output gives instantaneous real power informa­tion. This output is intended to be used for calibration purposes.

The ADE7752 includes a power supply monitoring circuit on the
V

pin. The ADE7752 will remain inactive until the supply voltage

DD

on V

reaches 4 V. If the supply falls below 4 V, the ADE7752 will

DD

also be reset and no pulses will be issued on F1, F2, and CF.

Internal phase matching circuitry ensures that the voltage and
current channels are phase matched. An internal no load threshold
ensures the part does not exhibit any creep when there is no load.

FUNCTIONAL BLOCK DIAGRAM

5

IAP

IAN

6

16

VA P

IBP

7

8

IBN

15

VBP

9

ICP

10

ICN

VCP

14

13

VN

2.4V REF

11 12 4 18 21 22 23 24 1

AGND

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

ADC

ADC

ADC

ADC

ADC

ADC

Ω

4k

REF

IN/OUT

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

HPF

Φ

PHASE

CORRECTION

Figure 1. Functional Block Diagram

The ADE7752 is available in a 24-lead SOIC package.

ADE7752

Σ

V

DD

3

POWER
SUPPLY

MONITOR

2

DGND

19

CLKIN

CLKOUT

20

CFS1 F1F2S0SCFNEGP

02676-A-001

ABS

17

LPF

LPF

LPF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

X

X

X

DIGITAL-TO-FREQUENCY CONVER TER

Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADE7752

TABLE OF CONTENTS

Specifications..................................................................................... 3

Meter Connections..................................................................... 15

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

Terminology ...................................................................................... 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Test Circuit ......................................................................................11

Theory of Operation...................................................................... 12

Power Factor Considerations.................................................... 12

Nonsinusoidal Voltage and Current......................................... 13

Analog Inputs.................................................................................. 14

Current Channels....................................................................... 14

Voltage Channels........................................................................ 14

Typical Connection Diagrams ...................................................... 15

Current Channel Connection................................................... 15

Voltage Channels Connection .................................................. 15

Power Supply Monitor ................................................................... 17

HPF and Offset Effects .............................................................. 17

Digital-to-Frequency Conversion................................................ 18

Mode Selection of the Sum of the Three Active Energies .... 19

Power Measurement Considerations....................................... 19

Transfer Function........................................................................... 20

Frequency Outputs F1 and F2.................................................. 20

Frequency Output CF................................................................ 21

Selecting a Frequency for an Energy Meter Application........... 22

Frequency Outputs..................................................................... 22

No Load Threshold .................................................................... 23

Negative Power Information..................................................... 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

Location Page

9/03—Data Sheet Changed from Rev. A to Rev. B

Updated Format................................................................................................................................................................................................... Universal

Change to Figure 19 .........................................................................................................................................................................................................15

5/03—Data Sheet Changed from Rev. 0 to Rev. A

to F

Changed F

Change to Figure 6 ...........................................................................................................................................................................................................10

Changes to Frequency Outputs F1 and F2 section ......................................................................................................................................................13

Replaced Table II ..............................................................................................................................................................................................................13

Changes to Examples 1, 2, and 3.....................................................................................................................................................................................14

Replaced Table III.............................................................................................................................................................................................................14

Replaced Tables IV, V, and VI ..........................................................................................................................................................................................15

Changes to SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION section.......................................................................15

Changes to NO LOAD THRESHOLD section .............................................................................................................................................................16

Replaced Table VII............................................................................................................................................................................................................16

1–5

............................................................................................................................................................................................. Universal

1–7

Rev. B | Page 2 of 24

ADE7752

SPECIFICATIONS

Table 1. VDD = 5 V± 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, T

Parameter Conditions Min Typ Max Unit

ACCURACY

Measurement Error on Current

Channel

Phase Error between Channels

1, 2

PF = 0.8 Capacitive
PF = 0.5 Capacitive

Voltage Channel with Full-Scale Signal (±500 mV), 25°C,
Over a Dynamic Range of 500 to 1 0.1 % Reading

AC Power Supply Rejection SCF = 0; S0 = S1 = 1

Output Frequency Variation (CF)

IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms,
@ 50 Hz, Ripple on VDD of 200 mV rms @ 100 Hz

DC Power Supply Rejection S1 = 1; S0 = SCF = 0

Output Frequency Variation (CF)

V1 = 100 mV rms, V2 = 100 mV rms, V

= 5 V ±250 mV 0.1

DD

ANALOG INPUTS See Analog Inputs Section

Maximum Signal Levels VAP–VN, VBP–VN, VCP–VN, IAP–IAN, IBP–IBN, ICP–ICN ±0.5 V peak Diff.

Input Impedance (DC) CLKIN = 10 MHz 370 410 kΩ

Bandwidth (–3 dB) CLKIN/256, CLKIN = 10 MHz 14 kHz

ADC Offset Error

1, 2

Gain Error External 2.5 V Reference, IA = IB = IC = 500 mV dc ±9

REFERENCE INPUT

REF

Input Voltage Range 2.4 V + 8%

IN/OUT

Input Impedance

Input Capacitance

2.4 V – 8% 2.2

ON-CHIP REFERENCE Nominal 2.4 V

Reference Error

Temperature Coefficient
CLKIN All Specifications for CLKIN of 10 MHz

Input Clock Frequency
LOGIC INPUTS3

ACF, S0, S1, and ABS

Input High Voltage, V
Input Low Voltage, V

V

INH

V

INL

= 5 V ±5% 2.4

DD

= 5 V ±5%

DD

Input Current, IIN Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN

LOGIC OUTPUTS3

F1 and F2

Output High Voltage, VOH I
Output Low Voltage, VOL I

CF and NEGP

Output High Voltage, VOH V
Output Low Voltage, VOL V

= 10 mA, V

SOURCE

= 10 mA, VDD = 5 V

SINK

= 5 V 4.5

DD

= 5 V, I

DD

= 5 V, I

DD

= 5 mA 4

SOURCE

= 5 mA

SINK

POWER SUPPLY For Specified Performance

VDD 5 V ±5% 4.75

IDD

1

See section for explanation of specifications. Terminology

2

See plots in Typi . cal Performance Characteristics

3

Sample tested during initial release and after any redesign or process change that may affect this parameter.

MIN

to T

= –40°C to+ 85°C

MAX

±0.1 °(Degrees)
±0.1 °(Degrees)

0.01 % Reading

3.3

±25 mV

2.6 V

10 pF

% Reading

% Ideal

V
kΩ

±200 mV

25 ppm/°C

10 MHz

0.8 V
±3 µA

V

10 pF

0.5 V

0.5 V

V

V

5.25 V

12 16 mA

Rev. B | Page 3 of 24

ADE7752

TIMING CHARACTERISTICS

Table 2. VDD = 5 V ± 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, T

MIN

to T

= –40°C to +85°C

MAX

Parameter Conditions Unit

3

t

275 F1 and F2 Pulse Width (Logic High) ms

1

t2 See Table 6 Output Pulse Period. See Transfer Function section. sec
t3 1/2 t2 Time between F1 Falling Edge and F2 Falling Edge sec

3, 4

t

96 CF Pulse Width (Logic High) ms

4

5

t

See Table 7 CF Pulse Period. See Transfer Function section. sec

5

t6 CLKIN/4 Minimum Time between F1 and F2 Pulse sec

1

Sample tested during initial release and after any redesign or process change that may affect this parameter.

2

See . Figure 2

3

The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See Fre section. quency Outputs

4

CF is not synchronous to F1 or F2 frequency outputs.

5

The CF pulse is always 1 µs in the high frequency mode. See section.

Frequency Outputs

t

1

F1

t

6

t

2

t

F2

3

1, 2

t

4

CF

t

5

02676-A-003

Figure 2. Timing Diagram for Frequency Outputs

Rev. B | Page 4 of 24

ADE7752

ABSOLUTE MAXIMUM RATINGS

Table 3. TA = 25°C, unless otherwise noted

Parameter Rating

VDD to AGND –0.3 V to +7 V
VDD to DGND –0.3 V to +7 V
Analog Input Voltage to AGND

VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN,

ICP, and ICN –6 V to +6 V
Reference Input Voltage to AGND –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
24-Lead SOIC, Power Dissipation 88 mW
θJA Thermal Impedance 250°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 5 of 24

ADE7752

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7752 is defined by the following formula:



=

ErrorPercentage 100




7752

EnergyTrue

Error between Channels

The HPF (high-pass filter) in the current channel has a phase
lead response. To offset this phase response and equalize the
phase response between channels, a phase correction network is
also placed in the current channel. The phase correction net­work ensures a phase match between the current channels and
voltage channels to within ±0.1° over a range of 45 Hz to 65 Hz
and ±0.2° over a range of 40 Hz to 1 kHz. See Figure 25 and
Figure 26.

Power Supply Rejection

This quantifies the ADE7752 measurement error as a
percentage of reading when the power supplies are varied.

For the ac PSR measurement, a reading at a nominal supply
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supply and a second reading is obtained under the



EnergyTrue–ADE by Registered Energy

%

×




same input signal levels. Any error introduced is expressed as a
percentage of reading. See definition for Measurement Error.

For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supply is then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

ADC Offset Error

This refers to the dc offset associated with the analog inputs to
the ADCs. It means that with the analog inputs connected to
AGND, the ADCs still see an analog input signal offset.
However, as the HPF is always present, the offset is removed
from the current channel and the power calculation is not
affected by this offset.

Gain Error

The gain error of the ADE7752 is defined as the difference
between the measured output frequency (minus the offset) and
the ideal output frequency. The difference is expressed as a
percentage of the ideal frequency. The ideal frequency is
obtained from the ADE7752 transfer function. See the Transfer
Function section.

Rev. B | Page 6 of 24

ADE7752

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CF

Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This
output is intended to be used for calibration purposes. See the SCF pin description.

2 DGND

This provides the ground reference for the digital circuitry in the ADE7752, i.e., multiplier, filters, and digital-to­frequency converter. Because the digital return currents in the ADE7752 are small, it is acceptable to connect
this pin to the analog ground plane of the whole system.

3 VDD

Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply voltage
should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF
capacitor in parallel with a 100 nF ceramic capacitor.

4 NEGP

This logic output will go logic high when negative power is detected on any of the three phase inputs, i.e.,
when the phase angle between the voltage and the current signals is greater than 90°. This output is not
latched and will be reset when positive power is once again detected. See the
section.

5, 6;
7, 8;
9, 10

IAP, IAN;
IBP, IBN;
ICP, ICN

Analog Inputs for Current Channel. This channel is intended for use with the current transducer and is
referenced in this document as the current channel. These inputs are fully differential voltage inputs with
maximum differential input signal levels of ±0.5 V. See the Analog Inputs section. Both inputs have internal ESD
protection circuitry; in addition, an overvoltage of ±6 V can be sustained on these inputs without risk of
permanent damage.

11 AGND

This pin provides the ground reference for the analog circuitry in the ADE7752, i.e., ADCs, temperature sensor,
and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the
system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and
voltage transducers, and so on. To keep ground noise around the ADE7752 to a minimum, the quiet ground
plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device
on the analog ground plane.

12 REF

IN/OUT

This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V ±
8% and a typical temperature coefficient of 20 ppm/°C. An external reference source may also be connected at
this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic capacitor.

13–16

VN, VCP, VBP,
VAP

Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer and is
referenced in this document as the voltage channel. These inputs are single-ended voltage inputs with a
maximum signal level of ±0.5 V with respect to VN for specified operation. All inputs have internal ESD
protection circuitry; in addition, an overvoltage of ± 6 V can be sustained on these inputs without risk of
permanent damage.

17

This logic input is used to select the way the three active energies from the three phases are summed. This

ABS

offers the designer the capability to do the arithmetical sum of the three energies (ABS
the absolute values (ABS

18 SCF

Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table
7 shows how the calibration frequencies are selected.

19 CLKIN

Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of
between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data
sheet for load capacitance requirements.

23

22

21

20

19

18

17

16

15

14

13

F1

F2

S1

S0

CLKOUT

CLKIN

SCF

ABS

VAP

VBP

VCP

VN

02676-A-003

REF

124

CF

2

DGND

V

3

DD

4

NEGP

5

IAP

ADE7752

6

IAN

TOP VIEW

(Not to Scale)

7

IBP

8

IBN

9

ICP

10

ICN

11

AGND

12

IN/OUT

Figure 3. Pin Configuration

Negative Power Information

logic high) or the sum of

logic low). See the section.

Mode Selection of the Sum of the Three Active Energies

Rev. B | Page 7 of 24

ADE7752

Pin No. Mnemonic Description

20 CLKOUT

21, 22 S0, S1

24, 23 F1, F2

A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the
ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a
crystal is being used.

These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the
an Energy Meter Application

Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used
to drive electromechanical counters and 2-phase stepper motors directly. See the Transfer Function section.

Selecting a Frequency for

section.

Rev. B | Page 8 of 24

ADE7752

TYPICAL PERFORMANCE CHARACTERISTICS

1

0.5

WYE CONNECTION
ON-CHIP REFERENCE

0.4

0.3

0.2

0.1

PHASE B

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

PHASE C

A

ASE

P

H

CURRENT CHANNEL (% of Full Scale)

PHASE A + B + C

Figure 4. Error as a Percent of Reading

with Internal Reference (Wye Connection)

1.0

WYE CONNECTION
ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1

+85°C PF = +0.5

5

2

+

°

C

P

F = +

–

4

0

°

C

P

+

F

=

CURRENT CHANNEL (% of Full Scale)

1

0

.5

+25°C PF = –0.5

Figure 5. Error as a Percent of Reading over Power Factor

with Internal Reference (Wye Connection)

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

+85°C PF = +0.5

+25°C

P

F = +

1

–

4

0

°

C

P

0

.5

+

F

=

+25°C PF = –0.5

CURRENT CHANNEL (% of Full Scale)

Figure 6. Error as a Percent of Reading over Power Factor

with External Reference (Wye Connection)

02676-A-004

10010

02676-A-005

10010

02676-A-006

10010

1.0

WYE CONNECTION
ON-CHIP REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1

+85°C PF = 1

F

=

+25°C PF = 1

1

–

4

0

°

C

P

CURRENT CHANNEL (% of Full Scale)

Figure 7. Error as a Percent of Reading over Temperature

with Internal Reference (Wye Connection)

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

DELTA CONNECTION
ON-CHIP REFERENCE

PF = –0.5

PF = +1

0

P

.5

+

F

=

CURRENT CHANNEL (% of Full Scale)

Figure 8. Error as a Percent of Reading over Power Factor

with Internal Reference (Delta Connection)

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

+85°C PF = 1

5

2

+

°

C

P

F = 1

–

4

0

°

C

P

1

F

=

CURRENT CHANNEL (% of Full Scale)

Figure 9. Error as a Percent of Reading over Temperature

with External Reference (Wye Connection)

02676-A-007

10010

02676-A-008

10010

02676-A-009

10010

Rev. B | Page 9 of 24

ADE7752

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

45

Figure 10. Error as a Percent of Reading over Frequency

0.5

WYE CONNECTION
EXTERNAL REFERENCE

0.4

0.3

0.2

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1

Figure 11. Error as a Percent of Reading over Power Supply

WYE CONNECTION
ON-CHIP REFERENCE

PF = 1

F = 0

P

.5

FREQUENCY (Hz)

with an Internal Reference (Wye Connection)

4.75V

5

V

5

V

5

.2

CURRENT CHANNEL (% of Full Scale)

with External Reference (Wye Connection)

N: 88

18

MEAN: 4.48045
SD: 3.23101
MIN: –2.47468 MAX: 12.9385
RANGE: 15.4132

15

12

9

6

3

60 655550

02676-A-010

0

–20 –10–15

CH_I PhA OFFSET (mV)

02676-A-012

2015105–5 0

Figure 12. Channel 1 Offset Distribution

0.5

WYE CONNECTION
ON-CHIP REFERENCE

0.4

0.3

0.2

0.1

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

02676-A-011

10010

–0.5

4.75V

0

5

V

5

.2

0.1 1

CURRENT CHANNEL (% of Full Scale)

V

5

02676-A-013

10010

Figure 13. Error as a Percent of Reading over Power Supply

with Internal Reference (Wye Connection)

Rev. B | Page 10 of 24

ADE7752

TEST CIRCUIT

V

DD

1kΩ

33nF

1kΩ

33nF

100nF

V

DD

5

IAP

ADE7752

6

IAN

IBP

7

8

IBN

ICP

9

10

ICN

16

VAP

15

VBP

VCP

14

VN AGND DGND

13 11

1kΩ

33nF

3

17

ABS

CLKOUT

CLKIN

REF

IN/OUT

NEGP

F1

F2

CF

S0

S1

SCF

2

24

23

825Ω

1

20

10MHz

19

21

22

18

12

100nF 10µF

4

NOT
CONNECTED

22pF

22pF

1kΩ

PS2501-1

V

DD

K7

TO FREQ.
COUNTER

K8

02676-A-014

220V

1MΩ

1kΩ

LOAD

I

33nF

10µF

RB

SAME AS
IAP, IAN

SAME AS
IAP, IAN

SAME AS VAP

SAME AS VAP

Figure 14. Test Circuit for Performance Curves

Rev. B | Page 11 of 24

ADE7752

THEORY OF OPERATION

The six voltage signals from the current and voltage transducers
are digitized with ADCs. These ADCs are 16-bit second order
∑-∆ with an oversampling rate of 833 kHz. This analog input
structure greatly simplifies transducer interface by providing a
wide dynamic range for direct connection to the transducer and
also simplifying the antialiasing filter design. A high-pass filter
in the current channel removes the dc component from the
current signal. This eliminates any inaccuracies in the real
power calculation due to offsets in the voltage or current
signals—see HPF and Offset Effects section.

The real power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals of each
phase. In order to extract the real power component (i.e., the dc
component), the instantaneous power signal is low-pass filtered
on each phase. Figure 15 illustrates the instantaneous real power
signal and shows how the real power information can be
extracted by low-pass filtering the instantaneous power signal.
This method is used to extract the real power information on
each phase of the polyphase system. The total real power
information is then obtained by adding the individual phase
real power. This scheme correctly calculates real power for
nonsinusoidal current and voltage waveforms at all power
factors. All signal processing is carried out in the digital domain
for superior stability over temperature and time.

The low frequency output of the ADE7752 is generated by
accumulating the total real power information. This low
frequency inherently means a long accumulation time between
output pulses. The output frequency is therefore proportional to
the average real power. This average real power information can,
in turn, be accumulated (e.g., by a counter) to generate real
energy information. Because of its high output frequency and
therefore shorter integration time, the CF output is proportional
to the instantaneous real power. This pulse is useful for system
calibration purposes that would take place under steady load
conditions.

POWER FACTOR CONSIDERATIONS

The method used to extract the real power information from
the individual instantaneous power signal (i.e., by low-pass
filtering) is still valid when the voltage and current signals of
each phase are not in phase. Figure 16 displays the unity power
factor condition and a DPF (displacement power factor) = 0.5,
i.e., current signal lagging the voltage by 60°, for one phase of
the polyphase. If we assume the voltage and current waveforms
are sinusoidal, the real power componen of the instantaneous
power signal (i.e., the dc term) is given by:

×

1V






2






()

°×

60cos

p(t) = i(t) × v(t)

V × I

V × I

IAP
IAN

VA P

IBP
IBN

VBP

ICP
ICN

VCP

VN

2

TIME

WHERE:

v(t) = V × cos (ωt)
i(t) = I × cos (ωt)
p(t) =

V × I

{1+ cos (2ωt)}

2

INSTANTANEOUS

POWER SIGNAL - p(t)

HPF

ADC

MULTIPLIER

ADC

HPF

ADC

MULTIPLIER

ADC

HPF

ADC

MULTIPLIER

ADC

V × I

2

LPF

LPF

LPF

INSTANTANEOUS

REAL POWER SIGNAL

ABS

|X|

|X|

|X|

Σ

VA × IA + VB × IB +

VC×IC

2

INSTANTANEOUS

TOTAL

POWER SIGNAL

DIGITAL-TO-

FREQUENCY

Σ

DIGITAL-TO-

FREQUENCY

Σ

CF

F1
F2

02676-A-015

Figure 15. Signal Processing Block Diagram

Rev. B | Page 12 of 24

ADE7752

∞

φ×=

∞

This is the correct real power calculation.

INSTANTANEOUS
POWER SIGNAL

INSTANTANEOUS
REAL POWER SIGNAL

()

O

∑

n

=

0

n

(

tnIVIti βω××+=

sin2

)

(2)

n

V× I

2

0V

CURRENT

VO LTA G E

V× I

INSTANTANEOUS
POWER SIGNAL

× cos(60°)

2

0V

VO LTA G E

Figure 16. DC Component of Instantaneous Power Signal

Conveys Real Power Information PF < 1

INSTANTANEOUS REAL
POWER SIGNAL

60°

CURRENT

NONSINUSOIDAL VOLTAGE AND CURRENT

The real power calculation method also holds true for nonsin­usoidal current and voltage waveforms. All voltage and current
waveforms in practical applications will have some harmonic
content. Using the Fourier Transform, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content:

∞

()

∑

n

=

0

where:

v(t) is the instantaneous voltage
V

is the average value

O

Vn is the rms value of voltage harmonic n

and

α

is the phase angle of the voltage harmonic

n

sin2

no

(

tnVVtv α+ω××+=

)

(1)

n

where:

i(t) is the instantaneous current
I

is the dc component

O

I

is the rms value of current harmonic n

n

β

is the phase angle of the current harmonic

n

Using Equations 1 and 2, the real power, P, can be expressed in
terms of its fundamental real power (P
power (P

).

H

P = P

) and harmonic real

1

+ PH

1

where:

cos

IVP

1111

(3)

111

cos

IVP

φ×=

n

nn

nn

(4)

∑

n

β−α=φ

=

1

β−α=φ

02676-A-016

H

n

As can be seen from Equation 4, a harmonic real power compo­nent is generated for every harmonic, provided that harmonic is
present in both the voltage and current waveforms. The power
factor calculation has been shown to be accurate in the case of a
pure sinusoid. Therefore, the harmonic real power must also
correctly account for power factor since it is made up of a series
of pure sinusoids.

Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 10 MHz.

Rev. B | Page 13 of 24

ADE7752

ANALOG INPUTS

CURRENT CHANNELS

The voltage outputs from the current transducers are connected
to the ADE7752 current channels, which are fully differential
voltage inputs. IAP, IBP, and ICP are the positive inputs for IAN,
IBN, and ICN, respectively.

VOLTAGE CHANNELS

The output of the line voltage transducer is connected to the
ADE7752 at this analog input. Voltage channels are a pseudo­differential voltage input. VAP, VBP, and VCP are the positive
inputs with respect to VN.

The maximum peak differential signal on the current channel
should be less than ±500 mV (353 mV rms for a pure sinusoidal
signal) for the specified operation.

IAP–IAN

+500mV

V

CM

–500mV

DIFFERENTIAL INPUT

±500mV MAX PEAK

COMMON-MODE

±25mV MAX

AGND

Figure 17. Maximum Signal Levels, Current Channel

IAP

IA

IAN

V

CM

02676-A-017

Figure 17 illustrates the maximum signal levels on IAP and
IAN. The maximum differential voltage between IAP and IAN
is ±500 mV. The differential voltage signal on the inputs must
be referenced to a common mo de, e.g., AGND. The maximum
common-mode signal shown in Figure 17 is ±25 mV.

The maximum peak differential signal on the voltage channel is
±500 mV (353 mV rms for a pure sinusoidal signal) for
specified operation.

Figure 18

illustrates the maximum signal levels that can be

connected to the ADE7752’s voltage channels.

VA P– V N

+500mV

V

CM

–500mV

DIFFERENTIAL INPUT

±500mV MAX PEAK

COMMON-MODE

±25mV MAX

AGND

Figure 18. Maximum Signal Levels, Voltage Channel

VA

VCM

VA P

VN

02676-A-018

Voltage channels must be driven from a common-mode voltage,
i.e., the differential voltage signal on the input must be
referenced to a common mode (usually AGND). The analog
inputs of the ADE7752 can be driven with common-mode
voltages of up to 25 mV with respect to AGND. However, best
results are achieved using a common mode equal to AGND.

Rev. B | Page 14 of 24

ADE7752

(

)

(

(

(

)

φ+ω

φ××

=

TYPICAL CONNECTION DIAGRAMS

CURRENT CHANNEL CONNECTION

Figure 19
channel (IA). A CT (current transformer) is the current trans­ducer selected for this example. Notice the common-mode
voltage for the current channel is AGND and is derived by
center tapping the burden resistor to AGND. This provides the
complementary analog input signals for IAP and IAN. The CT
turns ratio and burden resistor Rb are selected to give a peak
differential voltage of ±500 mV at maximum load.

IP

shows a typical connection diagram for the current

CT

NEUTRALPHASE

Figure 19. Typical Connection for Current Channels

Rf

R

±500mV

b

Rf

IAP

Cf

IAN

Cf

VOLTAGE CHANNELS CONNECTION

Figure 20
The first option uses a PT (potential transformer) to provide
complete isolation from the main voltage. In the second option,
the ADE7752 is biased around the neutral wire, and a resistor
divider is used to provide a voltage signal proportional to the
line voltage. Adjusting the ratio of Ra, Rb, and VR is also a
convenient way of carrying out a gain calibration on the meter.

shows two typical connections for the voltage channel.

PT

±500mV

AGND

NEUTRALPHASE

Ra

NEUTRALPHASE

Figure 20. Typical Connections for Voltage Channels

Cf

*

Rb

*

±500mV

VR

*

Ra >> Rf + VR;*Rb + VR = Rf

*

Rf

Rf

Rf

VA P

Cf

VN

Cf

VA P

VN

Cf

02676-A-019

02676-A-018

METER CONNECTIONS

In 3-phase service, two main power distribution services exist:
3-phase 4-wire or 3-phase 3-wire. The additional wire in the
3-phase 4-wire arrangement is the neutral wire. The voltage
lines have a phase difference of ±120° (±2π/3 radians) between
each other. See Equation 5.

where V

()

()

()

, VB, and VC represent the voltage rms values of the

A

AA

BB

CC

different phases.

The current inputs are represented by Equation 6:

()

()

()

where I
each phase and ϕ

, IB, and IC represent the rms value of the current of

A

cos2

AA

cos2

BB

cos2

CC

, ϕB, and ϕC represent the phase difference of

A

the current and voltage channel of each phase.

The instantaneous powers can then be calculated as follows:

P

A

P

P

Then:

)

()

()

As shown in Equation 7, in the ADE7752, the real power calcu­lation per phase is made when current and voltage inputs of one
phase are connected to the same channel (A, B, or C). Then the
summation of each individual real power calculation gives the
total real power information, P(t) = PA(t) + PB(t) + PC(t).

tVtV

cos2

ω××=

()

l

2



cos2






cos2




l




l






l



π

tVtV

+ω××=

l

3

4

π

tVtV

+ω××=

l

3

tItI

φ+ω×=

A

2

π

tItI

+ω×=

3

4

π

tItI

+ω×=

3

(t) = VA(t) × IA(t)
(t) = VB(t) × IB(t)

B

(t) = VC(t) × IC(t)

C

)

()

()

××−

AAAAAA

BBBBBB

CCCCCC



(5)










(6)

φ+



B





φ+



C



tIVIVtP

2coscos

A

l

π

4



tIVIVtP

+ω××−φ××=

2coscos



l





+ω××−φ××=

tIVIVtP

2coscos



l





φ+



B

3



π

8



φ+



C

3



(7)

Rev. B | Page 15 of 24

ADE7752

Figure 21
inputs with the power lines in a 3-phase 3-wire Delta service.

PHASE A

SOURCE

PHASE B

Note that only two current inputs and two voltage inputs of the
ADE7752 are used in this case. The real power calculated by the
ADE7752 does not depend on the selected channels.

shows the connections of the ADE7752’s analog

Cf

Ra*

Rb*

VR*

Ra*

Rb*

VR*

Rb*

CT

PHASE C

Cf

Ra >> Rf + VR;*Rb + VR = Rf

*

CT

Rb*

ANTIALIASING

FILTERS

Rf

ANTIALIASING

FILTERS

Figure 21. 3-Phase 3-Wire Meter Connection with ADE7752

VA P

IAP

IAN

VN

Cf

IBP

IBN

VBP

LOAD

Figure 22 shows the connections of the ADE7752’s analog
inputs with the power lines in a 3-phase 4-wire Wye service.

Cf

Ra*

Rb*

CT

VAP
IAP

IAN

ANTIALIASING

Rb*

FILTERS

ICP

ICN

VCP

LOAD

IBP
IBN

VBP

02676-A-022

VR*

Rb*

CT

PHASE A

SOURCE

02676-A-021

PHASE B

PHASE C

Cf

Ra*

Rb*

VR*

Rf

VN

Ra >> Rf + VR;*Rb + VR = Rf

CF

*

Ra*

Rb*

VR*

CT

ANTIALIASING

Cf

Rb*

FILTERS

ANTIALIASING

FILTERS

Figure 22. 3-Phase 4-Wire Meter Connection with ADE7752

Rev. B | Page 16 of 24

ADE7752

L

V

POWER SUPPLY MONITOR

The ADE7752 contains an on-chip power supply monitor. The
power supply (VDD) is continuously monitored by the ADE7752.
If the supply is less than 4 V ± 5%, the outputs of the ADE7752
will be inactive. This is useful to ensure correct device startup at
power-up and power-down. The power supply monitor has
built-in hysteresis and filtering. This gives a high degree of
immunity to false triggering due to noisy supplies.

As can be seen from F , the trigger level is nominally set

igure 23
at 4 V. The tolerance on this trigger level is about ±5%. The
power supply and decoupling for the part should be such that
the ripple at V

does not exceed 5 V ± 5% as specified for

DD

normal operation.

V

DD

5V

4V

0V

TIME

INTERNA

RESET

INACTIVE

ACTIVE INACTIVE

× I

OS

OS

V × I

2

Figure 24. Effect of Channel Offset on the Real Power Calculation

The HPF in the current channels have an associated phase
response that is compensated for on-chip. Figure 25 and F

show the phase error between channels with the com-

26
pensation network. The ADE7752 is phase compensated up to
1 kHz as shown. This ensures correct active harmonic power
calculation even at low power factors.

0.07

0.06

0.05

DC COMPONENT (INCLUDING ERRORTERM)
IS EXTRACTED BYTHE LPF FOR REAL
POWER CALCULATION

IOS× V

V

× I

OS

0

ω

FREQUENCY – RAD/S

2ω

02676-A-024

igure

02676-A-023

Figure 23. On-Chip Power Supply Monitor

HPF AND OFFSET EFFECTS

Figure 24 shows the effect of offsets on the real power calcula­tion. As can be seen, an offset on the current channel and
voltage channel contribute a dc component after multiplication.
Since this dc component is extracted by the LPF and is used to
generate the real power information for each phase, the offsets
will have contributed a constant error to the total real power
calculation. This problem is easily avoided by the HPF in the
current channels. By removing the offset from at least one
channel, no error component can be generated at dc by the
multiplication. Error terms at cos(ωt) are removed by the LPF
and the digital-to-frequency conversion. See the Digital-to­Frequency Conversion section.

()

{}

IV

×

2

IV

×

+

2

()

2cos

t

ω×

()

{}

coscos

ItIVtV

=+ω×+ω

OSOS

() ()

coscos

tVItIVIV

OSOSOSOS

ω×+ω×+×+

0.04

0.03

0.02

PHASE (Degrees)

0.01

0

–0.01

100 300 500 700 900

0 1000200 400 600 800

FREQUENCY (Hz)

02676-A-025

Figure 25. Phase Error between Channels (0 Hz to 1 kHz)

0.010

0.008

0.006

0.004

0.002

PHASE (Degrees)

0

–0.002

–0.004

40 7045 50

55 60 65

FREQUENCY (Hz)

02676-A-026

Figure 26. Phase Error bet ween Channels (40 Hz to 70 Hz)

Rev. B | Page 17 of 24

ADE7752

DIGITAL-TO-FREQUENCY CONVERSION

As previously described, after multiplication the digital output
of the low-pass filter contains the real power information of
each phase. However since this LPF is not an ideal “brick wall”
filter implementation, the output signal also contains attenuated
components at the line frequency and its harmonics, i.e.,
cos(hωt), where h = 1, 2, 3, …

The magnitude response of the filter is given by

()

||

Where the –3 dB cutoff frequency of the low-pass filter is 8 Hz.
For a line frequency of 50 Hz, this would give an attenuation of
the 2ω (100 Hz) component of approximately –22 dB. The dom­inating harmonic will be twice the line frequency, i.e., cos(2ωt),
due to the instantaneous power signal. F shows the
instantaneous real power signal at the output of the CF, which
still contains a significant amount of instantaneous power infor­mation, i.e., cos (2

This signal is then passed to the digital-to-frequency converter
where it is integrated (accumulated) over time to produce an
output frequency. This accumulation of the signal will suppress
or average out any non-dc component in the instantaneous real

1

=ffH (8)

1

2





+





8





igure 27

ωt).

power signal. The average value of a sinusoidal signal is zero.
Thus, the frequency generated by the ADE7752 is proportional
to the average real power. F shows the digital-to-

igure 27
frequency conversion for steady load conditions, i.e., constant
voltage and current.

As can be seen in the diagram, the frequency output CF varies
over time, even under steady load conditions. This frequency
variation is primarily due to the cos(2ωt) components in the
instantaneous real power signal. The output frequency on CF
can be up to 160 times higher than the frequency on F1 and F2.
The higher output frequency is generated by accumulating the
instantaneous real power signal over a much shorter time, while
converting it to a frequency. This shorter accumulation period
means less averaging of the cos(2ωt) component. As a conse­quence, some of this instantaneous power signal passes through
the digital-to-frequency conversion. This will not be a problem
in the application. Where CF is used for calibration purposes,
the frequency should be averaged by the frequency counter.
This will remove any ripple. If CF is being used to measure
energy, e.g., in a microprocessor based application, the CF
output should also be averaged to calculate power. Because the
outputs F1 and F2 operate at a much lower frequency, much
more averaging of the instantaneous real power signal is carried
out. The result is a greatly attenuated sinusoidal content and a
virtually ripple-free frequency output.

MULTIPLIER

MULTIPLIER

MULTIPLIER

VA

VB

VC

ABS

LPF

|X|

IA

LPF

|X|

IB

LPF

|X|

IC

Figure 27. Real Power-to-Frequency Conversion

Σ

LPF TO EXTRACT

REAL POWER

(DC TERM)

DIGITAL-TO-

FREQUENCY

Σ

DIGITAL-TO-

FREQUENCY

Σ

V× I

2

0

INSTANTANEOUS REAL POWER SIGNAL

F1

F1
F2

FREQUENCY

TIME

CF

CF

FREQUENCY

TIME

cos(2ωt)

ATTENUATED BY LPF

ω

FREQUENCY – RAD/S

(FREQUENCY DOMAIN)

2ω

02676-A-027

Rev. B | Page 18 of 24

ADE7752

MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES

The ADE7752 can be configured to execute the arithmetic sum
of the three active energies, Wh = Wh
sum of the absolute value of these energies, Wh = |Wh

| + |WhϕC| The selection between the two modes can be

|Wh

ϕB

made by setting the
on the

pin correspond to the arithmetic sum and the sum

ABS

pin. Logic high and logic low applied

ABS

of absolute values, respectively.

When the sum of the absolute values is selected, the active
energy from each phase is always counted positive in the total
active energy. It is particularly useful in 3-phase 4-wire installa­tion where the sign of the active power should always be the
same. If the meter is misconnected to the power lines, i.e., CT
connected in the wrong direction, the total active energy
recorded without this solution can be reduced by two-thirds.

+ WhϕB + WhϕC, or the

ϕA

| +

ϕA

The sum of the absolute values assures that the active energy
recorded represents the actual active energy delivered. In this
mode, the reverse power pin still detects when negative power is
present on any of the three phase inputs.

POWER MEASUREMENT CONSIDERATIONS

Calculating and displaying power information will always have
some associated ripple that will depend on the integration
period used in the MCU to determine average power as well as
the load. For example, at light loads, the output frequency may
be 10 Hz. With an integration period of 2 seconds, only about
20 pulses will be counted. The possibility of missing one pulse
always exists since the ADE7752 output frequency is running
asynchronously to the MCU timer. This would result in a 1-in­20 or 5% error in the power measurement.

Rev. B | Page 19 of 24

ADE7752

(

)

×

=

×

TRANSFER FUNCTION

FREQUENCY OUTPUTS F1 AND F2

The ADE7752 calculates the product of six voltage signals (on
current channel and voltage channel) and then low-pass filters
this product to extract real power information. This real power
information is then converted to a frequency. The frequency
information is output on F1 and F2 in the form of active high
pulses. The pulse rate at these outputs is relatively low, e.g.,

29.32 Hz maximum for ac signals with SCF = 1; S0 = S1 = 1.
(See Table 6.) This means that the frequency at these outputs is
generated from real power information accumulated over a
relatively long period of time. The result is an output frequency
that is proportional to the average real power. The averaging of
the real power signal is implicit to the digital-to-frequency
conversion. The output frequency or pulse rate is related to the
input voltage signals by the following equation:

Freq

922.5

=

AAN

BBN

2

V

REF

where:

Freq = Output frequency on F1 and F2 (Hz)
V

and VCN = Differential rms voltage signal on voltage

AN, VBN,

channels (Volts)

and IC = Differential rms voltage signal on current

I

A, IB,

channels (Volts)

= The reference voltage (2.4 V ± 8%) (Volts)

V

REF

= One of seven possible frequencies selected by using the

F

1–7

logic inputs SCF, S0, and S1. See Table 5.

Table 5. F

SCF S1 S0 F

Frequency Selection1

1–7

1–7

(Hz)

0 0 0 1.27
1 0 0 1.19
0 0 1 5.09
1 0 1 4.77
0 1 0 19.07
1 1 0 19.07
0 1 1 76.29
1 1 1 0.60

1

F

is a fraction of the master clock and therefore will vary if the specified

1–7

CLKIN frequency is altered.

Example 1

Thus, if full-scale differential dc voltages of +500 mV are
applied to VA, VB, VC, IA, IB, and IC, respectively (500 mV is
the maximum differential voltage that can be connected to
current and voltage channels), the expected output frequency is
calculated as follows:

FIVIVIV

××+×+××

−

CCN

71

F

= 0.60 Hz, SCF = S0 = S1 = 1

1–7

= VBN = VCN = IA = IB = IC

V

AN

= 500 mV dc = 0.5 V(rms of dc = dc)

= 2.4 V (nominal reference value)

V

REF

Note that if the on-chip reference is used, actual output fre­quencies may vary from device to device due to reference
tolerance of ±8%.

××

60.05.05.0922.5

×=

3

2

4.2

=

HzFreq 462.0

Example 2

In this example, with ac voltages of ±500 mV peak applied to
the voltage channels and current channels, the expected output
frequency is calculated as follows:

SSSCFHzF

110,60.0

−

AN

REF

71

BN

CN

500

()

4.2

=

===

ICIBIAVVV

=====

5.0

==

2

VrmsACpeakmV

valuereferencenominalVV

Note that if the on-chip reference is used, actual output fre­quencies may vary from device to device due to reference
tolerance of ±8%.

596.05.05.0922.5

×=

3

××

2

4.222

××

HzFreq 23.0

=

As can be seen from these two example calculations, the
maximum output frequency for ac inputs is always half of that
for dc input signals. The maximum frequency also depends on
the number of phases connected to the ADE7752. In a 3-phase
3-wire Delta service, the maximum output frequency is
different from the maximum output frequency in a 3-phase
4-wire Wye service. The reason is that there are only two phases
connected to the analog inputs, but also that in a Delta service,
the current channel input and voltage channel input of the same
phase are not in phase in normal operation.

Example 3

In this example, the ADE7752 is connected to a 3-phase 3-wire
Delta service as shown in F . The total real energy

igure 21
calculation processed in the ADE7752 can be expressed as

Total Re a l P o w e r = (V

Where V

, VB, and VC represent the voltage on phase A, B, and

A

C, respectively. I

and IB represent the current on phase A and B,

A

– VC) × IA + (VB – VC) × IB

A

respectively.

Rev. B | Page 20 of 24

ADE7752

()()(

)

z

As the voltage and current inputs respect Equations 5 and 6, the
total real power (P) is

()











A

A

B

B

()

l

cos2

tI

ω×××

()

l



cos2






cos2

tI



l



cos2cos2

C

2

π



+ω××+



l

3



2

π



+ω×××



3



−×−+−−=

IBNIBPVCVBIANIAPVCVAP

π

4







C



+ω××−ω××=

tVtVP

l





3





4



cos2




π



tVvtV

+ω××−



l

3



For simplification, we assume that ϕA = ϕB = ϕC = 0 and

= VB = VC = V. The preceding equation becomes:

V

A

2

π





sin2

×××=

A

sin2

×××+

B

sin





3





π







()



3



2

π







()

cos

ttIVP

+ω×

3

ω×




cossin

ll

(9)

π

2







+ω×π+ω×

ttIV



ll

3



P then becomes:

π

2





××=

sin





A

××+

B

3





π





sin





3









2sin













2sin









π

2





+ω+

tIVANP





l

3





(10)

π





+ω+

tIVBN





l

3





where VA N = V × sin(2π/3) and VBN = V × sin(π/3).

As the LPF on each channel eliminates the 2

ω

component of

l

the equation, the real power measured by the ADE7752 is

3

AAN

2

3

××+××=

IVIVP

BBN

2

If full-scale ac voltage of ±500 mV peak is applied to the voltage
channels and current channels, the expected output frequency is
calculated as follows:

110,60.0

SSSCFH

F

71

−

BN

AN

ICV

0

CN

REF

==

4.2

=

====

500

5.0

======

rmsVacpeakVmICIBIAVV

2

value referencenominal VV

Note that if the on-chip reference is used, actual output fre­quencies may vary from device to device due to reference
tolerance of ±8%.

2

×=

Table 6

shows a complete listing of all maximum output fre-

×××

2

4.222

××

quencies when using all three channel inputs.

Table 6. Maximum Output Frequency on F1 and F2






SCF S1 S0

0 0 0 0.49 0.98
1 0 0 0.46 0.91
0 0 1 1.95 3.91
1 0 1 1.83 3.67
0 1 0 7.33 14.66
1 1 0 7.33 14.66
0 1 1 29.32 58.65
1 1 1 0.23 0.46

Max Frequency for
AC Inputs (Hz)

FREQUENCY OUTPUT CF

The pulse output CF (calibration frequency) is intended for use
during calibration. The output pulse rate on CF can be up to
160 times the pulse rate on F1 and F2. The lower the F
quency selected, the higher the CF scaling. shows how
the two frequencies are related, depending on the states of the
logic inputs S0, S1, and SCF. Because of its relatively high pulse
rate, the frequency at this logic output is proportional to the
instantaneous real power. As is the case with F1 and F2, the
frequency is derived from the output of the low-pass filter after
multiplication. However, because the output frequency is high,
this real power information is accumulated over a much shorter
time. Thus, less averaging is carried out in the digital-to­frequency conversion. With much less averaging of the real
power signal, the CF output is much more responsive to power
fluctuations. See Figure 15.

Table 7. Maximum Output Frequency on CF

SCF S1 S0 F

0 0 0 1.27 160 × F1, F2 = 78.19
1 0 0 1.19 8 × F1, F2 = 3.66
0 0 1 5.09 160 × F1, F2 = 312.77
1 0 1 4.77 16 × F1, F2 = 29.32
0 1 0 19.07 16 × F1, F2 = 117.3
1 1 0 19.07 8 × F1, F2 = 58.65
0 1 1 76.29 8 × F1, F2 = 234.59
1 1 1 0.60 16 × F1, F2 = 3.67

(Hz) CF Max for AC Signals (Hz)

1–7

3

60.05.05.0922.5

=×

2

Max Frequency for
DC Inputs (Hz)

Table 7

HzFreq 134.0

fre-

1–7

Rev. B | Page 21 of 24

ADE7752

SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION

As shown in , the user can select one of seven frequen-

Table 5
cies. This frequency selection determines the maximum
frequency on F1 and F2. These outputs are intended to be used
to drive the energy register (electromechanical or other). Since
only seven different output frequencies can be selected, the
available frequency selection has been optimized for a 3-phase
4-wire service with a meter constant of 100 imp/kWhr and a
maximum current of between 10 A and 100 A. T shows
the output frequency for several maximum currents (I

able 8

MAX

) with
a line voltage of 220 V (phase neutral). In all cases, the meter
constant is 100 imp/kWhr

Table 8. V. F1 and F2 Frequency at 100 imp/kWhr

I

(A) F1 and F2 (Hz)

MAX

10 0.10
25 0.25
40 0.40
60 0.60
80 0.80
100 1.00

The F

frequencies allow complete coverage of this range of

1–7

output frequencies on F1 and F2. When designing an energy
meter, the nominal design voltage on the voltage channels
should be set to half scale to allow for calibration of the meter
constant. The current channel should also be no more than half
scale when the meter sees maximum load. This will allow
overcurrent signals and signals with high crest factors to be
accommodated. shows the output frequency on F1 and

Table 9

F2 when all six analog inputs are half scale.

Table 9. F1 and F2 Frequency with Half-Scale AC Inputs

Frequency on F1 and F2

SCF S1 S0 F

0 0 0 1.27 0.24
1 0 0 1.19 0.23
0 0 1 5.09 0.98
1 0 1 4.77 0.92
0 1 0 19.07 3.67
1 1 0 19.07 3.67
0 1 1 76.29 14.66
1 1 1 0.60 0.11

1–7

(Half-Scale AC Inputs)

When selecting a suitable F
frequency output at I

(maximum load) with a 100 imp/kWhr

MAX

meter constant should be compared with Column 5 of T
The frequency that is closest in will determine the best
choice of frequency (F

). For example, if a 3-phase 4-wire Wye

1–7

meter with a 25 A maximum current is being designed, the
output frequency on F1 and F2 with a 100 imp/kWhr meter
constant is 0.25 Hz at 25 A and 220 V (from ). Looking at
Table 9

, the closest frequency to 0.25 Hz in Column 5 is 0.24 Hz.

Therefore, F

= 1.27 Hz is selected for this design.

1–7

FREQUENCY OUTPUTS

Figure 2 shows a timing diagram for the various frequency
outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or electro­mechanical impulse counter. The F1 and F2 outputs provide
two alternating high going pulses. The pulse width (t
275 ms, and the time between the rising edges of F1 and F2 (t
is approximately half the period of F1 (t
period of F1 and F2 falls below 550 ms (1.81 Hz), the pulse
width of F1 and F2 is set to half of their period. The maximum
output frequencies for F1 and F2 are shown in . Table 6

The high frequency CF output is intended to be used for com­munications and calibration purposes. CF produces a 96 ms­wide active high pulse (t
power. The CF output frequencies are given in Table 7. As in the
case of F1 and F2, if the period of CF (t
CF pulse width is set to half the period. For example, if the CF
frequency is 20 Hz, the CF pulse width is 25 ms. One exception
to this is when the mode is S0 = 1, SCF = S1 = 0. In this case, the
CF pulse width is 66% of the period.

) at a frequency proportional to active

4

frequency for a meter design, the

1–7

able 9

Table 9

Table 8

) is set at

1

). If, however, the

2

) falls below 192 ms, the

5

)

3

Rev. B | Page 22 of 24

ADE7752

NO LOAD THRESHOLD

The ADE7752 also includes no load threshold and start-up cur­rent features that eliminate any creep effects in the meter. The
ADE7752 is designed to issue a minimum output frequency.
Any load generating a frequency lower than this minimum fre­quency will not cause a pulse to be issued on F1, F2, or CF. The
minimum output frequency is given as 0.005% of the full-scale
output frequency for each of the F
approximately 0.00204% of the F
For example, for an energy meter with a 100 imp/kWhr meter
constant using F
F1 or F2 would be 9.15 × 10

(4.77 Hz), the minimum output frequency at

1–7

–5

at CF (16 × F1 Hz). In this example, the no load threshold
would be equivalent to 3.3 W of load or a start-up current of

13.75 mA at 240 V.

Table 10. CF, F1, and F2 Minimum Frequency at No Load
Threshold

SCF S1 S0 F1, F2 Min (mHz) CF Min (mHz)

0 0 0 2.44 × 10–5 3.91 × 10–3
1 0 0 2.29 × 10–5 1.83 × 10–4
0 0 1 9.77 × 10–5 1.56 × 10–2
1 0 1 9.16 × 10–5 1.47 × 10–3
0 1 0 3.67 × 10–4 5.86 × 10–3
1 1 0 3.67 × 10–4 2.93 × 10–3
0 1 1 1.47 × 10–3 1.17 × 10–2
1 1 1 1.15 × 10–5 1.83 × 10–4

frequency selections or

1–7

frequency (see ).

1–7

Table 10

Hz. This would be 1.46 × 10–6 Hz

NEGATIVE POWER INFORMATION

The ADE7752 detects when the current and voltage channels of
any of the three phase inputs have a phase difference greater
than 90°, i.e., ϕ
wrong connection of the meter or generation of active energy.
The NEGP pin output will go active high when negative power
is detected on any of the three phase inputs. If positive active
energy is detected on all the three phases, NEGP pin output is
low. The NEGP pin output changes state at the same time as a
pulse is issued on CF. If several phases measure negative power,
the NEGP pin output will stay high until all the phases measure
positive power. If a phase has gone below the NO LOAD
threshold, NEGP detection on this phase is disabled. NEGP
detection on this phase resumes when the power returns out of
NO LOAD condition. See the No Load Threshold section.

or ϕB or ϕC > 90°. This mechanism can detect

A

Rev. B | Page 23 of 24

ADE7752

Y

OUTLINE DIMENSIONS

15.60 (0.6142)

15.20 (0.5984)

24 13

1

0.30 (0.0118)

0.10 (0.0039)

COPLANARIT

0.10

1.27 (0.0500)
BSC

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-013AD

0.51 (0.020)

0.31 (0.012)

7.60 (0.2992)

7.40 (0.2913)

12

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

×

45°

1.27 (0.0500)

0.40 (0.0157)

Figure 28. 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Package Description Package Option

ADE7752AR SOIC Package RW-24
ADE7752ARRL SOIC Package RW-24 on 13" Reels
EVAL-ADE7752EB ADE7752 Evaluation Board

1

RW = Small Outline Wide Body Package in Tubes

1

© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

C02676–0–9/03(B)

Rev. B | Page 24 of 24