ANALOG DEVICES ADE7518 Service Manual

Single-Phase Energy Measurement IC with

GENERAL FEATURES

Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes

Full operation: 4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.2 mA to 400 μA (PLL clock dependent)
Sleep mode

Real-time clock (RTC) mode: 1.5 μA

RTC and LCD mode: 27 μA
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead RoHS package option

Low profile quad flat package (LQFP)

Operating temperature range: −40°C to +85°C

ENERGY MEASUREMENT FEATURES

Proprietary analog-to-digital converters (ADCs) and digital

signal processing (DSP) provide high accuracy active
(WATT), reactive (VAR), and apparent energy (VA)
measurement
Less than 0.1% error on active energy over a dynamic

range of 1000 to 1 @ 25°C

Less than 0.5% error on reactive energy over a dynamic

range of 1000 to 1 @ 25°C

Less than 0.5% error on root mean square (rms)

measurements over a dynamic range of 500 to 1 for

current (I

Supports IEC 62053-21, IEC 62053-22, IEC 62053-23,

EN 50470-3 Class A, Class B, and Class C, and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)

supports shunts and current transformers

High frequency outputs proportional to I

or apparent power (AP)

) and 100 to 1 for voltage (V

rms

) @ 25°C

rms

, active, reactive,

rms

8052 MCU, RTC, and LCD Driver

ADE7518

MICROPROCESSOR FEATURES

8052-based core

Single-cycle 4 MIPS 8052 core
8052-compatible instruction set

32.768 kHz external crystal with on-chip PLL
Two external interrupt sources
External reset pin

Low power battery mode

Wake-up from I/O, alarm, and universal asynchronous

receiver/transmitter (UART)

LCD driver operation

Real-time clock

Counter for seconds, minutes, and hours
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.5 μA
Selectable output frequency: 1 Hz to 16.384 kHz
Embedded digital crystal frequency compensation for

calibration and temperature variation: 2 ppm resolution

Integrated LCD driver

108-segment driver
2×, 3×, or 4× multiplexing
LCD voltages generated with external resistors

On-chip peripherals

UART, SPI or I
Power supply management with user-selectable levels
Memory: 16 kB flash memory, 512 bytes RAM
Development tools

Single-pin emulation

IDE-based assembly and C-source debugging

2

C, and watchdog timer

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009 Analog Devices, Inc. All rights reserved.

ADE7518

TABLE OF CONTENTS

General Features ............................................................................... 1

Energy Measurement Features ........................................................ 1

Microprocessor Features .................................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Energy Metering ........................................................................... 5

Analog Peripherals ....................................................................... 6

Digital Interface ............................................................................ 7

Timing Specifications .................................................................. 9

Absolute Maximum Ratings .......................................................... 14

Thermal Resistance .................................................................... 14

ESD Caution ................................................................................ 14

Pin Configuration and Function Descriptions ........................... 15

Typical Performance Characteristics ........................................... 17

Terminology .................................................................................... 20

SFR Mapping ................................................................................... 21

Power Management ........................................................................ 22

Power Management Register Details ....................................... 22

Power Supply Architecture ........................................................ 25

Battery Switchover ...................................................................... 25

Power Supply Management (PSM) Interrupt ......................... 26

Using the Power Supply Features ............................................. 28

Operating Modes ............................................................................ 30

PSM0 (Normal Mode) ............................................................... 30

PSM1 (Battery Mode) ................................................................ 30

PSM2 (Sleep Mode) .................................................................... 30

3.3 V Peripherals and Wake-Up Events ................................... 31

Transitioning Between Operating Modes ............................... 32

Using the Power Management Features .................................. 32

Energy Measurement ..................................................................... 33

Access to Energy Measurement SFRs ...................................... 33

Access to Internal Energy Measurement Registers ................ 33

Energy Measurement Registers ................................................ 35

Energy Measurement Internal Registers Details .................... 36

Interrupt Status/Enable SFRs .................................................... 38

Analog Inputs .............................................................................. 40

Analog-to-Digital Conversion .................................................. 41

Power Quality Measurements ................................................... 44

Phase Compensation ................................................................. 46

RMS Calculation ........................................................................ 46

Active Power Calculation .......................................................... 48

Active Energy Calculation ........................................................ 50

Reactive Power Calculation ...................................................... 53

Reactive Energy Calculation ..................................................... 54

Apparent Power Calculation ..................................................... 58

Apparent Energy Calculation ................................................... 59

Ampere-Hour Accumulation ................................................... 60

Energy-to-Frequency Conversion............................................ 61

Energy Register Scaling ............................................................. 62

Energy Measurement Interrupts .............................................. 62

8052 MCU CORE Architecture .................................................... 63

MCU Registers ............................................................................ 63

Basic 8052 Registers ................................................................... 65

Standard 8052 SFRs .................................................................... 66

Memory Overview ..................................................................... 66

Addressing Modes ...................................................................... 67

Instruction Set ............................................................................ 69

Read-Modify-Write Instructions ............................................. 71

Instructions That Affect Flags .................................................. 71

Dual Data Pointers ......................................................................... 73

Interrupt System ............................................................................. 74

Standard 8052 Interrupt Architecture ..................................... 74

Interrupt Architecture ............................................................... 74

Interrupt Registers...................................................................... 74

Interrupt Priority ........................................................................ 75

Interrupt Flags ............................................................................ 76

Interrupt Vectors ........................................................................ 78

Interrupt Latency ........................................................................ 78

Context Saving ............................................................................ 78

Watchdog Timer ............................................................................. 79

LCD Driver ...................................................................................... 81

LCD Registers ............................................................................. 81

LCD Setup ................................................................................... 84

LCD Timing and Waveforms .................................................... 84

Blink Mode .................................................................................. 85

Display Element Control ........................................................... 85

LCD External Circuitry ............................................................. 86

LCD Function in PSM2 ............................................................. 86

Rev. 0 | Page 2 of 128

ADE7518

Flash Memory .................................................................................. 87

Overview ...................................................................................... 87

Flash Memory Organization ...................................................... 88

Using the Flash Memory ............................................................ 88

Protecting the Flash Memory .................................................... 91

In-Circuit Programming ............................................................ 92

Timers ............................................................................................... 93

Timer Registers ............................................................................ 93

Timer 0 and Timer 1 ................................................................... 95

Timer 2 ......................................................................................... 96

PLL .................................................................................................... 98

PLL Registers ............................................................................... 98

Real-Time Clock ........................................................................... 100

RTC Registers ........................................................................... 100

Read and Write Operations .................................................... 103

RTC Modes ............................................................................... 103

RTC Interrupts ......................................................................... 103

RTC Calibration ....................................................................... 104

UART Serial Interface .................................................................. 105

UART Registers ........................................................................ 105

UART Operation Modes ......................................................... 108

UART Baud Rate Generation ................................................. 109

UART Additional Features ...................................................... 111

Serial Peripheral Interface (SPI) .................................................. 112

SPI Registers .............................................................................. 112

SPI Pins ....................................................................................... 115

SPI Master Operating Modes .................................................. 116

SPI Interrupt and Status Flags ................................................. 117

I2C-Compatible Interface ............................................................. 118

Serial Clock Generation ........................................................... 118

Slave Addresses .......................................................................... 118

I2C Registers ............................................................................... 118

Read and Write Operations ..................................................... 119

I2C Receive and Transmit FIFOs ............................................. 120

I/O Ports ......................................................................................... 121

Parallel I/O ................................................................................. 121

I/O Registers .............................................................................. 122

Port 0 ........................................................................................... 125

Port 1 ........................................................................................... 125

Port 2 ........................................................................................... 125

Determining the Version of the ADE7518 ................................ 126

Outline Dimensions ...................................................................... 127

Ordering Guide ......................................................................... 127

REVISION HISTORY

1/09—Revision 0: Initial Version

Rev. 0 | Page 3 of 128

ADE7518

A

)

GENERAL DESCRIPTION

The ADE75181 integrates the Analog Devices, Inc., energy
(ADE) metering IC analog front end and fixed function DSP
solution with an enhanced 8052 MCU core, an RTC, an LCD
driver, and all the peripherals to make an electronic energy
meter with an LCD display in a single part.

The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure­ments. This information is ready to use for energy billing by using
built-in energy scalars. Many power line supervisory features,
such as SAG, peak, and zero crossing, are included in the energy
measurement DSP to simplify energy meter design.

The microprocessor functionality includes a single-cycle 8052 core,
a real-time clock with a power supply backup pin, a UART, and an

2

SPI or I

C® interface. The ready-to-use information from the
ADE core reduces the program memory size requirement, making
it easy to integrate complicated design into 16 kB of flash
memory.

The ADE7518 also includes a 108-segment LCD driver. This
driver generates waveforms capable of driving LCDs up to 3.3 V.

DGND

GND

V

BAT

FUNCTIONAL BLOCK DIAGRAM

A

K
L
C

S

S

S

SPI/I2C

SERIAL

USER RAM

256 BYTES

USER XRAM

256 BYTES

LDO

62

D
T
N

I

V

O
S

I
M

T
A
D
S

/

I
S
O
M

LDO

59

1

T0T

T2T

3 × 16-BIT
COUNTER

TIMERS

POR

A
T
N

I

V

56

X
E
2

SINGLE

CYCLE

T
E
S
E
R

8052
MCU

T
U
O

/
N

I

F
E
R

57

1.20V
REF

+

52

I

P

PGA1

–

53

I

N

+

49

V

P

PGA2

–

50

V

N

63

54

58

ADC

ADC

POWER SUPPLY

CONTROL AND

MONIT ORING

64

60

N
I

C
D

V

2

1

F

F
C

C

43 42 39 38 7 6 45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 1038 39 40 41

INTERFACE

ENERGY

MEASUREMENT

DSP

PROGRAM MEMORY

16kB FLASH

61

D
D

V

T
U
O

W
S

V

)
1
T

N

I

/
L
R
T
C
B

(
0

.
0
P

1-PIN

EMULATOR

51

EA

)
L
A
C
C
T

)

R

/

)

9

1

2

1

F

F

P
F

C

C

(

(

(

2

1

3

.

.

.

0

0

0

P

P

P

DOWNLOADER

DEBUGGER

UART

TIMER

44

N
E
D
S

A
T
A

)
0

D

T

S

/

)

/

I

K

O

S

L

S

I

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C
S

M

M

(

(

(

5

6

4

.

.

.

0

0

0

P

P

P

WATCHDOG

TIMER

UART

SERIAL

PORT

36

D
x
T

)
1
T

/
S
S

(
7

.
0
P

37

D
x

R

)
4
2
P
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/

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5

X

2

D

D

E

x

x

P

2

R

T

F

T

(

(

(

(

0

3

1

2

.

.

.

.

1

1

1

1

P

P

P

P

ADE7518

LCD

LEVELS

108-SEGMENT

LCD DRIVER

RTC

)
3
2

)

P

2

F

2

/
2

P

T

F

(

(

4

5

.

.

1

1

P

P

PLL

OSC

4647 48 45

1
L
A
T
X

)

)

1

0

2

2

P

P

F

F

(

(

6

7

.

.

1

1

P

P

P2.0 (FP18)

12

P2.1 (FP17)

13

P2.2 (FP16)

14

P2.3 (SDEN)

44

19

LCDVP1

16

LCDVP2

18

LCDVA

17

LCDVB

15

LCDVC

4

COM0

.
.

...

.

COM3

1

FP0

35

.
.

...

.

20

FP15

FP16

14

13

FP17

12

FP18

FP19

11

10

FP20

FP21

9

8

FP22

FP23

7

6

FP24

5

FP25

55

FP26

2

1

0

L

T

T

A

N

N

I

I

T
X

07327-001

Figure 1.

1

Patents pending.

Rev. 0 | Page 4 of 128

ADE7518

SPECIFICATIONS

VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTAL = 32.768 kHz, T

ENERGY METERING

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

MEASUREMENT ACCURACY1

Phase Error Between Channels

PF = 0.8 Capacitive ±0.05 Degrees 37° phase lead
PF = 0.5 Inductive ±0.05 Degrees 60° phase lag

Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 @ 25°C

AC Power Supply Rejection2 V

Output Frequency Variation 0.01 % IP = VP = ±100 mV rms

DC Power Supply Rejection2 V

Output Frequency Variation 0.01 %
Active Energy Measurement Bandwidth1 8 kHz
Reactive Energy Measurement Error2 0.5 % of reading Over a dynamic range of 1000 to 1 @ 25°C
V

Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 @ 25°C

rms

V

Measurement Bandwidth1 3.9 kHz

rms

I

Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 @ 25°C

rms

I

Measurement Bandwidth1 3.9 kHz

rms

ANALOG INPUTS

Maximum Signal Levels ±400 mV peak VP − VN differential input

±400 mV peak IP − IN differential input
Input Impedance (DC) 770 kΩ
ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1

±1 mV PGA1 = 16

Gain Error2

Current Channel −3 + 3 % IP = 0.4 V dc or IP = 0.4 dc

Voltage Channel −3 + 3 % Voltage channel = 0.4 V dc
Gain Error Match ±0.2 %

CF1 AND CF2 PULSE OUTPUT

Maximum Output Frequency 13.5 kHz

Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz
Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz

1

These specifications are not production tested but are guaranteed by design and/or characterization data on production release.

2

See the Terminology section for definition.

MIN

to T

= −40°C to +85°C, unless otherwise noted.

MAX

= 3.3 V + 100 mV rms/120 Hz

DD

= 3.3 V ± 117 mV dc

DD

− VN = 400 mV peak, IP − IN = 250 mV,

V

P

PGA1 = 2 sine wave

Rev. 0 | Page 5 of 128

ADE7518

ANALOG PERIPHERALS

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER-ON RESET (POR)

VDD POR

Detection Threshold 2.5 2.95 V
POR Active Timeout Period 33 ms

V

POR

SWOUT

Detection Threshold 1.8 2.2 V
POR Active Timeout Period 20 ms

V

POR

INTD

Detection Threshold 2.03 2.22 V
POR Active Timeout Period 16 ms

V

POR

INTA

Detection Threshold 2.05 2.15 V
POR Active Timeout Period 120 ms

BATTERY SWITCHOVER

Voltage Operating Range (V
VDD to V

Switching

BAT

Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 10 ns When VDD to V
30 ms When VDD to V

V

to VDD Switching

BAT

Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 30 ms Based on VDD > 2.75 V

V

To V

SWOUT

Leakage Current 10 nA V

BAT

LCD, RESISTOR LADDER ACTIVE

Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA

ON-CHIP REFERENCE

Reference Error ±0.9 mV TA = 25°C
Power Supply Rejection 80 dB
Temperature Coefficient 10 50 ppm/°C

) 2.4 3.7 V

SWOUT

= 0 V, V

BAT

switch activated by VDD

BAT

switch activated by V

BAT

= 3.43 V, TA = 25°C

SWOUT

DCIN

Rev. 0 | Page 6 of 128

ADE7518

DIGITAL INTERFACE

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

All Inputs Except XTAL1, XTAL2, BCTRL,

, INT1, RESET

INT0

Input High Voltage, V

Input Low Voltage, V

2.0 V

INH

0.4 V

INL

BCTRL, INT0, INT1, RESET

Input High Voltage, V

Input Low Voltage, V

1.3 V

INH

0.4 V

INL

Input Currents

RESET

Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or V

−3.75 −8.5 μA Internal pull-up enabled, input = 0 V, V
Input Capacitance 10 pF All digital inputs

FLASH MEMORY

Endurance1 10,000 Cycles
Data Retention2 20 Years TJ = 85°C

CRYSTAL OSCILLATOR

Crystal Equivalent Series Resistance 30 50 kΩ
Crystal Frequency 32 32.768 33.5 kHz
XTAL1 Input Capacitance 12 pF
XTAL2 Output Capacitance 12 pF

MCU CLOCK RATE (f

) 4.096 MHz Crystal = 32.768 kHz and CD[2:0] = 0b000

CORE

32 kHz Crystal = 32.768 kHz and CD[2:0] = 0b111
LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%

I

80 μA

SOURCE

Output Low Voltage, V

I

2 mA

SINK

3

0.4 V VDD = 3.3 V ± 5%

OL

START-UP TIME4

PSM0 Power-On Time 448 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 1 (PSM1)

PSM1 → PSM0

From Power Saving Mode 2 (PSM2)

PSM2 → PSM1
PSM2 → PSM0

POWER SUPPLY INPUTS

VDD 3.13 3.3 3.46 V
V

2.4 3.3 3.7 V

BAT

INTERNAL POWER SUPPLY SWITCH (V

V

to V

BAT

VDD to V
V

←→ VDD Switching Open Time

BAT

On Resistance 22 Ω V

SWOUT

On Resistance 10.2 Ω VDD = 3.13 V

SWOUT

SWOUT

BCTRL State Change and Switch Delay 18 μs
V

Output Current Drive 1 6 mA

SWOUT

POWER SUPPLY OUTPUTS

V

2.25 2.75 V

INTA

V

2.3 2.70 V

INTD

V

Power Supply Rejection 60 dB

INTA

V

Power Supply Rejection 50 dB

INTD

100 nA

RESET = V

130 ms V

48

ms Wake-up event to PSM1 code execution

186 ms V

at 2.75 V to PSM0 code execution

DD

at 2.75 V to PSM0 code execution

DD

)

= 2.4 V

BAT

40 ns

SWOUT

= 3.3 V

SWOUT

SWOUT

= 3.3 V

Rev. 0 | Page 7 of 128

ADE7518

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY CURRENTS

Current in Normal Mode (PSM0) 4 5.3 mA f

2.1 mA f

1.6 mA f

3.2 4.25 mA

3 3.9 mA

Current in PSM1 3.2 5.05 mA f
880 μA f
Current in PSM2 38 μA LCD active at 3.3 V + RTC (real-time clock)

1.5 μA RTC only, TA = 25°C, V

POWER SUPPLY CURRENTS

Current in Normal Mode (PSM0) 4 5.3 mA f

1

Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

2

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

3

Test performed with all the I/Os set to a low output level.

4

Delay between power supply valid and execution of first instruction by 8052 core.

= 4.096 MHz, LCD and meter active

CORE

= 1.024 MHz, LCD and meter active

CORE

= 32.768 kHz, LCD and meter active

CORE

= 4.096 MHz, meter DSP active, metering ADC

f

CORE

powered down

= 4.096 MHz, metering ADC and DSP powered

f

CORE

down

= 4.096 MHz, LCD active, V

CORE

= 1.024 MHz, LCD active

CORE

= 3.3 V

BAT

= 4.096 MHz, LCD and meter active

CORE

= 3.7 V

BAT

Rev. 0 | Page 8 of 128

ADE7518

V

–

V

TIMING SPECIFICATIONS

AC inputs during testing were driven at V
and 0.45 V for Logic 0. Timing measurements were made at V
minimum for Logic 1 and V

maximum for Logic 0, as shown in

IL

Figure 2.

0.5

SWOUT

0.45V

Table 4. Clock Input (External Clock Driven XTAL1) Parameters

32.768 kHz External Crystal

Parameter Description Min Typ Max Unit

tCK XTAL1 period 30.52 μs
t

XTAL1 width low 6.26 μs

CKL

t

XTAL1 width high 6.26 μs

CKH

t

XTAL1 rise time 9 ns

CKR

t

XTAL1 fall time 9 ns

CKF

1/t

Core clock frequency1 0.032768 1.024 4.096 MHz

CORE

1

The ADE7518 internal PLL locks onto a multiple (512 times) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system.

The core can operate at this frequency or at a binary submultiple defined by the CD[2:0] bits, selected via the POWCON SFR (see Table 24).

− 0.5 V for Logic 1

SWOUT

0.2V

0.2V

+ 0.9V

SWOUT

TEST POINTS

– 0.1V

SWOUT

IH

Figure 2. Timing Waveform Characteristics

For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
float when a 100 mV change from the loaded V
occurs, as shown in Figure 2.

Fo r Ta bl e 4 t o Tabl e 9 , C

3.6 V, and all specifications T

– 0.1V

V

LOAD

V

LOAD

V

+ 0.1V

LOAD

TIMING

REFERENCE

POINTS

= 80 pF for all outputs, VDD = 2.7 V to

LOAD

to T

MIN

, unless otherwise noted.

MAX

– 0.1V

V

V

LOAD

LOAD

– 0.1V

V

LOAD

OH/VOL

07327-002

level

Table 5. I2C-Compatible Interface Timing Parameters (400 kHz)

Parameter Description Typ Uni t

t

Bus-free time between stop condition and start condition 1.3 μs

BUF

tL SCLK low pulse width 1.36 μs
tH SCLK high pulse width 1.14 μs
t

Start condition hold time 251.35 μs

SHD

t

Data setup time 740 ns

DSU

t

Data hold time 400 ns

DHD

t

Setup time for repeated start 12.5 ns

RSU

t

Stop condition setup time 400 ns

PSU

tR Rise time of both SCLK and SDATA 200 ns
tF Fall time of both SCLK and SDATA 300 ns

1

t

Pulse width of spike suppressed 50 ns

SUP

1

Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of less than 50 ns.

t

SDATA (I/O)

SCLK (I)

BUF

MSB

t

DSU

t

PSU

PS

STOP

CONDITI ON

START

CONDITI ON

t

SHD

1

t

DHD

2TO 7

Figure 3. I

2

C-Compatible Interface Timing

t

SUP

LSB ACK MSB

t

DSU

t

H

89 1

t

t

SUP

L

t

DHD

t

RSU

S(R)

REPEATED

START

t

R

t

F

t

R

t

F

7327-003

Rev. 0 | Page 9 of 128

ADE7518

Table 6. SPI Master Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2
tSH SCLK high pulse width 2
t

Data output valid after SCLK edge 3 × t

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

t

DAV

t

SH

t

SL

MSB

t

DF

SPIR

× t

SPIR

× t

1

CORE

= 2CD/4.096 MHz.

CORE

t

DR

BITS [6:1]

1

ns

CORE

1

ns

CORE

1

ns

CORE

ns

t

SR

t

SF

LSB

MISO

t

DSU

MSB IN

t

BITS [6:1]

DHD

LSB IN

07327-004

Figure 4. SPI Master Mode Timing (SPICPHA = 1)

Rev. 0 | Page 10 of 128

ADE7518

Table 7. SPI Master Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2
tSH SCLK high pulse width 2
t

Data output valid after SCLK edge 3 × t

DAV

t

Data output setup before SCLK edge 75 ns

DOSU

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

t

DOSU

MSB

t

SH

t

SL

t

DAV

t

DF

t

DR

BITS [6:1]

SPIR

× t

SPIR

× t

1

ns

CORE

= 2CD/4.096 MHz.

CORE

1

(SPIR + 1) × t

CORE

1

(SPIR + 1) × t

CORE

t

SR

LSB

1

ns

CORE

1

ns

CORE

t

SF

1

ns

CORE

MISO

t

DSU

MSB IN

BITS [6:1]

t

DHD

LSB IN

7327-005

Figure 5. SPI Master Mode Timing (SPICPHA = 0)

Rev. 0 | Page 11 of 128

ADE7518

Table 8. SPI Slave Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

tSS

to SCLK edge

SS
tSL SCLK low pulse width 6 × t
tSH SCLK high pulse width 6 × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
t

SFS

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t

CORE

high after SCLK edge

SS

CORE

SS

t

SS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

t

SH

t

SL

145 ns

1

ns

CORE

1

ns

CORE

1

+ 0.5 μs

CORE

0 ns

= 2CD/4.096 MHz.

t

SFS

t

SR

t

SF

t

DAV

MISO

MOSI BITS [6:1]

t

DSU

MSB IN

MSB

t

DHD

t

DF

t

DR

BITS [6:1]

LSB

LSB IN

07327-006

Figure 6. SPI Slave Mode Timing (SPICPHA = 1)

Rev. 0 | Page 12 of 128

ADE7518

Table 9. SPI Slave Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

tSS

to SCLK edge

SS
tSL SCLK low pulse width 6 × t
tSH SCLK high pulse width 6 × t
t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
t

DOSS

t

SFS

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR (see Table 24); t

CORE

Data output valid after SS

high after SCLK edge

SS

edge

= 2CD/4.096 MHz.

CORE

SS

t

SS

145 ns

1

ns

CORE

1

ns

CORE

1

+ 0.5 μs

CORE

0 ns
0 ns

t

SFS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MISO

MOSI

t

DOSS

t

DSU

MSB IN

MSB

t

DHD

t

SH

t

DF

t

SL

t

DAV

t

DR

BITS [6:1]

BITS [6:1]

t

LSB IN

LSB

t

SF

07327-007

SR

Figure 7. SPI Slave Mode Timing (SPICPHA = 0)

Rev. 0 | Page 13 of 128

ADE7518

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 10.

Parameter Rating

VDD to DGND −0.3 V to +3.7 V
V

to DGND −0.3 V to +3.7 V

BAT

V

to DGND −0.3 V to V

DCIN

Input LCD Voltage to AGND, LCDVA,

LCDVB, LCDVC

1

Analog Input Voltage to AGND, VP, VN, IP,

and I

N

−0.3 V to V

−2 V to +2 V

Digital Input Voltage to DGND −0.3 V to V
Digital Output Voltage to DGND −0.3 V to V

SWOUT

SWOUT

SWOUT

SWOUT

+ 0.3 V
+ 0.3 V

+ 0.3 V

+ 0.3 V
Operating Temperature Range (Industrial) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
64-Lead LQFP, Power Dissipation 1 W
Lead Temperature

Soldering 300°C
Time 30 sec

1

When used with external resistor divider.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 11. Thermal Resistance

Package Type θJA θ

Unit

JC

64-Lead LQFP 60 20.5 °C/W

ESD CAUTION

Rev. 0 | Page 14 of 128

ADE7518

T

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

INTA

BAT

V

V

59

58

57

ADE7518

TOP VIEW

(Not to Scale)

24

IN/OU

REF

FP26

AGND53I

RESET

56

55

54

25

26

FP927FP828FP729FP630FP531FP432FP3

FP11

FP10

N

51EA50

P

V

V

49

48

INT0

47

XTAL1

46

XTAL2

45

BCTRL/INT1/P0.0

44

SDEN/P2.3

43

P0.2/CF1/RTCCAL

42

P0.3/CF2

41

P0.4/MOSI/SDATA

40

P0.5/MISO

39

P0.6/SCLK/T0

38

P0.7/SS/T1

37

P1.0/RxD

36

P1.1/TxD

35

FP0

34

FP1

33

FP2

07327-008

N

P

I

52

COM3/F P27

COM2/F P28

COM1

COM0

P1.2/FP25

P1.3/T2EX/FP24

P1.4/T2/ FP23

P1.5/FP22

P1.6/FP21

P1.7/FP20

P0.1/FP19

P2.0/FP18

P2.1/FP17

P2.2/FP16

LCDVC

LCDVP2

DCIN

INTD

SWOUT

61

19

20

LCDVP1

DD

V

V

60

FP1521FP1422FP1323FP12

V

DGND62V

64

63

1

PIN 1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

LCDVA

LCDVB

Figure 8. Pin Configuration

Table 12. Pin Function Descriptions

Pin No. Mnemonic Description

1 COM3/FP27 Common Output 3 or LCD Segment Output 27. COM3 is used for LCD backplane.
2 COM2/FP28 Common Output 2 or LCD Segment Output 28. COM2 is used for LCD backplane.
3 COM1 Common Output 1. COM1 is used for LCD backplane.
4 COM0 Common Output 0. COM0 is used for LCD backplane.
5 P1.2/FP25 General-Purpose Digital I/O Port 1.2 or LCD Segment Output 25.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3, Timer 2 Control Input, or LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4, Timer 2 Input, or LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5 or LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6 or LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7 or LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1 or LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0 or LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1 or LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2 or LCD Segment Output 16.
15 LCDVC

This pin is internally connected to V

. A resistor should be connected between LCDVC and LCDVB to

DD

generate the top two voltages for the LCD waveforms (see the LCD Driver section).
16 LCDVP2 This pin is internally connected to LCDVP1 (see the LCD Driver section).
17 LCDVB

This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVB and LCDVC to

generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be

connected between LCDVB and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode,

LCDVB and LCDVA are internally connected (see the LCD Driver section).
18 LCDVA

This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVA and LCDVP1

to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be

connected between LCDVB and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode,

LCDVB and LCDVA are internally connected (see the LCD Driver section).
19 LCDVP1

This pin is an input voltage for the LCD driver. A resistor should be connected between LCDVA and LCDVP1

to generate an intermediate voltage for the LCD driver. Another resistor must be connected between

LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).
35 to 20 FP0 to F15 LCD Segment Output 0 to LCD Segment Output 15.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1 or Transmitter Data Output (Asynchronous).

Rev. 0 | Page 15 of 128

ADE7518

Pin No. Mnemonic Description

37 P1.0/RxD General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous).
38

P0.7/SS

/T1
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6, Clock Output for I2C or SPI Port, or Timer 0 Input.
40 P0.5/MISO General-Purpose Digital I/O Port 0.5 or Data Input for SPI Port.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4, Data Output for SPI Port, or I2C-Compatible Data Line.
42 P0.3/CF2

43 P0.2/CF1/RTCCAL

44

45

/P2.3 Serial Download Mode Enable or Digital Output Port P2.3. This pin is used to enable serial download mode

SDEN

BCTRL/INT1

/P0.0 Digital Input for Battery Control, External Interrupt Input 1, or General-Purpose Digital I/O Port 0.0. This logic

46 XTAL2

47 XTAL1

48

INT0

49, 50 VP, VN

51

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

EA

52, 53 IP, IN

54 AGND This pin provides the ground reference for the analog circuitry.
55 FP26 LCD Segment Output 26.
56
57 REF

58 V

59 V

RESET

IN/OUT

BAT

INTA

60 VDD

61 V

62 V

SWOUT

INTD

63 DGND This pin provides the ground reference for the digital circuitry.
64 V

DCIN

General-Purpose Digital I/O Port 0.7, Slave Select When SPI is in Slave Mode, or Timer 1 Input.

General-Purpose Digital I/O Port 0.3 or Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, I

, or apparent power information.

rms

General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency
Logic Output. The CF1 logic output gives instantaneous active, reactive, I

, or apparent power information.

rms

The RTCCAL logic output gives access to the calibrated RTC output.

through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input
and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high
and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug
kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be
used as a digital output port pin (P2.3).

or V

input connects V

DD

BAT

to V

open, the connection between V

internally when set to logic high or logic low, respectively. When left

SWOUT

and V

DD

or between V

SWOUT

BAT

and V

is selected internally.

SWOUT

A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source for the ADE7518. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1
or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across XTAL1 and XTAL2 to provide a clock source for the ADE7518. The clock frequency for
specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

internal program memory locations. The ADE7518 does not support external code memory. This pin should
not be left floating.

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.

Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled
with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

Power Supply Input from the Battery with a 2.4 V to 2.7 V Range. This pin is connected internally to V

when

DD

the battery is selected as the power supply for the ADE7518.
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Input from the Regulator. This pin is connected internally to V

when the regulator is

DD

selected as the power supply for the ADE7518. This pin should be decoupled with a 10 μF capacitor in
parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7518. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V

with respect to

SWOUT

AGND. This pin is used to monitor the preregulated dc voltage.

Rev. 0 | Page 16 of 128

ADE7518

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

GAIN = 1
INTERNAL REFERENCE

1.5

MID CLASS C

2.0
GAIN = 1
INTERNAL REFERENCE

1.5

1.0

0.5
+25°C; PF = 1

0

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

+85°C; PF = 1

–40°C; PF = 1

MID CLASS C

Figure 9. Active Energy Error as a Percentage of Reading (Gain = 1) over

Temperature with Internal Reference

1.5

GAIN = 1
INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% of Read ing)

–1.0

–1.5

+25°C; PF = 1
+85°C; PF = 1
–40°C; PF = 1

0

+25°C; PF = 0.5
+85°C; PF = 0.5
–40°C; PF = 0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

MID CLASS C

Figure 10. Active Energy Error as a Percentage of Reading (Gain = 1) over

Power Factor with Internal Reference

2.0

GAIN = 1
INTERNAL REFERENCE

1.5

1.0

0.5

0

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

0.1 1 10 100

07327-009

+85°C; PF = 0.866
+25°C; PF = 0.866
–40°C; PF = 0 .866

+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

07327-012

Figure 12. Reactive Energy Error as a Percentage of Reading (Gain = 1) over

Power Factor with Internal Reference

2.0

GAIN = 1
INTERNAL REFERENCE

1.5

1.0

0.5
+25°C; PF = 1

0

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

–2.0

0.1 1 10 100

07327-010

+85°C; PF = 1

–40°C; PF = 1

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

MID CLASS C

07327-013

Figure 13. Current RMS Error as a Percentage of Reading (Gain = 1) over

Temperature with Internal Reference

2.0

GAIN = 1
INTERNAL REFERENCE

1.5

MID CLASS C

1.0

0.5

0

–0.5

ERROR (% of Read ing)

–1.0

–1.5

–2.0

0.1 1 10 100

+85°C; PF = 0
+25°C; PF = 0
–40°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

07327-011

Figure 11. Reactive Energy Error as a Percentage of Reading (Gain = 1) over

Temperature with Internal Reference

Rev. 0 | Page 17 of 128

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

+25°C; PF = 1
+25°C; PF = 0.5

0

–40°C; PF = 1
–40°C; PF = 0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

+85°C; PF = 1
+85°C; PF = 0.5

MID CLASS C

Figure 14. Current RMS Error as a Percentage of Reading (Gain = 1) over

Power Factor with Internal Reference

07327-014

ADE7518

0.5
GAIN = 1
INTERNAL REFERENCE

0.4

0.3

0.2

0.1

I

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1 10 100

I

; 3.3V

rms

; 3.43V

rms

I

; 3.13V

rms

CURRENT CHANNEL (% of Full S cale)

V

; 3.3V

rms

V

; 3.43V

rms

V

; 3.13V

rms

07327-015

Figure 15. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)

over Power Supply with Internal Reference

1.0
GAIN = 1

INTERNAL REFERENCE

0.8

0.6

0.4

0.2

PF = 0.5

0

–0.2

–0.4

ERROR (% o f Readi ng)

–0.6

–0.8

–1.0

40 45 50 55 60 65 70

PF = 1

MID CLASS B

MID CLASS B

LINE FREQ UENCY (Hz)

07327-016

Figure 16. Active Energy Error as a Percentage of Reading (Gain = 1) over

Frequency with Internal Reference

0.5
GAIN = 1
INTERNAL REFERENCE

0.4

0.3

0.2

VAR; 3.3V

0.1

0

–0.1

–0.2

ERROR (% o f Readi ng)

–0.3

–0.4

–0.5

0.1 1 10 100

VAR; 3.43V

WATT; 3. 3V

VAR; 3.13V

WATT; 3. 13V

CURRENT CHANNEL (% of Full Scale)

WATT; 3. 43V

07327-017

Figure 17. Active and Reactive Energy Error as a Percentage of Reading (Gain = 1)

over Power Supply with Internal Reference

1.5
GAIN = 8
INTERNAL REFERENCE

1.0

0.5

PF = 1

0

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

0.1 1 10 100

PF = –0.5

PF = +0.5

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

MID CLASS C

7327-018

Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference

1.0

GAIN = 8
INTERNAL REFERENCE

0.8

0.6

0.4

PF = 1

0.2

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

PF = +0.5

0

PF = –0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

07327-019

Figure 19. Reactive Energy Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference

1.5
GAIN = 8
INTERNAL REFERENCE

1.0

0.5

PF = 1

0

–0.5

ERROR (% of Read ing)

–1.0

–1.5

0.1 1 10 100

PF = +0.5

PF = –0.5

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

MID CLASS C

7327-020

Figure 20. Current RMS Error as a Percentage of Reading (Gain = 8) over

Power Factor with Internal Reference

Rev. 0 | Page 18 of 128

ADE7518

2.0

GAIN = 16
INTERNAL REFERENCE

1.5

1.0

0.5
+25°C; PF = 1

0

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

–40°C; PF = 1

+85°C; PF = 1

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

MID CLASS C

Figure 21. Active Energy Error as a Percentage of Reading (Gain = 16) over

Temperature with Internal Reference

2.0

GAIN = 16
INTERNAL REFERENCE

1.5

1.0

0.5

0

–0.5

ERROR (% of Read ing)

–1.0

+85°C; PF = 0.5
+25°C; PF = 1
+25°C; PF = 0.5

+85°C; PF = 1
–40°C; PF = 1
–40°C; PF = 0.5

MID CLASS C

1.0
GAIN = 16
INTERNAL REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Read ing)

–0.6

–0.8

–1.0

0.1 1 10 100

07327-021

CURRENT CHANNEL (% of Full Scale)

–40°C; PF = 0
+85°C; PF = 0
+85°C; PF = 0.866
–40°C; PF = 0.866

+25°C; PF = 0.866
+25°C; PF = 0

7327-024

Figure 24. Reactive Energy Error as a Percentage of Reading (Gain = 16) over

Power Factor with Internal Reference

2.0

GAIN = 16
INTERNAL REFERENCE

1.5

1.0

0.5
–40°C; PF = 1

0

–0.5

+85°C; PF = 1

ERROR (% of Reading)

–1.0

+25°C; PF = 1

MID CLASS C

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

07327-022

Figure 22. Active Energy Error as a Percentage of Reading (Gain = 16) over

Power Factor with Internal Reference

1.0
GAIN = 16
INTERNAL REFERENCE

0.8

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1 10 100

+85°C; PF = 0

–40°C; PF = 0

+25°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

07327-023

Figure 23. Reactive Energy Error as a Percentage of Reading (Gain = 16) over

Temperature with Internal Reference

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 25. Current RMS Error as a Percentage of Reading (Gain = 16) over

Temperature with Internal Reference

2.0

GAIN = 16
INTERNAL REFERENCE

1.5

1.0

0.5

0

–0.5

ERROR (% of Read ing)

–1.0

–1.5

–2.0

0.1 1 10 100

–40°C; PF = 1
+25°C; PF = 1
–40°C; PF = 0. 5

+85°C; PF = 0.5
+25°C; PF = 0.5
+85°C; PF = 1

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

MID CLASS C

Figure 26. Current RMS Error as a Percentage of Reading (Gain = 16) over

Power Factor with Internal Reference

07327-025

07327-026

Rev. 0 | Page 19 of 128

ADE7518

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the
ADE7518 is defined by the following formula:

Percentage Error =

⎛
⎜
⎜
⎝

Phase Error Between Channels

The digital integrator and the high-pass filter (HPF) in the current
channel have a nonideal phase response. To offset this phase
response and equalize the phase response between channels,
two phase correction networks are placed in the current channel:
one for the digital integrator and the other for the HPF. The
phase correction networks correct the phase response of the
corresponding component and ensure a phase match between
current channel and voltage channel to within ±0.1° over a
range of 45 Hz to 65 Hz with the digital integrator off. With
the digital integrator on, the phase is corrected to within ±0.4°
over a range of 45 Hz to 65 Hz.

Power Supply Rejection (PSR)

PSR quantifies the ADE7518 measurement error as a percentage
of reading when the power supplies are varied. For the ac PSR
measurement, a reading at nominal supplies (3.3 V) is taken.
A second reading is obtained with the same input signal levels
when an ac (100 mV rms/120 Hz) signal is introduced onto the
supplies. Any error introduced by this ac signal is expressed as a
percentage of reading (see the Measurement Error definition).

−

EnergyTrue

⎞

EnergyTrueRegisterEnergy

⎟
⎟
⎠

%100×

For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is again expressed as a percentage of the reading.

ADC Offset Error

ADC offset error is the dc offset associated with the analog
inputs to the ADCs. It means that, with the analog inputs
connected to AGND, the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain and
input range selection (see the Typical Performance Characteristics
section). However, when HPF1 is switched on, the offset is
removed from the current channel, and the power calculation
is not affected by this offset. The offsets can be removed by
performing an offset calibration (see the Analog Inputs section).

Gain Error

Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the
Current Channel ADC section and the Voltage Channel ADC
section). It is measured for each of the gain settings on the
current channel (1, 2, 4, 8, and 16). The difference is expressed
as a percentage of the ideal code.

Rev. 0 | Page 20 of 128

ADE7518

SFR MAPPING

Table 13.

Mnemonic Address Details

INTPR 0xFF Table 15
SCRATCH4 0xFE Table 23
SCRATCH3 0xFD Table 22
SCRATCH2 0xFC Table 21
SCRATCH1 0xFB Table 20
IPSMF 0xF8 Table 16
TEMPCAL 0xF7 Table 116
RTCCOMP 0xF6 Table 115
BATPR 0xF5 Table 17
PERIPH 0xF4 Table 18
B 0xF0 Table 45
LCDSEGE2 0xED Table 77
IPSME 0xEC Table 19
SPISTAT 0xEA Table 131
SPI2CSTAT 0xEA Table 135
SPIMOD2 0xE9 Table 130
I2CADR 0xE9 Table 134
SPIMOD1 0xE8 Table 129
I2CMOD 0xE8 Table 133
WAV2H 0xE7 Table 29
WAV2M 0xE6 Table 29
WAV2L 0xE5 Table 29
WAV1H 0xE4 Table 29
WAV1M 0xE3 Table 29
WAV1L 0xE2 Table 29
ACC 0xE0 Table 45
MIRQSTH 0xDE Table 39
MIRQSTM 0xDD
MIRQSTL 0xDC Table 37
MIRQENH 0xDB Table 42
MIRQENM 0xDA Table 41
MIRQENL 0xD9 Table 40
IRMSH 0xD6 Table 29
IRMSM 0xD5 Table 29
IRMSL 0xD4 Table 29
VRMSH 0xD3 Table 29
VRMSM 0xD2 Table 29
VRMSL 0xD1 Table 29
PSW 0xD0 Table 46
TH2 0xCD Table 99
TL2 0xCC Table 100
RCAP2H 0xCB Table 101
RCAP2L 0xCA Table 102
T2CON 0xC8 Table 94
EADRH 0xC7 Table 89
EADRL 0xC6 Table 88
POWCON 0xC5 Table 24
KYREG 0xC1 Table 105
WDCON 0xC0 Table 65
PROTR 0xBF Table 87

Table

38

Mnemonic Address Details

PROTB1 0xBE Table 86
PROTB0 0xBD Table 85
EDATA 0xBC Table 84
PROTKY 0xBB Table 83
FLSHKY 0xBA Table 82
ECON 0xB9 Table 81
IP 0xB8 Table 59
PINMAP2 0xB4 Table 140
PINMAP1 0xB3 Table 139
PINMAP0 0xB2 Table 138
LCDCONY 0xB1 Table 70
CFG 0xAF Table 52
LCDDAT 0xAE Table 76
LCDPTR 0xAC Table 75
IEIP2 0xA9 Table 60
IE 0xA8 Table 58
DPCON 0xA7 Table 56
INTVAL 0xA6 Table 114
HOUR 0xA5 Table 113
MIN 0xA4 Table 112
SEC 0xA3 Table 111
HTHSEC 0xA2 Table 110
TIMECON 0xA1 Table 109
P2 0xA0 Table 143
EPCFG 0x9F Table 137
SBAUDT 0x9E Table 123
SBAUDF 0x9D Table 124
LCDCONX 0x9C Table 69
SPI2CRx 0x9B Table 128
SPI2CTx 0x9A Table 127
SBUF 0x99 Table 122
SCON 0x98 Table 121
LCDSEGE 0x97 Table 74
LCDCLK 0x96 Table 71
LCDCON 0x95 Table 68
MDATH 0x94 Table 29
MDATM 0x93 Table 29
MDATL 0x92 Table 29
MADDPT 0x91 Table 29
P1 0x90 Table 142
TH1 0x8D Table 97
TH0 0x8C Table 95
TL1 0x8B Table 98
TL0 0x8A Table 96
TMOD 0x89 Table 92
TCON 0x88 Table 93
PCON 0x87 Table 47
DPH 0x83 Table 49
DPL 0x82 Table 48
SP 0x81 Table 51
P0 0x80 Table 141

Rev. 0 | Page 21 of 128

ADE7518

POWER MANAGEMENT

The ADE7518 has elaborate power management circuitry that manages the regular power supply to battery switchover and power supply
failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Table 14).

Table 14. Power Management SFRs

SFR Address R/W Mnemonic Description

0xEC R/W IPSME Power Management Interrupt Enable. See Table 19.
0xF5 R/W BATPR Battery Switchover Configuration. See Table 17.
0xF8 R/W IPSMF Power Management Interrupt Flag. See Table 16.
0xFF R/W INTPR Interrupt Pins Configuration. See Table 15.
0xF4 R/W PERIPH Peripheral Configuration SFR. See Table 18.
0xC5 R/W POWCON Power Control. See Table 24.
0xFB R/W SCRATCH1 Scratch Pad 1. See Table 20.
0xFC R/W SCRATCH2 Scratch Pad 2. See Table 21.
0xFD R/W SCRATCH3 Scratch Pad 3. See Table 22.
0xFE R/W SCRATCH4 Scratch Pad 4. See Table 23.

POWER MANAGEMENT REGISTER DETAILS

Table 15. Interrupt Pins Configuration SFR (INTPR, 0xFF)

Bit Mnemonic Default Description

7 RTCCAL 0

6 to 5 FSEL[1:0] 00 Sets the RTC calibration output frequency and calibration window.

4 Reserved N/A
3 to 1 INT1PRG[2:0] 000

0 INT0PRG 0

Controls the RTC calibration output. When this bit is set, the RTC calibration frequency selected by
FSEL[1:0] is output on the P0.2/CF1/RTCCAL pin.

FSEL[1:0] Result (Calibration Window, Frequency)

00 30.5 sec, 1 Hz
01 30.5 sec, 512 Hz
10 0.244 sec, 500 Hz
11 0.244 sec, 16.384 kHz

Controls the function of INT1

INT1PRG[2:0] Result

x00 GPIO enabled
x01 BCTRL enabled
01x

11x

Controls the function of INT0

INT0PRG Result
0
1

INT1
INT1

INT0
INT0

.

input disabled
input enabled

.

input disabled
input enabled

Writing to the Interrupt Pins Configuration SFR (INTPR, 0xFF)

To protect the RTC from runaway code, a key must be written to the Key SFR (KYREG, 0xC1) to obtain write access to INTPR. KYREG
(see Table 105) should be set to 0xEA to unlock this SFR and then reset to zero after a timekeeping register is written to. The RTC
registers can be written using the following 8052 assembly code:

MOV KYREG, #0EAh
MOV INTPR, #080h

Rev. 0 | Page 22 of 128

ADE7518

Table 16. Power Management Interrupt Flag SFR (IPSMF, 0xF8)

Bit Address Mnemonic Default Description

7 0xFF FPSR 0

Power Supply Restored Interrupt Flag. Set when the V
This occurs when the source of V

changes from V

SWOUT

6 0xFE FPSM 0 PSM Interrupt Flag. Set when an enabled PSM interrupt condition occurs.
5 0xFD FSAG 0 Voltage SAG Interrupt Flag. Set when an ADE energy measurement SAG condition occurs.
4 0xFC Reserved 0 This bit must be kept cleared for proper operation.
3 0xFB Reserved 0 This bit must be kept cleared for proper operation.
2 0xFA Reserved 0 This bit must be kept cleared for proper operation.
1 0xF9 FBSO 0 Battery Switchover Interrupt Flag. Set when V
0 0xF8 FVDCIN 0 V

Monitor Interrupt Flag. Set when V

DCIN

SWOUT

falls below 1.2 V.

DCIN

Table 17. Battery Switchover Configuration SFR (BATPR, 0xF5)

Bit Mnemonic Default Description

7 to 2 Reserved 0 These bits must be kept to 0 for proper operation.
1 to 0 BATPRG[1:0] 00 Control Bits for Battery Switchover.

BATPRG[1:0] Result

00 Battery switchover enabled on low VDD
01 Battery switchover enabled on low VDD and low V
1x Battery switchover disabled

Table 18. Peripheral Configuration SFR (PERIPH, 0xF4)

Bit Mnemonic Default Description

7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2.
6 VSWSOURCE 1 Indicates the power supply that is internally connected to V
5 VDD_OK 1 If set, indicates that the VDD power supply is ready for operation.
4 PLL_FLT 0

If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLL_FTL_ACK bit (see
Table 107) in the Start ADC Measurement SFR (ADCGO, 0xD8) to acknowledge the fault and clear

the PLL_FLT bit.
3 Reserved 0 This bit should be kept to 0.
2 Reserved 0 This bit should be kept to 0.
1 to 0 RXPROG[1:0] 00 Controls the function of the P1.0/RxD pin.

RXPROG[1:0] Result

00 GPIO

01 RxD with wake-up disabled

11 RxD with wake-up enabled

power supply has been restored.

DD

to VDD.

BAT

switches from VDD to V

DCIN

SWOUT

(0 V

SWOUT

= V

BAT

, 1 V

BAT.

SWOUT

= VDD).

Table 19. Power Management Interrupt Enable SFR (IPSME, 0xEC)

Bit Mnemonic Default Description

7 EPSR 0 Enables a PSM interrupt when the power supply restored flag (FPSR) is set.
6 Reserved 0 Reserved.
5 ESAG 0 Enables a PSM interrupt when the voltage SAG flag (FSAG) is set.
4 to 2 Reserved 0 These bits must be kept cleared for proper operation.
1 EBSO 0 Enables a PSM interrupt when the battery switchover flag (FBSO) is set.
0 EVDCIN 0 Enables a PSM interrupt when the V

monitor flag (FVDCIN) is set.

DCIN

Table 20. Scratch Pad 1 SFR (SCRATCH1, 0xFB)

Bit Mnemonic Default Description

7 to 0 SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Rev. 0 | Page 23 of 128

ADE7518

Table 21. Scratch Pad 2 SFR (SCRATCH2, 0xFC)

Bit Mnemonic Default Description

7 to 0 SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 22. Scratch Pad 3 SFR (SCRATCH3, 0xFD)

Bit Mnemonic Default Description

7 to 0 SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 23. Scratch Pad 4 SFR (SCRATCH4, 0xFE)

Bit Mnemonic Default Description

7 to 0 SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Clearing the Scratch Pad Registers (SCRATCH1, 0xFB to SCRATCH4, 0xFE)

Note that these scratch pad registers are only cleared when the part loses VDD and V
PLL reset and, therefore, need to be set correctly in these situations.

Table 24. Power Control SFR (POWCON, 0xC5)

Bit Mnemonic Default Description

7 Reserved 1 Reserved.
6 METER_OFF 0

Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if

metering functions are not needed in PSM0.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to shut down the core and enter PSM2 if in PSM1 operating mode.
3 Reserved 0 Reserved.
2 to 0 CD[2:0] 010 Controls the core clock frequency, f

CD[2:0] Result (f

in MHz)

CORE

000 4.096

001 2.048

010 1.024

011 0.512

100 0.256

101 0.128

110 0.064

111 0.032

. They are not cleared by software, watchdog, or

BAT

. f

CORE

= 4.096 MHz/2CD.

CORE

Writing to the Power Control SFR (POWCON, 0xC5)

Writing data to the POWCON SFR involves writing 0xA7 into the Key SFR (KYREG, 0xC1), which is described in Table 105, followed by
a write to the POWCON SFR. For example,

MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h ;Shutdown the core

Rev. 0 | Page 24 of 128

ADE7518

V

V

POWER SUPPLY ARCHITECTURE

The ADE7518 has two power supply inputs, VDD and V
requires only a single 3.3 V power supply at V

for full operation.

DD

A battery backup, or secondary power supply, with a maximum
of 3.7 V, can be connected to the V
ADE7518 connects V

DD

or V

BAT

power for the ADE7518 circuitry. The V
the voltage at the internal power supply (V

input. Internally, the

BAT

to V

, which is used to derive

SWOUT

SWOUT

output pin reflects

) and has a

SWOUT

maximum output current of 6 mA. This pin can also be used
to power a limited number of peripheral components. The 2.5 V
analog supply (V
(V

) are derived by on-chip linear regulators from V

INTD

) and the 2.5 V supply for the core logic

INTA

Figure 27 shows the power supply architecture of ADE7518.

The ADE7518 provides automatic battery switchover between
V

DD

and V

based on the voltage level detected at VDD or V

BAT

Additionally, the BCTRL input can be used to trigger a battery
switchover. The conditions for switching V

and back to VDD are described in the Battery Switchover

V

BAT

section. V

is an input pin that can be connected to a 0 V to

DCIN

from VDD to

SWOUT

3.3 V dc signal. This input is intended for power supply super­visory purposes and does not provide power to the ADE7518
circuitry (see the Battery Switchover section).

BCTRL

DCINVDDVBAT

POWER SUPPLY

MANAGEMENT

SCRATCHPAD LCD RTC

Figure 27. Power Supply Architecture

SWOUT

V

INTD

LDO

V

SW

LDO

V

3.3V

INTA

SWOUT

MCU

ADE

SPI/I2C

UART

2.5V

BAT

, and

.

DCIN

.

BATTERY SWITCHOVER

The ADE7518 monitors VDD, V

DD

to V

DD

, V

, or BCTRL pin. Battery switchover is

DCIN

switchover from V
status of the V
enabled by default. Setting Bit 1 in the Battery Switchover Configu­ration SFR (BATPR, 0xF5) disables battery switchover so that

is always connected to V

V

DD

is indicated by Bit 6 in the Peripheral Configuration SFR

V

SWOUT

(PERIPH, 0xF4), which is described in Table 18. Bit 6 is set
when V
connected to V

is connected to VDD and cleared when V

SWOUT

.

BAT

, and V

BAT

can be configured based on the

BAT

(see Table 17). The source of

SWOUT

. Automatic battery

DCIN

SWOUT

is

07327-027

The battery switchover functionality provided by the ADE7518

to V

allows a seamless transition from V

DD

. An automatic

BAT

battery switchover option ensures a stable power supply to the
ADE7518, as long as the external battery voltage is above 2.75 V.
It allows continuous code execution even while the internal

to V

power supply is switching from V

DD

the energy metering ADCs are not available when V
used for V

SWOUT

.

and back. Note that

BAT

is being

BAT

Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the V

DD

power supply is restored (see the Power Supply Management
(PSM) Interrupt section).

V

to V

BAT

DD

The following three events switch the internal power supply
(V

SWOUT

• V

from V

) from VDD to V

< 1.2 V. When V

DCIN

to V

DD

:

BAT

falls below 1.2 V, V

DCIN

. This event is enabled when the

BAT

SWOUT

switches

BATPRG[1:0] bits in the Battery Switchover Configuration
SFR (BATPR, 0xF5) = 0b01. Setting these bits disables
switchover based on V

is disabled by default.

V

DCIN

• V

< 2.75 V. When VDD falls below 2.75 V, V

DD

DD

to V

from V

. This event is enabled when BATPRG[1:0] in

BAT

. Battery switchover on low

DCIN

SWOUT

switches

the BATPR SRF are cleared.

• Falling edge on BCTRL. When the battery control pin,

BCTRL, goes low, V

switches from VDD to V

SWOUT

external switchover signal can trigger a switchover to V

BAT

. This

BAT

at any time. Setting the bits INT1PRG[2:0] to 0bx01 in the
Interrupt Pins Configuration SFR (INTPR, 0xFF) enables
the battery control pin (see Table 15).

Switching from V

To s wit c h V

SWOUT

to VDD

BAT

from V

to VDD, all of the following events

BAT

that are enabled to force battery switchover must be false:

• V

• V

• BCTRL enabled. V

< 1.2 V and VDD < 2.75 V enabled. If the low V

DCIN

condition is enabled, V
remains above 1.2 V and V

< 2.75 V enabled. V

DD

remains above 2.75 V.

V

DD

SWOUT

switches to VDD after V

SWOUT

remains above 2.75 V.

DD

switches back to VDD after

SWOUT

switches back to VDD after BCTRL

DCIN

DCIN

is high, and the first or second bullet point is satisfied.

Rev. 0 | Page 25 of 128

ADE7518

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

The power supply management (PSM) interrupt alerts the 8052
core of power supply events. The PSM interrupt is disabled by
default. Setting the EPSM bit in the Interrupt Enable and Priority 2
SFR (IEIP2, 0xA9) enables the PSM interrupt (see Table 60).

EPSR
FPSR

ESAG

FSAG

The Power Management Interrupt Enable SFR (IPSME, 0xEC)
controls the events that result in a PSM interrupt (see Table 19).
Figure 28 is a diagram illustrating how the PSM interrupt vector
is shared among the PSM interrupt sources. The PSM interrupt
flags are latched and must be cleared by writing to the IPSMF flag
register (see Table 16).

EBSO

FBSO

EVDCIN
FVDCIN

IPSME ADDR. 0xEC

IPSMF ADDR. 0xF8

IEIP2 ADDR. 0xA9

FPSM

EPSM

EPSR RESERVED ESAG RESERVED EBSO EVDCIN

FPSR F PSM FSAG RESERVED FBSO FVDCIN

RESERVED PTI RESE RVED PSI EADE ETI EPSM ESI

NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN

TRUE?

RESERVED RESERVED

RESERVED RESERVED

PENDING PSM

INTERRUPT

07327-028

Figure 28. PSM Interrupt Sources

Rev. 0 | Page 26 of 128

ADE7518

Battery Switchover and Power Supply Restored PSM Interrupt

The ADE7518 can be configured to generate a PSM interrupt
when the source of V

changes from VDD to V

SWOUT

, indicating

BAT

battery switchover. Setting the EBSO bit in the Power Management
Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate
a PSM interrupt (see Table 19).

The ADE7518 can also be configured to generate an interrupt
when the source of V
that the V

power supply has been restored. Setting the EPSR bit

DD

changes from V

SWOUT

to VDD, indicating

BAT

in the Power Management Interrupt Enable SFR (IPSME, 0xEC)
enables this event to generate a PSM interrupt.

The flags in the IPSMF SFR for these interrupts, FBSO and
FPSR, are set regardless of whether the respective enable bits
have been set. The battery switchover and power supply restore
event flags, FBSO and FPSR, are latched. These events must be
cleared by writing 0 to these bits. Bit 6 in the Peripheral
Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the
source of V

. The bit is set when V

SWOUT

and cleared when V

is connected to V

SWOUT

is connected to VDD

SWOUT

.

BAT

V

Monitor PSM Interrupt

DCIN

The V

voltage is monitored by a comparator. The FVDCIN

DCIN

bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8)
is set when the V

input level is lower than 1.2 V. Setting the

DCIN

EVDCIN bit in the IPSME SFR enables this event to generate
a PSM interrupt. This event, which is associated with the SAG
monitoring, can be used to detect a power supply (V

) being

DD

compromised and to trigger further actions prior to deciding a

to V

switch of V

DD

BAT

.

SAG Monitor PSM Interrupt

The ADE7518 energy measurement DSP monitors the ac voltage
input at the V

and VN input pins. The SAGLVL register is used

P

to set the threshold for a line voltage SAG event. The FSAG bit
in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is
set if the line voltage stays below the level set in the SAGLVL
register for the number of line cycles set in the SAGCYC register.
See the Line Voltage SAG Detection section for more informa­tion. Setting the ESAG bit in the Power Management Interrupt
Enable SFR (IPSME, 0xEC) enables this event to generate a
PSM interrupt.

Rev. 0 | Page 27 of 128

ADE7518

V

V

USING THE POWER SUPPLY FEATURES

In an energy meter application, the 3.3 V power supply (VDD)
is typically generated from the ac line voltage and regulated to

3.3 V by a voltage regulator IC. The preregulated dc voltage,
typically 5 V to 12 V, can be connected to V
tor divider. A 3.6 V battery can be connected to V
shows how the ADE7518 power supply inputs are set up in this
application.

Figure 30 shows the sequence of events that occurs if the main
power supply generated by the PSU starts to fail in the power
meter application shown in Figure 29. The SAG detection can
provide the earliest warning of a potential problem on V

(240V, 220V, 110V TYPICAL)

AC INPUT

through a resis-

DCIN

. Figure 29

BAT

.

DD

BCTRL

V

V

45

P

49

N

50

When a SAG event occurs, user code can be configured to back
up data and prepare for battery switchover if desired. The rela­tive spacing of these interrupts depends on the design of the
power supply.

Figure 31 shows the sequence of events that occurs if the main
power supply starts to fail in the power meter application shown
in Figure 29, with battery switchover on low V

or low VDD

DCIN

enabled.

Finally, the transition between V

and V

DD

and the different

BAT

power supply modes (see the Operating Modes section) are
represented in Figure 32 and Figure 33.

SAG

DETECT ION

5V TO 12V DC

PSU

3.3V

REGULATOR

V

SWOUT

V

DCIN

64

V

DD

60

61

58

V

BAT

VOLTAG E

SUPERVISORY

VOLTAG E

SUPERVISORY

POWER SUPPLY

MANAGEMENT

V

SW

IPSMF SFR

(ADDR. 0xF8)

07327-029

Figure 29. Power Supply Management for Energy Meter Application

–

P

N

SAG LEVEL TRIP POINT

SAGCYC = 1

V

DCIN

1.2V

V

2.75V

t

DD

1

t

2

SAG EVENT

(FSAG = 1)

Figure 30. Power Supply Management Interrupts and Battery Switchover with Only V

V

EVENT

DCIN

(FVDCIN = 1)

IF SWITCHOVER ON LOW VDD IS ENABLED,

AUTOMATIC BAT TERY SWI TCHOVER

V

CONNECTED TO V

SWOUT

BSO EVENT

(FBSO = 1)

Enabled for Battery Switchover

DD

BAT

7327-030

Rev. 0 | Page 28 of 128

ADE7518

VP–

V

Table 25. Power Supply Event Timing Operating Modes

Parameter Time Description

t1 10 ns min Time between when V
t2 10 ns min Time between when VDD falls below 2.75 V and when battery switchover occurs.
t3 30 ms typ

Time between when V
battery switchover.

t4 130 ms typ

Time between when power supply restore conditions are met (V
BATPR[1:0] = 0b01 or V

N

SAG LEVEL TRIP POINT
SAGCYC = 1

V

DCIN

1.2V

V

DD

2.75V

falls below 1.2 V and when FVDCIN is raised.

DCIN

falls below 1.2 V and when battery switchover occurs if V

DCIN

above 1.2 V and VDD above 2.75 V if

above 2.75 V if BATPR[1:0] = 0b00) and when V

DD

DCIN

SWOUT

t

3

t

1

is enabled to cause

DCIN

switches to VDD.

SAG EVENT

(FSAG = 1)

Figure 31. Power Supply Management Interrupts and Battery Switchover with V

V

EVENT

DCIN

(FVDCIN = 1)

or V

DD

IF SWI TCHOVER ON L OW V

ENABLED, AUTO MATIC BATTERY

SWITCHOVER V

Enabled for Battery Switchover

DCIN

CONNECT ED TO V

SWOUT

BSO EVENT

(FBSO = 1)

DCIN

IS

BAT

07327-031

VP − V

N

SAG LEVEL
TRIP POINT

EVENT

V

DCIN

1.2V

V

2.75V

BATTERY SWITCH

ENABLED ON

LOW V

DCIN

SAG EVENT

BAT

V

DD

V

SW

PSM0 PSM0

V

DCIN

30ms MIN

V

DCIN

130ms MIN

PSM1 OR PSM2

EVENT

V

BATTERY SWITCH

ENABLED ON

LOW V

DD

SW

PSM0 PSM0

PSM1 OR PSM2

07327-032

Figure 32. Power Supply Management Transitions Between Modes

Rev. 0 | Page 29 of 128

ADE7518

OPERATING MODES

PSM0 (NORMAL MODE)

In PSM0, normal operating mode, V
All of the analog circuitry and digital circuitry powered by

and V

V

INTD

default clock frequency, f

are enabled by default. In normal mode, the

INTA

, established during a power-on

CORE

reset or software reset, is 1.024 MHz.

is connected to VDD.

SWOUT

PSM1 (BATTERY MODE)

In PSM1, battery mode, V
operating mode, the 8052 core and all of the digital circuitry are
enabled by default. The analog circuitry for the ADE energy
metering DSP powered by V
automatically restarts, and the switch to the V
occurs when the V

supply is above 2.75 V and the PWRDN

DD

bit in the MODE1 register (0x0B) is cleared (see Table 31). The
default f

for PSM1, established during a power-on reset or

CORE

software reset, is 1.024 MHz.

is connected to V

SWOUT

is disabled. This analog circuitry

INTA

BAT

power supply

DD

. In this

PSM2 (SLEEP MODE)

PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, V

2.5 V digital and analog circuitry powered through V
are disabled, including the MCU core, resulting in the following:

• The RAM in the MCU is no longer valid.

• The program counter for the 8052, also held in volatile

memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from
where it left off but always starts from the power-on reset
vector when the ADE7518 exits PSM2.

The 3.3 V peripherals (RTC, and LCD) are active in PSM2.
They can be enabled or disabled to reduce power consumption
and are configured for PSM2 operation when the MCU core is
active (see Table 27 for more information about the individual
peripherals and their PSM2 configuration). The ADE7518
remains in PSM2 until an event occurs to wake them up.

In PSM2, the ADE7518 provides four scratch pad RAM SFRs
that are maintained during this mode. These SFRs can be used
to save data from PSM0 or PSM1 when entering PSM2 (see
Table 20 to Table 23).

In PSM2, the ADE7518 maintains some SFRs (see Table 26).
The SFRs that are not listed in this table should be restored
when the part enters PSM0 or PSM1 from PSM2.

is connected to V

SWOUT

. All of the

BAT

and V

INTA

INTD

Table 26. SFRs Maintained in PSM2

I/O Configuration Power Supply Management RTC Peripherals LCD Peripherals

Interrupt Pins Configuration SFR
(INTPR, 0xFF), see Table 15

Peripheral Configuration SFR
(PERIPH, 0xF4), see Table 18

Battery Switchover Configuration
SFR (BATPR, 0xF5), see Table 17

RTC Nominal Compensation SFR
(RTCCOMP, 0xF6), see Table 115

RTC Temperature Compensation
SFR (TEMPCAL, 0xF7),

LCD Segment Enable 2 SFR
(LCDSEGE2, 0xED), see Table 77

LCD Configuration Y SFR
(LCDCONY, 0xB1), see Table 70

see Table 116

Port 0 Weak Pull-Up Enable SFR
(PINMAP0, 0xB2), see Table 138

Port 1 Weak Pull-Up Enable SFR
(PINMAP1, 0xB3), see Table 139

RTC Configuration SFR
(TIMECON, 0xA1), see Table 109

Hundredths of a Second
Counter SFR

LCD Configuration X SFR
(LCDCONX, 0x9C), see Table 69

LCD Configuration SFR
(LCDCON, 0x95), see Table 68

(HTHSEC, 0xA2), see Table 110

Port 2 Weak Pull-Up Enable SFR
(PINMAP2, 0xB4), see Table 140

Scratch Pad 1 SFR
(SCRATCH1, 0xFB), see Table 20

Scratch Pad 2 SFR
(SCRATCH2, 0xFC), see Table 21

Scratch Pad 3 SFR
(SCRATCH3, 0xFD), see Table 22

Scratch Pad 4 SFR

Seconds Counter SFR
(SEC, 0xA3), see Table 111

Minutes Counter SFR
(MIN, 0xA4), see Table 112

Hours Counter SFR
(HOUR, 0xA5), see Table 113

Alarm Interval SFR
(INTVAL, 0xA6), see Table 114

LCD Clock SFR
(LCDCLK, 0x96), see Table 71

LCD Segment Enable SFR
(LCDSEGE, 0x97), see Table 74

LCD Pointer SFR
(LCDPTR, 0xAC), see Table 75

LCD Data SFR
(LCDDAT, 0xAE), see Table 76

(SCRATCH4, 0xFE), see Table 23

Rev. 0 | Page 30 of 128