Datasheet ADE7116, ADE7156, ADE7166, ADE7169, ADE7569 Datasheet (ANALOG DEVICES)

Single-Phase Energy Measurement IC

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

with 8052 MCU, RTC, and LCD Driver

GENERAL FEATURES

Wide supply voltage operation: 2.4 V to 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM)

Full operation: 4 mA to 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA to 400 μA (PLL clock dependent) Sleep mode

Real-time clock (RTC) mode: 1.5 μA

RTC and LCD mode: 38 μA (LCD charge pump enabled) Reference: 1.2 V ± 0.1% (10 ppm/°C drift) 64-lead RoHS package options

Lead frame chip scale package (LFCSP) Low profile quad flat package (LQFP)

Operating temperature range: −40°C to +85°C

ENERGY MEASUREMENT FEATURES

Proprietary analog-to-digital converters (ADCs) and digital

signal processing (DSP) provide high accuracy active (watt), reactive (var), and apparent energy (volt-ampere (VA)) measurement <0.1% error on active energy over a dynamic range of

1000 to 1 @ 25°C

<0.5% error on reactive energy over a dynamic range of

1000 to 1 @ 25°C (ADE7169 and ADE7569 only)

<0.5% error on root mean square (rms) measurements

over a dynamic range of 500 to 1 for current (I

100 to 1 for voltage (V

) @ 25°C

rms

Supports IEC 62053-21, IEC 62053-22, and IEC 62053-23;

EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16 Differential input with programmable gain amplifiers (PGAs)

supports shunts, current transformers, and di/dt current sensors (ADE7169 and ADE7569 only)

2 current inputs for antitamper detection in the

ADE7116/ADE7156/ADE7166/ADE7169

High frequency outputs proportional to I

, active, reactive,

rms

or apparent power (AP)

Table 1. Features Available on Each Part

Feature Part No.

Antitamper ADE7116, ADE7156, ADE7166, ADE7169 Watt, VA, I

rms

, V

ADE7116, ADE7156, ADE7166, ADE7169,

rms

ADE7566, ADE7569 Var ADE7169, ADE7569 di/dt Sensor ADE7169, ADE7569

rms

) and

MICROPROCESSOR FEATURES

8052-based core

Single-cycle 4 MIPS 8052 core 8052-compatible instruction set

32.768 kHz external crystal with on-chip PLL 2 external interrupt sources External reset pin

Low power battery mode

Wake-up from I/O, temperature change

universal asynchronous receiver/transmitter (UART) LCD driver operation Temperature measurement

Real-time clock (RTC)

Counter for seconds, minutes, and hours Automatic battery switchover for RTC backup Operation down to 2.4 V Ultralow battery supply current: 1.5 μA Selectable output frequency: 1 Hz to 16 kHz Embedded digital crystal frequency compensation for

calibration and temperature variation of 2 ppm resolution

Integrated LCD driver

108-segment driver for the ADE7566/ADE7569 and

104-segment driver for the ADE7116/ADE7156/

ADE7166/ADE7169 2×, 3×, or 4× multiplexing LCD voltages generated internally Internal adjustable drive voltages up to 5 V independent

of power supply level

On-chip peripherals

UART interface

SPI or I

Watchdog timer

Power supply management with user-selectable levels Memory: 16 kB flash memory, 512 bytes RAM Development tools

Single-pin emulation IDE-based assembly and C-source debugging

Not available in the ADE7116.

Not available in the ADE7116 or ADE7156.

, alarm, and

or with external resistors

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

General Features ............................................................................... 1

Energy Measurement Features ........................................................ 1

Microprocessor Features .................................................................. 1

Revision History ............................................................................... 3

General Description ......................................................................... 4

Functional Block Diagrams ............................................................. 4

Specifications ..................................................................................... 6

Energy Metering ........................................................................... 6

Analog Peripherals ....................................................................... 7

Digital Interface ............................................................................ 8

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 15

Thermal Resistance .................................................................... 15

ESD Caution ................................................................................ 15

Pin Configurations and Function Descriptions ......................... 16

Typical Performance Characteristics ........................................... 22

Performance Curves for the ADE7169 and ADE7569 Only 25

Terminology .................................................................................... 26

Special Function Register (SFR) Mapping .................................. 27

Power Management ........................................................................ 29

Power Management Register Details ....................................... 29

Power Supply Architecture ........................................................ 32

Battery Switchover ...................................................................... 32

Power Supply Management (PSM) Interrupt ......................... 33

Using the Power Supply Features ............................................. 35

Operating Modes ............................................................................ 37

PSM0 (Normal Mode) ............................................................... 37

PSM1 (Battery Mode) ................................................................ 37

PSM2 (Sleep Mode) .................................................................... 37

3.3 V Peripherals and Wake-Up Events ................................... 38

Transitioning Between Operating Modes ............................... 39

Using the Power Management Features .................................. 39

Energy Measurement ..................................................................... 40

Access to Energy Measurement SFRs ...................................... 40

Access to Internal Energy Measurement Registers ................ 40

Energy Measurement Registers ................................................ 43

Energy Measurement Internal Register Details ..................... 44

Interrupt Status/Enable SFRs .................................................... 47

Analog Inputs .............................................................................. 49

Analog-to-Digital Conversion .................................................. 50

Fault Detection ........................................................................... 54

di/dt Current Sensor and Digital Integrator for the

ADE7169/ADE7569 ................................................................... 55

Power Quality Measurements ................................................... 57

Phase Compensation ................................................................. 59

RMS Calculation ........................................................................ 59

Active Power Calculation .......................................................... 62

Active Energy Calculation ........................................................ 64

Reactive Power Calculation (ADE7169/ADE7569) .............. 67

Reactive Energy Calculation (ADE7169/ADE7569) ............. 68

Apparent Power Calculation ..................................................... 72

Apparent Energy Calculation ................................................... 73

Ampere-Hour Accumulation ................................................... 74

Energy-to-Frequency Conversion............................................ 75

Energy Register Scaling ............................................................. 76

Energy Measurement Interrupts .............................................. 76

Temperature, Battery, and Supply Voltage Measurements........ 77

Temperature Measurement ....................................................... 79

Battery Measurement ................................................................. 79

External Voltage Measurement ................................................ 80

8052 MCU Core Architecture....................................................... 82

MCU Registers ............................................................................ 82

Basic 8052 Registers ................................................................... 84

Standard 8052 SFRs .................................................................... 85

Memory Overview ..................................................................... 85

Addressing Modes ...................................................................... 86

Instruction Set ............................................................................ 88

Read-Modify-Write Instructions ............................................. 90

Instructions That Affect Flags .................................................. 90

Dual Data Pointers ......................................................................... 92

Interrupt System ............................................................................. 93

Standard 8052 Interrupt Architecture ..................................... 93

Interrupt Architecture ............................................................... 93

Interrupt Registers...................................................................... 93

Interrupt Priority ........................................................................ 94

Interrupt Flags ............................................................................ 95

Interrupt Vectors ........................................................................ 97

Interrupt Latency ........................................................................ 97

Context Saving ............................................................................ 97

Watchdog Timer ............................................................................. 98



Rev. B | Page 2 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

LCD Driver ................................................................................... 100

LCD Registers ........................................................................... 100

LCD Setup ................................................................................. 103

LCD Timing and Waveforms ................................................. 103

Blink Mode ................................................................................ 104

Display Element Control ......................................................... 104

Voltage Generation .................................................................. 105

LCD External Circuitry ........................................................... 106

LCD Function in PSM2 Mode ............................................... 106

Flash Memory ............................................................................... 108

Flash Memory Overview ......................................................... 108

Flash Memory Organization ................................................... 109

Using the Flash Memory ......................................................... 109

Protecting the Flash Memory ................................................. 113

In-Circuit Programming ......................................................... 114

Timers ............................................................................................ 115

Timer Registers ......................................................................... 115

Timer 0 and Timer 1 ................................................................ 117

Timer 2 ...................................................................................... 118

PLL ................................................................................................. 120

PLL Registers ............................................................................ 120

Real-Time Clock (RTC) .............................................................. 121

RTC SFRs .................................................................................. 121

Read and Write Operations .................................................... 124

RTC Modes ............................................................................... 124

RTC Interrupts ......................................................................... 124

REVISION HISTORY

11/08—Rev. A to Re v. B

Added ADE7116/ADE7156 ......................................... Throughout

Changes to Table 1 ............................................................................ 1

Added Figure 2 .................................................................................. 5

Changes to Table 13 ........................................................................ 16

Added Figure 10 and Table 14; Renumbered Sequentially ........ 19

Added Exposed Pad Notation to Outline Dimensions ............148

Changes to Ordering Guide .........................................................149

12/07—Rev. 0 to Rev. A

Added ADE7166/ADE7169 .............................................. Universal

Changes to Table 1 ............................................................................ 1

Changes to Ordering Guide .........................................................144

11/07—Revision 0: Initial Version

RTC Calibration ........................................................................ 125

UART Serial Interface ................................................................... 126

UART SFRs ................................................................................ 126

UART Operation Modes .......................................................... 129

UART Baud Rate Generation .................................................. 130

UART Additional Features ...................................................... 132

Serial Peripheral Interface (SPI) .................................................. 133

SPI Registers .............................................................................. 133

SPI Pins ....................................................................................... 136

SPI Master Operating Modes .................................................. 137

SPI Interrupt and Status Flags ................................................. 138

I2C-Compatible Interface ............................................................. 139

Serial Clock Generation ........................................................... 139

Slave Addresses .......................................................................... 139

I2C Registers ............................................................................... 139

Read and Write Operations ..................................................... 140

I2C Receive and Transmit FIFOs ............................................. 141

I/O Ports ......................................................................................... 142

Parallel I/O ................................................................................. 142

I/O Registers .............................................................................. 143

Port 0 ........................................................................................... 146

Port 1 ........................................................................................... 146

Port 2 ........................................................................................... 146

Determining the Version of the Part .......................................... 147

Outline Dimensions ...................................................................... 148

Ordering Guide ......................................................................... 149

Rev. B | Page 3 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

GENERAL DESCRIPTION

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

ADE7569

integrate the Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make an electronic energy meter with an LCD display in a single part.

The ADE measurement core includes active, reactive, and apparent energy calculations, as well as voltage and current rms measurements. This information is accessible for energy billing by using the built-in energy scalars. Many power line supervisory features such as SAG, peak, and zero crossing are included in the energy measurement DSP to simplify energy meter design.

FUNCTIONAL BLOCK DIAGRAMS

The microprocessor functionality includes a single-cycle 8052 core, a real-time clock with a power supply backup pin, an SPI

or I

C® interface, and a UART interface. The ready-to-use information from the ADE core reduces the program memory size requirement, making it easy to integrate complicated design into 16 kB of flash memory.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 also include a 108-/104-segment LCD driver. In the ADE7166/ADE7169/ADE7566/ADE7569, this driver generates voltages capable of driving LCDs up to 5 V.

Patents pending.

DGND

AGND

BAT

T1/P0.0)

K L C

SPI/I2C

SERIAL

USER RAM 256 BYTES

USER XRAM

256 BYTES

LDO

D T N

O S

I M

T A D S

I S O M

3 × 16-BIT COUNTER

LDO

T0T

TIMERS

POR

A T N

0 (BCTRL/I N

E 2

T2T

P0.

45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10

SINGLE

CYCLE

8052 MCU

1-PIN

EMULATOR

T E

S E R

T U O

/ N

F E R

1.20V REF

PGA1

–

PGA2

–

TEMP

SENSOR

BATTERY

ADC

TEMP

ADC

POWER SUPPLY

CONTROL AND

MONIT ORING

N I

C D

43 42 39 38 7 638 39 40 41

INTERFACE

ENERGY

MEASUREMENT

DSP

PROGRAM MEMORY

16kB FLASH

VDCIN

ADC

D D

T U O

W S

.1/FP19P0.2/CF1/RTCC

0.3/CF2

DOWNLOADER

DEBUGGER

UART

TIMER

N E D S

/SCLK/T0

5/MISO

.7/SS/T1

.4/MOSI/SDA

P0.6

P0.

P1.0/RxD

ADE7566/ADE7569

CHARGE PUMP

108-SEGMENT

WATCHDOG

TIMER

UART

SERIAL

PORT

P24

/TxD

P1.1

P1.2/FP25

P1.3/T2EX/F

3V/5V LCD

LCD DRIVER

PLL

RTC

OSC

1 L A T X

2/FP23

P1.6/FP21P1.7

P1.4/T

P1.5/FP22

4647 48 45

2 L A T X

/FP20

0 T N

P2.0/FP18

P2.1/FP17

P2.2/FP16

P2.3 (SDEN/P2.3) LCDVP2

LCDVA

LCDVB

LCDVC

COM0

. .

...

COM3

FP0

. .

...

FP15

FP16

FP17

FP18

FP19

FP20

FP21

FP22

FP23

FP24

FP25

FP26

FP27

FP28

1 T N

06353-001

Figure 1. ADE7566/ADE7569 Functional Block Diagram

Rev. B | Page 4 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

.0)

DGND

AGND

BAT

K L C

SPI/I2C

SERIAL

USER RAM 256 BYTES

USER XRAM

256 BYTES

LDO

D T N

O S

I M

T A D S

I S O M

LDO

T2T

T0T

3 × 16-BIT COUNTER

TIMERS

POR

A T N

T U O

/ N

1.20V REF

F E R

43 42 39 38 7 638 39 40 41

INTERFACE

PGA1

–

PGA1

PGA2

–

TEMP

SENSOR

BATTERY

ADC

TEMP

ADC

POWER SUPPLY

CONTROL AND

MONITORING

N I

ENERGY

MEASUREMENT

D D

DSP

PROGRAM MEMORY

16kB FLASH

VDCIN

ADC

T U O

W S

RL/INT1/P0

/RTCCAL

X E 2

P0.0 (BCT

P0.1/FP19P0.2/CF1

45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10

K/T0

SI/SDATA

P0.3/CF

/T1

1.0/RxD

P0.7/SS

P0.6/SCL

P0.5/MISOP0.4/MO

ADE7116/ADE7156/ADE7166/ADE7169

CHARGE PUMP

104-SEGME NT

SINGLE

CYCLE

T E S E R

8052 MCU

1-PIN

EMULATOR

UART

TIMER

WATCHDOG

TIMER

DOWNLOADER

DEBUGGER

UART

SERIAL

PORT

N E D S

D x T

D x

LCD DRIVER

RTC

/FP25

/T2EX/ FP24

.1/TxD P1

P1.2

P1.3

3V/5V LCD

P1.4/T2/FP23P1.5

PLL

OSC

4647 48 45

1 L A T X

/FP22

P1.6/FP21

P1.7/FP

P2.0/FP18

P2.1/FP17

P2.2/FP16

P2.3 (SDEN/P2.3)

LCDVP1

LCDVP2

LCDVA

LCDVB

LCDVC

COM0

...

COM3

FP0

...

FP15

FP16

FP17

FP18

FP19

FP20

FP21

FP22

FP23

FP24

FP25

FP27

FP28

T X

06353-119

Figure 2. ADE7116/ADE7156/ADE7166/ADE7169 Functional Block Diagram

Rev. B | Page 5 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

SPECIFICATIONS

VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, T

ENERGY METERING

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

MEASUREMENT ACCURACY

Phase Error Between Channels

PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°

Active Energy Measurement Error

AC Power Supply Rejection

Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms

DC Power Supply Rejection

Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth Reactive Energy Measurement Error V

Measurement Error

rms

Measurement Bandwidth

rms

Measurement Error

rms

Measurement Bandwidth

rms

ANALOG INPUTS

Maximum Signal Levels ±400 mV peak VP − VN differential input

ADE7566/ADE7569 ±400 mV peak IP − IN differential input

ADE7116/ADE7156/ADE7166/ADE7169 ±250 mV peak IPA − IN and IPB − IN differential inputs Input Impedance (DC) 770 kΩ ADC Offset Error

±1 mV PGA1 = 16

Gain Error

Current Channel ±3 % IPA = IPB = 0.4 V dc or IP = 0.4 V dc

Voltage Channel ±3 +3 % VP − VN = 0.4 V dc Gain Error Match ±0.2 %

CF1 AND CF2 PULSE OUTPUT

Maximum Output Frequency 13.5 kHz

Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz

FAU LT D ETEC T ION

Fault Detection Threshold

Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active Input Swap Threshold

Inactive Input > Active Input 6.25 % of active IPA or IPB active Accuracy Fault Mode Operation

IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1

IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds

These specifications are not production tested but are guaranteed by design and/or characterization data on production release.

See the Terminology section for definition.

This function is not available in the ADE7166 or ADE7566.

This function is not available in the ADE7566 or ADE7569.

2, 3

0.5 % of reading Over a dynamic range of 100 to 1 at 25°C

3.9 kHz

0.5 % of reading Over a dynamic range of 500 to 1 at 25°C

3.9 kHz

±10 mV PGA1 = PGA2 = 1

0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C

8 kHz

0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C

MIN

to T

= −40°C to +85°C, unless otherwise noted.

MAX

= 3.3 V + 100 mV rms/120 Hz

= 3.3 V ± 117 mV dc

− VN = 400 mV peak, IPA − IN = 250 mV,

PGA1 = 2 sine wave

Rev. B | Page 6 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ANALOG PERIPHERALS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

INTERNAL ADCs (BATTERY, TEMPERATURE, V

Power Supply Operating Range 2.4 3.7 V Measured on V No Missing Codes Conversion Delay

ADC Gain

Measurement 15.3 mV/LSB

DCIN

Measurement 14.6 mV/LSB

BAT

Temperature Measurement 0.78 °C/LSB

ADC Offset

Measurement at 3 V 206 LSB

DCIN

Measurement at 3.7 V 205 LSB

BAT

Temperature Measurement at 25°C 129 LSB

Analog Input

DCIN

Maximum Signal Levels 0 3.3 V Input Impedance (DC) 1 MΩ Low V

Detection Threshold 1.09 1.2 1.27 V

DCIN

POWER-ON RESET (POR)

VDD POR

Detection Threshold 2.5 2.95 V POR Active Timeout Period 33 ms

POR

SWOUT

Detection Threshold 1.8 2.2 V POR Active Timeout Period 20 ms

POR

INTD

Detection Threshold 2.0 2.25 V POR Active Timeout Period 16 ms

POR

INTA

Detection Threshold 2.05 2.25 V POR Active Timeout Period 120 ms

BATTERY SWITCHOVER

Voltage Operating Range (V VDD to V

Switching

BAT

) 2.4 3.7 V

SWOUT

Switching Threshold (VDD) 2.5 2.95 V Switching Delay 10 ns When VDD to V 30 ms When VDD to V

to VDD Switching

BAT

Switching Threshold (VDD) 2.5 2.95 V Switching Delay 30 ms Based on VDD > 2.75 V

to V

SWOUT

LCD, CHARGE PUMP ACTIVE

Leakage Current 10 nA V

BAT

Charge Pump Capacitance Between LCDVP1 and

LCDVP2 LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF LCDVA 0 1.75 V LCDVB 0 3.5 V 1/3 bias mode LCDVC 0 5.3 V 1/3 bias mode V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 V3 Segment Line Voltage LCDVC − 0.1 DC Voltage Across Segment and COMx Pin 50 mV

DCIN

)

SWOUT

8 Bits 38 μs

switch activated by VDD

BAT

= 0 V, V

BAT

switch activated by V

BAT

= 3.43 V, TA = 25°C

SWOUT

DCIN

100 nF

LCDVB V Current on segment line = −2 μA LCDVC V Current on segment line = −2 μA

LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA

Rev. B | Page 7 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Parameter Min Typ Max Unit Test Conditions/Comments

LCD, RESISTOR LADDER ACTIVE

Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA

ON-CHIP REFERENCE

Reference Error ±0.9 mV TA = 25°C Power Supply Rejection 80 dB Temperature Coefficient

This function is not available in the ADE7116.

These specifications are not production tested but are guaranteed by design and/or characterization data on production release.

Delay between ADC conversion request and interrupt set.

This function is not available in the ADE7116 or ADE7156.

DIGITAL INTERFACE

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

All Inputs Except XTAL1, XTAL2, BCTRL,

INT0 Input High Voltage, V Input Low Voltage, V

BCTRL, INT0, INT1, RESET

Input High Voltage, V Input Low Voltage, V

Input Currents

RESET Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or V

−3.75 −8.5 μA Internal pull-up enabled, input = 0 V, V Input Capacitance 10 pF All digital inputs

FLASH MEMORY

Endurance Data Retention

CRYSTAL OSCILLATOR

Crystal Equivalent Series Resistance 30 50 kΩ Crystal Frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF

MCU CLOCK RATE (f 32 kHz Crystal = 32.768 kHz and CD bits = 111 LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%

SOURCE

Output Low Voltage, V

SINK

START-UP TIME

PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 1 (PSM1)

PSM1 to PSM0 130

From Power Saving Mode 2 (PSM2)

PSM2 to PSM1 48 PSM2 to PSM0 186

, INT1, RESET

80 μA

2 mA

10 50 ppm/°C

2.0 V

INH

0.8 V

INL

1.3 V

INH

0.8 V

INL

100 nA

RESET

= V

SWOUT

= 3.3 V

20,000 Cycles 20 Years TJ = 85°C

) 4.096 MHz Crystal = 32.768 kHz and CD bits = 000

CORE

0.4 V VDD = 3.3 V ± 5%

ms VDD at 2.75 V to PSM0 code execution

ms Wake-up event to PSM1 code execution ms VDD at 2.75 V to PSM0 code execution

SWOUT

= 3.3 V

Rev. B | Page 8 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY INPUTS

VDD 3.13 3.3 3.46 V V

2.4 3.3 3.7 V

BAT

INTERNAL POWER SUPPLY SWITCH (V

to V

BAT

VDD to V V

to/from VDD Switching Open Time 40 ns

BAT

On Resistance 22 Ω V

SWOUT

On Resistance 10.2 Ω VDD = 3.13 V

SWOUT

BCTRL State Change and Switch Delay 18 μs V

Output Current Drive 6 mA

SWOUT

POWER SUPPLY OUTPUTS

2.3 2.70 V

INTA

2.3 2.70 V

INTD

Power Supply Rejection 60 dB

INTA

Power Supply Rejection 50 dB

INTD

POWER SUPPLY CURRENTS

Current in Normal Mode (PSM0) 4 5.3 mA f

2.1 mA f

1.6 mA f 3 3.9 mA

Current in PSM1 3.2 5.05 mA f 880 μA f Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC, V

1.5 μA RTC only, TA = 25°C, V

Specifications guaranteed by design.

Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

Recommended crystal specifications.

Test carried out with all the I/Os set to a low output level.

Delay between power supply valid and execution of first instruction by 8052 core.

)

SWOUT

= 2.4 V

BAT

= 4.096 MHz, LCD and meter active

CORE

= 1.024 MHz, LCD and meter active

CORE

= 32.768 kHz, LCD and meter active

CORE

= 4.096 MHz, metering ADC and DSP powered

CORE

down

= 4.096 MHz, LCD active, V

CORE

= 1.024 MHz, LCD active

CORE

BAT

= 3.3 V

= 3.7 V

BAT

= 3.3 V

BAT

Rev. B | Page 9 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TIMING SPECIFICATIONS

AC inputs during testing were driven at V and at 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and at V

maximum for Logic 0, as shown in

− 0.5 V for Logic 1

SWOUT

Figure 3.

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to

– 0.5V

SWOUT

0.45V

0.2V

SWOUT

TEST POINTS

0.2V

SWOUT

+ 0.9V

– 0.1V

Figure 3. Timing Waveform Characteristics

Table 5. Clock Input (External Clock Driven XTAL1) Parameter

32.768 kHz External Crystal

Parameter Description Min Typ Max Unit

tCK XTAL1 period 30.52 μs t

XTAL1 width low 6.26 μs

CKL

XTAL1 width high 6.26 μs

CKH

XTAL1 rise time 9 ns

CKR

XTAL1 fall time 9 ns

CKF

1/t

Core clock frequency

CORE

The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can

operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).

float when a 100 mV change from the loaded V

OH/VOL

level

occurs, as shown in Figure 3.

for all outputs is equal to 80 pF, unless otherwise noted.

LOAD

= 2.7 V to 3.6 V; all specifications T

MIN

to T

MAX

, unless

otherwise noted.

LOAD

– 0.1V

+ 0.1V

TIMING

REFERENCE

POINTS

LOAD

– 0.1V

LOAD

06353-002

1.024 MHz

Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)

Parameter Description Typ Uni t

Bus-free time between stop condition and start condition 1.3 μs

BUF

tL SCLK low pulse width 1.36 μs tH SCLK high pulse width 1.14 μs t

Start condition hold time 251.35 μs

SHD

Data setup time 740 ns

DSU

Data hold time 400 ns

DHD

Setup time for repeated start 12.5 ns

RSU

Stop condition setup time 400 ns

PSU

tR Rise time of both SCLK and SDATA 200 ns tF Fall time of both SCLK and SDATA 300 ns

SUP

Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.

SDATA (I/O)

Pulse width of spike suppressed 50 ns

SCLK (I)

PSU

STOP

CONDITI ON

BUF

START

CONDITI ON

DSU

SHD

MSB

DHD

2TO 7

Figure 4. I

C-Compatible Interface Timing

SUP

LSB ACK MSB

DSU

89 1

SUP

RSU

DHD

S(R)

REPEATED

START

06353-003

Rev. B | Page 10 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2 tSH SCLK high pulse width 2 t

Data output valid after SCLK edge 3 × t

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

DAV

MSB

SPIR

CORE

BITS [6:1]

× t

CORE

× t

CORE

= 2CD/4.096 MHz.

CORE

ns ns

CORE

LSB

MISO

MSB IN

DSU

DHD

BITS [6:1]

LSB IN

06353-004

Figure 5. SPI Master Mode Timing (SPICPHA = 1)

Rev. B | Page 11 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2 tSH SCLK high pulse width 2 t

Data output valid after SCLK edge 3 × t

DAV

Data output setup before SCLK edge 75 ns

DOSU

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

DOSU

MSB

DAV

BITS [6:1]

SPIR

CORE

× t

CORE

× t

(SPIR + 1) × t

CORE

= 2CD/4.096 MHz.

CORE

(SPIR + 1) × t

LSB

CORE

MISO

DSU

MSB IN

BITS [6:1]

DHD

LSB IN

6353-005

Figure 6. SPI Master Mode Timing (SPICPHA = 0)

Rev. B | Page 12 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

SS to SCLK edge

tSL SCLK low pulse width 6 × t tSH SCLK high pulse width 6 × t t

Data output valid after SCLK edge 25 ns

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns t

SFS

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

high after SCLK edge

145 ns

CORE

+ 0.5 μs μs

CORE

0 ns

= 2CD/4.096 MHz.

CORE

SFS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MISO

MOSI

DAV

DSU

MSB IN

MSB

DHD

BITS

[6:1]

LSB

LSB IN

06353-006

Figure 7. SPI Slave Mode Timing (SPICPHA = 1)

Rev. B | Page 13 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

SS to SCLK edge

tSL SCLK low pulse width 6 × t tSH SCLK high pulse width 6 × t t

Data output valid after SCLK edge 25 ns

DAV

Data input setup time before SCLK edge 0 ns

DSU

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns t

DOSS

SFS

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

Data output valid after SS

high after SCLK edge

edge

145 ns

CORE

+ 0.5 μs μs

CORE

0 ns 0 ns

= 2CD/4.096 MHz.

CORE

SFS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MISO

MOSI

DOSS

DSU

MSB IN

MSB

DHD

DAV

BITS [6:1]

BITS [ 6:1]

LSB IN

LSB

06353-007

Figure 8. SPI Slave Mode Timing (SPICPHA = 0)

Rev. B | Page 14 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 11.

Parameter Rating

VDD to DGND −0.3 V to +3.7 V V

to DGND −0.3 V to +3.7 V

BAT

to DGND −0.3 V to V

DCIN

Input LCD Voltage to AGND, LCDVA,

LCDVB, LCDVC

Analog Input Voltage to AGND, VP, VN,

, IPA, IPB, and IN

−0.3 V to V

−2 V to +2 V

Digital Input Voltage to DGND −0.3 V to V Digital Output Voltage to DGND −0.3 V to V Operating Temperature R ange

−40°C to +85°C

SWOUT

+ 0.3 V + 0.3 V

(Industrial) Storage Temperature Range −65°C to +150°C 64-Lead LQFP, Power Dissipation

Lead Temperature (Soldering, 30 sec) 300°C

When used with external resistor divider.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 12. Thermal Resistance

Package Type θJA θ

Unit

64-Lead LQFP 60 20.5 °C/W 64-Lead LFCSP 27.1 2.3 °C/W

ESD CAUTION

Rev. B | Page 15 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

DCIN

INTDVSWOUTVDDVINTAVBAT

DGND

646362616059585756555453525150

PIN 1

COM1 COM0

LCDVC

LCDVP2

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

ADE7566/ADE7569

171819202122232425262728293031

FP15

LCDVA

LCDVB

LCDVP1

COM3/FP27 COM2/FP28

P1.2/FP25

P1.3/T2EX/FP24

P1.4/T2/FP23

P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16

NOTES

1. IT IS RECOMMENDED THAT THE EXPO SED PAD ON THE BO TTOM OF THE L FCSP BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

Figure 9. Pin Configuration for the ADE7566/ADE7569

IN/OU

REF

TOP VIEW

(Not to Scale)

FP11

FP14

FP13

FP12

RESET

FP10

FP26

AGND

FP9

FP8

INIPVNV

FP7

FP6

FP5

FP4

FP3

INT0

XTAL1

XTAL2

BCTRL/INT1/P0.0

SDEN/P2.3

P0.2/CF1/RTCCAL

P0.3/CF2

P0.4/MOSI/SDATA

P0.5/MISO

P0.6/SCLK/T0

P0.7/SS/T1

P1.0/RxD

P1.1/TxD

FP0

FP1

FP2

06353-120

Table 13. Pin Function Descriptions

Pin No. Mnemonic Description

1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. 15 LCDVC

. A resistor should be connected

between this pin and LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section).

16 LCDVP2

17 LCDVB

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally connected (see the LCD Driver section).

Rev. B | Page 16 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

18 LCDVA

19 LCDVP1

20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38

P0.7/SS

/T1 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. 42 P0.3/CF2

43 P0.2/CF1/RTCCAL

/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial

SDEN

BCTRL/INT1

/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

46 XTAL2

47 XTAL1

INT0

49, 50 VP, VN

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

52, 53 IP, IN

54 AGND This pin provides the ground reference for the analog circuitry. 55 FP26 LCD Segment Output 26. 56

57 REF

58 V

59 V

RESET

IN/OUT

BAT

INTA

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section).

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, I

, or apparent power information.

rms

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I

, or apparent information. The RTCCAL

rms

logic output gives access to the calibrated RTC output.

download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3).

input connects V open, the connection between V

or V

BAT

to V

internally when set to logic high or logic low, respectively. When left

SWOUT

or V

BAT

and V

is selected internally.

SWOUT

A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

External Interrupt Input 0. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin should not be left floating.

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA.

Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V

when

the battery is selected as the power supply for the ADE7566/ADE7569. This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

Rev. B | Page 17 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

60 VDD

3.3 V Power Supply Input from the Regulator. This pin is connected internally to V selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

61 V

SWOUT

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

62 V

INTD

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V

DCIN

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V

AGND. This pin is used to monitor the preregulated dc voltage. EP Exposed Pad

The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected

to ground inside the package. It is recommended that the exposed pad be connected to the ground plane

on the board.

when the regulator is

SWOUT

with respect to

SWOUT

Rev. B | Page 18 of 152

ADE7169/ADE7566/ADE7569ADE7116/ADE7156/ADE7166/

TOP VIEW

(Not to Scale)

151413 FPFPFP

IN/OUT

REF

121110 FPFPFP

RESET

IPBAGND

FP9

FP8

INIPAVNV

FP7

FP6

FP5

FP4

INT0

XTAL1

XTAL2

BCTRL/INT1/P0.0

SDEN/P2.3

P0.2/CF1/RTCCAL

P0.3/CF2

P0.4/MOSI/SDATA

P0.5/MISO

P0.6/SCLK/T0

P0.7/SS/T1

P1.0/RxD

P1.1/TxD

FP0

FP1

FP2

FP3

06353-120

DCIN

INTDVSWOUTVDDVINTAVBAT

DGND

646362616059585756555453525150

PIN 1

COM1 COM0

LCDVC

LCDVP2

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

ADE7116/ADE7156/

ADE7166/ADE7169

171819202122232425262728293031 B

LCD

LCDV

COM3/FP27 COM2/FP28

P1.2/FP25

P1.3/T2EX/FP24

P1.4/T2/FP23

P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16

NOTES

1. IT IS RECOMMENDED THAT THE EXPO SED PAD ON THE BO TTOM OF THE L FCSP BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

Figure 10. Pin Configuration for the ADE7116/ADE7156/ADE7166/ADE7169

Table 14. Pin Function Descriptions

Pin No. Mnemonic Description

. A resistor should be connected between this pin and

LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section).

16 LCDVP2

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116 and ADE7156, this pin is always an analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section).

17 LCDVB

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally connected (see the LCD Driver section).

Rev. B | Page 19 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

18 LCDVA

19 LCDVP1

20 to 35 FP15 to FP0 LCD Segment Output 0 to LCD Segment Output 15. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38

P0.7/SS

43 P0.2/CF1/RTCCAL

/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial

SDEN

BCTRL/INT1

/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

46 XTAL2

47 XTAL1

INT0

49, 50 VP, VN

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

52, 53 IPA, IN

54 AGND This pin provides the ground reference for the analog circuitry. 55 IPB

56 57 REF

58 V

RESET

IN/OUT

BAT

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section).

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, I

, or apparent power information.

rms

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I

, or apparent power information. The

rms

RTCCAL logic output gives access to the calibrated RTC output.

or V

input connects V

BAT

to V

open, the connection between V

internally when set to logic high or logic low, respectively. When left

SWOUT

or V

BAT

and V

is selected internally.

SWOUT

A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/ ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

External Interrupt Input 0. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external code memory. This pin should not be left floating.

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA.

Analog Input for Second Current Channel (I level of ±400 mV, referred to I

for specified operation. This channel also has an internal PGA.

). This input is fully differential with a maximum differential

Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V

when

the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.

Rev. B | Page 20 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

59 V

60 VDD

61 V

62 V

63 DGND Ground Reference for Digital Circuitry. 64 V

EP Exposed Pad

INTA

SWOUT

INTD

DCIN

This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Input from the Regulator. This pin is connected internally to V

when the regulator is

SWOUT

selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V

with respect to

SWOUT

AGND. This pin is used to monitor the preregulated dc voltage. The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected

to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the board.

Rev. B | Page 21 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5 +25°C; PF = 1

–0.5

ERROR (% of Reading)

–1.0

MID CLASS C

+85°C; PF = 1

–40°C; PF = 1

2.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.5

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

+85°C; PF = 0.866 +25°C; PF = 0.866 –40°C; PF = 0 .866

+85°C; PF = 0 +25°C; PF = 0 –40°C; PF = 0

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

1.5 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

–1.5

+25°C; PF = 1 +85°C; PF = 1 –40°C; PF = 1

+25°C; PF = 0.5 +85°C; PF = 0.5 –40°C; PF = 0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

2.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.5

1.0

0.5

–0.5

ERROR (% of Read ing)

–1.0

+85°C; PF = 0 +25°C; PF = 0 –40°C; PF = 0

–1.5

–2.0

0.1 1 10 100

06353-107

CURRENT CHANNEL (% of Full Scale)

06353-115

Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

+25°C; PF = 1

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

–2.0

0.1 1 10 100

06353-108

+85°C; PF = 1

–40°C; PF = 1

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

06353-109

Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

+25°C; PF = 1 +25°C; PF = 0.5

–40°C; PF = 1 –40°C; PF = 0.5

MID CLASS C

+85°C; PF = 1 +85°C; PF = 0.5

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

06353-114

Rev. B | Page 22 of 152

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

06353-110

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

0.5 GAIN = 1 INTEGRATOR OFF

0.4 INTERNAL REFERENCE

0.3

0.2

0.1

–0.1

–0.2

ERROR (% of Read ing)

–0.3

–0.4

–0.5

0.1 1 10 100

rms

; 3.3V

rms

; 3.43V

; 3.13V

rms

CURRENT CHANNEL (% of Full S cale)

; 3.3V

rms

; 3.43V

rms

; 3.13V

rms

06353-111

Figure 17. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)

over Power Supply with Internal Reference, Integrator Off

1.0 GAIN = 1

INTEGRATOR OFF

0.8

INTERNAL REFERENCE

0.6

0.4

0.2

PF = 0.5

–0.2

–0.4

ERROR (% of Read ing)

–0.6

–0.8

–1.0

40 45 50 55 60 65 70

PF = 1

MID CLASS B

LINE FREQ UENCY (Hz)

06353-112

Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)

over Frequency with Internal Reference, Integrator Off

0.5 GAIN = 1 INTEGRATOR OFF

0.4 INTERNAL REFERENCE

0.3

0.2

VAR; 3.3V

0.1

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1 10 100

VAR; 3.43V

W; 3.3V

VAR; 3.13V

W; 3.13V

CURRENT CHANNEL (% of Full Scale)

W; 3.43V

06353-113

Figure 19. Active and Reactive Energy Error as a Percentage of Reading

(Gain = 1) over Power Supply with Internal Reference, Integrator Off

1.5 GAIN = 8 INTEGRATOR OFF INTERNAL REFE RENCE

1.0

0.5

PF = 1

–0.5

ERROR (% of Reading)

–1.0

–1.5

0.1 1 10 100

PF = –0.5

PF = +0.5

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

1.0

GAIN = 8 INTEGRATO R OFF

0.8

INTERNAL REFERENCE

0.6

0.4

PF = 1

0.2

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

PF = +0.5

PF = –0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

1.5 GAIN = 8 INTEGRATO R OFF INTERNAL REFERENCE

1.0

0.5

PF = 1

–0.5

ERROR (% of Read ing)

–1.0

–1.5

0.1 1 10 100

PF = +0.5

PF = –0.5

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

06353-094

06353-095

06353-096

Rev. B | Page 23 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFE RENCE

1.0

0.5

+25°C; PF = 1

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

–40°C; PF = 1

+85°C; PF = 1

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFE RENCE

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

+85°C; PF = 0.5 +25°C; PF = 1 +25°C; PF = 0.5

+85°C; PF = 1 –40°C; PF = 1 –40°C; PF = 0 .5

MID CLASS C

1.0 GAIN = 16 INTEGRATOR OFF

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1 10 100

06353-097

CURRENT CHANNEL (% of Full Scale)

–40°C; PF = 0 +85°C; PF = 0 +85°C; PF = 0.866 –40°C; PF = 0. 866

+25°C; PF = 0.866 +25°C; PF = 0

06353-100

Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5

INTERNAL REFERENCE

1.0

0.5

–40°C; PF = 1

–0.5

+85°C; PF = 1

ERROR (% of Reading)

–1.0

+25°C; PF = 1

MID CLASS C

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

1.0 GAIN = 16

INTEGRATOR OFF

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1 10 100

+85°C; PF = 0

–40°C; PF = 0

+25°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

–1.5

–2.0

0.1 1 10 100

06353-098

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-101

Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

–2.0

0.1 1 10 100

06353-099

–40°C; PF = 1 +25°C; PF = 1 –40°C; PF = 0. 5

+85°C; PF = 0.5 +25°C; PF = 0.5 +85°C; PF = 1

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-102

Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

Rev. B | Page 24 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY

2.0

GAIN = 16 INTEGRATOR ON

1.5 INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% o f Readi ng)

–1.0

–40°C; PF = 1 +85°C; PF = 0.5 +25°C; PF = 0.5 –40°C; PF = 0. 5

+25°C; PF = 1 +85°C; PF = 1

MID CLASS C

2.0

GAIN = 16 INTEGRATOR ON

1.5 INTERNAL REFERENCE

1.0

+25°C; PF = 1 +25°C; PF = 0.5 +85°C; PF = 0.5

0.5

+85°C; PF = 1 –40°C; PF = 0. 5

–0.5

ERROR (% of Reading)

–1.0

MID CLASS C

–40°C; PF = 1

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

1.0 GAIN = 16

INTEGRATOR ON

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

–0.2

–0.4

ERROR (% of Read ing)

–40°C; PF = 0.866

–0.6

–0.8

–1.0

0.1 1 10 10 0

+25°C; PF = 0 +85°C; PF = 0.866 –40°C; PF = 0 +25°C; PF = 0.866

+85°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

–1.5

–2.0

0.1 1 10 100

06353-103

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-105

Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

06353-104

Rev. B | Page 25 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is defined by the following formula:

Percentage Error =

⎛ ⎜

⎜ ⎝

Phase Error Between Channels

The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz.

Power Supply Rejection (PSR)

PSR quantifies the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition).

−

EnergyTrue

⎞

EnergyTrueRegisterEnergy

⎟

⎟ ⎠

(1)

%100×

For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.

ADC Offset Error

ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typi ca l Per f o r ma n c e Characteristics section). However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section).

Gain Error

Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.

Rev. B | Page 26 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

SPECIAL FUNCTION REGISTER (SFR) MAPPING

Table 15.

Mnemonic Address Description

INTPR 0xFF

Interrupt pins configuration

(see Table 17). SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch Pad 2 (see Table 23). SCRATCH1 0xFB Scratch Pad 1 (see Table 22). BATVTH 0xFA

Battery detection threshold

(see Table 52). STRBPER 0xF9

Peripheral ADC strobe period

(see Table 49). IPSMF 0xF8

Power management interrupt flag

(see Table 18). TEMPCAL 0xF7

RTC temperature compensation

(see Table 135). RTCCOMP 0xF6

RTC nominal compensation

(see Table 134). BATPR 0xF5

Battery switchover configuration (see

Table 19). PERIPH 0xF4

Peripheral configuration

(see Table 20). DIFFPROG 0xF3

Temperature and supply delta

(see Table 50). B 0xF0 Auxiliary math (see Table 56). VDCINADC 0xEF V

ADC value (see Table 53).

DCIN

LCDSEGE2 0xED LCD Segment Enable 2 (see Table 98). IPSME 0xEC

Power management interrupt enable

(see Table 21). SPISTAT 0xEA SPI interrupt status (see Table 150). SPI2CSTAT 0xEA I2C interrupt status (see Table 154). SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 149). I2CADR 0xE9 I2C slave address (see Table 153). SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 148). I2CMOD 0xE8 I2C mode (see Table 152). WAV2H 0xE7 Selection 2 sample MSB (see Table 31). WAV2 M 0xE 6

Selection 2 sample middle byte

(see Table 31). WAV2L 0xE5 Selection 2 sample LSB (see Table 31). WAV1H 0xE4 Selection 1 sample MSB (see Table 31). WAV1 M 0xE 3

Selection 1 sample middle byte (see

Table 31). WAV1L 0xE2 Selection 1 sample LSB (see Table 31). ACC 0xE0 Accumulator (see Table 56). BATADC 0xDF Battery ADC value (see Table 54). MIRQSTH 0xDE Interrupt Status 3 (see Table 42). MIRQSTM 0xDD Interrupt Status 2 (see Table 41). MIRQSTL 0xDC Interrupt Status 1 (see Table 40). MIRQENH 0xDB Interrupt Enable 3 (see Table 45). MIRQENM 0xDA Interrupt Enable 2 (see Table 44). MIRQENL 0xD9 Interrupt Enable 1 (see Table 43). ADCGO 0xD8 Start ADC measurement (see Table 51).

Mnemonic Address Description

TEMPADC 0xD7 Temperature ADC value (see Table 55). IRMSH 0xD6 I IRMSM 0xD5

measurement MSB (see Table 31).

rms

measurement middle byte

rms

(see Table 31). IRMSL 0xD4 I VRMSH 0xD3 V VRMSM 0xD2

measurement LSB (see Table 31).

rms

measurement MSB (see Table 31).

rms

measurement middle byte

rms

(see Table 31). VRMSL 0xD1 V

measurement LSB (see Table 31).

rms

PSW 0xD0 Program status word (see Table 57). TH2 0xCD Timer 2 high byte (see Table 120). TL2 0xCC Timer 2 low byte (see Table 121). RCAP2H 0xCB

Timer 2 reload/capture high byte

(see Table 122). RCAP2L 0xCA

Timer 2 reload/capture low byte

(see Table 123). T2CON 0xC8 Timer/Counter 2 control (see Table 115). EADRH 0xC7 Flash high byte address (see Table 110). EADRL 0xC6 Flash low byte address (see Table 109). POWCON 0xC5 Power control (see Table 26). KYREG 0xC1 Key (see Table 126). WDCON 0xC0 Watchdog timer (see Table 85). PROTR 0xBF Flash read protection (see Table 108). PROTB1 0xBE

Flash Write/Erase Protection 1

(see Table 107). PROTB0 0xBD

Flash Write/Erase Protection 0

(see Table 106). EDATA 0xBC Flash data (see Table 105). PROTKY 0xBB Flash protection key (see Table 104). FLSHKY 0xBA Flash key (see Table 103). ECON 0xB9 Flash control (see Table 102). IP 0xB8 Interrupt priority (see Table 79). PINMAP2 0xB4

Port 2 weak pull-up enable

(see Table 159). PINMAP1 0xB3

Port 1 weak pull-up enable

(see Table 158). PINMAP0 0xB2

Port 0 weak pull-up enable

(see Table 157). LCDCONY 0xB1 LCD Configuration Y (see Table 91). CFG 0xAF Configuration (see Table 63). LCDDAT 0xAE LCD data (see Table 97). LCDPTR 0xAC LCD pointer (see Table 96). IEIP2 0xA9

Interrupt Enable and Priority 2

(see Table 80). IE 0xA8 Interrupt enable (see Table 78). DPCON 0xA7 Data pointer control (see Table 76). INTVAL 0xA6 RTC alarm interval (see Table 133). HOUR 0xA5 RTC hours counter (see Table 132). MIN 0xA4 RTC minutes counter (see Table 131). SEC 0xA3 RTC seconds counter (see Table 130).

Rev. B | Page 27 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Mnemonic Address Description

HTHSEC 0xA2

TIMECON 0xA1 RTC configuration (see Table 128). P2 0xA0 Port 2 (see Table 162). EPCFG 0x9F

SBAUDT 0x9E

SBAUDF 0x9D

LCDCONX 0x9C LCD Configuration X (see Tab le 89). SPI2CRx 0x9B SPI/I2C receive buffer (see Table 147). SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 146). SBUF 0x99 Serial port buffer (see Table 141). SCON 0x98

LCDSEGE 0x97 LCD segment enable (see Table 95 ). LCDCLK 0x96 LCD clock (see Table 92). LCDCON 0x95 LCD configuration (see Table 88). MDATH 0x94

RTC hundredths of a second counter (see Table 129).

Extended port configuration (see Table 156).

Enhanced serial baud rate control (see Table 142).

UART timer fractional divider (see Table 143).

Serial communications control (see Table 140).

Energy measurement pointer data MSB (see Tab le 31).

Mnemonic Address Description

MDATM 0x93

MDATL 0x92

MADDPT 0x91

P1 0x90 Port 1 (see Table 161). TH1 0x8D Timer 1 high byte (see Table 118). TH0 0x8C Timer 0 high byte (see Table 116). TL1 0x8B Timer 1 low byte (see Table 119). TL0 0x8A Timer 0 low byte (see Table 117). TMOD 0x89

TCON 0x88

PCON 0x87 Program control (see Table 58 ). DPH 0x83 Data pointer high (see Tab le 60). DPL 0x82 Data pointer low (see Table 5 9). SP 0x81 Stack pointer (see Tab le 62). P0 0x80 Port 0 (see Table 160).

Energy measurement pointer data middle byte (see Table 31).

Energy measurement pointer data LSB (see Tab le 31).

Energy measurement pointer address (see Tab le 30).

Timer/Counter 0 and Timer/Counter 1 mode (see Table 113).

Timer/Counter 0 and Timer/Counter 1 control (see Table 114).

Rev. B | Page 28 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

POWER MANAGEMENT

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have elaborate power management circuitry that manages the switchover from regular power supply to battery

Table 16. Power Management SFRs

SFR Address R/W Mnemonic Description

0xEC R/W IPSME Power management interrupt enable (see Tabl e 21). 0xF5 R/W BATPR Battery switchover configuration (see Table 19 ). 0xF8 R/W IPSMF Power management interrupt flag (see Tabl e 18). 0xFF R/W INTPR Interrupt pins configuration (see Table 1 7). 0xF4 R/W PERIPH Peripheral configuration (see Tab le 20). 0xC5 R/W POWCON Power control (see Table 26). 0xFB R/W SCRATCH1 Scratch Pad 1 (see Ta ble 22 ). 0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23). 0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 2 4). 0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25).

POWER MANAGEMENT REGISTER DETAILS

Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)

Bit Mnemonic Default Description

7 RTCCAL 0

[6:5] FSEL 00 Sets RTC calibration output frequency and calibration window.

4 Reserved N/A [3:1] INT1PRG 000

0 INT0PRG 0

Controls RTC calibration output. When set, the RTC calibration frequency selected by the FSEL bits is output on the P0.2/CF1/RTCCAL pin.

FSEL Result (Calibration Window, Frequency)

00 30.5 sec, 1 Hz 01 30.5 sec, 512 Hz 10 0.244 sec, 500 Hz 11 0.244 sec, 16 kHz

Controls the function of INT1

INT1PRG Result

X00 GPIO enabled X01 BCTRL enabled 01X 11X

Controls the function of INT0

INT0PRG Result 0 1

INT1 INT1

INT0 INT0

input disabled input enabled

and manages power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Tabl e 16 ).

Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)

To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to INTPR. KYREG (see Table 126) should be set to 0xEA to unlock this SFR and reset to 0 after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code:

MOV KYREG, #0EAh MOV INTPR, #080h

Rev. B | Page 29 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)

Bit Bit Address Mnemonic Default Description

7 0xFF FPSR 0

Power supply restored interrupt flag. Set when the V This occurs when the source of V

changes from V

SWOUT

6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC Reserved 0 This bit must be kept at 0 for proper operation. 3 0xFB FVADC

VDCINADC monitor interrupt flag. Set when V

DCIN

measurement is ready. 2 0xFA FBAT 1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when V 0 0xF8 FVDCIN

This feature is not available in the ADE7116.

0 V

monitor interrupt flag. Set when V

BAT

monitor interrupt flag. Set when V

DCIN

falls below BATVTH or when V

BAT

SWOUT

falls below 1.2 V.

DCIN

Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)

Bit Mnemonic Default Description

[7:2] Reserved 00 These bits must be kept at 0 for proper operation. [1:0] BATPRG 00 Control bits for battery switchover.

BATPRG Result

00 Battery switchover enabled on low VDD 01 Battery switchover enabled on low VDD and low V 1X Battery switchover disabled

power supply has been restored.

to VDD.

BAT

changes by VDCIN_DIFF or when V

measurement is ready.

BAT

switches from VDD to V

DCIN

BAT.

DCIN

Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)

Bit Mnemonic Default Description

7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to V

SWOUT

(0: V

SWOUT

= V

BAT

; 1: V

SWOUT

= VDD). 5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation. 4 PLL_FLT 0

If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the PLL_FLT bit.

3 REF_BAT_EN 0

Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in

PSM1 and PSM2 mode. 2 Reserved 0 This bit must be kept at 0 for proper operation. [1:0] RXPROG 00 Controls the function of the P1.0/RxD pin.

RXPROG Result

00 GPIO 01 RxD with wake-up disabled 11 RxD with wake-up enabled

Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)

Bit Mnemonic Default Description

7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set. 6 Reserved 0 Reserved. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set. 4 Reserved 0 This bit must be kept at 0 for proper operation. 3 EVADC 2 EBAT1 0 Enables a PSM interrupt when the V

0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.

monitor interrupt flag (FBAT) is set.

BAT

1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set. 0 EVDCIN1 0 Enables a PSM interrupt when the V

This feature is not available in the ADE7116.

monitor interrupt flag (FVDCIN) is set.

DCIN

Rev. B | Page 30 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)

Bit Mnemonic Default Description

[7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)

Bit Mnemonic Default Description

[7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)

Bit Mnemonic Default Description

[7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)

Bit Mnemonic Default Description

[7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes.

Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)

Note that these scratch pad registers are cleared only when the part loses VDD and V

Table 26. Power Control SFR (POWCON, Address 0xC5)

Bit Mnemonic Default Description

7 Reserved 1 Reserved. 6 METER_OFF 0

Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if

metering functions are not needed in PSM0 mode. 5 Reserved 0 This bit should be kept at 0 for proper operation. 4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode. 3 Reserved 0 Reserved. [2:0] CD 010 Controls the core clock frequency, f

CD Result (f

in MHz)

CORE

000 4.096

001 2.048

010 1.024

011 0.512

100 0.256

101 0.128

110 0.064

111 0.032

BAT

CORE

. f

= 4.096 MHz/2CD.

CORE

Writing to the Power Control SFR (POWCON, Address 0xC5)

Writing data to the POWCON SFR involves writing 0xA7 into the key SFR (KYREG, Address 0xC1), which is described in Table 126, followed by a write to the POWCON SFR. For example,

MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR MOV POWCON,#10h ;Shut down the core

Rev. B | Page 31 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

POWER SUPPLY ARCHITECTURE

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two power supply inputs, V

require only a single 3.3 V power supply at V

and V

, which

BAT

for full operation.

A battery backup, or secondary power supply, with a maximum of 3.7 V can be connected to the V

input. Internally, the

BAT

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 connect V the device circuitry. The V the internal power supply (V

or V

BAT

to V

, which is used to derive power for

SWOUT

output pin reflects the voltage at

SWOUT

) and has a maximum output

SWOUT

current of 6 mA. This pin can also be used to power a limited number of peripheral components. The 2.5 V analog supply (V and the 2.5 V supply for the core logic (V chip linear regulators from V

. Figure 32 shows the power

SWOUT

) are derived by on-

INTD

INTA

supply architecture of the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide automatic battery switchover between V and V

based on the voltage level detected at VDD or V

BAT

DCIN

. In addition, the BCTRL input can be used to trigger a battery switchover. The conditions for switching V V

and back to VDD are described in the Battery Switchover

BAT

section. V

is an input pin that can be connected to a 0 V to

DCIN

from VDD to

SWOUT

3.3 V dc signal. This input is intended for power supply supervisory purposes and does not provide power to the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 circuitry.

DCINVDDVBAT

BCTRL

*NOT AVAILABLE IN THE ADE7116.

POWER SUPPLY

MANAGEMENT

SCRATCH PAD LCD RTC

TEMPERATURE ADC

Figure 32. Power Supply Architecture

ADC

SWOUT

INTD

LDO

INTA

LDO

3.3V

MCU

ADE

SPI/I2C

UART

2.5V

BATTERY SWITCHOVER

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

, V

ADE7569 monitor V over from V the V

to V

, V

, or BCTRL pin. Battery switchover is enabled by

DCIN

BAT

, and V

BAT

can be configured based on the status of

default. Setting Bit 1 in the Battery Switchover Configuration SFR (BATPR, Address 0xF5) disables battery switchover so that V is always connected to V V

is indicated by Bit 6 in the Peripheral Configuration SFR

SWOUT

(PERIPH, Address 0xF4), which is described in Ta b le 2 0 . Bit 6 is set when V connected to V

is connected to VDD and cleared when V

SWOUT

BAT

. Automatic battery switch-

DCIN

(see Tab l e 1 9 ). The source of

SWOUT

)

06353-011

The battery switchover functionality provided by the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 allows a seamless transition from V

to V

. An automatic battery

BAT

switchover option ensures a stable power supply to the device, as long as the external battery voltage is above 2.75 V. It allows continuous code execution even while the internal power supply is switching from V energy metering ADCs are not available when V used for V

SWOUT

to V

and back. Note that the

BAT

is being

BAT

Power supply monitor (PSM) interrupts can be enabled to indicate when battery switchover occurs and when the V

power supply is restored (see the Power Supply Management (PSM) Interrupt section.)

to V

BAT

The following three events switch the internal power supply (V

) from VDD to V

SWOUT

• V

DCIN

switches from V

< 1.2 V. When V

BAT

falls below 1.2 V, V

DCIN

to V

. This event is enabled when the

BAT

SWOUT

BATPRG[1:0] bits in the battery switchover configuration SFR (BATPR, Address 0xF5) = 0b01. Setting these bits disables switchover based on V low V

• V

switches from V

is disabled by default.

DCIN

< 2.75 V. When VDD falls below 2.75 V, V

to V

. This event is enabled when the

BAT

. Battery switchover on

DCIN

SWOUT

BATPRG[1:0] bits in the BATPR SFR are cleared.

• Falling edge on BCTRL. When the battery control pin,

BCTRL, goes low, V external switchover signal can trigger a switchover to V

switches from VDD to V

SWOUT

BAT

. This

BAT

at any time. Setting the INT1PRG bits to X01 in the interrupt pins configuration SFR (INTPR, Address 0xFF) enables the battery control pin (see Tab l e 1 7 ).

Switching from V

To s wit c h V

SWOUT

to VDD

BAT

from V

to VDD, all of the following events

BAT

must be true:

• V

> 2.75 V. V

switches back to VDD after VDD remains

SWOUT

above 2.75 V.

• V

> 1.2 V and VDD > 2.75 V. If the low V

DCIN

is enabled, V above 1.2 V and V

switches to VDD after V

SWOUT

remains above 2.75 V.

DCIN

condition

remains

• Rising edge on BCTRL. If the battery control pin is enabled,

switches back to VDD after BCTRL is high, and the

SWOUT

first or second bullet point is satisfied.

Rev. B | Page 32 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

The power supply monitor interrupt alerts the 8052 core of power supply events. The PSM interrupt is disabled by default. Setting the EPSM bit in the interrupt enable and Priority 2 SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see Tab l e 80 ).

EPSR FPSR

ESAG FSAG

EVADC

FVADC

EBAT FBAT

EBSO FBSO

EVDCIN FVDCIN

FPSM

EPSM

The power management interrupt enable SFR (IPSME, Address 0xEC) controls the events that result in a PSM interrupt (see Table 2 1). Figure 33 illustrates how the PSM interrupt vector is shared among the PSM interrupt sources. The PSM interrupt flags are latched and must be cleared by writing to the IPSMF power management interrupt flag SFR, Address 0xF8 (see Table 1 8).

TRUE?

PENDING PSM

INTERRUPT

IPSME ADDR. 0xEC

IPSMF ADDR. 0xF8

IEIP2 ADDR. 0xA9

NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN.

*NOT AVAILABLE I N THE ADE7116.

EPSR RESERVED ESAG RESERVED EVADC* EBAT* EBSO EVDCIN*

FPSR FPSM FSAG RESERVED FVADC* FBAT* FBSO FVDCIN*

RESERVED PTI RESERVED PSI EADE ETI EPSM ESI

06353-012

Figure 33. Power Supply Management Interrupt Sources

Rev. B | Page 33 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Battery Switchover and Power Supply Restored PSM Interrupt

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can be configured to generate a PSM interrupt when the source of V

changes from VDD to V

SWOUT

, indicating

BAT

battery switchover. Setting the EBSO bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt (see Ta b l e 2 1 ).

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can also be configured to generate an interrupt when the source of V the V

power supply has been restored. Setting the EPSR bit in

changes from V

SWOUT

to VDD, indicating that

BAT

the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt.

The flags in the IPSMF SFR for these interrupts, FBSO and FPSR, are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, FBSO and FPSR, are latched. These events must be cleared by writing a 0 to these bits. Bit 6 (VSWSOURCE) in the peripheral configuration SFR (PERIPH, Address 0xF4) tracks the source of V V

and cleared when V

ADC PSM Interrupt

DCIN

. The bit is set when V

SWOUT

is connected to V

SWOUT

is connected to

SWOUT

BAT

The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 can be configured to generate a PSM interrupt when V

DCIN

changes magnitude by more than a configurable threshold. This threshold is set in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), which is described in Ta b le 5 0 . See the External Voltage Measurement section for more information. Setting the EVADC bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt. Note that this feature is not available in the ADE7116.

The V

voltage is measured using a dedicated ADC. These

DCIN

measurements take place in the background at intervals to check the change in V

. Conversions can also be initiated by writing to

DCIN

the start ADC measurement SFR (ADCGO, Address 0xD8), as described in Ta ble 5 1. The FVADC flag in the power management interrupt flag SFR (IPSMF, Address 0xF8) indicates when a V

measurement is ready. See the External Voltage

DCIN

Measurement section for details on how V

is measured.

DCIN

Monitor PSM Interrupt

BAT

The V

voltage is measured using a dedicated ADC. These

BAT

measurements take place in the background at intervals to check the change in V

. The FBAT bit is set when the battery

BAT

level is lower than the threshold set in the battery detection threshold SFR (BATVTH, Address 0xFA), described in Tabl e 52 , or when a new measurement is ready in the battery ADC value SFR (BATADC, Address 0xDF), described in Ta b l e 54. See the Battery Measurement section for more information. Setting the EBAT bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt. Note that this feature is not available in the ADE7116.

Monitor PSM Interrupt

DCIN

The V

voltage is monitored by a comparator. The FVDCIN

DCIN

bit in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set when the V

input level is lower than

DCIN

1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this event to generate a PSM interrupt. This event, which is associated with the SAG monitoring, can be used to detect that a power supply (V prior to initiating a switch from V

) is compromised and to trigger further actions

to V

. Note that this

BAT

feature is not available in the ADE7116.

SAG Monitor PSM Interrupt

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 energy measurement DSP monitors the ac voltage input at the V

and VN input pins. The SAGLVL register

(Address 0x14) is used to set the threshold for a line voltage SAG event. The FSAG bit in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register (Address 0x13). See the Line Voltage SAG Detection section for more information. Setting the ESAG bit in the power management interrupt enable SFR (IPSME, Address 0xEC) enables this event to generate a PSM interrupt.

Rev. B | Page 34 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

USING THE POWER SUPPLY FEATURES

In an energy meter application, the 3.3 V power supply (VDD) is typically generated from the ac line voltage and regulated to 3.3 V by a voltage regulator IC. The preregulated dc voltage, typically 5 V to 12 V, can be connected to V A 3.6 V battery can be connected to V the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 power supply inputs are set up in this application.

Figure 35 shows the sequence of events that occurs if the main power supply generated by the PSU starts to fail in the power meter application shown in Figure 34. The SAG detection can provide the earliest warning of a potential problem on V

(240V, 220V, 110V TYPICAL)

AC INPUT

through a resistor divider.

DCIN

. Figure 34 shows how

BAT

BCTRL

When a SAG event occurs, user code can be configured to back up data and prepare for battery switchover if desired. The relative spacing of these interrupts depends on the design of the power supply.

Figure 36 shows the sequence of events that occurs if the main power supply starts to fail in the power meter application shown in Figure 34, with battery switchover on low V

or low VDD

DCIN

enabled.

Finally, the transition between V

and V

and the different

BAT

power supply modes (see the Operating Modes section) are represented in Figure 37 and Figure 38.

SAG

DETECT ION

5V TO 12V DC

PSU

3.3V

REGULATOR

SWOUT

DCIN

BAT

VOLTAG E

SUPERVISORY

VOLTAG E

SUPERVISORY

POWER SUPPLY

MANAGEMENT

IPSMF SFR

(ADDR. 0xF8)

06353-013

Figure 34. Power Supply Management for Energy Meter Application

VP – V

SAG LEVEL TRIP POINT

SAGCYC = 1

DCIN

1.2V

2.75V

SAG EVENT

(FSAG = 1)

EVENT

DCIN

(FVDCIN = 1)

Figure 35. Power Supply Management Interrupts and Battery Switchover with Only V

Rev. B | Page 35 of 152

IF SWITCHOVER ON LOW VDD IS ENABLED,

AUTOMATIC BAT TERY SWI TCHOVER

OCCURS. V

Enabled for Battery Switchover

IS CONNECTED TO V

SWOUT

BSO EVENT

(FBSO = 1)

BAT

06353-014

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 27. Power Supply Event Timing Operating Modes

Parameter Time Description

t1 10 ns min Time between when V t2 10 ns min Time between when VDD falls below 2.75 V and when battery switchover occurs. t3 30 ms typ

Time between when V battery switchover.

t4 130 ms typ

Time between when power supply restore conditions are met (V 0b01 or V

> 2.75 V if BATPRG[1:0] = 0b00) and when V

VP– V

SAG LEVEL TRIP POINT SAGCYC = 1

DCIN

1.2V

2.75V

goes below 1.2 V and when FVDCIN is raised.

DCIN

falls below 1.2 V and when battery switchover occurs if V

DCIN

> 1.2 V and VDD > 2.75 V if BATPRG[1:0] =

DCIN

switches to VDD.

SWOUT

is enabled to cause

DCIN

SAG EVENT

(FSAG = 1)

Figure 36. Power Supply Management Interrupts and Battery Switchover with V

EVENT

DCIN

(FVDCIN = 1)

IF SWITCHOVER ON LOW V ENABLED, AUTO MATIC BATTERY

SWITCHOVER OCCURS. V

IS CONNECTED TO V

BSO EVENT

(FBSO = 1)

or V

Enabled for Battery Switchover

DCIN

SWOUT

BAT

06353-015

VP − V

SAG LEVEL TRIP POINT

EVENT

DCIN

1.2V

2.75V

BATTERY SWITCH

ENABLED ON

LOW V

DCIN

SAG EVENT

BAT

PSM0 PSM0

DCIN

30ms MIN.

DCIN

130ms MIN.

PSM1 OR PSM2

EVENT

BATTERY SWITCH

ENABLED ON

LOW V

PSM0 PSM0

PSM1 OR PSM2

06353-016

Figure 37. Power Supply Management Transitions Between Modes

Rev. B | Page 36 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

OPERATING MODES

PSM0 (NORMAL MODE)

In PSM0, or normal operating mode, V

. All of the analog circuitry and the digital circuitry powered

by V default clock frequency, f

INTD

and V

are enabled by default. In normal mode, the

INTA

, which is established during a

CORE

power-on reset or software reset, is 1.024 MHz.

is connected to

SWOUT

PSM1 (BATTERY MODE)

In PSM1, or battery mode, V operating mode, the 8052 core and all of the digital circuitry are enabled by default. The analog circuitry for the ADE energy metering DSP powered by V automatically restarts, and the switch to the V occurs, when the V

supply is >2.75 V and the PWRDN bit in

the MODE1 register (Address 0x0B) is cleared (see Table 33). The default f

for PSM1, established during a power-on reset or

CORE

software reset, is 1.024 MHz.

is connected to V

SWOUT

is disabled. This analog circuitry

INTA

. In this

BAT

power supply

PSM2 (SLEEP MODE)

PSM2 is a low power consumption sleep mode for use in battery operation. In this mode, V

is connected to V

SWOUT

2.5 V digital and analog circuitry powered through V is disabled, including the MCU core, resulting in the following:

• The RAM in the MCU is no longer valid.

. All of the

BAT

and V

INTA

INTD

• The program counter for the 8052, also held in volatile

memory, becomes invalid when the 2.5 V supply is shut down. Therefore, the program does not resume from where it left off but always starts from the power-on reset vector when the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 exit PSM2.

The 3.3 V peripherals (temperature ADC

, V

DCIN

ADC1, RTC, and LCD) are active in PSM2. They can be enabled or disabled to reduce power consumption and are configured for PSM2 operation when the MCU core is active (see Table 29 for more information about the peripherals and their PSM2 configuration). The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 remain in PSM2 until an event occurs to wake them up.

In PSM2 mode, the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 provide four scratch pad RAM SFRs that are maintained during this mode. These SFRs can be used to save data from PSM0 or PSM1 mode when entering PSM2 mode (see Table 22 to Table 25).

In PSM2, the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 maintain some SFRs (see Table 28). The SFRs that are not listed in this table should be restored when the part enters PSM0 or PSM1 mode from PSM2 mode.

Table 28. SFRs Maintained in PSM2 Mode

I/O Configuration Power Supply Management RTC Peripherals LCD Peripherals

Interrupt pins configuration SFR (INTPR, Address 0xFF); see Table 17

Peripheral configuration SFR (PERIPH, Address 0xF4); see Table 20

Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2); see Table 157

Port 1 weak pull-up enable SFR (PINMAP1, Address 0xB3); see Table 158

Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4); see Table 159

Scratch Pad 1 SFR (SCRATCH1, Address 0xFB); see Table 22

Battery detection threshold SFR (BATVTH, Address 0xFA); see Table 52

Battery switchover configuration SFR (BATPR, Address 0xF5); see Table 19

Battery ADC value SFR (BATADC, Address 0xDF); see Table 54

Peripheral ADC strobe period SFR (STRBPER, Address 0xF9); see Table 491

Temperature and supply delta SFR (DIFFPROG, Address 0xF3); see Tab le 501

ADC value SFR (VDCINADC,

DCIN

Address 0xEF); see Table 53

RTC nominal compensation SFR (RTCCOMP, Address 0xF6); see Table 134

RTC temperature compensation SFR (TEMPCAL, Address 0xF7); see Table 135

RTC configuration SFR (TIMECON, Address 0xA1); see Table 128

Hundredths of a second counter SFR (HTHSEC, 0xA2); see Table 129

Seconds counter SFR (SEC, 0xA3); see Table 130

Minutes counter SFR (MIN, 0xA4); see Table 131

LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED); see Table 98

LCD Configuration Y SFR (LCDCONY, Address 0xB1); see Table 91

LCD Configuration X SFR (LCDCONX, Address 0x9C); see Table 89

LCD configuration SFR (LCDCON, Address 0x95); see Table 88

LCD clock SFR (LCDCLK, Address 0x96); see Table 92

LCD segment enable SFR (LCDSEGE, Address 0x97); see Table 95

Scratch Pad 2 SFR (SCRATCH2, Address 0xFC); see Table 23

Temperature ADC value SFR (TEMPADC, Address 0xD7); see

Hours counter SFR (HOUR, 0xA5); see Table 132

LCD pointer SFR (LCDPTR, Address 0xAC); see Table 96

Table 551

Scratch Pad 3 SFR (SCRATCH3, Address 0xFD); see Table 24

Scratch Pad 4 SFR (SCRATCH4,

Alarm interval SFR (INTVAL, 0xA6); see Table 133

LCD data SFR (LCDDAT, Address 0xAE); see Table 97

Address 0xFE); see Table 25

This feature is not available in the ADE7116.

Rev. B | Page 37 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

3.3 V PERIPHERALS AND WAKE-UP EVENTS

Some of the 3.3 V peripherals are capable of waking the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2 mode. The events that can cause the devices to wake up from PSM2 mode are listed in the Wake-Up Event column in Tabl e 29.

Table 29. 3.3 V Peripherals and Wake-Up Events

Wake -

3.3 V Peripheral

Temperature

Up Event

Wake-Up Enable Bits

Flag

Interrupt Vec tor

∆T Maskable

ADC

ADC ΔV Maskable FVADC IPSM

DCIN

Power Supply

PSR Nonmaskable PSR IPSM

Management

RTC Midnight Nonmaskable Midnight IRTC

Alarm Maskable ALARM IRTC

I/O Ports

Rx Edge

External

INT0

INT1

INT0PRG = 1 IE0

INT1PRG = 11x IE1

RXPROG[1:0] = 11

PERIPH[7] (RXFG)

RESET Nonmaskable

Reset

LCD

Scratch Pad The four SCRATCHx registers remain intact in PSM2 mode.

All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2), Port 1

weak pull-up enable SFR (PINMAP1, Address 0xB3), and Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4) to decrease current consumption. The interrupts can be enabled or disabled.

The interrupt flag associated with these events must be cleared prior to executing instructions that put the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 in PSM2 mode after wake-up.

Comments

The temperature ADC can wake up the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569. A pending interrupt is generated according to the description in the Temperature Measurement section. This wake-up event can be disabled by disabling temperature measurements in the temperature and supply delta SFR (DIFFPROG, Address 0xF3) in PSM2 mode. The temperature interrupt needs to be serviced and acknowledged prior to entering PSM2 mode.

The V

measurement can wake up the ADE7156/ADE7166/

DCIN

ADE7169/ADE7566/ADE7569. FVADC is set according to the description in the External Voltage Measurement section. This wakeup event can be disabled by clearing EVADC in the power management interrupt enable SFR (IPSME, Address 0xEC); see Table 21. The FVADC flag needs to be cleared prior to entering PSM2 mode.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 wake up if the power supply is restored (if V

). The VSWSOURCE flag, Bit 6 of the peripheral configuration SFR

to V

(PERIPH, Address 0xF4), is set to indicate that V

switches to be connected

SWOUT

is connected to VDD.

SWOUT

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 wake up at midnight every day to update their calendars. The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode.

An alarm can be set to wake the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 after the desired amount of time. The RTC alarm is enabled by setting the ALARM bit in the RTC configuration SFR (TIMECON, 0xA1). The RTC interrupt needs to be serviced and acknowledged prior to entering PSM2 mode.

The edge of the interrupt is selected by the IT0 bit in the TCON SFR (TCON, Address 0x88). The IE0 flag bit in the TCON SFR is not affected. The Interrupt 0 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode.

The edge of the interrupt is selected by the IT1 bit in the TCON SFR (TCON, Address 0x88). The IE1 flag bit in the TCON SFR is not affected. The Interrupt 1 interrupt needs to be serviced and acknowledged prior to entering PSM2 mode.

An Rx edge event occurs if a rising or falling edge is detected on the Rx line. The UART RxD flag needs to be cleared prior to entering PSM2 mode.

If the RESET

pin is brought low while the ASE7116/ADE7156/

ADE7166/ADE7169/ADE7566/ADE7569 are in PSM2 mode, they wake up to PSM1 mode.

The LCD can be enabled/disabled in PSM2 mode. The LCD data memory remains intact.

Rev. B | Page 38 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TRANSITIONING BETWEEN OPERATING MODES

The operating mode of the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 is determined by the power supply connected to V supply, such as when V

switches to VDD, alter the operating mode. This section

SWOUT

describes events that change the operating mode.

Automatic Battery Switchover (PSM0 to PSM1)

If any of the enabled battery switchover events occurs (see the Battery Switchover section), V switchover results in a transition from PSM0 to PSM1 operating mode. When battery switchover occurs, the analog circuitry used in the ADE energy measurement DSP is disabled. To reduce power consumption, the user code can initiate a transition to PSM2.

Entering Sleep Mode (PSM1 to PSM2)

To reduce power consumption when VSWOUT is connected to

, user code can initiate sleep mode, PSM2, by setting Bit 4

BAT

in the power control SFR (POWCON, Address 0xC5) to shut down the MCU core. Events capable of waking the MCU can be enabled (see the 3.3 V Peripherals and Wake-Up Events section).

Servicing Wake-Up Events (PSM2 to PSM1)

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 may need to wake up from PSM2 mode to service wake-up events (see the 3.3 V Peripherals and Wake-Up Events). PSM1 code execution begins at the power-on reset vector. After servicing the wake-up event, the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 can return to PSM2 mode by setting Bit 4 in the power control SFR (POWCON, Address 0xC5) to shut down the MCU core.

. Therefore, changes in the power

SWOUT

switches from VDD to V

SWOUT

switches to V

SWOUT

BAT

or when

BAT

. This

POWER SUPPLY

RESTORED

Automatic Switch to VDD (PSM2 to PSM0)

If the conditions to switch V

SWOUT

from V

to VDD occur (see

BAT

the Battery Switchover section), the operating mode switches to PSM0. When this switch occurs, the analog circuitry used in the ADE energy measurement DSP automatically restarts. Note that code execution continues normally. A software reset can be performed to start PSM0 code execution at the power-on reset vector.

USING THE POWER MANAGEMENT FEATURES

Because program flow is different for each operating mode, the status of V bit in the peripheral configuration SFR (PERIPH, Address 0xF4) indicates the power supply to which V (see Tabl e 20 ). This bit can be used to control program flow on wake-up. Because code execution always starts at the power-on reset vector, Bit 6 of the PERIPH SFR can be tested to determine which power supply is being used and to branch to normal code execution or to wake up event code execution. Power supply events can also occur when the MCU core is active. To be aware of the events that change what V following guidelines:

• Enable the battery switchover interrupt (EBSO)

if V

• Enable the power supply restored interrupt (EPSR)

if V

An early warning that battery switchover is about to occur is provided by SAG detection and, possibly, by low V (see the Battery Switchover section).

For a user-controlled battery switchover, enable automatic battery switchover on low V event to generate the PSM interrupt. When a low V occurs, start data backup. Upon completion of the data backup, enable battery switchover on low V occurs 30 ms later.

must be known at all times. The VSWSOURCE

SWOUT

is connected to, use the

SWOUT

= VDD at power-up.

SWOUT

= V

SWOUT

at power-up.

BAT

only. Next, enable the low V

. Battery switchover

DCIN

is connected

detection

DCIN

event

DCIN

NORMAL MODE

CONNECT ED TO V

SWOUT

PSM0

AUTOMATIC BATTERY

SWITCHOVER

POWER SUPPLY

RESTORED

PSM2

SLEEP MODE

CONNECTED TO V

SWOUT

Figure 38. Transitioning Between Operating Modes

Rev. B | Page 39 of 152

BAT

SWOUT

WAKE-UP

EVENT

BATTERY MODE

CONNECT ED TO V

PSM1

BAT

USER CODE DIRECTS MCU

TO SHUT DOWN CORE AFTER

SERVICING WAKE-UP EVENT

06353-017

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ENERGY MEASUREMENT

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 offer a fixed function, energy measurement, digital processing core that provides all the information needed to measure energy in single-phase energy meters. The part provides two ways to access the energy measurements: direct access through SFRs for time sensitive information and indirect access through address and data SFRs for the majority of energy measurements. The I

, V

, interrupts, and waveform registers

rms

are readily available through the SFRs, as shown in Ta bl e 3 1 . Other energy measurement information is mapped to a page of memory that is accessed indirectly through the MADDPT, MDATL, MDATM, and MDATH SFRs. The address and data SFRs act as pointers to the energy measurement internal registers.

ACCESS TO ENERGY MEASUREMENT SFRs

Access to the energy measurement SFRs is achieved by reading or writing to the SFR addresses provided in Tab le 3 1 . The internal data for the MIRQx SFRs is latched byte by byte into the SFR when the SFR is read.

The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte SFRs. The 24-bit data is latched into these SFRs when the high byte is read. Reading the low or medium byte before the high byte results in reading the data from the previous latched sample.

Sample code to read the VRMSx register is as follows:

MOV R1, VRMSH //latches data in VRMSH, VRMSM, and VRMSL SFRs

MOV R2, VRMSM MOV R3, VRMSL

ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS

Access to the internal energy measurement registers is achieved by writing to the energy measurement pointer address SFR (MADDPT, Address 0x91). This SFR selects the energy measurement register to be accessed and determines whether a read or a write is performed (see Ta b le 3 0 ).

Table 30. Energy Measurement Pointer Address SFR (MADDPT, Address 0x91)

Bit Description

7 1 = write, 0 = read [6:0] Energy measurement internal register address

Writing to the Internal Energy Measurement Registers

When Bit 7 of the energy measurement pointer address SFR (MADDPT, Address 0x91) is set, the content of the MDATx SFRs (MDATL, MDATM, and MDATH) is transferred to the internal energy measurement register designated by the address

in the MADDPT SFR. If the internal register is one byte long, only the MDATL SFR content is copied to the internal register, and the MDATM SFR and MDATH SFR contents are ignored.

The energy measurement core functions with an internal clock of 4.096 MHz/5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096 MHz2

, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is written to the internal energy measurement registers, a small wait period needs to be implemented before another read or write to these registers can take place.

Sample code to write 0x0155 to the 2-byte SAGLVL register located at Address 0x14 in the energy measurement memory space is as follows:

MOV MDATM,#01h MOV MDATL,#55h MOV MADDPT,#SAGLVL_W (Address 0x94) MOV A,#05h DJNZ ACC,$

;Next write or read to energy measurement SFR can be done after this.

Reading the Internal Energy Measurement Registers

When Bit 7 of the energy measurement pointer address SFR (MADDPT, Address 0x91) is cleared, the content of the internal energy measurement register designated by the address in MADDPT is transferred to the MDATx SFRs. If the internal register is one byte long, only the MDATL SFR content is updated with a new value, and the MDATM SFR and MDATH SFR contents are reset to 0x00.

The energy measurement core functions with an internal clock of 4.096 MHz/5 or 819.2 kHz. Because the 8052 core functions with another clock, 4.096 MHz2

, synchronization between the two clock environments when CD = 0 or 1 is an issue. When data is read from the internal energy measurement registers, a small wait period needs to be implemented before the MDATx SFRs are transferred to another SFR.

Sample code to read the peak voltage in the 2-byte VPKLVL register located at 0x16 into the data pointer is as follows:

MOV MADDPT,#VPKLVL_R (Address 0x16) MOV A,#05h DJNZ ACC,$ MOV DPH,MDATM MOV DPL,MDATL

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 31. Energy Measurement SFRs

Address R/W Mnemonic Description

0x91 R/W MADDPT Energy measurement pointer address. 0x92 R/W MDATL Energy measurement pointer data LSB. 0x93 R/W MDATM Energy measurement pointer data middle byte. 0x94 R/W MDATH Energy measurement pointer data MSB. 0xD1 R VRMSL V 0xD2 R VRMSM V 0xD3 R VRMSH V 0xD4 R IRMSL I 0xD5 R IRMSM I 0xD6 R IRMSH I 0xD9 R/W MIRQENL Energy measurement interrupt enable LSB. 0xDA R/W MIRQENM Energy measurement interrupt enable middle byte. 0xDB R/W MIRQENH Energy measurement interrupt enable MSB. 0xDC R/W MIRQSTL Energy measurement interrupt status LSB. 0xDD R/W MIRQSTM Energy measurement interrupt status middle byte. 0xDE R/W MIRQSTH Energy measurement interrupt status MSB. 0xE2 R WAV1L Selection 1 sample LSB. 0xE3 R WAV1M Selection 1 sample middle byte. 0xE4 R WAV1H Selection 1 sample MSB. 0xE5 R WAV2L Selection 2 sample LSB. 0xE6 R WAV2M Selection 2 sample middle byte. 0xE7 R WAV2H Selection 2 sample MSB.

×1, ×2, ×4, ×8, ×16

{GAIN[ 2:0]}

PGA1

PGA2

ADC

HPF

ADC

INTEGRATOR

PHCAL[7:0]

HPF

Figure 39. ADE7566 and ADE7569 Energy Metering Block Diagram

measurement LSB.

rms

measurement middle byte.

rms

measurement MSB.

rms

measurement LSB.

rms

measurement middle byte.

rms

measurement MSB.

rms

MULTIPLIER

LPF2

WATTOS[15:0]

IRMSOS[11:0]

LPF

VRMSOS[11:0]

LPF

LPF2

WGAIN[11:0]

VARO S[ 15: 0]

VADIV[7:0]

VARGAIN[ 11:0]

VAGAIN[11:0]

VARDIV[7:0]

METERING SFRs

CF1NUM[15:0]

DFC

CF1DEN[15:0]

CF2NUM[15:0]

DFC

WDIV[7:0]

CF2DEN[15:0]

CF1

CF2

06353-092

Rev. B | Page 41 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

×1, ×2, ×4, ×8, ×16

{GAIN[ 2:0]}

PGA1

PGA2

ADC

HPF

IBGAIN[11:0]

ADC

INTEGRATOR

PHCAL[7:0]

HPF

MULTIPLIER

IRMSOS[11:0]

VRMSOS[11:0]

LPF

WGAIN[11:0]

LPF2

WATTOS[15:0]

VARGAIN[ 11 :0]

LPF2

VAROS[15:0]

VAGAIN[11:0]

VADIV[7:0]

VARDIV[7:0]

METERI NG SFRs

WDIV[7:0]

DFC

CF1NUM[15:0]

CF1DEN[15:0]

CF2NUM[15:0]

CF2DEN[15:0]

CF1

CF2

06353-118

Figure 40. ADE7116, ADE7156, ADE7166, and ADE7169 Energy Metering Block Diagram

Rev. B | Page 42 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ENERGY MEASUREMENT REGISTERS

Table 32. Energy Measurement Register List

Address MADDPT[6:0] Mnemonic R/W

0x01 WATTHR R 24 S 0 Reads Wh accumulator without reset. 0x02 RWATTHR R 24 S 0 Reads Wh accumulator with reset. 0x03 LWATTHR R 24 S 0 Reads Wh accumulator synchronous to line cycle. 0x04 VARHR 0x05 RVARHR 0x06 LVARHR

R 24 S 0 Reads VARh accumulator with reset.

R 24 S 0 Reads VARh accumulator synchronous to line cycle.

0x07 VAHR R 24 S 0

0x08 RVAHR R 24 S 0

0x09 LVAHR R 24 S 0

0x0A PER_FREQ R 16 U 0 Reads line period or frequency register depending on MODE2 register. 0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33). 0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Tabl e 34). 0x0D WAVMODE R/W 8 U 0

0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36). 0x0F ACCMODE R/W 8 U 0

0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section). 0x11 ZXTOUT R/W 12 0x0FFF

0x12 LINCYC R/W 16 U 0xFFFF

0x13 SAGCYC R/W 8 U 0xFF

0x14 SAGLVL R/W 16 U 0

0x15 IPKLVL R/W 16 U 0xFFFF

0x16 VPKLVL R/W 16 U 0xFFFF

0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section). 0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section). 0x19 VPEAK R 24 U 0

0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section). 0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 3 8). 0x1C IBGAIN

0x1D WGAIN R/W 12 S 0 Sets watt gain register. 0x1E VARGAIN

R/W 12 S 0 Sets var gain register.

0x1F VAGAIN R/W 12 S 0 Sets VA gain register. 0x20 WATTOS R/W 16 S 0 Sets watt offset register. 0x21 VAROS

R/W 16 S 0 Sets var offset register.

0x22 IRMSOS R/W 12 S 0 Sets current rms offset register. 0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register. 0x24 WDIV R/W 8 U 0 Sets watt energy scaling register.

Length (Bits)

Signed/ Unsigned Default Description

R 24 S 0 Reads VARh accumulator without reset.

Reads VAh accumulator without reset. If the VARMSCFCON bit in the MODE2 register (Address 0x0C) is set, this register accumulates I

Reads VAh accumulator with reset. If the VARMSCFCON bit in the MODE2 register (Address 0x0C) is set, this register accumulates I

Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON bit in the MODE2 register (Address 0x0C) is set, this register accumulates

rms

Sets configuration of Waveform Sample 1 and Waveform Sample 2 (see Tab le 35).

Sets configuration of watt and var accumulation and various tamper alarms (see Tabl e 37).

Sets timeout for zero-crossing timeout detection (see the ZeroCrossing Timeout section).

Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR accumulators.

Sets number of half-line cycles for SAG detection (see the Line Voltage SAG Detection section).

Sets detection level for SAG detection (see the Line Voltage SAG Detection section).

Sets peak detection level for current peak detection (see the Peak Detection section).

Sets peak detection level for voltage peak detection (see the Peak Detection section).

Reads voltage peak level without reset (see the Peak Detection section).

R/W 12 S 0 Sets matching gain for IPB current input.

rms

Rev. B | Page 43 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Address MADDPT[6:0] Mnemonic R/W

0x25 VARDIV R/W 8 U 0 Sets var energy scaling register. 0x26 VADIV R/W 8 U 0 Sets VA energy scaling register. 0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register. 0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register. 0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register. 0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register. 0x3B Reserved 0 This register must be set to its default value for proper operation. 0x3C Reserved 0x0300 This register must be set to its default value for proper operation. 0x3D CALMODE

0x3E Reserved 0 This register must be set to its default value for proper operation. 0x3F Reserved 0 This register must be set to its default value for proper operation.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

This function is not available in the ADE7566 or ADE7569.

ENERGY MEASUREMENT INTERNAL REGISTER DETAILS

Table 33. MODE1 Register (MODE1, Address 0x0B)

Bit Mnemonic Default Description

7 SWRST 0 Setting this bit resets all of the energy measurement registers to their default values. 6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter. 5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor. 4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC. 3 PWRDN 0 Setting this bit powers down voltage and current ADCs. 2 DISCF2 1 Setting this bit disables Frequency Output CF2. 1 DISCF1 1 Setting this bit disables Frequency Output CF1. 0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels.

Length (Bits)

Signed/ Unsigned Default Description

R/W 8 U 0 Set calibration mode.

Table 34. MODE2 Register (MODE2, Address 0x0C)

Bit Mnemonic Default Description

[7:6] CF2SEL 01 Configuration bits for CF2 output.

CF2SEL Result

00 CF2 frequency is proportional to active power. 01 CF2 frequency is proportional to reactive power.

1X CF2 frequency is proportional to apparent power or I

[5:4] CF1SEL 00 Configuration bits for CF1 output.

CF1SEL Result

00 CF1 frequency is proportional to active power. 01 CF1 frequency is proportional to reactive power.

1X CF1 frequency is proportional to apparent power or I 3 VARMSCFCON 0

Configuration bits for apparent power or I

for CF1, CF2 outputs and VA accumulation registers

rms

(VAHR, RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to I

, and vice versa.

rms

VARMSCFCON Result

0 If CF1SEL[1:0] = 1X, CF1 is proportional to VA. If CF2SEL[1:0] = 1X, CF2 is proportional to VA. 1 If CF1SEL[1:0] = 1X, CF1 is proportional to I If CF2SEL[1:0] = 1X, CF2 is proportional to I

rms

. .

2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.

rms

Rev. B | Page 44 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Bit Mnemonic Default Description

1 FREQSEL 0

0 PER_FREQ register holds a period measurement. 1 PER_FREQ register holds a frequency measurement. 0 WAVEN 0 When this bit is set, waveform sampling mode is enabled.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Table 35. Waveform Mode Register (WAVMODE, Address 0x0D)

Bit Mnemonic Default Description

[7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.

000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output 100 VA multiplier output 101 I Others Reserved [4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode.

000 Current 001 Voltage 010 Active power multiplier output 011 Reactive power multiplier output 100 VA multiplier output 101 I Others Reserved [1: 0] DTRT 00 Waveform samples output data rate.

00 25.6 kSPS (clock/32) 01 12.8 kSPS (clock/64) 10 6.4 kSPS (clock/128) 11 3.2 kSPS (clock/256)

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Configuration bits to select period or frequency measurement for PER_FREQ register (Address 0x0A).

FREQSEL Result

WAV2SEL Source

LPF output

rms

WAV1SEL Source

LPF output (low 24-bit)

rms

DTRT Update Rate (Clock = f

/5 = 819.2 kHz)

CORE

Table 36. No Load Configuration Register (NLMODE, Address 0x0E)

Bit Mnemonic Default Description

7 DISVARCMP 6 IRMSNOLOAD 0

0 Setting this bit disables fundamental var gain compensation over line frequency.

Logic 1 enables I

no load threshold detection. The level is defined by the setting of the

rms

VANOLOAD bits.

[5:4] VANOLOAD 00 Apparent power no load threshold.

VANOLOAD Res ult

00 No load detection disabled 01 No load detection enabled with threshold = 0.030% of full scale 10 No load detection enabled with threshold = 0.015% of full scale 11 No load detection enabled with threshold = 0.0075% of full scale

Rev. B | Page 45 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Bit Mnemonic Default Description

[3:2] VARNOLOAD

00 No load detection disabled 01 No load detection enabled with threshold = 0.015% of full scale 10 No load detection enabled with threshold = 0.0075% of full scale 11 No load detection enabled with threshold = 0.0037% of full scale [1:0] APNOLOAD 00 Active power no load threshold.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F)

Bit Mnemonic Default Description

7 ICHANNEL

6 FAULTSIGN

5 VARSIGN

4 APSIGN 0

3 ABSVARM

2 SAVARM

1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output. 0 ABSAM 0

This function is not available in the ADE7566 or ADE7569.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

00 Reactive power no load threshold.

VARNOLOAD Result

APNOLOAD Result

0 This bit indicates the current channel used to measure energy in antitampering mode.

0 = Channel A (I

)

1 = Channel B (IPB)

0 Configuration bit to select the event that triggers a fault interrupt.

0 = FAULT interrupt occurs when part enters fault mode 1 = FAULT interrupt occurs when part enters normal mode

Configuration bit to select the event that triggers a reactive power sign interrupt. If cleared to 0, a VARSIGN interrupt occurs when reactive power changes from positive to negative. If set to 1, a VARSIGN interrupt occurs when reactive power changes from negative to positive.

Configuration bit to select event that triggers an active power sign interrupt. If cleared to 0, an APSIGN interrupt occurs when active power changes from positive to negative. If set to 1, an APSIGN interrupt occurs when active power changes from negative to positive.

Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.

Logic 1 enables reactive power accumulation depending on the sign of the active power. If active power is positive, var is accumulated as it is. If active power is negative, the sign of the var is reversed for the accumulation. This accumulation mode affects both the var registers (VARHR, RVARHR, LVARHR) and the pulse output when connected to var.

Logic 1 enables absolute value accumulation of active power in energy register and pulse output.

Table 38. Gain Register (GAIN, Address 0x1B)

Bit Mnemonic Default Description

[7:5] PGA2 000 These bits define the voltage channel input gain.

PGA2 Result

000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16 4 Reserved 0 Reserved.

Rev. B | Page 46 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Bit Mnemonic Default Description

3 CFSIGN_OPT 0

[2:0] PGA1 000 These bits define the current channel input gain.

000 Gain = 1 001 Gain = 2 010 Gain = 4 011 Gain = 8 100 Gain = 16

This gain is not recommended in the ADE7166 or ADE7169 because it can create an overranging of the ADC when both current inputs are in opposite phase.

Table 39. Calibration Mode Register (CALMODE, Address 0x3D)1

Bit Mnemonic Default Description

[7:6] Reserved 0 These bits must be kept at 0 for proper operation. [5:4] SEL_I_CH 0 These bits define the current channel used for energy measurements.

3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground. 2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground. [1:0] Reserved These bits must be kept at 0 for proper operation.

This register is not available in the ADE7566 or ADE7569.

INTERRUPT STATUS/ENABLE SFRs

This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.

CFSIGN_OPT Result

Filtered power signal

On a per-CF basis

PGA1 Result

SEL_I_CH Result

00 Current channel automatically selected by the tampering condition 01 Current channel connected to I

10 Current channel connected to IPB 11 Current channel automatically selected by the tampering condition

Table 40. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)

Bit Interrupt Flag Description

7 ADEIRQFLAG

This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt is set. This bit is

automatically cleared when all of the enabled ADE status flags are cleared. 6 Reserved Reserved. 5 FAULTSIGN 4 VARSIGN

Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register.

Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE

register. 3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register. 2 VANOLOAD

1 RNOLOAD

Logic 1 indicates that an interrupt has been caused by reactive power no load detection.

Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is

also used to reflect that the part is entering the I

no load mode.

rms

0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection.

This function is not available in the ADE7566 or ADE7569.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Rev. B | Page 47 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 41. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)

Bit Interrupt Flag Description

7 CF2

6 CF1

5 VAEOF Logic 1 indicates that the VAHR register has overflowed. 4 REOF

3 AEOF Logic 1 indicates that the WATTHR register has overflowed. 2 VAEHF Logic 1 indicates that the VAHR register is half full. 1 REHF

Logic 1 indicates that the VARHR register is half full.

0 AEHF Logic 1 indicates that the WATTHR register is half full.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Table 42. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)

Bit Interrupt Flag Description

7 RESET Indicates the end of a reset (for both software and hardware reset). 6 Reserved Reserved. 5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7). 4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value. 3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value. 2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles. 1 ZXTO Logic 1 indicates that no zero crossing on the line voltage happened for the last ZXTOUT half-line cycles. 0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel.

Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not enabled by clearing Bit 2 of the MODE1 register.

Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not enabled by clearing Bit 1 of the MODE1 register.

Logic 1 indicates that the VARHR register has overflowed.

Table 43. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)

Bit Interrupt Enable Bit Description

[7:6] Reserved Reserved. 5 FAULTSIGN 4 VARSIGN

When this bit is set to Logic 1, the FAULTSIGN bit set creates a pending ADE interrupt to the 8052 core.

When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core. 3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core. 2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core. 1 RNOLOAD

When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.

This function is not available in the ADE7566 or ADE7569.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Table 44. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)

Bit Interrupt Enable Bit Description

7 CF2 When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core. 6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core. 5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core. 4 REOF

When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core. 3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core. 2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core. 1 REHF

When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.

0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.

This function is not available in the ADE7116, ADE7156, ADE7166, or ADE7566.

Rev. B | Page 48 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)

Bit Interrupt Enable Bit Description

[7:6] Reserved Reserved. 5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core. 4 PKI When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core. 3 PKV When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core. 2 CYCEND When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core. 1 ZXTO When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core. 0 ZX When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.

ANALOG INPUTS

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two fully differential voltage input channels. The maximum differential input voltage for the V input pairs is ±0.4 V.

For the ADE7116/ADE7156/ADE7166/ADE7169, PGA1 = 1 is not recommended because, at full scale, when both I 180° out of phase, the ADC can be overranged. It is recommended, for these products, that PGA1 = 2, 4, 8, or 16 be used.

Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the GAIN register (see Tabl e 38 and Figure 41). Bit 2 to Bit 0 select the gain for the PGA in the current channel, and Bit 7 to Bit 5 select the gain for the PGA in the voltage channel. Figure 42 shows how a gain selection for the current channel is made using the gain register.

P/VN

and IP/IN

and IPB are

CURRENT AND VOLTAGE CHANNELS PGA CONTROL

PGA2 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16

*REGISTER CO NTENTS SHO W POWER-ON DEFAULTS.

GAIN REGISTER*

76543210

00000000

CFSIGN_OPT

RESERVED

Figure 41. Analog Gain Register

GAIN[7:0]

76543210

00000000

ADDR: 0x1B

PGA1 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16

GAIN (K) SELECTION

06353-019

K × V

06353-018

Figure 42. PGA in Current Channel

Rev. B | Page 49 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ANALOG-TO-DIGITAL CONVERSION

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has two Σ- analog-to-digital converters (ADCs). The outputs of these ADCs are mapped directly to waveform sampling SFRs (Address 0xE2 to Address 0xE7) and are used for energy measurement internal digital signal processing. In PSM1 (battery mode) and PSM2 (sleep mode), the ADCs are powered down to minimize power consumption.

For simplicity, the block diagram in Figure 44 shows a firstorder Σ-∆ ADC. The converter is made up of the Σ-∆ modulator and the digital low-pass filter (LPF).

A Σ-∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569, the sampling clock is equal to 4.096 MHz/5. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC output (and, therefore, the bit stream) can approach that of the input signal level.

For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged is a meaningful result obtained. This averaging is carried into the second part of the ADC, the digital LPF. By averaging a large number of bits from the modulator, the low-pass filter can produce 24-bit data-words that are proportional to the input signal level.

The Σ-∆ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the

ANALOG

LOW-PASS FILTER

INTEGRATOR

–

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is 4.096 MHz/5 (819.2 kHz), and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest is lowered (see Figure 43).

However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of four is required to increase the SNR by only 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at the higher frequencies. In the Σ-∆ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at the higher frequencies where it can be removed by the digital LPF. This noise shaping is shown in Figure 43.

ANTIALIAS

FILTER

REF

SIGNAL

NOISE

SIGNAL

NOISE

MCLK/5

COMPARATOR

DIGITAL

FILTER

HIGH RESOLUTION

OUTPUT FROM DIGITAL

LPF

(RC)

SHAPED

409.60 819.22

FREQUENCY (kHz)

409.60 819.22

FREQUENCY (kHz)

Figure 43. Noise Reduction Due to Oversampling and

Noise Shaping in the Analog Modulator

DIGITAL

LATCHED

LOW-PASS

FILTER

NOISE

SAMPLING

FREQUENCY

06353-021

... 10100101 ...

1-BIT DAC

Figure 44. First-Order

-∆ ADC

06353-020

Rev. B | Page 50 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Antialiasing Filter

Figure 44 also shows an analog LPF (RC) on the input to the modulator. This filter is present to prevent aliasing, an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate. Figure 45 illustrates the effect. Frequency components (the black arrows) above half the sampling frequency (also known as the Nyquist frequency, that is, 409.6 kHz) are imaged or folded back down below 409.6 kHz. This happens with all ADCs, regardless of the architecture. In the example shown, only frequencies near the sampling frequency (819.2 kHz) move into the band of interest for metering (40 Hz to 2 kHz). This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (at approximately 819.2 kHz) noise and prevents distortion in the band of interest.

For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 819.2 kHz (see Figure 45). The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors. However, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the −20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the

−40 dB per decade attenuation needed.

ALIASING EFFECTS

IMAGE

FREQUENCIES

409.60 819.22

FREQUENCY (kHz)

Figure 45. ADC and Signal Processing in Current Channel Outline Dimensions

SAMPLING

FREQUENCY

06353-022

ADC Transfer Function

Both ADCs in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 are designed to produce the same output code for the same input signal level. With a full-scale signal on the input of 0.4 V and an internal reference of 1.2 V, the ADC output code is nominally 2,147,483 or 0x20C49B. The maximum code from the ADC is ±4,194,304; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, it is recommended that the full-scale input signal level of 0.4 V not be exceeded.

Current Channel ADC

Figure 46 and Figure 47 show the ADC and signal processing chain for the current channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (4.096 MHz/160).

With the specified full-scale analog input signal of 0.4 V and PGA1 = 1, the ADC produces an output code that is approximately between 0x20C49B (+2,147,483d) and 0xDF3B65 (−2,147,483d). For inputs of 0.25 V, 0.125 V, 62.5 mV, and 31.3 mV with PGA1 = 2, 4, 8, and 16, respectively, the ADC produces an output code that is approximately between 0x28F5C2 (+2,684,354d) and 0xD70A3E (−2,684,354d).

Rev. B | Page 51 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

×1, ×2, ×4 ×8, ×16 {GAIN[2:0]}

PGA1

0.25V, 0.125V,

62.5mV, 31.3 mV

ANALOG INPUT RANGE

*WHEN DIGITAL INTEGRATOR IS ENABLED, F ULL-SCALE OUTPUT DATA IS ATTENUATED

NDING ON THE SIGNAL FREQUENCY BECAUSE T HE INTEGRAT OR HAS A –20dB/DECADE

DEPE FREQUENCY RESPONSE. WHEN DISABLED, T HE OUTPUT I S NOT FURTHER ATTENUATED.

NOT AVAIL ABLE IN THE ADE7566.

REFERENCE

ADC

HPF

0x28F5C2

0x000000

0xD70A3E

Figure 46. ADC and Signal Processing in Current Channel with PGA1 = 1, 2, 4, 8, or 16 for the ADE7566 and ADE7569

0.25V, 0.125V,

62.5mV, 31.3mV

ANALOG INPUT RANGE

×1, ×2, ×4 ×8, ×16 {GAIN[2:0]}

PGA1

REFERENCE

ADC

HPF

IBGAIN

0x28F5C2

0x000000

0xD70A3E

MODE1[5]

DIGITAL

INTEGRATOR*

CURRENT CHANNEL WAVEFORM DATA RANGE

INTEGRATO R*

CURRENT CHANNEL WAVEFORM DATA RANGE

0x2B7850

0x000000

0xD487B0

MODE1[5]

DIGITAL

60Hz

CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (60Hz)

CURRENT CHANNEL WAVEFORM DATA RANGE AFTER

0x2B7850

0x000000

INTEGRAT OR (60Hz)

CURRENT RMS (I CALCULATIO N

WAVEFORM SAMPLE REGISTER

ACTIVE AND REACTI VE POWER CALCUL ATION

50Hz

CURRENT RMS (I CALCULATIO N

WAVEFORM SAMPLE REGISTER

ACTIVE AND REACTI VE POWE R CALCULA TION

60Hz

rms

0x342CD0

0x000000

0xCBD330

50Hz

0x342CD0

0x000000

0xCBD330

)

CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (50Hz)

)

rms

CURRENT CHANNEL WAVEFORM DATA RANGE AFTER INTEGRATOR (50Hz)

06353-023

0xD487B0

*WHEN DIGIT AL INTEG RATOR IS ENABLED, FULL-SCALE OUT PUT DATA IS ATTENUATED

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTE GRATOR HAS A –20d B/DECADE FREQUENCY RESPONSE. WHEN DISABLED, T HE OUTPUT I S NOT FURT HER ATTENUATED.

NOT AVAIL ABLE IN THE ADE7116, ADE7156, O R ADE7166.

06353-117

Figure 47. ADC and Signal Processing in Current Channel with PGA1 = 2, 4, 8, or 16 for the ADE7116, ADE7156, ADE7166, and ADE7169

Rev. B | Page 52 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Voltage Channel ADC

Figure 48 shows the ADC and signal processing chain for the voltage channel. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 25.6 kSPS (MCLK/160). The ADC produces an output code that is approximately between 0x28F5 (+10,485d) and 0xD70B (−10,485d).

Channel Sampling

The waveform samples of the current ADC and voltage ADC can also be routed to the waveform registers to be read by the MCU core. The active, reactive, and apparent power and energy calculation remain uninterrupted during waveform sampling.

ACTIVE AND REACT IVE

POWE R CALCULA TION

HPF

0.5V, 0.25V ,

0.125V, 62.5mV,

31.3mV

ANALOG INPUT RANGE

×1, ×2, ×4, ×8, ×16

{GAIN[7:5]}

PGA2

REFERENCE

ADC

0x28F5

0x0000

0xD70B

VOLTAGE CHANNEL WAVEFORM DATA RANGE

When in waveform sampling mode, one of four output sample rates can be chosen by using the DTRT[1:0] bits of the WAV MO DE re g is t er ( se e Tab le 3 5 ). The output sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS. If the WFSM enable bit is set in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB), the 8052 core has a pending ADE interrupt. The sampled signals selected in the WAVMODE register are latched into the waveform SFRs when the waveform high byte (WAV1H or WAV2H) is read.

The ADE interrupt stays active until the WFSM status bit is cleared (see the Energy Measurement Interrupts section).

VOLTAGE RMS (V CALCULATIO N

WAVEFORM SAMPLE REGISTER

VOLTAGE PEAK DETECT

LPF1

= 63.7Hz

–3dB

MODE 1[6]

)

rms

ZX DETECTION

ZX SIGNAL DATA RANGE FOR 60Hz SIGNAL

0x1DD0

0x0000

0xE230

ZX SIGNAL DATA RANGE FOR 50Hz SIGNAL

0x2037

0x0000

0xDFC9

06353-024

Figure 48. ADC and Signal Processing in Voltage Channel

Rev. B | Page 53 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

FAULT DETECTION

The ADE7116/ADE7156/ADE7166/ADE7169 incorporate a fault detection scheme that warns of fault conditions and allows the part to continue accurate measurement during a fault event. (This function is not available in the ADE7566/ ADE7569.) The ADE7116/ADE7156/ADE7166/ADE7169 do this by continuously monitoring both current inputs (I understanding, these currents are referred to as phase and neutral (return) currents. A fault condition is defined when the difference between I

and IPB is greater than 6.25% of the active

channel. If a fault condition is detected and the inactive channel is larger than the active channel, the ADE7116/ADE7156/ ADE7166/ADE7169 automatically switch current measurement to the inactive channel. During a fault, the active, reactive, and apparent power and the I two currents. On power-up, I

are generated using the larger of the

rms

is the current input selected for

active, reactive, and apparent power and I

To prevent a false alarm, averaging is done for the fault detection, and a fault condition is detected approximately 1 second after the event. Fault detection is automatically disabled when the voltage signal is less than 0.3% of the fullscale input range. This eliminates false detection of a fault due to noise at light loads.

Because the ADE7116/ADE7156/ADE7166/ADE7169 look for a difference between the voltage signals on I important that both current transducers be closely matched.

Channel Selection Indication

The current channel selected for measurement is indicated by Bit 7 (ICHANNEL) in the ACCMODE register (Address 0x0F). When this bit is cleared, I

is selected and, when it is set, IPB is

selected. The ADE7166/ADE7169 automatically switch from one channel to the other and report the channel configuration in the ACCMODE register (Address 0x0F).

The current channel selected for measurement can also be forced. Setting the SEL_I_CH[1:0] bits in the CALMODE register (Address 0x3D) selects I

both bits are cleared or set, the current channel used for measurement is selected automatically based on the fault detection.

and IPB). For ease of

calculations.

rms

and IPB, it is

and IPB, respectively. When

Fault Indication

The ADE7116/ADE7156/ADE7166/ADE7169 provide an indication of the part going in or out of a fault condition. The new fault condition is indicated by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).

When the FAULTSIGN bit (Bit 6) of the ACCMODE register (Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is entering a fault condition or a normal condition.

When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), and the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set, the 8052 core has a pending ADE interrupt.

Fault with Active Input Greater Than Inactive Input

If IPA is the active current input (that is, being used for billing), and the voltage signal on I

93.75% of I

, and the FAULTSIGN bit (Bit 6) of the ACCMODE

(the inactive input) falls below

register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. Both analog inputs are filtered and averaged to prevent false triggering of this logic output. As a consequence of the filtering, there is a time delay of approximately 3 seconds on the logic output after the fault event. The FAULTSIGN flag is independent of any activity. Because I greater than I the I

input occurs. IPA remains the active input.

, billing is maintained on IPA; that is, no swap to

is the active input and it is still

Rev. B | Page 54 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Fault with Inactive Input Greater Than Active Input

If the difference between IPB, the inactive input, and IPA, the active input (that is, being used for billing), becomes greater than 6.25% of I

, and the FAULTSIGN bit (Bit 6) of the

ACCMODE register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. The I

analog input becomes the active input.

Again, a time constant of about 3 seconds is associated with this swap. I greater than I order—becomes greater than 6.25% of I

does not become the active channel again until IPA is

and the difference between IPA and IPB—in this

. However, if the

FAULTSIGN bit (Bit 6) of the ACCMODE register (Address 0x0F) is set, the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set as soon as I of I

. This threshold eliminates potential chatter between IPA

and I

is within 6.25%

Calibration Concerns

Typically, when a meter is calibrated, the voltage and current circuits are separated, as shown in Figure 49. Current passes through only the phase circuit or the neutral circuit. Figure 49 shows current being passed through the phase circuit. This is the preferred option because the ADE7116/ADE7156/ ADE7166/ADE7169 start billing on the I The phase circuit CT is connected to I

input on power-up.

in the diagram.

Because the current sensors are not perfectly matched, it is important to match current inputs. The ADE7116/ ADE7156/ADE7166/ADE7169 provide a gain calibration register for I

, IBGAIN (Address 0x1C). IBGAIN is a 12-bit,

signed, twos complement register that provides a gain resolution of 0.0244%/LSB.

For calibration, a first measurement should be done on I

setting the SEL_I_CH bits to 0b01 in the CALMODE register (Address 0x3D). This measurement should be compared to the measurement on I

. Measuring IPB can be forced by setting the

SEL_I_CH bits to 0b10 in the CALMODE register (Address 0x3D). The gain error between these two measurements can be evaluated using the following equation:

()

Error−=%

The two channels, I

and IPB, can then be matched by writing

−Error(%)/(1 + Error (%)) × 2

() ()

()

ItMeasuremen

to the IBGAIN register

ItMeasuremenItMeasuremen

(2)

(Address 0x1C). This matching adjustment is valid for all energy measurements made by the ADE7116/ADE7156/ ADE7166/ADE7169, including active power, reactive power (ADE7169 only), apparent power, and I

rms

TEST

CURRENT

240V rms

PHASE

AGND

NEUTRAL

Figure 49. Fault Conditions for Inactive Input Greater Than Active Input

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7169/ADE7569

A di/dt sensor, a feature available for the AD7169/ADE7569 but not for the ADE7116/ADE7156/ADE7166/ADE7169, detects changes in the magnetic field caused by ac currents. Figure 50 shows the principle of a di/dt current sensor.

MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORT IONAL TO CURRENT)

+ EMF (ELE CTROMOT IVE FO RCE)

– INDUCED BY CHANG ES IN

MAGNETIC F LUX DENSITY (di /dt)

Figure 50. Principle of a di/dt Current Sensor

The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. The changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal needs to be recovered from the di/dt signal before it can be used. An integrator is, therefore, necessary to restore the signal to its original form.

06353-025

06353-026

Rev. B | Page 55 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

The ADE7169/ADE7569 have a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on the current channel is switched off by default when the ADE7169/ADE7569 are powered up. Setting the INTE bit (Bit 5) in the MODE1 register (Address 0x0B) turns on the integrator. Figure 51 to Figure 54 show the gain and phase response of the digital integrator.

–10

–20

GAIN (dB)

–30

–40

–50

Figure 51. Combined Gain Response of the Digital Integrator and

–88.0

–88.5

100 1000

FREQUENCY ( Hz)

Phase Compensator

06353-027

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

GAIN (dB)

–4.0

–4.5

–5.0

–5.5

–6.0

40 7045

50 55 60 65

FREQUENCY ( Hz)

Figure 53. Combined Gain Response of the Digital Integrator and

Phase Compensator (40 Hz to 70 Hz)

–89.70

–89.75

–89.80

–89.85

–89.90

–89.95

PHASE (Degrees)

–90.00

–90.05

06353-029

–89.0

–89.5

PHASE (Degrees)

–90.0

–90.5

FREQUENCY ( Hz)

FREQ

Figure 52. Combined Phase Response of the Digital Integrator and

Phase Compensator

40 45 7050 55 60 65

FREQUENCY ( Hz)

06353-030

Figure 54. Combined Phase Response of the Digital Integrator and

Phase Compensator (40 Hz to 70 Hz)

Note that the integrator has a −20 dB/dec attenuation and an approximately −90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor

06353-106

has a 20 dB/dec gain associated with it. It also generates significant high frequency noise. Therefore, a more effective antialiasing filter is needed to avoid noise due to aliasing (see the Antialiasing Filter section).

When the digital integrator is switched off, the ADE7169/ADE7569 can be used directly with a conventional current sensor, such as a current transformer (CT), or with a low resistance current shunt.

Rev. B | Page 56 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has a zero-crossing detection circuit on the voltage channel. This zero crossing is used to produce a zero-crossing internal signal (ZX) and is used in calibration mode.

The zero crossing is generated by default from the output of LPF1. This filter has a low cutoff frequency and is intended for 50 Hz and 60 Hz systems. If needed, this filter can be disabled to allow a higher frequency signal to be detected or to limit the group delay of the detection. If the voltage input fundamental frequency is below 60 Hz, and a time delay in ZX detection is acceptable, it is recommended that LPF1 be enabled. Enabling LPF1 limits the variability in the ZX detection by eliminating the high frequency components. Figure 55 shows how the zerocrossing signal is generated.

×1, ×2, ×4, ×8, ×16

{GAIN [7:5]}

PGA2

REFERENCE

ADC 2

–3dB

HPF

LPF1

= 63.7Hz

ZERO

CROSSING

crossing is detected on the voltage channel. The default power-on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE), and the ZXTO bit (Bit 1) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a pending ADE interrupt.

The ADE interrupt stays active until the ZXTO status bit is cleared (see the Energy Measurement Interrupts section). The ZXTOUT register (Address 0x11) can be written to or read by the user (see the Energy Measurement Register List section). The resolution of the register is 160/MCLK seconds per LSB. Thus, the maximum delay for an interrupt is 0.16 seconds (1/MCLK × 2

) when MCLK = 4.096 MHz.

Figure 56 shows the mechanism of the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than MCLK/160 × ZXTOUT seconds.

12-BIT INT ERNAL

ZXTOUT

VOLTAGE

CHANNEL

MODE 1[6]

1.0

0.73

Figure 55. Zero-Crossing Detection on the Voltage Channel

43.24° @ 60Hz

LPF1

06353-031

The zero-crossing signal, ZX, is generated from the output of LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at MCLK = 4.096 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase lag response of LPF1 results in a time delay of approximately 2 ms (@ 60 Hz) between the zero crossing on the analog inputs of the voltage channel and ZX detection.

The zero-crossing detection also drives the ZX flag in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If the ZX bit in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the ZX status bit is cleared (see the Energy Measurement Interrupts section).

Zero-Crossing Timeout

The zero-crossing detection also has an associated timeout register, ZXTOUT (Address 0x11). This unsigned, 12-bit register is decremented (1 LSB) every 160/MCLK seconds. The register is reset to its user programmed, full-scale value every time a zero

ZXTO

FLAG

BIT

Figure 56. Zero-Crossing Timeout Detection

06353-032

Period or Frequency Measurements

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide the period or frequency measurement of the line. The period or frequency measurement is selected by clearing or setting the FREQSEL bit (Bit 1) in the MODE2 register (Address 0x0C). The period/frequency register, PER_FREQ (Address 0x0A), is an unsigned 16-bit register that is updated every period. If LPF1 is enabled, a settling time of 1.8 sec is associated with this filter before the measurement is stable.

When the period measurement is selected, the measurement has a

2.44 µs/LSB (4.096 MHz/10) resolution, which represents 0.014% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 0d6827. The length of the register enables the measurement of line frequencies as low as 12.5 Hz. The period register is stable at ±1 LSB when the line is established, and the measurement does not change.

When the frequency measurement is selected, the measurement has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which represents 0.104% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the frequency register is 0d960. The frequency register is stable at ±4 LSB when the line is established, and the measurement does not change.

Rev. B | Page 57 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Line Voltage SAG Detection

In addition to detection of the loss of the line voltage signal (zero crossing), the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 can also be programmed to detect when the absolute value of the line voltage drops below a certain peak value for a number of line cycles. This condition is illustrated in Figure 57.

FULL SCALE

SAGLVL [15:0]

SAG FLA

SAGCYC [7:0] = 0x04

VOLTAGE CHANNEL

3 LINE CYCLES

Figure 57. SAG Detection

SAG RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL [15:0] AND SAG FLAG RESET

06353-033

Figure 57 shows the line voltage falling below a threshold that is set in the SAG level register (SAGLVL[15:0], Address 0x14) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, when the SAG cycle (SAGCYC[7:0], Address 0x13) contains 0x04, FSAG (Bit 5) in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set at the end of the third line cycle after the line voltage falls below the threshold. If the SAG enable bit (ESAG, Bit 5) in the power management interrupt enable SFR (IPSME, Address 0xEC) is set, the 8052 core has a pending power supply management interrupt. The PSM interrupt stays active until the ESAG bit is cleared (see the Power Supply Management (PSM) Interrupt section).

In Figure 57, the SAG flag (FSAG) is set on the fifth line cycle after the signal on the voltage channel first dropped below the threshold level.

SAG Level Set

The 2-byte contents of the SAG level register (SAGLVL, Address 0x14) are compared to the absolute value of the output from LPF1.

Therefore, when LPF1 is enabled, writing 0x2038 to the SAG level register puts the SAG detection level at full scale (see Figure 57). Writing 0x00 or 0x01 puts the SAG detection level at

0. The SAG level register is compared to the input of the ZX detection, and detection is made when the ZX input falls below the contents of the SAG level register.

Peak Detection

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 58 illustrates the behavior of the peak detection for the voltage channel. Both voltage and current channels are monitored at the same time.

VPKLVL[15:0]

PKV RESET LOW WHEN MIRQSTH SF R

PKV INTERRUPT

RESET BIT PKV

IN MIRQ STH S F

FLAG

Figure 58. Peak Level Detection

IS READ

06353-034

Figure 58 shows a line voltage exceeding a threshold that is set in the voltage peak register (VPKLVL, Address 0x16). The voltage peak event is recorded by setting the PKV flag in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If the PKV enable bit (Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB), the 8052 core has a pending ADE interrupt. Similarly, the current peak event is recorded by setting the PKI flag (Bit 4) in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). The ADE interrupt stays active until the PKV or PKI status bit is cleared (see the Energy Measurement Interrupts section).

Peak L evel Set

The contents of the VPKLVL (Address 0x16) and IPKLVL (Address 0x15) registers are compared to the absolute value of the voltage and 2 MSBs of the current channel, respectively. Thus, for example, the nominal maximum code from the current channel ADC with a full-scale signal is 0x28F5C2 (see the Current Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL register puts the current channel peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the current channel detection level at 0. The detection is done by comparing the contents of the IPKLVL register to the incoming current channel sample. The PKI flag indicates that the peak level is exceeded. If the PKI or PKV bit is set in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB), the 8052 core has a pending ADE interrupt.

Peak Level Record

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 records the maximum absolute value reached by the current and voltage channels in two different registers, IPEAK (Address 0x17) and VPEAK (Address 0x19), respectively. Each register is a 24-bit unsigned register that is updated each time the absolute value of the waveform sample from the corresponding channel is above the value stored in the IPEAK or VPEAK register. The contents of the VPEAK register correspond to the maximum absolute value observed on the voltage channel input. The contents of IPEAK and VPEAK represent the maximum absolute value observed on the current and voltage input, respectively. Reading the RSTIPEAK (Address 0x18) and RSTVPEAK (Address 0x1A) registers clears their respective contents after the read operation.

Rev. B | Page 58 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

PHASE COMPENSATION

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 must work with transducers that can have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). These phase errors can vary from part to part, and they must be corrected to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 provide a means of digitally calibrating these small phase errors. The part allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors. Because the compensation is in time, this technique should be used only for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics.

The phase calibration register (PHCAL[7:0], Address 0x10) is a twos complement, signed, single-byte register that has values ranging from 0x82 (−126d) to 0x68 (+104d).

The PHCAL register is centered at 0x40, meaning that writing 0x40 to the register gives 0 delay. By changing this register, the time delay in the voltage channel signal path can change from

−231.93 µs to +48.83 µs (MCLK = 4.096 MHz). One LSB is equivalent to a 1.22 µs (4.096 MHz/5) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.026° at the fundamental (that is, 360° × 1.22 µs × 60 Hz).

Figure 59 illustrates how the phase compensation is used to remove a 0.1° phase lead in the current channel due to the external transducer. To cancel the lead (0.1°) in the current channel, a phase lead must also be introduced into the voltage channel. The resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.026°. The phase lead is achieved by introducing a time advance into the voltage channel. A time advance of 4.88 µs is made by writing −4 (0x3C) to the time delay block, thus reducing the amount of time delay by 4.88 µs or, equivalently, a phase lead of approximately 0.1° at a line frequency of 60 Hz (0x3C represents −4 because the register is centered with 0 at 0x40).

PGA1

PGA2

ADC 1

ADC 2

0.1°

60Hz

–231.93µs TO +48.83µs

Figure 59. Phase Calibration

HPF

DELAY BLOCK

1.22µs/LSB

PHCAL[7:0]

CHANNEL 2 DELAY REDUCED BY 4.88µs (0.1°LE AD AT 60Hz) 0x0B IN PHCAL[7:0]

110100

LPF2

60Hz

06353-035

RMS CALCULATION

The root mean square (rms) value of a continuous signal V(t) is defined as

rms

×=

For time sampling signals, rms calculation involves squaring the signal, taking the average, and obtaining the square root. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 implement this method by serially squaring the inputs, averaging them, and then taking the square root of the average. The averaging part of this signal processing is done by implementing a low-pass filter (LPF3 in Figure 60, Figure 62, and Figure 63). This LPF has a −3 dB cutoff frequency of 2 Hz when MCLK = 4.096 MHz.

()

where V is the rms voltage.

When this signal goes through LPF3, the cos(2ωt) term is attenuated and only the dc term, V through.

V(t ) = √2 × V sin(ωt)

INPUT

The I

signal can be read from the waveform register by setting

rms

the WAVMODE register (Address 0x0D) and setting the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of

25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.

It is important to note that when the current input is larger than 40% of full scale, the I represent the true processed rms value. The rms value processed with this level of input is larger than the 24-bit read by the waveform register, making the value read truncated on the high end.

Current Channel RMS Calculation

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 simultaneously calculates the rms values for the current and voltage channels in different registers. Figure 61 and Figure 62 show the details of the signal processing chain for the rms calculation on the current channel. The current channel rms value is processed from the samples used in the current channel waveform sampling mode and is stored in an unsigned 24-bit register (I

). One LSB of the current channel rms register is

rms

equivalent to 1 LSB of a current channel waveform sample.

dttV

)(

∫

(3)

)sin(2 tVtV ω×= (4)

222

(

)

tVVtV ω−= 2cos)(

(5)

(shown as V2 in Figure 60) goes

rms

V2(t) = V2 – V2 cos (2ωt)

LPF3

(t) = V

Figure 60. RMS Signal Processing

waveform sample register does not

rms

06353-036

Rev. B | Page 59 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

The update rate of the current channel rms measurement is

4.096 MHz/5. To minimize noise in the reading of the register,

the I

rms

zero crossing of the voltage input. This configuration is done by setting the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).

With the different specified full-scale analog input signal PGA1 values, the ADC produces an output code that is approximately ±0d2,147,483 (PGA1 = 1) or ±0d2,684,354 (PGA1 = 2, 4, 8, or 16); see the Current Channel ADC section. Similarly, the equivalent rms value of a full-scale ac signal is 0d1,518,499 (0x172BA3) when PGA = 1 and 0d1,898,124 (0x1CF68C) when PGA1 = 2, 4, 8, or 16.

The current rms measurement provided in the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is accurate to within 0.5% for signal inputs between full scale and full scale/500. The conversion from the register value to amps must be done externally in the microprocessor using an amps/LSB constant.

60Hz

0x2B7850

Current Channel RMS Offset Compensation

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporate a current channel rms offset compensation register (IRMSOS). This is a 12-bit signed register that can be used to remove offset in the current channel rms calculation. An offset can exist in the rms calculation due to input noises

that are integrated into the dc component of V

(t).

One LSB of the current channel rms offset is equivalent to 16,384 LSBs of the square of the current channel rms register. Assuming that the maximum value from the current channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the current channel rms offset represents 0.23% of measurement error at −60 dB down from full scale.

where I

CURRENT CHANNEL WAVEFORM DATA RANGE WIT H INTEGRATOR ON (60Hz)

is the rms measurement without offset correction.

rms0

rmsrms

×+= IRMSOSII

(6)

768,32

*NOT AVAIL ABLE IN THE ADE7566.

HPF

INTEGRATOR*

Figure 61. ADE7566/ADE7569 Current Channel RMS Signal Processing with PGA1 = 1, 2, 4, 8, or 16

MODE1[5]

DIGITAL

0x000000

0xD487B0

HPF1

0x28F5C2

0x000000

0xD70A3E

CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF

sgn 2

LPF3

IRMSOS[ 11:0]

26225

(t)

2172

rms

0x00

[23:0]

rms

06353-037

Rev. B | Page 60 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

0x2B7850

0x000000

0xD487B0

MODE1[5]

HPF

IBGAIN

*NOT AVAIL ABLE IN T HE ADE7116, ADE7156, OR ADE7166.

DIGITAL

INTEGRATOR*

HPF1

0x28F5C2

0x000000

0xD70A3E

CURRENT CHANNEL

60Hz

WAVEFORM DATA RANGE WIT H INTEGRATOR ON (60Hz)

CURRENT CHANNEL WAVEFORM DATA RANGE WITH INTEGRATOR OFF

sgn 2

LPF3

IRMSOS[ 11:0]

26225

(t)

2172

rms

0x00

rms

[23:0]

06353-116

Figure 62. ADE7116/ADE7156/ADE7166/ADE7169 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16

VOLTAGE CHANNEL

VOLTAGE SIGNAL (V(t))

0x28F5

0x0

LPF1

0xD70B

LPF3

|X|

Figure 63. Voltage Channel RMS Signal Processing

VRMSOS[11:0]

sgn 2

272

0x28F5C2

0x00

(t)

rmsx

[23:0]

rmsx

06353-038

Rev. B | Page 61 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Voltage Channel RMS Calculation

Figure 63 shows details of the signal processing chain for the rms calculation on the voltage channel. This voltage rms estimation is done in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 using the mean absolute value calculation, as shown in Figure 63. The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode and is stored in the unsigned 24-bit V

rms

The update rate of the voltage channel rms measurement is MCLK/5. To minimize noise in the reading of the register, the V

rms

crossing of the voltage input. This configuration is done by setting the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).

With the specified full-scale ac analog input signal of 0.4 V, the output from LPF1 in Figure 63 swings between 0x28F5 and 0xD70B at 60 Hz (see the Vol tag e Chan ne l AD C section). The equivalent rms value of this full-scale ac signal is approximately 0d1,898,124 (0x1CF68C) in the V

rms

measurement provided in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 is accurate to within ±0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a V/LSB constant.

Voltage Channel RMS Offset Compensation

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporate a voltage channel rms offset compensation register (VRMSOS). This is a 12-bit signed register that can be used to remove offset in the voltage channel rms calculation. An offset can exist in the rms calculation due to input noises and dc offset in the input samples. One LSB of the voltage channel rms offset is equivalent to 64 LSBs of the rms register. Assuming that the maximum value from the voltage channel rms calculation is 0d1,898,124 with full-scale ac inputs, then 1 LSB of the voltage channel rms offset represents 3.37% of measurement error at

−60 dB down from full scale.

= V

where V

rms

+ 64 × VRMSOS (7)

rms0

is the rms measurement without offset correction.

rms0

ACTIVE POWER CALCULATION

Active power is defined as the rate of energy flow from source to load. It is the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at every instant of time.

The unit of power is the watt or joules/second. Equation 8 gives an expression for the instantaneous power signal in an ac system.

()

)sin(2 tVtv ω×= (8)

)sin(2 tIti ω×= (9)

where:

v is the rms voltage. i is the rms current.

)()()( titvtp ×=

)2cos()( tVIVItp ω−= (10)

The average power over an integral number of line cycles (n) is given by the expression in Equation 11.

)(

∫

(11)

VIdttp

where:

T is the line cycle period. P is referred to as the active or real power.

Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 11, that is, VI. This is the relationship used to calculate active power in the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 64.

0x19999A

0xCCCCD

0x00000

INSTANTANEO US POWER SIG NAL

CURRENT i(t) = √2 × i × sin(ωt)

VOLTAG E v(t) = √2 × v × sin(ωt)

Figure 64. Active Power Calculation

p(t) = v × i – v × i × cos(2ωt)

ACTIVE REAL POWER SIGNAL = v × i

Because LPF2 does not have an ideal brick wall frequency response (see Figure 65), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because of its sinusoidal nature, the ripple is removed when the active power signal is integrated to calculate energy (see the Active Energy Calculation section).

06353-039

Rev. B | Page 62 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

–4

–8

–12

(dB)

–16

–20

–24

310301

FREQUENCY ( Hz)

Figure 65. Frequency Response of LPF2

06353-040

Active Power Gain Calibration

Figure 66 shows the signal processing chain for the active power calculation in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569. The active power is calculated by filtering the output of the multiplier with a low-pass filter. Note that, when re the gain

ading the waveform samples from the output of LPF2,

of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0], Address 0x1D). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 12 shows how the gain adjustment is related to the contents of the watt gain register.

⎛ ⎜

⎜ ⎝

PowerActiveWGAINOutput

⎧

⎨ ⎩

WGAIN

+×=

⎞

⎫

⎟

(12)

⎬

⎟

⎭

⎠

For example, when 0x7FF is written to the watt gain register, the

power output is scaled up by 50% (0x7FF = 2047d, 2047/2

= 0.5). Similarly, 0x800 = −2048d (signed, twos complement) and power output is scaled by −50%. Each LSB scales the power output by 0.0244%. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.

Active Power Offset Calibration

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 also incorporate an active power offset register (WATTOS[15:0], Address 0x20). It is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation (see Figure 64). An offset can exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the active power register to be maintained at 0 when no power is being consumed.

The 256 LSBs (WATTOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample

register. Assuming the average value, output from LPF2 is 0xCCCCD (838,861d) when inputs on the voltage and current channels are both at full scale. At −60 dB down on the current channel (1/1000 of the current channel full-scale input), the average word value output from LPF2 is 838.861 (838,861/1000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register. Therefore, the power offset correction resolution is 0.000464%/LSB (0.119%/256) at −60 dB.

Active Power Sign Detection

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 detect a change of sign in the active power. The APSIGN flag (Bit 3) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) records when a change of sign has occurred according to the APSIGN bit (Bit 4) in the ACCMODE register (Address 0x0F). If the APSIGN flag (Bit 3) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APSIGN status bit is cleared (see the Energy Measurement Interrupts section).

When APSIGN (Bit 4) in the ACCMODE register (Address 0x0F) is cleared (default), the APSIGN flag (Bit 3) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when a transition from positive to negative active power occurs.

When the APSIGN bit (Bit 4) in the ACCMODE register (Address 0x0F) is set, the APSIGN flag (Bit 3) in the MIRQSTL SFR (Address 0xDC) is set when a transition from negative to positive active power occurs.

Active Power No Load Detection

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 include a no load threshold feature on the active energy that eliminates any creep effects in the meter. The part accomplishes this by not accumulating energy if the multiplier output is below the no load threshold. When the active power is below the no load threshold, the APNOLOAD flag (Bit 0) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the APNOLOAD bit (Bit 0) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section).

The no load threshold level is selectable by setting the APNOLOAD bits (Bits[1:0]) in the NLMODE register (Address 0x0E). Setting these bits to 0b00 disables the no load detection, and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.015%, 0.0075%, or 0.0037% of the multiplier’s full-scale output frequency, respectively. The IEC 62053-21 specification states that the meter must start up with a load of ≤0.4% I

, which translates to 0.0167% of the full-scale

output frequency of the multiplier.

Rev. B | Page 63 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ACTIVE ENERGY CALCULATION

As stated in the Active Power Calculation section, power is defined as the rate of energy flow. This relationship can be expressed mathematically, as shown in Equation 13.

P =

where:

P is power. E is energy.

Conversely, energy is given as the integral of power.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 achieve the integration of the active power signal by continuously accumulating the active power signal in an internal, nonreadable, 49-bit energy register. The register (WATTHR[23:0], Address 0x01) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 15 expresses the relationship.

where:

n is the discrete time sample number. T is the sample period.

The discrete time sample period (T) for the accumulation register in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 is 1.22 µs (5/MCLK). In addition to calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 66 shows this discrete time integration or accumulation. The active

(13)

= dttPE )(

∫

(14)

→

CURRENT CHANNEL

VOLTAGE CHANNEL

∞

⎧

∑

⎨

⎩

⎫

(15)

)(lim)(

TnTpdttpE

×==

⎬ ⎭

FOR WAVEFORM SAMPLING

WATTO S[1 5:0 ]

sgn 252–62–72

LPF2

ACTIVE POWER

SIGNAL

CLKIN

–8

WAVEFORM

VALUES

WGAIN[11:0]

power signal in the waveform register is continuously added to the internal active energy register.

The active energy accumulation depends on the setting of POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register (Address 0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the active energy contents. When both bits are set, the ADE7166/ ADE7169/ADE7566/ADE7569 are set to be in the more restrictive mode, the positive-only accumulation mode.

When POAM (Bit 1) in the ACCMODE register (Address 0x0F) is set, only positive power contributes to the active energy accumulation. When ABSAM (Bit 0) in the ACCMODE register (Address 0x0F) is set, the absolute active power is used for the active energy accumulation (see the Wa tt - Ab s o lu t e Accumulation Mode section).

The output of the multiplier is divided by the value in the WDIV register (Address 0x24). If the value in the WDIV register is equal to 0, the internal active energy register is divided by 1. WDIV is an 8-bit, unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (WATTHR[23:0], Address 0x01). A read to the RWATTHR register (Address 0x02) returns the contents of the WATTHR register, and the upper 24 bits of the internal register are cleared. As shown in Figure 66, the active power signal is accumulated in an internal 49-bit signed register. The active power signal can be read from the waveform register by setting the WAVMODE register (Address 0x0D) and setting the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS,

6.4 kSPS, and 3.2 kSPS.

UPPER 24 BITS ARE ACCESSIBLE THROUGH WATTHR[23:0] REGIST ER

WDIV[7:0]

48 0

TO DIGITAL-TO-FREQUENCY CONVERTER

WATTHR[23:0]

23 0

OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INT EGRATED) I N THE INTERNAL ACTIVE ENERG Y REGIST ER

OUTPUT LPF2

TIME (nT)

Figure 66. Active Energy Calculation

Rev. B | Page 64 of 152

06353-041

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three displayed curves illustrate the minimum period of time it takes the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, that is, 0x7FF.

TTHR[23:0]

0x7F,FFFF

0x3F,FFFF

0x00,0000

0x40,0000

0x80,0000

Figure 67. Energy Register Rollover Time for Full-Scale Power

6.823.41 10.2

(Minimum and Maximum Power Gain)

13.7

WGAIN = 0x7FF WGAIN = 0x000 WGAIN = 0x800

TIME (Minutes)

Note that the energy register contents roll over to full-scale negative (0x800000) and continue to increase in value when the power or energy flow is positive (see Figure 67). Conversely, if the power is negative, the energy register underflows to fullscale positive (0x7FFFFF) and continues to decrease in value.

Using the interrupt enable register (MIRQENM, Address 0xDA), the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the active energy register is half full (positive or negative) or when an overflow or underflow occurs.

Integration Time Under Steady Load: Active Energy

As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is

1.22 µs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the WGAIN register (Address 0x1D) set to 0x000, the average word value from each LPF2 is 0xCCCCD (see Figure 64). The maximum positive value that can be stored

in the internal 49-bit register is 2

(or 0xFFFF,FFFF,FFFF) before it overflows. The integration time under these conditions when WDIV = 0 is calculated in the following equation:

Time =

FFFFFFFF,xFFFF,0

xCCCCD0

==μ×

min82.6sec6.409s22.1

(16)

06353-042

When WDIV is set to a value other than 0, the integration time varies, as shown in Equation 17.

Time = Time

× WDIV (17)

WDIV = 0

Active Energy Accumulation Modes

Watt -Si g ne d Ac cum ula tio n Mo d e

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 active energy default accumulation mode is a wattsigned accumulation based on the active power information.

Watt Positive-Only Accumulation Mode

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are placed in watt positive-only accumulation mode by setting the POAM bit (Bit 1) in the ACCMODE register (Address 0x0F). In this mode, the energy accumulation is done only for positive power, ignoring any occurrence of negative power above or below the no load threshold (see Figure 68). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow and detection of no load threshold are active in this mode.

ACTIVE ENERGY

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

APSIGN FL AG

INTERRUPT ST ATUS REGIS TERS

Figure 68. Energy Accumulation in Positive-Only Accumulation Mode

NEG

POSPOS

06353-043

Watt-Absolute Accumulation Mode

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are placed in watt-absolute accumulation mode by setting the ABSAM bit (Bit 0) in the ACCMODE register (Address 0x0F). In this mode, the energy accumulation is done using the absolute active power, ignoring any occurrence of power below the no load threshold (see Figure 69). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Detection of the transitions in the direction of power flow, and detection of no load threshold are active in this mode.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ADE7566/ADE7569 can be synchronized to the voltage channel zero crossing so that active energy can be accumulated over an integral number of half-line cycles. The advantage of summing the active energy over an integer number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This

ACTIVE ENERGY

NO-LOAD

THRESHOLD

ACTIVE POWER

NO-LOAD

THRESHOLD

APSIGN FL AG

APNOLOAD APNOLOAD

INTERRUPT ST ATUS REGIS TERS

NEG

POSPOS

06353-044

Figure 69. Energy Accumulation in Absolute Accumulation Mode

Active Energy Pulse Output

All of the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 circuitry has a pulse output whose frequency is proportional to active power (see the Active Power Calculation section). This pulse frequency output uses the calibrated signal from the WGAIN register (Address 0x1D) output, and its behavior is consistent with the setting of the active energy accumulation mode in the ACCMODE register (Address 0x0F). The pulse output is active low and should preferably be connected to an LED, as shown in Figure 80.

Line Cycle Active Energy Accumulation Mode

In line cycle active energy accumulation mode, the energy accumulation of the ADE7116/ADE7156/ADE7166/ADE7169/

DIGITAL -TO-FREQUENCY

CONVERTER

eliminates any ripple in the energy calculation. Energy is calculated more accurately and more quickly because the integration period can be shortened. By using this mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced.

In the line cycle active energy accumulation mode, the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 accumulate the active power signal in the LWATTHR register (Address 0x03) for an integral number of line cycles, as shown in Figure 70. The number of half-line cycles is specified in the LINCYC register.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can accumulate active power for up to 65,535 halfline cycles. Because the active power is integrated on an integral number of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LWATTHR register (Address 0x03) is not read before a new CYCEND flag is set, the LWATTHR register is overwritten by a new value.

WGAIN[11:0]

48 0

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL

ADC

LPF1

ZERO-CROSS ING

DETECT ION

WDIV[7:0]WATTOS [15:0]

CALIBRATION

CONTROL

LINCYC[15:0]

23 0

LWATTHR[ 23:0]

ACTIVE ENERGY IS ACCUMULATED IN THE INTERNAL REGISTER, AND THE LWATTHR REGISTER IS UPDATED AT THE END OF THE LINCYC HALF-LINE CYCLES

06353-046

Figure 70. Line Cycle Active Energy Accumulation

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

When a new half-line cycle is written in the LINCYC register (Address 0x12), the LWATTHR register (Address 0x03) is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached. This implementation provides a valid measurement at

′

sin2)( tIti (22)

the first CYCEND interrupt after writing to the LINCYC register (see Figure 71). The line active energy accumulation uses the same signal path as the active energy accumulation. The LSB size of these two registers is equivalent.

where:

θ is the phase difference between the voltage and current channel. v is the rms voltage. i is the rms current.

q(t) = v(t) × i’(t) (23)

LWATTHR REGISTER

q(t) = VI sin (θ) + VI sin

The average reactive power over an integral number of lines (n)

CYCEND IRQ

LINCYC

VALUE

Figure 71. Energy Accumulation When LINCYC Changes

Using the information from Equation 10 and Equation 11,

()

⎧ ⎪ ⎪

dtVItE

−=

⎨ ⎪

⎛

⎜

⎪

⎝

⎩

⎫ ⎪

nTnT

⎪

()

dtft

2cos

⎬

∫∫

⎪

⎞ ⎟

⎪

9.8

⎠

⎭

(18)

where:

n is an integer. T is the line cycle period.

Because the sinusoidal component is integrated over an integer number of line cycles, its value is always 0. Therefore,

∫

00+=

VIdtE (19)

06353-045

is given in Equation 24.

∫

where:

T is the line cycle period. q is referred to as the reactive power.

Note that the reactive power is equal to the dc component of the instantaneous reactive power signal q(t) in Equation 23.

The instantaneous reactive power signal q(t) is generated by multiplying the voltage and current channels. In this case, the phase of the current channel is shifted by 90°. The dc component of the instantaneous reactive power signal is then extracted by a low-pass filter to obtain the reactive power information (see Figure 72).

In addition, the phase-shifting filter has a nonunity magnitude response. Because the phase-shifted filter has a large attenuation at high frequency, the reactive power is primarily for calculation at line frequency. The effect of harmonics is largely ignored in the reactive power calculation. Note that, because of the mag-

E(t) = VInT (20)

Note that in this mode, the 16-bit LINCYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration of over 65,535 half-line cycles. At a 60 Hz line frequency, it translates to a total duration of 65,535/120 Hz = 546 sec.

REACTIVE POWER CALCULATION (ADE7169/ADE7569)

Reactive power, a function available for the ADE7169/ADE7569 only, is defined as the product of the voltage and current waveforms when one of these signals is phase-shifted by 90°. The resulting waveform is called the instantaneous reactive power signal. Equation 23 gives an expression for the instantaneous reactive power signal in an ac system when the phase of the current channel is shifted by 90°.

nitude characteristic of the phase shifting filter, the weight of the reactive power is slightly different from the active power calculation (see the Energy Register Scaling section).

The frequency response of the LPF in the reactive signal path is identical to the one used for LPF2 in the average active power calculation. Because LPF2 does not have an ideal brick wall frequency response (see Figure 65), the reactive power signal has some ripple due to the instantaneous reactive power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the reactive power signal is integrated to calculate energy.

The reactive power signal can be read from the waveform register by setting the WAVMODE register (Address 0x0D) and the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current and voltage channels waveform sampling modes, the waveform data is available at sample rates of

25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.

)sin(2)( θtVtv +ω= (21)

)sin(2)( tIti ω=

⎛ ⎜ ⎝

⎞

+ω=

⎟

⎠

)2( θ+ωt

θ==

VIdttq

)sin()(

(24)

Rev. B | Page 67 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Reactive Power Gain Calibration

Figure 72 shows the signal processing chain for the ADE7169/ ADE7569 reactive power calculation. As explained in the Reactive Power Calculation (ADE7169/ADE7569) section, the reactive power is calculated by applying a low-pass filter to the instantaneous reactive power signal. Note that, when reading the waveform samples from the output of LPF2, the gain of the reactive energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the var gain register (VARGAIN[11:0], Address 0x1E). Equation 25 shows how the gain adjustment is related to the contents of the var gain register.

Output VARGAIN =

⎛ ⎜

PowerReactive

⎝

The resolution of the VARGAIN register is the same as the WGAIN register (see the Active Power Gain Calibration section). VARGAIN can be used to calibrate the reactive power (or energy) calculation in the ADE7169/ADE7569.

⎧

+×

⎨ ⎩

VARGAIN

⎞

⎫

(25)

⎟

⎬ ⎭

⎠

Reactive Power Offset Calibration

The ADE7169/ADE7569 also incorporate a reactive power offset register (VAROS[15:0], Address 0x21). This signed, twos complement, 16-bit register can be used to remove offsets in the reactive power calculation (see Figure 72). An offset can exist in the reactive power calculation due to crosstalk between channels on the PCB or in the IC itself. The offset calibration allows the contents of the reactive power register to be maintained at 0 when no power is being consumed.

The 256 LSBs (VAROS = 0x100) written to the reactive power offset register are equivalent to 1 LSB in the WAVMODE register (Address 0x0D).

Sign of Reactive Power Calculation

Note that the average reactive power is a signed calculation. The phase shift filter has −90° phase shift when the integrator is enabled, and +90° phase shift when the integrator is disabled. Tabl e 46 summarizes the relationship of the phase difference between the voltage and the current and the sign of the resulting var calculation.

Table 46. Sign of Reactive Power Calculation

Angle Integrator Sign

Between 0° to +90° Between −90° to 0° Between 0° to +90° Between −90° to 0°

Off Positive Off Negative On Positive On Negative

Reactive Power Sign Detection

The ADE7169/ADE7569 detect a change of sign in the reactive power. The VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR

(MIRQSTL, Address 0xDC) records when a change of sign has occurred according to the VARSIGN bit (Bit 5) in the ACCMODE register (Address 0x0F). If the VARSIGN bit is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the VARSIGN status bit is cleared (see the Energy Measurement Interrupts section).

When VARSIGN (Bit 5) in the ACCMODE register (Address 0x0F) is cleared (default), the VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when a transition from positive to negative reactive power occurs.

When VARSIGN in the ACCMODE register (Address 0x0F) is set, the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set when a transition from negative to positive reactive power occurs.

Reactive Power No Load Detection

The ADE7169/ADE7569 include a no load threshold feature on the reactive energy that eliminates any creep effects in the meter. The ADE7169/ADE7569 accomplish this by not accumulating reactive energy when the multiplier output is below the no load threshold. When the reactive power is below the no load threshold, the RNOLOAD flag (Bit 1) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the RNOLOAD bit (Bit 1) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the RNOLOAD status bit is cleared (see the Energy Measurement Interrupts section).

The no load threshold level is selectable by setting the VARNOLOAD bits (Bits[3:2]) in the NLMODE register (Address 0x0E). Setting these bits to 0b00 disables the no load detection, and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.015%, 0.0075%, and 0.0037% of the full-scale output frequency of the multiplier, respectively.

REACTIVE ENERGY CALCULATION (ADE7169/ADE7569)

As for active energy, the ADE7169/ADE7569 achieve the integration of the reactive power signal by continuously accumulating the reactive power signal in an internal, nonreadable, 49-bit energy register. The reactive energy register (VARHR[23:0], Address 0x04) represents the upper 24 bits of this internal register. The VARHR register and its function are available for the ADE7169/ADE7569 only.

The discrete time sample period (T) for the accumulation register in the ADE7169/ADE7569 is 1.22 µs (5/MCLK). As well as calculating the energy, this integration removes any sinusoidal components that may be in the active power signal. Figure 72 shows this discrete time integration or accumulation. The reactive power signal in the waveform register is continuously added to the internal reactive energy register.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

The reactive energy accumulation depends on the setting of the SAVARM and ABSVARM bits in the ACCMODE register (Address 0x0F). When both bits are cleared, the addition is signed and, therefore, negative energy is subtracted from the reactive energy contents. When both bits are set, the ADE7169/ADE7569 are set to be in the more restrictive mode, which is the absolute accumulation mode. When the SAVARM bit (Bit 2) in the ACCMODE register (Address 0x0F) is set, the reactive power is accumulated depending on the sign of the active power. When the active power is positive, the reactive power is added as it is to the reactive energy register. When the active power is negative, the reactive power is subtracted from the reactive energy accumulator (see the Var A n tit amp e r Accumulation Mode section).

When the ABSVARM bit (Bit 3) in the ACCMODE register (Address 0x0F) is set, the absolute reactive power is used for the reactive energy accumulation (see the Var Ab sol u te Accumulation Mode section).

The output of the multiplier is divided by VARDIV. If the value in the VARDIV register (Address 0x25) is equal to 0, the internal reactive energy register is divided by 1. VARDIV is an 8-bit, unsigned register. After dividing by VARDIV, the reactive energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the reactive energy register (VARHR[23:0], Address 0x04). A read to the RVAHR register (Address 0x08) returns the

VAROS[15:0]

sgn 252–62–72

LPF2

REACTIVE POWER

SIGNAL

CLKIN

WAVEFORM

VALUES

CURRENT CHANNEL

VOLTAGE CHANNEL

HPF

PHCAL[7:0]

90° PHASE

SHIFTING FILTER

FOR WAVEF ORM

–8

content of the VARHR register, and the upper 24 bits of the internal register are cleared.

As shown in Figure 72, the reactive power signal is accumulated in an internal 49-bit, signed register. The reactive power signal can be read from the waveform register by setting the WAVMODE register (Address 0x0D) and setting the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS,

6.4 kSPS, and 3.2 kSPS.

Figure 67 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. These curves also apply for the reactive energy accumulation.

Note that the energy register contents roll over to full-scale negative (0x800000) and continue to increase in value when the power or energy flow is positive. Conversely, if the power is negative, the energy register underflows to full-scale positive (0x7FFFFF) and continues to decrease in value.

Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA), the ADE7169/ADE7569 can be configured to issue an ADE interrupt to the 8052 core when the reactive energy register is half-full (positive or negative) or when an overflow or underflow occurs.

UPPER 24 BITS ARE ACCESSIBLE THROUGH

SAMPLING

VARGAIN[11:0]

23 0

VARDIV[7:0]

48 0

DIGITAL -TO-F REQUENCY

CONVERTER

VARHR[23:0 ]

VARHR[23:0] REGIS TER

OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INT EGRATED) I N THE INTERNAL REACTIVE ENE RGY REGISTER

OUTPUT LPF2

TIME (nT)

06353-047

Figure 72. Reactive Energy Calculation

Rev. B | Page 69 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Integration Time Under Steady Load: Reactive Energy

As mentioned in the Active Energy Calculation section, the discrete time sample period (T) for the accumulation register is

1.22 µs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VARGAIN register (Address 0x1E) and the VARDIV register (Address 0x25) set to 0x000, the integration time before the reactive energy register overflows is calculated in Equation 26.

Time =

0xCCCCD

FFFFFFFF,0xFFFF,

==μ×

min82.6sec6.409s22.1

(26)

When VARDIV is set to a value different from 0, the integration time varies, as shown in Equation 27.

WDIV×==0

VARDIVTimeTime

(27)

Reactive Energy Accumulation Modes

Var Signed Accumulation Mode

The ADE7169/ADE7569 reactive energy default accumulation mode is a signed accumulation based on the reactive power information.

Var Antitamper Accumulation Mode

The ADE7169/ADE7569 are placed in var antitamper accumulation mode by setting the SAVARM bit in the ACCMODE register (Address 0x0F). In this mode, the reactive power is accumulated depending on the sign of the active power. When the active power is positive, the reactive power is added as it is to the reactive energy register. When the active power is negative, the reactive power is subtracted from the reactive energy accumulator (see Figure 73). The CF pulse also reflects this accumulation method when in this mode. The default setting for this mode is off. Transitions in the direction of power flow and no load threshold are active in this mode.

REACTIVE ENERGY

NO-LO AD

THRESHOLD

REACTIVE POWER

NO-LO AD

THRESHOLD

NO-LO AD

THRESHOLD

ACTIVE POWER

NO-LO AD

THRESHOLD

APSIGN FLAG

POSPOS

NEG

INTERRUP T STAT US REGI STERS

Figure 73. Reactive Energy Accumulation in

Antitamper Accumulation Mode

6353-048

Rev. B | Page 70 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Var Absolute Accumulation Mode

The ADE7169/ADE7569 are placed in absolute accumulation mode by setting the ABSVARM bit (Bit 3) in the ACCMODE register (Address 0x0F). In absolute accumulation mode, the reactive energy accumulation is done by using the absolute reactive power and ignoring any occurrence of power below the no load threshold for the reactive energy (see Figure 74). The CF pulse also reflects this accumulation method when in the absolute accumulation mode. The default setting for this mode is off. Transitions in the direction of power flow and no load threshold are active in this mode.

REACTIVE ENERG Y

NO-LOAD

THRESHOLD

REACTIVE POWER

NO-LOAD

THRESHOLD

Figure 74. Reactive Energy Accumulation in Absolute Accumulation Mode

06353-049

Reactive Energy Pulse Output

The ADE7169/ADE7569 provide all the circuitry with a pulse output whose frequency is proportional to reactive power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VARGAIN, and its behavior is consistent with the setting of the reactive energy accumulation mode in the ACCMODE register (Address 0x0F). The pulse output is active low and should preferably be connected to an LED, as shown in Figure 80.

DIGIT AL- TO-FREQU ENCY

CONVERTER

Line Cycle Reactive Energy Accumulation Mode

In line cycle reactive energy accumulation mode, the energy accumulation of the ADE7169/ADE7569 can be synchronized to the voltage channel zero crossing so that reactive energy can be accumulated over an integral number of half-line cycles. The advantages of this mode are similar to the ones described in the Line Cycle Active Energy Accumulation Mode section.

In line cycle active energy accumulation mode, the ADE7169/ADE7569 accumulate the reactive power signal in the LVARHR register (Address 0x06) for an integral number of line cycles, as shown in Figure 75. The number of half-line cycles is specified in the LINCYC register (Address 0x12). The ADE7169/ADE7569 can accumulate active power for up to 65,535 half-line cycles.

Because the reactive power is integrated on an integral number of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set at the end of an active energy accumulation line cycle. If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CYCEND status bit is cleared (see the Energy Measurement Interrupts section). Another calibration cycle starts as soon as the CYCEND flag is set. If the LVARHR register (Address 0x06) is not read before a new CYCEND flag is set, the LVARHR register is overwritten by a new value.

When a new half-line cycle is written in the LINCYC register (Address 0x12), the LVARHR register is reset, and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted internally until the value programmed in LINCYC is reached. This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register. The line reactive energy accumulation uses the same signal path as the reactive energy accumulation. The LSB size of these two registers is equivalent.

VARGAIN[11:0]

48 0

OUTPUT

FROM

LPF2

FROM VOLTAGE

CHANNEL ADC

LPF1

VARDIV[7:0]VAROS[15:0]

ZERO-CROSSING

DETECTION

Figure 75. Line Cycle Reactive Energy Accumulation Mode

CALIBRATION

CONTROL

LINCYC[15:0]

23 0

LVARHR[23:0]

ACTIVE ENERGY IS ACCUMULATED I N THE INTERNAL REGIST ER, AND THE LWATTHR REGISTER IS UPDATED AT THE END OF THE LINCYC HALF-LINE CYCLES

06353-050

Rev. B | Page 71 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

APPARENT POWER CALCULATION

Apparent power is defined as the maximum power that can be delivered to a load. V current delivered to the load, respectively. Therefore, the apparent power (AP) = V phase angle between the current and the voltage.

Equation 31 gives an expression of the instantaneous power signal in an ac system with a phase shift.

() 2 sin( )

vt V t

()

Figure 76 illustrates the signal processing for the calculation of the apparent power in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.

The apparent power signal can be read from the waveform register by setting the WAVMODE register (Address 0x0D) and setting the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current and voltage channel waveform sampling modes, the waveform data is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.

and I

rms

× I

. This equation is independent of the

rms

are the effective voltage and

rms

(28)

)sin(2 θ+ω= tIti

(29)

)()()( titvtp ×= (30)

)2cos()cos( θ+ω−θ= tIVIVtp

rmsrmsrmsrms

rms

CURRENT RMS SIG NAL – i(t)

0x1CF68C

rms

VOLTAGE RMS SIGNAL – v(t)

0x1CF 68C

(31)

0x00

Figure 76. Apparent Power Signal Processing

The gain of the apparent energy can be adjusted by using the multiplier and by writing a twos complement, 12-bit word to the VAGAIN register (VAGAIN[11:0], Address 0x1F). Equation 32 shows how the gain adjustment is related to the contents of the VAG AI N r eg is te r.

Output VAGAIN =

⎛ ⎜

PowerApparent (32)

⎝

⎧

+×

⎨ ⎩

VAGAIN

⎞

⎫

⎟

⎬ ⎭

⎠

For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50% (0x7FF = 2047d, 2047/2 Similarly, 0x800 = −2047d (signed twos complement) and power output is scaled by −50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.

Apparent Power Offset Calibration

Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value (see the Current Channel RMS Calculation and the Voltage Channel RMS Calculation section). The voltage and current channels rms values are then multiplied together in the apparent power signal processing. Because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement.

VARMSCFCON

APPARENT POWER SIGNAL (P)

0x1A36E2

VAGAIN

DIGITAL -TO-FREQUENCY

CONVERTER

06353-051

= 0.5).

Rev. B | Page 72 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

APPARENT ENERGY CALCULATION

The apparent energy is given as the integral of the apparent power.

= dttPowerApparentEnergyApparent )(

∫

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 achieve the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 48-bit register. The apparent energy register (VAHR[23:0], Address 0x07) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 34 expresses the relationship.

∞

⎧ ⎨

∑

=→0

⎩

where:

n is the discrete time sample number. T is the sample period.

The discrete time sample period (T) for the accumulation register in the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 is 1.22 µs (5/MCLK).

Figure 77 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition even if the apparent energy theoretically remains positive.

The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register (Address 0x26) is 0, the internal apparent energy register is divided by 1. VADIV is an 8-bit, unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAHR[23:0], Address 0x07). The RVAHR register (Address 0x08), which is 24 bits long, is

(33)

⎫

(34)

)(lim

TnTPowerApparentEnergyApparent

×=

⎬ ⎭

23 0

provided to read the apparent energy. This register is reset to 0 after a read operation.

Note that the apparent energy register is unsigned. By setting the VAEHF bit (Bit 2) and the VAEOF bit (Bit 5) in the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA), the device can be configured to issue an ADE interrupt to the 8052 core when the apparent energy register is half-full or when an overflow occurs. The half-full interrupt for the unsigned apparent energy register is based on 24 bits as opposed to 23 bits for the signed active energy register.

Integration Time Under Steady Load: Apparent Energy

As mentioned in the Apparent Energy Calculation section, the discrete time sample period (T) for the accumulation register is

1.22 µs (5/MCLK). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register (Address 0x1F) set to 0x000, the average word value from the apparent power stage is 0x1A36E2 (see the Apparent Power Calculation section). The maximum value that can be stored in the apparent energy

or 0xFF,FFFF. The average word value is added to the internal register, which can store 2 or 0xFFFF,FFFF,FFFF before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows:

Time =

FFFFFFFF,0xFFFF,

0xD055

min33.3sec199s22.1

==μ×

When VADIV is set to a value different from 0, the integration time varies, as shown in Equation 36.

Time = Time

× VADIV (36)

WDIV = 0

VAHR[23:0]

(35)

APPARENT POW ER

rms

VADIV

48 0

APPARENT POWER SIG NAL = P

TIME (nT)

Figure 77. Apparent Energy Calculation

APPARE ACCUMULATED (INT EGRATED) IN THE APPARENT ENERGY REGISTER

NT POWER O R I

rms

06353-052

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Apparent Energy Pulse Output

All the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 circuitry has a pulse output whose frequency is proportional to apparent power (see the Energy-to-Frequency Conversion section). This pulse frequency output uses the calibrated signal after VAGAIN. This output can also be used to output a pulse whose frequency is proportional to I

. The pulse

rms

output is active low and should preferably be connected to an LED, as shown in Figure 80.

Line Apparent Energy Accumulation

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are designed with a special apparent energy accumulation mode that simplifies the calibration process. By using the on-chip, zero-crossing detection, the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 accumulate the apparent power signal in the LVAHR register (Address 0x09) for an integral number of half cycles, as shown in Figure 78. The line apparent energy accumulation mode is always active.

The number of half-line cycles is specified in the LINCYC register (Address 0x12), which is an unsigned 16-bit register. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 can accumulate apparent power for up to 65,535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active register and reactive energy register, these values can easily be compared. The energies are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation.

At the end of an energy calibration cycle, the CYCEND flag (Bit 2) in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set. If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is enabled, the 8052 core has a pending ADE interrupt.

As for LWATTHR, when a new half-line cycle is written in the LINCYC register (Address 0x12), the LVAHR register (Address 0x09) is reset and a new accumulation starts at the next zero crossing. The number of half-line cycles is then counted until LINCYC is reached.

This implementation provides a valid measurement at the first CYCEND interrupt after writing to the LINCYC register.

The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent.

Apparent Power No Load Detection

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 include a no load threshold feature on the apparent power that eliminates any creep effects in the meter. The ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 accomplish this by not accumulating energy if the multiplier output is below the no load threshold. When the apparent power is below the no load threshold, the VANOLOAD flag (Bit 2) in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the APNOLOAD status bit is cleared (see the Energy Measurement Interrupts section).

The no load threshold level is selectable by setting the VANOLOAD bits (Bits[5:4]) in the NLMODE register (Address 0x0E). Setting these bits to 0b00 disables the no load detection, and setting them to 0b01, 0b10, or 0b11 sets the no load detection threshold to 0.030%, 0.015%, and 0.0075% of the fullscale output frequency of the multiplier, respectively.

This no load threshold can also be applied to the I

rms

pulse output when selected. In this case, the level of no load threshold is the same as for the apparent energy.

AMPERE-HOUR ACCUMULATION

In a tampering situation where no voltage is available to the energy meter, the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 are capable of accumulating the ampere-hour instead of apparent power into the VAHR, RVAHR, and LVAHR. When the VARMSCFCON bit (Bit 3) of the MODE2 register (Address 0x0C) is set, the VAHR, RVAHR, and LVAHR, and the input for the digital-to-frequency converter accumulate I power. All the signal processing and calibration registers available for apparent power and energy accumulation remain the same when ampere-hour accumulation is selected. However, the scaling difference between I

and apparent power requires

rms

independent values for gain calibration in the VAGAIN (Address 0x1F), VADIV (Address 0x26), CFxNUM (Address 0x27 and Address 0x29), and CFxDEN (Address 0x28 and Address 0x2A) registers.

instead of apparent

rms

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

48 0

LVAHR REGIST ER IS UPDATED EVERY LINCYC ZERO CROSSI NG WIT H THE TOTAL APPARENT ENERGY DURING THAT DURATION

23 0

LVAHR[23:0]

VOLTAGE CHANNEL

FROM

ADC

APPARENT POWER

LPF1

or I

rms

ZERO-CROSSING

DETECTIO N

VADIV[7:0]

CALIBR

ATI ON

CONTROL

LINCYC[15:0]

Figure 78. Line Cycle Apparent Energy Accumulation

ENERGY-TO-FREQUENCY CONVERSION

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 also provide two energy-to-frequency conversions for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to do this is for the manufacturer to provide an output frequency that is proportional to the active power, reactive power, apparent power, or I conditions. This output frequency can provide a simple singlewire, optically isolated interface to external calibration equipment. Figure 79 illustrates the energy-to-frequency conversion in the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.

MODE2 REGI STER 0x0C

VARMSCFCON

rms

AVAILABLE O NLY IN T HE ADE7569 AND ADE7169

VAR

WATT

CFxSEL[1:0]

DFC

Figure 79. Energy-to-Frequency Conversion

Two digital-to-frequency converters (DFC) are used to generate the pulsed outputs. When WDIV = 0 or 1, the DFC generates a pulse each time 1 LSB in the energy register is accumulated. An output pulse is generated when a CFxNUM/CFxDEN number of pulses is generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power, reactive power, apparent power, or I CFxSEL bits in the MODE2 register (Address 0x0C).

Both pulse outputs can be enabled or disabled by clearing or setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the MODE1 register (Address 0x0B), respectively.

Both pulse outputs set separate flags in the Interrupt Status 2 SFR (MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt

under steady load

rms

CFxNUM

CFxDEN

, depending on the

rms

CFx PULSE OUTPUT

06353-054

06353-053

Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core has a pending ADE interrupt. The ADE interrupt stays active until the CF1 or CF2 status bit is cleared (see the Energy Measurement Interrupts section).

Pulse Output Configuration

The two pulse output circuits have separate configuration bits in the MODE2 register (Address 0x0C). Setting the CFxSEL bits to 0b00, 0b01, or 0b1X configures the DFC to create a pulse output proportional to active power , reactive power (ADE7169/ ADE7569 only), or apparent power or I

The selection between I

and apparent power is done by the

rms

, respectively.

rms

VARMSCFCON bit in the MODE2 register (Address 0x0C). With this selection, CF2 cannot be proportional to apparent power if CF1 is proportional to I proportional to apparent power if CF2 is proportional to I

, and CF1 cannot be

rms

Pulse Output Characteristic

The pulse output for both DFCs stays low for 90 ms if the pulse period is longer than 180 ms (5.56 Hz). If the pulse period is shorter than 180 ms, the duty cycle of the pulse output is 50%. The pulse output is active low and should be connected to an LED, as shown in Figure 80.

06353-055

Figure 80. CF Pulse Output

The maximum output frequency with ac input signals at full scale and with CFxNUM = 0x00 and CFxDEN = 0x00 is approximately 21.1 kHz.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporate two registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set the CFx frequency. These unsigned, 16-bit registers can be used to adjust the CFx frequency to a wide range of values. These frequency scaling registers are 16-bit

registers that can scale the output frequency by 1/2 a step of 1/2

to 1 with

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

If 0 is written to any of these registers, 1 is applied to the register. The ratio of CFxNUM/CFxDEN should be less than 1 to ensure proper operation. If the ratio of the CFxNUM/CFxDEN registers is greater than 1, the register values are adjusted to a ratio of 1. For example, if the output frequency is 1.562 kHz, and the content of CFxDEN is 0 (0x000), the output frequency can be set to 6.1 Hz by writing 0xFF to the CFxDEN register.

ENERGY REGISTER SCALING

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide measurements of active, reactive, and apparent energies that use separate paths and filtering for calculation. The difference in data paths can result in small differences in LSB weight between active, reactive, and apparent energy registers. These measurements are internally compensated so that the scaling is nearly one to one. The relationship between these registers is shown in Tabl e 47 .

Table 47. Energy Registers Scaling

Line Frequency = 50 Hz Line Frequency = 60 Hz Integrator

Var = 0.9952 × Watt Var = 0.9949 × Watt Off VA = 0.9978 × Watt VA = 1.0015 × Watt Off Var = 0.9997 × Watt Var = 0.9999 × Watt On VA = 0.9977 × Watt VA = 1.0015 × Watt On

ENERGY MEASUREMENT INTERRUPTS

The energy measurement part of the ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 has its own interrupt vector for the 8052 core, Vector Address 0x004B (see the Interrupt Vectors section). The bits set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), Interrupt Enable 2 SFR (MIRQENM, Address 0xDA), and Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) enable the energy measurement interrupts that are allowed to interrupt the 8052 core. If an event is not enabled, it cannot create a system interrupt.

The ADE interrupt stays active until the status bit that has created the interrupt is cleared. The status bit is cleared when a 0 is written to this register bit.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS

The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include temperature measurements as well as battery and supply voltage measurements. (This feature is not available in the ADE7116.) These measurements enable many forms of compensation. The temperature and supply voltage measurements can be used to compensate external circuitry. The RTC can be calibrated over temperature to ensure that it does not drift. Supply voltage measurements allow the LCD contrast to be maintained despite

Table 48. Temperature, Battery, and Supply Voltage Measurement SFRs

SFR Address R/W Mnemonic Description

0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 4 9). 0xF3 R/W DIFFPROG Temperature and supply delta (see Tabl e 50). 0xD8 R/W ADCGO Start ADC measurement (see Table 51). 0xFA R/W BATVTH Battery detection threshold (see Table 52 ). 0xEF R/W VDCINADC V 0xDF R/W BATADC Battery ADC value (see Tab le 54). 0xD7 R/W TEMPADC Temperature ADC value (see Tabl e 55).

ADC value (see Table 53 ).

DCIN

variations in voltage. Battery measurements allow low battery detection to be performed. All ADC measurements are configured through the SFRs, as shown in Tabl e 48 .

The temperature, battery, and supply voltage measurements can be configured to continue functioning in PSM1 and PSM2. Keeping the temperature measurement active ensures that it is not necessary to wait for the temperature measurement to settle before using it for compensation.

Table 49. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9)

Bit Mnemonic Default Description

[7:6] Reserved 00 These bits must be kept at 0 for proper operation. [5:4] VDCIN_PERIOD 0 Period for background external voltage measurements.

VDCIN_PERIOD Result

00 No V 01 8 min 10 2 min 11 1 min

[3:2] BATT_PERIOD 0 Period for background battery level measurements.

BATT_PERIOD Result

00 No battery measurement 01 16 min 10 4 min 11 1 min

[1:0] TEMP_PERIOD 0 Period for background temperature measurements.

TEMP_PERIOD Result

00 No temperature measurement 01 8 min 10 2 min 11 1 min

measurement

DCIN

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Table 50. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)

Bit Mnemonic Default Description

[7:6] Reserved 0 Reserved. [5:3] TEMP_DIFF 0

[2:0] VDCIN_DIFF 0

Difference threshold between last temperature measurement interrupting 8052 and new temperature measurement that should interrupt 8052.

TEMP_DIFF Result

000 No interrupt 001 1 LSB (≈ 0.8°C) 010 2 LSB (≈ 1.6°C) 011 3 LSB (≈ 2.4°C) 100 4 LSB (≈ 3.2°C) 101 5 LSB (≈ 4°C) 110 6 LSB (≈ 4.8°C) 111 Every temperature measurement Difference threshold between last external voltage measurement interrupting 8052 and new

external measurement that should interrupt 8052.

VDCIN_DIFF Result

000 No interrupt 001 1 LSB (≈ 120 mV) 010 2 LSB (≈ 240 mV) 011 3 LSB (≈ 360 mV) 100 4 LSB (≈ 480 mV) 101 5 LSB (≈ 600 mV) 110 6 LSB (≈ 720 mV) 111 Every V

measurement

DCIN

Table 51. Start ADC Measurement SFR (ADCGO, Address 0xD8)

Bit Address Mnemonic Default Description

7 0xDF PLLACK 0

[6:3] 0xDE to 0xDB Reserved 0 Reserved. 2 0xDA VDCIN_ADC_GO 0

1 0xD9 TEMP_ADC_GO 0

0 0xD8 BATT_ADC_GO 0

Set this bit to clear the PLL fault bit, PLL_FLT, in the PERIPH register (Address 0xF4). A PLL fault is generated if a reset is caused because the PLL lost lock.

Set this bit to initiate an external voltage measurement. This bit is cleared when the measurement request is received by the ADC.

Set this bit to initiate a temperature measurement. This bit is cleared when the measurement request is received by the ADC.

Set this bit to initiate a battery measurement. This bit is cleared when the measurement request is received by the ADC.

Table 52. Battery Detection Threshold SFR (BATVTH, Address 0xFA)

Bit Mnemonic Default Description

[7:0] BATVTH 0

Table 53. V

Bit Mnemonic Default Description

[7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs.

ADC Value SFR (VDCINADC, Address 0xEF)

DCIN

The battery ADC value is compared to this register, the battery threshold register. If BATADC is lower than the threshold, an interrupt is generated.

Table 54. Battery ADC Value SFR (BATADC, Address 0xDF)

Bit Mnemonic Default Description

[7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs.

Table 55. Temperature ADC Value SFR (TEMPADC, Address 0xD7)

Bit Mnemonic Default Description

[7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

In PSM1 operating mode, the 8052 is active, and the part is

TEMPERATURE MEASUREMENT

To provide a digital temperature measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. An 8-bit temperature ADC value SFR (TEMPADC, Address 0xD7) holds the results of the temperature conversion. The resolution of the temperature measurement is 0.78°C/LSB. There are two ways to initiate a temperature conversion: a single temperature measurement or background temperature measurements.

Single Temperature Measurement

Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measurement SFR (ADCGO, Address 0xD8) to obtain a temperature measurement (see Table 5 1). An interrupt is generated when the conversion is complete and when the temperature measurement is available in the temperature ADC value SFR (TEMPADC, Address 0xD7).

Background Temperature Measurements

Background temperature measurements are disabled by default. To configure the background temperature measurement mode, set a temperature measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Temperature measurements are then performed periodically in the background (see Tabl e 49 ).

When a temperature conversion completes, the new temperature ADC value is compared to the last temperature ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the TEMP_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), a TEMPADC interrupt is generated (see Tab le 5 0 ). This allows temperature measurements to take place completely in the background, requiring MCU activity only if the temperature changes more than a configurable delta.

To set up background temperature measurement,

Initiate a single temperature measurement by setting the

1. TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8).

Upon completion of this measurement, configure the

2. TEMP_DIFF bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3) to establish the change in temperature that triggers an interrupt.

Set up the interval for background temperature measurements

3. by configuring the TEMP_PERIOD[1:0] bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9).

Temperature ADC in PSM0, PSM1, and PSM2

Depending on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569, a temperature conversion is initiated only by certain actions.

In PSM0 operating mode, the 8052 is active. Temperature

•

measurements are available in the background measurement mode and by initiating a single measurement.

•

battery powered. Single temperature measurements can be initiated by setting the TEMP_ADC_GO bit in the start ADC measurement SFR (ADCGO, Address 0xD8). Background temperature measurements are not available.

In PSM2 operating mode, the 8052 is not active.

•

Temperature conversions are available through the background measurement mode only.

The temperature ADC value SFR (TEMPADC, Address 0xD7) is updated with a new value only when a temperature ADC interrupt occurs.

Temperature ADC Interrupt

The temperature ADC can generate an ADC interrupt when at least one of the following conditions occurs:

•

The difference between the new temperature ADC value and

the last temperature ADC value generating an ADC interrupt is larger than the value set in the TEMP_DIFF bits.

•

The temperature ADC conversion, initiated by setting the

start ADC measurement SFR (ADCGO, Address 0xD8), finishes.

When the ADC interrupt occurs, a new value is available in the temperature ADC value SFR (TEMPADC, Address 0xD7). Note that there is no flag associated with this interrupt.

BATTERY MEASUREMENT

To provide a digital battery measurement, each ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 includes a dedicated ADC. The battery measurement is available in the 8-bit battery ADC value SFR (BATADC, Address 0xDF). The battery measurement has a resolution of 14.6 mV/LSB. A battery conversion can be initiated by two methods: a single battery measurement or background battery measurements.

Single Battery Measurement

Set the BATT_ADC_GO bit (Bit 0) in the start ADC measurement SFR (ADCGO, Address 0xD8) to obtain a battery measurement. An interrupt is generated when the conversion is done and when the battery measurement is available in the battery ADC value SFR (BATADC, Address 0xDF).

Background Battery Measurements

To configure background measurements for the battery, establish a measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). Battery measurements are then performed periodically in the background (see Tab le 4 9 ).

When a battery conversion completes, the battery ADC value is compared to the low battery threshold, established in the battery detection threshold SFR (BATVTH, Address 0xFA). If the battery ADC value is below this threshold, a low battery flag is set. This low battery flag is the FBAT bit (Bit 2) in the power management interrupt flag SFR (IPSMF, Address 0xF8), used for power supply management.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

This low battery flag can be enabled to generate the PSM interrupt by setting the EBAT bit (Bit 2) in the power management interrupt enable SFR (IPSME, Address 0xEC). This method allows battery measurements to take place completely in the background, requiring MCU activity only if the battery drops below a user-specified threshold. To set up background battery measurements, follow these steps:

Configure the battery detection threshold SFR (BATVTH,

1. Address 0xFA) to establish a low battery threshold. If the BATADC measurement is below this threshold, the FBAT bit (Bit 2) in the power management interrupt flag SFR (IPSMF, Address 0xF8) is set.

Set up the interval for background battery measurements

2. by configuring the BATT_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9).

Battery ADC in PSM0, PSM1, and PSM2 Modes

Depending on the operating mode, a battery conversion is initiated only by certain actions.

•

In PSM0 operating mode, the 8052 is active. Battery

measurements are available in the background measurement mode and by initiating a single measurement.

In PSM1 operating mode, the 8052 is active and the part is

•

battery powered. Single battery measurements can be initiated by setting the BATT_ADC_GO bit (Bit 0) in the start ADC measurement SFR (ADCGO, Address 0xD8). Background battery measurements are not available.

In PSM2 operating mode, the 8052 is not active. Unlike

•

temperature and VDCIN measurements, the battery conversions are not available in this mode.

Battery ADC Interrupt

The battery ADC can generate an ADC interrupt when at least one of the following conditions occurs:

The new battery ADC value is smaller than the value set in

•

the battery detection threshold SFR (BATVTH, Address 0xFA), indicating a battery voltage loss.

•

A single battery measurement initiated by setting the

BATT_ADC_GO bit finishes.

When the battery flag (FBAT, Bit 2) is set in the power management interrupt flag SFR (IPSMF, Address 0xF8), a new ADC value is available in the battery ADC value SFR (BATADC, Address 0xDF). This battery flag can be enabled as a source of the PSM interrupt to generate a PSM interrupt every time the battery drops below a set voltage threshold or after a single conversion initiated by setting the BATT_ADC_GO bit is ready.

The battery ADC value SFR (BATADC, Address 0xDF) is updated with a new value only when the battery flag (FBAT) is set in the power management interrupt flag SFR (IPSMF, Address 0xF8).

EXTERNAL VOLTAGE MEASUREMENT

The ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 include a dedicated ADC to provide a digital measurement of an external voltage on the V

pin. An 8-bit SFR, the V

DCIN

ADC value SFR (VDCINADC, Address 0xEF), holds the results of the conversion. The resolution of the external voltage measurement is 15.3 mV/LSB. There are two ways to initiate an external voltage conversion: a single external voltage measurement or background external voltage measurements.

Single External Voltage Measurement

To obtain an external voltage measurement, set the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8). An interrupt is generated when the conversion is done and when the external voltage measurement is available in the V

ADC value SFR (VDCINADC,

DCIN

Address 0xEF).

Background External Voltage Measurements

Background external voltage measurements are disabled by default. To configure the background external voltage measurement mode, set an external voltage measurement interval in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9). External voltage measurements are performed periodically in the background (see Ta b le 4 9 ).

When an external voltage conversion is complete, the new external voltage ADC value is compared to the last external voltage ADC value that created an interrupt. If the absolute difference between the two values is greater than the setting in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3), a V

ADC flag is set. This V

DCIN

ADC flag is FVADC (Bit 3) in the power management interrupt flag SFR (IPSMF, Address 0xF8), which is used for power supply management. This V

ADC flag can be enabled to generate a

DCIN

PSM interrupt by setting the EVADC bit (Bit 3) in the power management interrupt enable SFR (IPSME, Address 0xEC).

This method allows external voltage measurements to take place completely in the background, requiring MCU activity only if the external voltage has changed more than a configurable delta.

To set up background external voltage measurements, follow these steps:

Initiate a single external voltage measurement by setting

the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8).

Upon completion of this measurement, configure the

2. VDCIN_DIFF[2:0] bits to establish the change in voltage that sets the FVDCIN bit (Bit 0) in the power management interrupt flag SFR (IPSMF, Address 0xF8).

Set up the interval for background external voltage measure-

3. ments by configuring the VDCIN_PERIOD bits in the peripheral ADC strobe period SFR (STRBPER, Address 0xF9).

DCIN

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

External Voltage ADC in PSM0, PSM1, and PSM2 Modes

An external voltage conversion is initiated only by certain actions that depend on the operating mode of the ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569.

In PSM0 operating mode, the 8052 is active. External

•

voltage measurements are available in the background measurement mode and by initiating a single measurement.

In PSM1 operating mode, the 8052 is active and the part is

•

powered from battery. Single external voltage measurements can be initiated by setting the VDCIN_ADC_GO bit (Bit 2) in the start ADC measurement SFR (ADCGO, Address 0xD8). Background external voltage measurements are not available.

In PSM2 operating mode, the 8052 is not active. External

•

voltage conversions are available through the background measurement mode only.

The external voltage ADC in the V (VDCINADC, Address 0xEF) is updated with a new value only when an external voltage ADC interrupt occurs.

External Voltage ADC Interrupt

The external voltage ADC can generate an ADC interrupt when at least one of the following conditions occurs:

•

The difference between the new external voltage ADC

value and the last external voltage ADC value generating an ADC interrupt is larger than the value set in the VDCIN_DIFF[2:0] bits in the temperature and supply delta SFR (DIFFPROG, Address 0xF3).

The external voltage ADC conversion initiated by setting

•

VDCIN_ADC_GO, finishes.

When the ADC interrupt occurs, a new value is available in the

ADC value SFR (VDCINADC, Address 0xEF). Note that

DCIN

there is no flag associated with this interrupt.

ADC value SFR

DCIN

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8052 MCU CORE ARCHITECTURE

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have an 8052 MCU core and use the 8052 instruction set. Some of the standard 8052 peripherals, such as the UART, have been enhanced. This section describes the standard 8052 core and enhancements that have been made to it in the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569.

The special function register (SFR) space is mapped into the upper 128 bytes of internal data memory space and is accessed by direct addressing only. It provides an interface between the CPU and all on-chip peripherals. See Figure 81 for a block diagram of the programming model for the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 via the SFR area.

All registers except the program counter (PC), instruction register (IR), and the four general-purpose register banks reside in the SFR area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals.

MCU REGISTERS

The registers used by the MCU are summarized in this section.

256 BYTES GENERAL-

PURPOSE

RAM

STACK

BANKS

Figure 81. Block Diagram Showing Programming Model via the SFRs

16kB ELECTRI CALLY

REPROGRAMMABLE

NONVOLATI LE

FLASH/EE

PROGRAM/DATA

MEMORY

8052

COMPATIBLE

CORE

256 BYTES XRAM

128-BYTE

SPECIAL FUNCTION REGISTER

AREA

ENERGY

MEASUREMENT

POWER

MANAGEMENT

RTC

LCD DRIVER

TEMPERATURE

ADC

BATTERY

ADC

OTHER ON-CHIP PERIPHERALS:

• SERIAL I/O

• WDT

• TIMER S

06353-056

Table 56. 8052 SFRs

SFR Address Bit Addressable Description

ACC 0xE0 Yes Accumulator. B 0xF0 Yes Auxiliary math. PSW 0xD0 Yes Program status word (see Table 57). PCON 0x87 No Program control (see Table 58). DPL 0x82 No Data pointer low (see Tabl e 59). DPH 0x83 No Data pointer high (see Tabl e 60). DPTR 0x82 and 0x83 No Data pointer (see Table 6 1). SP 0x81 No Stack pointer (see Table 62 ). CFG 0xAF No Configuration (see Table 63).

Table 57. Program Status Word SFR (PSW, Address 0xD0)

Bit Bit Address Mnemonic Description

7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions. 5 0xD5 F0 General-purpose flag available to the user. [4:3] 0xD4, 0xD3 RS1, RS0 Register bank select bits.

RS1 RS0 Selected Bank

0 0 0 0 1 1 1 0 2

1 1 3 2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions. 1 0xD1 F1 General-purpose flag available to the user. 0 0xD0 P

Parity bit. The number of bits set in the accumulator added to the value of the parity bit is

always an even number.

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Table 58. Program Control SFR (PCON, Address 0x87)

Bit Mnemonic Default Description

7 SMOD 0 Double baud rate control. [6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation.

Table 59. Data Pointer Low SFR (DPL, Address 0x82)

Bit Mnemonic Default Description

[7:0] DPL 0 These bits contain the low byte of the data pointer.

Table 60. Data Pointer High SFR (DPH, Address 0x83)

Bit Mnemonic Default Description

[7:0] DPH 0 These bits contain the high byte of the data pointer.

Table 61. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)

Bit Mnemonic Default Description

[15:0] DP 0

Table 62. Stack Pointer SFR (SP, Address 0x81)

Bit Mnemonic Default Description

[7:0] SP 7 These bits contain the eight LSBs of the pointer for the stack.

These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs.

Table 63. Configuration SFR (CFG, Address 0xAF)

Bit Mnemonic Default Description

7 Reserved 1 Reserved. This bit should be left set for proper operation. 6 EXTEN 0 Enhanced UART enable bit.

EXTEN Result

0 Standard 8052 UART without enhanced error-checking features.

5 SCPS 0 Synchronous communication selection bit.

SCPS Result

0 I2C port is selected for control of the shared I2C/SPI pins and SFRs. 1 SPI port is selected for control of the shared I2C/SPI pins and SFRs.

4 MOD38EN 0 38 kHz modulation enable bit.

MOD38EN Result

0 38 kHz modulation is disabled.

[3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation. [1:0] XREN1, XREN0 01

XREN[1:0] Result

XREN1 OR XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM. XREN1 AND XREN0 = 0 Disable MOVX instruction.

Enhanced UART with enhanced error checking (see the UART Additional Features section).

38 kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the extended port configuration SFR (EPCFG, Address 0x9F).

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BASIC 8052 REGISTERS

Program Counter (PC)

The program counter holds the 2-byte address of the next instruction to be fetched. The PC is initialized with 0x00 at reset and is incremented after each instruction is performed. Note that the amount that is added to the PC depends on the number of bytes in the instruction, therefore, the increment can range from one to three bytes. The program counter is not directly accessible to the user but can be directly modified by CALL and JMP instructions that change which part of the program is active.

Instruction Register (IR)

The instruction register holds the opcode of the instruction being executed. The opcode is the binary code that results from assembling an instruction. This register is not directly accessible to the user.

Register Banks

There are four banks, each containing an 8-byte-wide register, for a total of 32 bytes of registers. These registers are convenient for temporary storage of mathematical operands. An instruction involving the accumulator and a register can be executed in one clock cycle, as opposed to two clock cycles to perform an instruction involving the accumulator and a literal or a byte of general-purpose RAM. The register banks are located in the first 32 bytes of RAM.

The active register bank is selected by the RS0 and RS1 bits in the program status word SFR (PSW, Address 0xD0).

Accumulator

The accumulator is a working register, storing the results of many arithmetic or logical operations. The accumulator is used in more than half of the 8052 instructions where it is usually referred to as A. The program status register (PSW) constantly monitors the number of bits that are set in the accumulator to determine if it has even or odd parity. The accumulator is stored in the SFR space (see Tab l e 5 6 ).

B Register

The B register is used by the multiply and divide instructions, MUL AB and DIV AB to hold one of the operands. Because it is not used for many instructions, it can be used as a scratch pad register like those in the register banks. The B register is stored in the SFR space (see Tab l e 5 6 ).

Program Status Word (PSW)

The PSW register (PSW, Address 0xD0) reflects the status of arithmetic and logical operations through carry, auxiliary carry, and overflow flags. The parity flag reflects the parity of the contents of the accumulator, which can be helpful for communication protocols. The program status word SFR is bit addressable.

Data Pointer (DPTR)

The data pointer SFR (DPTR, Address 0x82 and Address 0x83) is made up of two 8-bit registers: DPL (low byte, Address 0x82), and DPH (high byte, Address 0x83). These SFRs provide memory addresses for internal code and data access. The DPTR can be manipulated as a 16-bit register (DPTR = DPH, DPL) or as two independent 8-bit registers (DPH and DPL) (see Tab l e 59 and Tab l e 60 ).

The 8052 MCU core architecture supports dual data pointers (see the 8052 MCU Core Architecture section).

Stack Pointer (SP)

The stack pointer SFR (SP, Address 0x81) keeps track of the current address of the top of the stack. To push a byte of data onto the stack, the stack pointer is incremented and the data is moved to the new top of the stack. To pop a byte of data off the stack, the top byte of data is moved into the awaiting address and the stack pointer is decremented. The stack is a last in, first out (LIFO) method of data storage because the most recent addition to the stack is the first to come off it.

The stack is used during CALL and RET instructions to keep track of the address to move into the PC when returning from the function call. The stack is also manipulated when vectoring for interrupts to keep track of the prior state of the PC.

The stack resides in the internal extended RAM, and the SP register holds the address of the stack in the extended RAM. The advantage of this solution is that the stack is segregated to the internal XRAM. The use of the general-purpose RAM can be limited to data storage. The use of the extended internal RAM can be limited to the stack pointer. This separation limits the chance of data RAM corruption when the stack pointer overflows in data RAM.

Data can still be stored in XRAM by using the MOVX command.

0xFF 0xFF

256 BYTES OF

RAM

(DATA)

0x00

Figure 82. Extended Stack Pointer Operation

0x00

256 BYTES OF

ON-CHIP XRAM

DATA + STACK

06353-057

To change the default starting address for the stack, move a value into the stack pointer (SP). For example, to enable the extended stack pointer and initialize it at the beginning of the XRAM space, use the following code:

MOV SP,#00H

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STANDARD 8052 SFRs

The standard 8052 SFRs include the accumulator (ACC), B, PSW, DPTR, and SP SFRs, as described in the Basic 8052 Registers section. The 8052 also defines standard timers, serial port interfaces, interrupts, I/O ports, and power-down modes.

Timer SFRs

The 8052 contains three 16-bit timers: the identical Timer 0 and Timer 1, as well as a Timer 2. These timers can also function as event counters. Timer 2 has a capture feature in which the value of the timer can be captured in two 8-bit registers upon the assertion of an external input signal (see Table 112 and the Timers section).

Serial Port SFRs

The full-duplex serial port peripheral requires two registers, one for setting up the baud rate and other communication parameters, and another byte for the transmit/receive buffer. The ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 also provide enhanced serial port functionality with a dedicated timer for baud rate generation with a fractional divisor and additional error detection. See Table 139 and the UART Serial Interface section.

Interrupt SFRs

There is a two-tiered interrupt system standard in the 8052 core. The priority level for each interrupt source is individually selectable as high or low. The ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 enhance this interrupt system by creating, in essence, a third interrupt tier for a highest priority power supply management interrupt (PSM). See the Interrupt System section.

I/O Port SFRs

The 8052 core supports four I/O ports, P0 through P3, where Port 0 and Port 2 are typically used for access to external code and data spaces. The ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569, unlike standard 8052 products, provide internal nonvolatile flash memory so that an external code space is unnecessary. The on-chip LCD driver requires many pins, some of which are dedicated to LCD functionality, and others that can be configured as LCD or general-purpose I/O. Due to the limited number of I/O pins, the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 do not allow access to external code and data spaces.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide 20 pins that can be used for general-purpose I/O. These pins are mapped to Port 0, Port 1, and Port 2 and are accessed through three bit-addressable 8052 SFRs: P0, P1, and P2. Another enhanced feature of these parts is that the weak pull-ups standard on 8052 Port 1, Port 2, and Port 3 can be disabled to make open-drain outputs, as is standard on Port 0. The weak pull-ups can be enabled on a pin-by-pin basis. See the I/O Ports section.

Rev. B | Page 85 of 152

Power Control Register (PCON, Address 0x87)

The 8052 core defines two power-down modes: power-down and idle. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 enhance the power control capability of the traditional 8052 MCU with additional power management functions. The POWCON register is used to define power control-specific functionality for the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569. The program control SFR (PCON, Address 0x87) is not bit addressable. See the Power Management section.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have many other peripherals not standard to the 8052 core:

ADE energy measurement DSP

•

RTC

•

LCD driver

•

Battery switchover/power management

•

Temperature ADC

•

Battery ADC

•

SPI/I

•

Flash memory controller

•

Wa t ch d og t ime r

C communication

MEMORY OVERVIEW

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 contain three memory blocks:

•

16 kB of on-chip Flash/EE program and data memory

•

256 bytes of general-purpose RAM

•

256 bytes of internal extended RAM (XRAM)

The 256 bytes of general-purpose RAM share the upper 128 bytes of its address space with the SFRs. All of the memory spaces are shown in Figure 81. The addressing mode specifies which memory space to access.

General-Purpose RAM

General-purpose RAM resides in Memory Location 0x00 through Memory Location 0xFF. It contains the register banks.

0x7F

GENERAL-PURPO SE AREA

BANKS

SELECTED

VIA

BITS IN PSW

0x30

0x20

0x18

0x10

0x08

Figure 83. Lower 128 Bytes of Internal Data Memory

0x2F

0x1F

0x17

0x0F

0x07

BIT-ADDRESSABL E (BIT ADDRESSES )

FOUR BANKS OF E IGHT REGISTERS R0 TO R7

RESET VALUE OF STACK POINT ER

06353-058

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Address 0x80 through Address 0xFF of general-purpose RAM are shared with the SFRs. The mode of addressing determines which memory space is accessed, as shown in Figure 84.

0xFF

ACCESSIBLE BY

INDIRECT ADDRESSI NG

0x80 0x7F

0x00

ONLY

ACCESSIBLE BY

DIRECT AND INDIRECT

ADDRESSING

GENERAL-PURPO SE RAM

SPECIAL FUNCT ION REGI STERS (SFRs)

Figure 84. General-Purpose RAM and SFR Memory Address Overlap

ACCESSIBLE BY

DIRECT ADDRESSI NG

ONLY

06353-059

Both direct and indirect addressing can be used to access generalpurpose RAM from 0x00 through 0x7F, but indirect addressing must be used to access general-purpose RAM with addresses in the range from 0x80 through 0xFF because they share the same address space with the SFRs.

The 8052 core also has the means to access individual bits of certain addresses in the general-purpose RAM and special function memory spaces. The individual bits of general-purpose RAM, Address 0x20 to Address 0x2F, can be accessed through Bit Address 0x00 to Bit Address 0x7F. The benefit of bit addressing is that the individual bits can be accessed quickly, without the need for bit masking, which takes more code memory and execution time. The bit addresses for general-purpose RAM Address 0x20 through Address 0x2F can be seen in Figure 85.

BYTE

ADDRESS BIT ADDRESSES (HEXA)

0x2F

0x2E

0x2D

0x2C

0x2B

0x2A

0x29

0x28

x27

0x26

0x25

0x24

0x23

0x22

0x21

0x20

06353-060

Figure 85. Bit Addressable Area of General-Purpose RAM

Bit addressing can be used for instructions that involve Boolean variable manipulation and program branching (see the Instruction Set section).

Special Function Registers (SFRs)

Special function registers are registers that affect the function of the 8052 core or its peripherals. These registers are located in RAM at Address 0x80 through Address 0xFF. They are accessible only through direct addressing as shown in Figure 84.

The individual bits of some of the SFRs can be accessed for use in Boolean and program branching instructions. These SFRs are labeled as bit-addressable and the bit addresses are given in Tabl e 15 .

Extended Internal RAM (XRAM)

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide 256 bytes of extended on-chip RAM. No external RAM is supported. This RAM is located in Address 0x00 through Address 0xFF in the extended RAM space. To select the extended RAM memory space, the extended indirect addressing modes are used.

0x00F

256 BYTES OF

EXTENDED INTE RNAL

RAM (XRAM)

0x0000

06353-061

Figure 86. Extended Internal RAM (XRAM) Space

Code Memory

Code and data memory is stored in the 16 kB flash memory space. No external code memory is supported. To access code memory, code indirect addressing is used.

ADDRESSING MODES

The 8052 core provides several addressing modes. The addressing mode determines how the core interprets the memory location or data value specified in assembly language code. There are six addressing modes, as shown in Tab le 6 4 .

Table 64. 8052 Addressing Modes

Core Clock

Addressing Mode Example Bytes

Immediate MOV A,#A8h 2 2 MOV DPTR,#A8h 3 3 Direct MOV A, A8h 2 2 MOV A, IE 2 2 MOV A, R0 1 1 Indirect MOV A, @R0 1 2 Extended Direct MOVX A, @DPTR 1 4 Extended Indirect MOVX A, @R0 1 4 Code Indirect MOVC A, @A+DPTR 1 4 MOVC A, @A+PC 1 4 JMP @A+ DPTR 1 3

Cycles

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Immediate Addressing

In immediate addressing, the expression entered after the number sign (#) is evaluated by the assembler and stored in the memory address specified. This number is referred to as a literal because it refers only to a value and not to a memory location.

Instructions using this addressing mode are slower than those between two registers because the literal must be stored and fetched from memory. The expression can be entered as a symbolic variable or as an arithmetic expression; the value is computed by the assembler.

Direct Addressing

With direct addressing, the value at the source address is moved to the destination address. Direct addressing provides the fastest execution time of all the addressing modes when an instruction is performed between registers. Note that indirect or direct addressing modes can be used to access general-purpose RAM Address 0x00 through Address 0x7F. An instruction with direct addressing that uses an address between 0x80 and 0xFF refers to a special function memory location.

Indirect Addressing

With indirect addressing, the value pointed to by the register is moved to the destination address. For example, to move the contents of internal RAM Address 0x82 to the accumulator, use the following two instructions, which require a total of four clock cycles and three bytes of storage in the program memory:

MOV R0,#82h MOV A,@R0

Indirect addressing allows addresses to be computed and is useful for indexing into data arrays stored in RAM.

Note that an instruction that refers to Address 0x00 through Address 0x7F is referring to internal RAM, and indirect or direct addressing mode can be used. An instruction with indirect addressing that uses an address between 0x80 and 0xFF refers to internal RAM, not to an SFR.

Extended Direct Addressing

The DPTR register (see Tabl e 61) is used to access internal extended RAM in extended indirect addressing mode. The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 have 256 bytes of XRAM, accessed through MOVX instructions. External memory spaces are not supported on this device.

In extended direct addressing mode, the DPTR register points to the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x100 to the accumulator:

MOV DPTR,#100h MOVX A,@DPTR

These two instructions require a total of seven clock cycles and four bytes of storage in the program memory.

Extended Indirect Addressing

The internal extended RAM is accessed through a pointer to the address in indirect addressing mode. The ADE7116/ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569 have 256 bytes of internal extended RAM, accessed through MOVX instructions. External memory is not supported on the devices.

In extended indirect addressing mode, a register holds the address of the byte of extended RAM. The following code moves the contents of extended RAM Address 0x80 to the accumulator:

MOV R0,#80h MOVX A,@R0

These two instructions require six clock cycles and three bytes of storage.

Note that there are 256 bytes of extended RAM, so both extended direct and extended indirect addressing can cover the whole address range. There is a storage and speed advantage to using extended indirect addressing because the additional byte of addressing available through the DPTR register that is not needed is not stored.

From the three examples demonstrating the access of internal RAM from 0x80 through 0xFF and extended internal RAM from 0x00 through 0xFF, it can be seen that it is most efficient to use the entire internal RAM accessible through indirect access before moving to extended RAM.

Code Indirect Addressing

The internal code memory can be accessed indirectly. This can be useful for implementing lookup tables and other arrays of constants that are stored in flash memory. For example, to move the data stored in flash memory at Address 0x8002 into the accumulator, use the following code:

MOV DPTR,#8002h CLR A MOVX A,@A+DPTR

The accumulator can be used as a variable index into the array of flash memory located at DPTR.

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INSTRUCTION SET

Tabl e 65 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting in a 4-MIPS peak performance. Note that throughout this section, A represents the accumulator.

Table 65. Instruction Set

Mnemonic Description Bytes Cycles

Arithmetic

ADD A,Rn Add register to A 1 1 ADD A,@Ri Add indirect memory to A 1 2 ADD A,dir Add direct byte to A 2 2 ADD A,#data Add immediate to A 2 2 ADDC A,Rn Add register to A with carry 1 1 ADDC A,@Ri Add indirect memory to A with carry 1 2 ADDC A,dir Add direct byte to A with carry 2 2 ADDC A,#data Add immediate to A with carry 2 2 SUBB A,Rn Subtract register from A with borrow 1 1 SUBB A,@Ri Subtract indirect memory from A with borrow 1 2 SUBB A,dir Subtract direct from A with borrow 2 2 SUBB A,#data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC @ Ri increment indirect memory 1 2 INC dir Increment direct byte 2 2 INC DPTR Increment data pointer 1 3 DEC A Decrement A 1 1 DEC Rn Decrement register 1 1 DEC @Ri Decrement indirect memory 1 2 DEC dir Decrement direct byte 2 2 MUL AB Multiply A by B 1 9 DIV AB Divide A by B 1 9 DA A A Decimal adjust A 1 2

Logic

ANL A,Rn AND register to A 1 1 ANL A,@Ri AND indirect memory to A 1 2 ANL A,dir AND direct byte to A 2 2 ANL A,#data AND immediate to A 2 2 ANL dir,A AND A to direct byte 2 2 ANL dir,#data AND immediate data to direct byte 3 3 ORL A,Rn OR register to A 1 1 ORL A,@Ri OR indirect memory to A 1 2 ORL A,dir OR direct byte to A 2 2 ORL A,#data OR immediate to A 2 2 ORL dir,A OR A to direct byte 2 2 ORL dir,#data OR immediate data to direct byte 3 3 XRL A,Rn Exclusive-OR register to A 1 1 XRL A,@Ri Exclusive-OR indirect memory to A 2 2 XRL A,#data Exclusive-OR immediate to A 2 2 XRL dir,A Exclusive-OR A to direct byte 2 2 XRL A,dir Exclusive-OR indirect memory to A 2 2 XRL dir,#data Exclusive-OR immediate data to direct 3 3 CLR A Clear A 1 1 CPL A Complement A 1 1 SWAP A Swap nibbles of A 1 1 RL A Rotate A left 1 1

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Mnemonic Description Bytes Cycles

RLC A Rotate A left through carry 1 1 RR A Rotate A right 1 1 RRC A Rotate A right through carry 1 1

Data Transfer

MOV A,Rn Move register to A 1 1 MOV A,@Ri Move indirect memory to A 1 2 MOV Rn,A Move A to register 1 1 MOV @Ri,A Move A to indirect memory 1 2 MOV A,dir Move direct byte to A 2 2 MOV A,#data Move immediate to A 2 2 MOV Rn,#data Move register to immediate 2 2 MOV dir,A Move A to direct byte 2 2 MOV Rn,dir Move register to direct byte 2 2 MOV dir,Rn Move direct to register 2 2 MOV @Ri,#data Move immediate to indirect memory 2 2 MOV dir,@Ri Move indirect to direct memory 2 2 MOV @Ri,dir Move direct to indirect memory 2 2 MOV dir,dir Move direct byte to direct byte 3 3 MOV dir,#data Move immediate to direct byte 3 3 MOV DPTR,#data Move immediate to data pointer 3 3 MOVC A,@A+DPTR Move code byte relative DPTR to A 1 4 MOVC A,@A+PC Move code byte relative PC to A 1 4 MOVX A,@Ri Move external (A8) data to A 1 4 MOVX A,@DPTR Move external (A16) data to A 1 4 MOVX @Ri,A Move A to external data (A8) 1 4 MOVX @DPTR,A Move A to external data (A16) 1 4 PUSH dir Push direct byte onto stack 2 2 POP dir Pop direct byte from stack 2 2 XCH A,Rn Exchange A and register 1 1 XCH A,@Ri Exchange A and indirect memory 1 2 XCHD A,@Ri Exchange A and indirect memory nibble 1 2 XCH A,dir Exchange A and direct byte 2 2

Boolean

CLR C Clear carry 1 1 CLR bit Clear direct bit 2 2 SETB C Set carry 1 1 SETB bit Set direct bit 2 2 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 2 ANL C,bit AND direct bit and carry 2 2 ANL C,/bit AND direct bit inverse to carry 2 2 ORL C,bit OR direct bit and carry 2 2 ORL C,/bit OR Direct bit inverse to carry 2 2 MOV C,bit Move direct bit to carry 2 2 MOV bit,C Move carry to direct bit 2 2

Branching

JMP @A+DPTR Jump indirect relative to DPTR 1 3 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 ACALL addr11 Absolute jump to subroutine 2 3 AJMP addr11 Absolute jump unconditional 2 3 SJMP rel Short jump (relative address) 2 3 JC rel Jump on carry equal to 1 2 3

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Mnemonic Description Bytes Cycles

JNC rel Jump on carry equal to 0 2 3 JZ rel Jump on accumulator = 0 2 3 JNZ rel Jump on accumulator ≠ 0 2 3 DJNZ Rn,rel Decrement register, JNZ relative 2 3 LJMP Long jump unconditional 3 4 LCALL addr16 Long jump to subroutine 3 4 JB bit,rel Jump on direct bit = 1 3 4 JNB bit,rel Jump on direct bit = 0 3 4 JBC bit,rel Jump on direct bit = 1 and clear 3 4 CJNE A,dir,rel Compare A, direct JNE relative 3 4 CJNE A,#data,rel Compare A, immediate JNE relative 3 4 CJNE Rn,#data,rel Compare register, immediate JNE relative 3 4 CJNE @Ri,#data,rel Compare indirect, immediate JNE relative 3 4 DJNZ dir,rel Decrement direct byte, JNZ relative 3 4

MISCELLANEOUS

NOP No operation 1 1

READ-MODIFY-WRITE INSTRUCTIONS

Some 8052 instructions read the latch and others read the pin. The state of the pin is read for instructions that input a port bit. Instructions that read the latch rather than the pins are the ones that read a value, possibly change it, and rewrite it to the latch. Because these instructions involve modifying the port, it is assumed that the pins being modified are outputs, so the output state of the pin is read from the latch. This prevents a possible misinterpretation of the voltage level of a pin. For example, if a port pin is used to drive the base of a transistor, a 1 is written to the bit to turn on the transistor. If the CPU reads the same port bit at the pin rather than the latch, it reads the base voltage of the transistor and interprets it as Logic 0. Reading the latch rather than the pin returns the correct value of 1.

The instructions that read the latch rather than the pins are called read-modify-write instructions and are listed in Tabl e 66. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin.

Table 66. Read-Modify-Write Instructions

Instruction Example Description

ANL ANL P0,A Logic AND ORL ORL P1,A Logic OR XRL XRL P2,A Logic EX-OR JBC JBC P1.1,LABEL Jump if bit = 1 and clear bit CPL CPL P2.0 Complement bit INC INC P2 Increment DEC DEC P2 Decrement DJNZ DJNZ P0,LABEL Decrement and jump if not zero MOV PX.Y,C1 MOV P0.0,C Move carry to Bit Y of Port X CLR PX.Y1 CLR P0.0 Clear Bit Y of Port X SETB PX.Y1 SETB P0.0 Set Bit Y of Port X

These instructions read the port byte (all eight bits), modify the addressed

bit, and write the new byte back to the latch.

INSTRUCTIONS THAT AFFECT FLAGS

Many instructions explicitly modify the carry bit, such as the MOV C bit and CLR C instructions. Other instructions that affect status flags are listed in this section.

ADD A, Source

This instruction adds the source to the accumulator. No status flags are referenced by the instruction.

Table 67. ADD A (Source) Affected Status Flags

Flag Description

AC Set if there is a carry out of Bit 3. Cleared otherwise.

ADDC A, Source

This instruction adds the source and the carry bit to the accumulator. The carry status flag is referenced by the instruction.

Table 68. ADDC A (Source) Affected Flags

Flag Description

AC Set if there is a carry out of Bit 3. Cleared otherwise.

Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned.

Set if there is a carry out of Bit 6 or a carry out of Bit 7, but not if both are set. Used to indicate an overflow for signed addition. This flag is set if two positive operands yield a negative result or if two negative operands yield a positive result.

Set if there is a carry out of Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

SUBB A, Source

This instruction subtracts the source byte and the carry (borrow) flag from the accumulator. It references the carry (borrow) status flag.

Table 69. SUBB A (Source) Affected Status Flags

Flag Description

AC Set if a borrow is needed for Bit 3. Cleared otherwise.

Set if there is a borrow needed for Bit 7. Cleared otherwise. Used to indicate an overflow if the operands are unsigned.

Set if there is a borrow needed for Bit 6 or Bit 7, but not for both. Used to indicate an overflow for signed subtraction. This flag is set if a negative number subtracted from a positive number yields a negative result or if a positive number subtracted from a negative number yields a positive result.

MUL AB

This instruction multiplies the accumulator by the B SFR. This operation is unsigned. The lower byte of the 16-bit product is stored in the accumulator and the higher byte is left in the B register. No status flags are referenced by the instruction.

Table 70. MUL AB Affected Status Flags

Flag Description

C Cleared OV Set if the result is greater than 255. Cleared otherwise.

DIV AB

This instruction divides the accumulator by the B SFR. This operation is unsigned. The integer part of the quotient is stored in the accumulator and the remainder goes into the B register. No status flags are referenced by the instruction.

Table 71. DIV AB Affected Status Flags

Flag Description

C Cleared OV

Cleared unless the B register is equal to 0, in which case the results of the division are undefined and the OV flag is set.

DA A

This instruction adjusts the accumulator to hold two 4-bit digits after the addition of two binary coded decimals (BCDs) with the ADD or ADDC instructions. If the AC bit is set or if the value of Bit 0 to Bit 3 exceeds 9, 0x06 is added to the accumulator

to correct the lower four bits. If the carry bit is set when the instruction begins, or if 0x06 is added to the accumulator in the first step, 0x60 is added to the accumulator to correct the higher four bits.

The carry and AC status flags are referenced by this instruction.

Table 72. DA A Affected Status Flag

Flag Description

Set if the result is greater than 0x99. Cleared otherwise.

RRC A

This instruction rotates the accumulator to the right through the carry flag. The old LSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new MSB of the accumulator.

The carry status flag is referenced by this instruction.

Table 73. RRC A Affected Status Flag

Flag Description

Equal to the state of ACC[0] before execution of the instruction.

RLC A

This instruction rotates the accumulator to the left through the carry flag. The old MSB of the accumulator becomes the new carry flag, and the old carry flag is loaded into the new LSB of the accumulator.

The carry status flag is referenced by this instruction.

Table 74. RLC A Affected Status Flag

Flag Description

Equal to the state of ACC[7] before execution of the instruction.

CJNE Destination, Source, Relative Jump

This instruction compares the source value to the destination value and branches to the location set by the relative jump if they are not equal. If the values are equal, program execution continues with the instruction after the CJNE instruction.

No status flags are referenced by this instruction.

Table 75. CJNE Destination (Source, Relative Jump) Affected Status Flags

Flag Description

Set if the source value is greater than the destination value. Cleared otherwise.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

DUAL DATA POINTERS

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 incorporates two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON, Address 0xA7). DPCON features automatic hardware postincrement and postdecrement, as well as an automatic data pointer toggle.

Note that this is the only section of the data sheet where the main and shadow data pointers are distinguished. Whenever the data pointer (DPTR) is mentioned elsewhere in the data sheet, active DPTR is implied.

In addition, only the MOVC/MOVX @DPTR instructions automatically postincrement and postdecrement the DPTR. Other MOVC/MOVX instructions, such as MOVC PC or MOVC @Ri, do not cause the DPTR to automatically postincrement and postdecrement.

To illustrate the operation of DPCON, the following code copies 256 bytes of code memory at Address 0xD000 into XRAM, starting from Address 0x0000:

Table 76. Data Pointer Control SFR (DPCON, Address 0xA7)

Bit Mnemonic Default Description

7 0 Not implemented. Write don’t care. 6 DPT 0

[5:4]

[3:2]

1 0 Not implemented. Write don’t care. 0 DPSEL 0

DP1m1, DP1m0

0 0 8052 behavior. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. 1 1

DP0m1, DP0m0

0 0 8052 behavior. 0 1 DPTR is postincremented after a MOVX or a MOVC instruction. 1 0 DPTR is postdecremented after a MOVX or MOVC instruction. 1 1

Data pointer automatic toggle enable. Cleared by the user to disable autoswapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.

Shadow data pointer mode. These bits enable extra modes of the shadow data pointer operation, allowing more compact and more efficient code size and execution.

DP1m1 DP1m0 Result (Behavior of the Shadow Data Pointer)

DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction can be useful for moving 8-bit blocks to/from 16-bit devices.

Main data pointer mode. These bits enable extra modes of the main data pointer operation, allowing more compact and more efficient code size and execution.

DP0m1 DP0m0 Result (Behavior of the Main Data Pointer)

DPTR LSB is toggled after a MOVX or MOVC instruction. This instruction is useful for moving 8-bit blocks to/from 16-bit devices.

Data pointer select. Cleared by the user to select the main data pointer, meaning that the contents of this 16-bit register are placed into the DPL SFR and DPH SFR. Set by the user to select the shadow data pointer, meaning that the contents of a separate 16-bit register appear in the DPL SFR and DPH SFR.

MOV DPTR,#0 ;Main DPTR = 0 MOV DPCON,#55H ;Select shadow DPTR ;DPTR1 increment mode ;DPTR0 increment mode ;DPTR auto toggling ON MOV DPTR,#0D000H ;DPTR = D000H MOVELOOP: CLR A MOVC A,@A+DPTR ;Get data ;Post Inc DPTR ;Swap to Main DPTR(Data) MOVX @DPTR,A ;Put ACC in XRAM ;Increment main DPTR ;Swap Shadow DPTR(Code) MOV A, DPL JNZ MOVELOOP

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

INTERRUPT SYSTEM

The unique power management architecture of the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 includes an operating mode (PSM2) where the 8052 MCU core is shut down. Events can be configured to wake the 8052 MCU core from the PSM2 operating mode. A distinction is drawn here between events that can trigger the wake-up of the 8052 MCU core and events that can trigger an interrupt when the MCU core is active. Events that can wake the core are referred to as wake-up events, whereas events that can interrupt the program flow when the MCU is active are called interrupts. See the 3.3 V Peripherals and Wake-Up Events section to learn more about events that can wake the 8052 core from PSM2 mode.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 provide 12 interrupt sources with three priority levels. The power management interrupt is at the highest priority level. The other two priority levels are configurable through the interrupt priority SFR (IP, Address 0xB8) and the interrupt enable and Priority 2 SFR (IEIP2, Address 0xA9).

STANDARD 8052 INTERRUPT ARCHITECTURE

The standard 8052 interrupt architecture includes two tiers of interrupts, where some interrupts are assigned a high priority and others are assigned a low priority.

HIGH

LOW

Figure 87. Standard 8052 Interrupt Priority Levels

PRIORITY 1

PRIORITY 0

06353-062

A Priority 1 interrupt can interrupt the service routine of a Priority 0 interrupt, and if two interrupts of different priorities occur at the same time, the Priority 1 interrupt is serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level occur simultaneously, a polling sequence is observed. See the Interrupt Priority section.

INTERRUPT ARCHITECTURE

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 possess advanced power supply management features. To ensure a fast response to time-critical power supply issues, such as a loss of line power, the power supply management interrupt should be able to interrupt any interrupt service routine. To enable the user to have full use of the standard 8052 interrupt priority levels, an additional priority level is added for the power supply management (PSM) interrupt. The PSM interrupt is the only interrupt at this highest interrupt priority level.

HIGH

LOW

Figure 88. Interrupt Architecture

PSM

PRIORITY 1

PRIORITY 0

06353-063

See the Power Supply Management (PSM) Interrupt section for more information on the PSM interrupt.

INTERRUPT REGISTERS

The control and configuration of the interrupt system are carried out through four interrupt-related SFRs, discussed in this section.

Table 77. Interrupt SFRs

SFR Address Default Bit Addressable Description

IE 0xA8 0x00 Yes Interrupt enable (see Table 78 ). IP 0xB8 0x00 Yes Interrupt priority (see Table 7 9). IEIP2 0xA9 0xA0 No Interrupt enable and Priority 2 (see Table 80). WDCON 0xC0 0x10 Yes

Watchdog timer (see Table 85 and the Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) section).

Table 78. Interrupt Enable SFR (IE, Address 0xA8)

Bit Bit Address Mnemonic Description

7 0xAF EA Enables all interrupt sources. Set by the user. Cleared by the user to disable all interrupt sources. 6 0xAE ETEMP

Enables the temperature ADC interrupt. Set by the user. 5 0xAD ET2 Enables the Timer 2 interrupt. Set by the user. 4 0xAC ES Enables the UART serial port interrupt. Set by the user. 3 0xAB ET1 Enables the Timer 1 interrupt. Set by the user. 2 0xAA EX1

Enables External Interrupt 1 (INT1

). Set by the user. 1 0xA9 ET0 Enables the Timer 0 interrupt. Set by the user. 0 0xA8 EX0

This feature is not available in the ADE7116.

Enables External Interrupt 0 (INT0

). Set by the user.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 79. Interrupt Priority SFR (IP, Address 0xB8)

Bit Bit Address Mnemonic Description

7 0xBF PADE ADE energy measurement interrupt Priority (1 = high, 0 = low). 6 0xBE PTEMP Temperature ADC interrupt priority (1 = high, 0 = low). 5 0xBD PT2 Timer 2 interrupt priority (1 = high, 0 = low). 4 0xBC PS UART serial port interrupt priority (1 = high, 0 = low). 3 0xBB PT1 Timer 1 interrupt priority (1 = high, 0 = low). 2 0xBA PX1 1 0xB9 PT0 Timer 0 interrupt priority (1 = high, 0 = low). 0 0xB8 PX0

Table 80. Interrupt Enable and Priority 2 SFR (IEIP2, Address 0xA9)

Bit Mnemonic Description

7 Reserved 6 PTI RTC interrupt priority (1 = high, 0 = low). 5 Reserved 4 PSI SPI/I2C interrupt priority (1 = high, 0 = low). 3 EADE Enables the energy metering interrupt (ADE). Set by the user. 2 ETI Enables the RTC interval timer interrupt. Set by the user. 1 EPSM Enables the PSM power supply management interrupt. Set by the user. 0 ESI Enables the SPI/I2C interrupt. Set by the user.

(External Interrupt 1) priority (1 = high, 0 = low).

INT1

(External Interrupt 0) priority (1 = high, 0 = low).

INT0

INTERRUPT PRIORITY

If two interrupts of the same priority level occur simultaneously, the polling sequence is observed (as shown in Tab l e 81 ).

Table 81. Priority Within Interrupt Level

Source Priority Description

IPSM 0 (highest) Power supply monitor interrupt. IRTC 1 RTC interval timer interrupt. IADE 2 ADE energy measurement interrupt. WDT 3 Watchdog timer overflow interrupt.

ITEMP IE0 5 External interrupt 0. TF0 6 Timer/Counter 0 interrupt. IE1 7 External Interrupt 1. TF1 8 Timer/Counter 1 Interrupt. ISPI/I2CI 9 SPI/I2C interrupt. RI/TI 10 UART serial port interrupt. TF2/EXF2 11 (lowest) Timer/Counter 2 interrupt.

This feature is not available in the ADE7116.

4 Temperature ADC interrupt

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INTERRUPT FLAGS

The interrupt flags and status flags associated with the interrupt vectors are shown in Tabl e 82 and Tabl e 83 . Most of the interrupts have flags associated with them.

Table 82. Interrupt Flags

Interrupt Source Flag Bit Name Description

IE0 TCON.1 IE0 External interrupt 0. TF0 TCON.5 TF0 Timer 0. IE1 TCON.3 IE1 External interrupt 1. TF1 TCON.7 TF1 Timer 1. RI + TI SCON.1 TI Transmit interrupt.

SCON.0 RI Receive interrupt.

TF2 + EXF2 T2CON.7 TF2 Timer 2 overflow flag.

ITEMP (Temperature ADC)

IPSM (Power Supply) IPSMF.6 FPSM PSM interrupt flag. IADE (Energy Measurement DSP) MIRQSTL.7 ADEIRQFLAG Read MIRQSTH, MIRQSTM, MIRQSTL.

This feature is not available in the ADE7116.

Table 83. Status Flags

Interrupt Source Flag Bit Address Description

ITEMP (Temperature ADC)

ISPI/I2CI SPI2CSTAT N/A SPI interrupt status register.

IRTC (RTC Interval Timer) TIMECON.7 MIDNIGHT RTC midnight flag.

WDT (Watchdog Timer) WDCON.2 WDS Watchdog timeout flag.

This feature is not available in the ADE7116.

A functional block diagram of the interrupt system is shown in Figure 89. Note that the PSM interrupt is the only interrupt in the highest priority level.

If an external wake-up event occurs to wake the ADE7116/ ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 from PSM2 mode, a pending external interrupt is generated. When the EX0 bit (Bit 0) or the EX1 bit (Bit 2) in the interrupt enable SFR (IE, Address 0xA8) is set to enable external interrupts, the program counter is loaded with the IE0 or IE1 interrupt vector. The IE0 and IE1 interrupt flags (Bit 1 and Bit 3, respectively) in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON, Address 0x88) are not affected by events that occur when the 8052 MCU core is shut down during PSM2. See the Power Supply Management (PSM) Interrupt section.

The RTC, temperature ADC, and I such that pending interrupts cannot be cleared without entering their respective interrupt service routines. Clearing the RTC midnight flags and alarm flags does not clear a pending RTC

T2CON.6 EXF2 Timer 2 external flag. N/A N/A Temperature ADC interrupt. Does not have an interrupt flag associated with it.

N/A N/A Temperature ADC interrupt. Does not have a status flag associated with it.

SPI2CSTAT N/A I2C interrupt status register.

TIMECON.2 ALARM RTC alarm flag.

interrupt. Similarly, clearing the I

C/SPI status bits in the SPI

Interrupt Status SFR (SPISTAT, Address 0xEA) does not cancel

a pending I until the RTC or I

C/SPI interrupt. These interrupts remain pending

C/SPI interrupt vectors are enabled. Their respective interrupt service routines are entered shortly thereafter.

Figure 89 shows how the interrupts are cleared when the interrupt service routines are entered. Some interrupts with multiple interrupt sources are not automatically cleared; specifically, the PSM, ADE, UART, and Timer 2 interrupt vectors. Note that the

INT0

and

INT1

interrupts are only cleared only if the external interrupt is configured to be triggered by a falling edge by setting IT0 (Bit 0) in the Timer/Counter 0 and Timer/Counter 1 control SFR (TCON,

C/SPI interrupts are latched

Address 0x88). If

INT0

INT1

is configured to interrupt on a low level, the interrupt service routine is reentered until the respective pin goes high.

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PRIORITY LEVEL

LOW HIGH HIGHEST

PSM

IPSMF

IPSME

FPSM

(IPSMF.6)

IE/IEIP2 REGISTERS IP/IEIP2 REGISTERS

RTC

ADE

WATCHDOG

TEMP ADC*

EXTERNAL

INTERRUPT 0

TIMER 0

EXTERNAL

INTERRUPT 1

MIDNIG HT

ALARM

MIRQSTH MIRQSTM MIRQSTL

MIRQENH MIRQENM MIRQENL

WATCHDOG T IMEOUT

TEMPADC INTE RRUPT

IT0

INT0

TF0

IT1

INT1

WDIR

IT0

IT1

IN OUT

LATCH

RESET

MIRQSTL.7

IN OUT

LATCH

RESET

PSM2

IE0

IE1

INTERRUPT POLLING SEQUENCE

TIMER 1

I2C/SPI

UART

TIMER 2

*NOT AVAIL ABLE IN THE ADE7116.

TF1

SPI INTERRUPT

I2C INTERRUPT

RI TI

TF2 EXF2

CFG.5

IN OUT

LATCH

RESET

INDIVIDUAL

INTERRUPT

ENABLE

GLOBAL

INTERRUPT

ENABLE (EA)

Figure 89. Interrupt System Functional Block Diagram

Rev. B | Page 96 of 152

LEGEND

AUTOMATIC CLEAR SIGNAL

06353-064

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

INTERRUPT VECTORS

When an interrupt occurs, the program counter is pushed onto the stack, and the corresponding interrupt vector address is loaded into the program counter. When the interrupt service routine is complete, the program counter is popped off the stack by an RETI instruction. This allows program execution to resume from where it was interrupted. The interrupt vector addresses are shown in Ta bl e 8 4 .

Table 84. Interrupt Vector Addresses

Source Vector Address

IE0 0x0003 TF0 0x000B IE1 0x0013 TF1 0x001B RI + TI 0x0023 TF2 + EXF2 0x002B ITEMP (Temperature ADC)1 0x0033 ISPI/I2CI 0x003B IPSM (Power Supply) 0x0043 IADE (Energy Measurement DSP) 0x004B IRTC (RTC Interval Timer) 0x0053 WDT (Watchdog Timer) 0x005B

This feature is not available in the ADE7116.

INTERRUPT LATENCY

The 8052 architecture requires that at least one instruction execute between interrupts. To ensure this, the 8052 MCU core hardware prevents the program counter from jumping to an ISR immediately after completing an RETI instruction or an access of the IP and IE SFRs.

The shortest interrupt latency is 3.25 instruction cycles, 800 ns with a clock of 4.096 MHz. The longest interrupt latency for a high priority interrupt results when a pending interrupt is generated during a low priority interrupt RETI, followed by a multiply instruction. This results in a maximum interrupt latency of 16.25 instruction cycles, 4 µs with a clock of 4.096 MHz.

CONTEXT SAVING

When the 8052 vectors to an interrupt, only the program counter is saved on the stack. Therefore, the interrupt service routine must be written to ensure that registers used in the main program are restored to their pre-interrupt state. Common SFRs that can be modified in the ISR are the accumulator register and the PSW register. Any general-purpose registers that are used as scratch pads in the ISR should also be restored before exiting the interrupt. The following example 8052 code shows how to restore some commonly used registers:

GeneralISR: ; save the current Accumulator value PUSH ACC ; save the current status and register bank

selection

PUSH PSW

; service interrupt …

; restore the status and registe r bank selection

POP PSW

; restore the accumulator

POP ACC RETI

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

WATCHDOG TIMER

The watchdog timer generates a device reset or interrupt within a reasonable amount of time if the ADE7116/ADE7156/ADE7166/ ADE7169/ADE7566/ADE7569 enter an erroneous state, possibly due to a programming error or electrical noise. The watchdog is enabled by default with a timeout of two seconds and creates a system reset if not cleared within two seconds. The watchdog function can be disabled by clearing the watchdog enable bit (WDE, Bit 1) in the watchdog timer SFR (WDCON, Address 0xC0).

The watchdog circuit generates a system reset or interrupt (WDS, Bit 2) if the user program fails to set the WDE bit within a predetermined amount of time (set by the PRE bits). The watchdog timer is clocked from the 32.768 kHz external crystal connected between the XTAL1 and XTAL2 pins.

Table 85. Watchdog Timer SFR (WDCON, Address 0xC0)

Bit Address Mnemonic Default Description

[7:4]

0000 15.6 ms 0001 31.2 ms 0010 62.5 ms 0011 125 ms 0100 250 ms 0101 500 ms 0110 1 sec 0111 2 sec 1000 0 sec, automatic reset 1001 0 sec, serial download reset 1010 to 1111 Not a valid selection 3 0xC3 WDIR 0

2 0xC2 WDS 0

1 0xC1 WDE 1

0 0xC0 WDWR 0

0xC7 to 0xC4

PRE 7

Watchdog prescaler. In normal mode, the 16-bit watchdog timer is clocked by the input clock (32.768 kHz). The PRE bits set which of the upper bits of the counter are used as the watchdog output, as follows:

PRE

WATCHDOG

PRE Result (Watchdog Timeout)

Watchdog interrupt response bit. When cleared, the watchdog generates a system reset when the watchdog timeout period has expired. When set, the watchdog generates an interrupt when the watchdog timeout period has expired.

Watchdog status bit. This bit is set to indicate that a watchdog timeout has occurred. It is cleared by writing a 0 or by an external hardware reset. A watchdog reset does not clear WDS; therefore, it can be used to distinguish between a watchdog reset and a hardware reset from the RESET

Watchdog enable bit. When set, this bit enables the watchdog and clears its counter. The watchdog counter is subsequently cleared again whenever WDE is set. If the watchdog is not cleared within its selected timeout period, it generates a system reset or watchdog interrupt, depending on the WDIR bit.

Watchdog write enable bit (see the Writing to the Watchdog Timer SFR (WDCON, Address 0xC0) section).

2 ×=

The WDCON SFR can be written to by user software only if the double write sequence described in Tabl e 85 is initiated on every write access to the WDCON SFR.

To prevent any code from inadvertently disabling the watchdog, a watchdog protection can be activated. This watchdog protection locks in the watchdog enable and event settings so they cannot be changed by user code. The protection is activated by clearing a watchdog protection bit in the flash memory. The watchdog protection bit is the most significant bit at Address 0x3FFA of the flash memory. When this bit is cleared, the WDIR bit (Bit 3) is forced to 0, and the WDE bit is forced to 1. Note that the sequence for configuring the flash protection bits must be followed to modify the watchdog protection bit at Address 0x3FFA (see the Protecting the Flash section).

CLKIN

pin.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 86. Watchdog and Flash Protection Byte in Flash (Flash Address = 0x3FFA)

Bit Mnemonic Default Description

7 WDPROT_PROTKY7 1 This bit holds the protection for the watchdog timer and the seventh bit of the flash protection key.

When this bit is cleared, the watchdog enable and event bits WDE and WDIR cannot be changed by user code. The watchdog configuration is then fixed to WDIR = 0 and WDE = 1. The watchdog timeout in the PRE bits can still be modified by user code.

The value of this bit is also used to set the flash protection key. If this bit is cleared to protect the watchdog, then the default value for the flash protection key is 0x7F instead of 0xFF (see the Protecting the Flash section for more information on how to clear this bit).

[6:0] PROTKY[6:0] 0xFF

Writing to the Watchdog Timer SFR (WDCON, Address 0xC0)

Writing data to the WDCON SFR involves a double instruction sequence. The WDWR (Bit 0) bit must be set, and the following instruction must be a write instruction to the WDCON SFR.

; Disable Watchdog CLR EA SETB WDWR CLR WDE SETB EA

This sequence is necessary to protect the WDCON SFR from code execution upsets that may unintentionally modify this SFR. Interrupts should be disabled during this operation due to the consecutive instruction cycles.

These bits hold the flash protection key. The content of this flash address is compared to the flash protection key SFR (PROTKY, Address 0xBB) when the protection is being set or changed. If the two values match, the new protection is written to the flash Address 0x3FFF to Address 0x3FFB. See the Protecting the Flash section for more information on how to configure these bits.

Watchdog Timer Interrupt

If the watchdog timer is not cleared within the watchdog timeout period, a system reset occurs unless the watchdog timer interrupt is enabled. The watchdog timer interrupt response bit (WDIR, Bit 3) is located in the watchdog timer SFR (WDCON, Address 0xC0). Enabling the WDIR bit allows the program to examine the stack or other variables that may have led the program to execute inappropriate code. The watchdog timer interrupt also allows the watchdog to be used as a long interval timer.

Note that WDIR is automatically configured as a high priority interrupt. This interrupt cannot be disabled by the EA bit (Bit 7) in the interrupt enable SFR (IE, Address 0xA8; see Tab l e 78). Even if all of the other interrupts are disabled, the watchdog is kept active to watch over the program.

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ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

LCD DRIVER

Using shared pins, the LCD module is capable of directly driving an LCD panel of 17 × 4 segments without compromising any ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 functions. It is capable of driving LCDs with 2×, 3×, and 4× multiplexing. The LCD waveform voltages generated through internal charge pump circuitry support up to 5 V LCDs for the ADE7156/ ADE7166/ADE7169/ADE7566/ADE7569. An external resistor ladder for LCD waveform voltage generation is also supported.

Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 has an embedded LCD control circuit, driver, and power supply circuit. The LCD module is functional in all operating modes (see the Operating Modes section).

Table 87. LCD Driver SFRs

SFR Address R/W Mnemonic Description

0x95 R/W LCDCON LCD configuration SFR (see Table 8 8). 0x96 R/W LCDCLK LCD clock (see

0x97 R/W LCDSEGE LCD segment Enable (see Table 95). 0x9C R/W LCDCONX LCD configuration X (see Table 89). 0xAC R/W LCDPTR LCD pointer (see Table 96). 0xAE R/W LCDDAT LCD data (see Table 9 7). 0xB1 R/W LCDCONY LCD configuration Y (see Table 91). 0xED R/W LCDSEGE2 LCD segment Enable 2 (see Table 98).

Table 88. LCD Configuration SFR (LCDCON, Address 0x95)

Bit Mnemonic Default Description

7 LCDEN 0 LCD enable. If this bit is set, the LCD driver is enabled. 6 LCDRST 0 LCD data registers reset. If this bit is set, the LCD data registers are reset to 0. 5 BLINKEN 0

4 LCDPSM2 0

3 CLKSEL 0 LCD clock selection.

2 BIAS 0 Bias mode.

[1:0] LMUX 0 LCD multiplex level.

Blink mode enable bit. If this bit is set, blink mode is enabled. The blink mode is configured by the BLKMOD and BLKFREQ bits in the LCD clock SFR (LCDCLK, Address 0x96).

Forces LCD off when in PSM2 (sleep) mode. Note that the internal voltage reference must be enabled by setting the REF_BAT_EN bit in the Peripheral Configuration SFR (PERIPH, Address 0xF4) to allow LCD operation in PSM2 mode.

LCDPSM2 Result

0 The LCD is disabled or enabled in PSM2 by the LCDEN bit 1 The LCD is disabled in PSM2 regardless of LCDEN setting

CLKSEL Result

0 f 1 f

BIAS Result

0 1/2 1 1/3

LMUX Result

00 Reserved. 01 2× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as FP28. 10 3× multiplexing. FP27/COM3 is used as FP27, and FP28/COM2 is used as COM2. 11 4× multiplexing. FP27/COM3 is used as COM3, and FP28/COM2 is used as COM2.

LCDC LK

= 2048 Hz = 128 Hz

LCD REGISTERS

There are six LCD control registers that configure the driver for the specific type of LCD in the end system and set up the user display preferences. The LCD configuration SFR (LCDCON, Address 0x95), LCD Configuration X SFR (LCDCONX, Address 0x9C), and LCD Configuration Y SFR (LCDCONY, Address 0xB1) contain general LCD driver configuration information including the LCD enable and reset, as well as the method of LCD voltage generation and multiplex level. The LCD clock SFR (LCDCLK, Address 0x96) configures timing settings for LCD frame rate and blink rate. LCD pins are configured for LCD functionality in the LCD segment enable SFR (LCDSEGE, Address 0x97) and the LCD Segment Enable 2 SFR (LCDSEGE2, Address 0xED).

Table 92).

Rev. B | Page 100 of 152

Datasheet ADE7116, ADE7156, ADE7166, ADE7169, ADE7569 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL FEATURES

ENERGY MEASUREMENT FEATURES

MICROPROCESSOR FEATURES

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

SPECIFICATIONS

ENERGY METERING

ANALOG PERIPHERALS

DIGITAL INTERFACE

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY

TERMINOLOGY

SPECIAL FUNCTION REGISTER (SFR) MAPPING

POWER MANAGEMENT

POWER MANAGEMENT REGISTER DETAILS

Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)

Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)

Writing to the Power Control SFR (POWCON, Address 0xC5)

POWER SUPPLY ARCHITECTURE

BATTERY SWITCHOVER

POWER SUPPLY MANAGEMENT (PSM) INTERRUPT

Battery Switchover and Power Supply Restored PSM Interrupt

SAG Monitor PSM Interrupt

USING THE POWER SUPPLY FEATURES

OPERATING MODES

PSM0 (NORMAL MODE)

PSM1 (BATTERY MODE)

PSM2 (SLEEP MODE)

3.3 V PERIPHERALS AND WAKE-UP EVENTS

TRANSITIONING BETWEEN OPERATING MODES

Automatic Battery Switchover (PSM0 to PSM1)

Entering Sleep Mode (PSM1 to PSM2)

Servicing Wake-Up Events (PSM2 to PSM1)

Automatic Switch to VDD (PSM2 to PSM0)

USING THE POWER MANAGEMENT FEATURES

ENERGY MEASUREMENT

ACCESS TO ENERGY MEASUREMENT SFRs

ACCESS TO INTERNAL ENERGY MEASUREMENT REGISTERS

Writing to the Internal Energy Measurement Registers

Reading the Internal Energy Measurement Registers

ENERGY MEASUREMENT REGISTERS

ENERGY MEASUREMENT INTERNAL REGISTER DETAILS

INTERRUPT STATUS/ENABLE SFRs

ANALOG INPUTS

ANALOG-TO-DIGITAL CONVERSION

Antialiasing Filter

ADC Transfer Function

Current Channel ADC

Voltage Channel ADC

Channel Sampling

FAULT DETECTION

Channel Selection Indication

Fault Indication

Fault with Active Input Greater Than Inactive Input

Fault with Inactive Input Greater Than Active Input

Calibration Concerns

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR FOR THE ADE7169/ADE7569

POWER QUALITY MEASUREMENTS

Zero-Crossing Detection

Zero-Crossing Timeout

Period or Frequency Measurements

Line Voltage SAG Detection

SAG Level Set

Peak Detection

Peak L evel Set

Peak Level Record

PHASE COMPENSATION

RMS CALCULATION

Current Channel RMS Calculation