ANALOG DEVICES ADE7116, ADE7156, ADE7166, ADE7169, ADE7569 Service Manual

Single-Phase Energy Measurement IC

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

with 8052 MCU, RTC, and LCD Driver

GENERAL FEATURES

Wide supply voltage operation: 2.4 V to 3.7 V Internal bipolar switch between regulated and battery inputs Ultralow power operation with power saving modes (PSM)

Full operation: 4 mA to 1.6 mA (PLL clock dependent) Battery mode: 3.2 mA to 400 μA (PLL clock dependent) Sleep mode

Real-time clock (RTC) mode: 1.5 μA

RTC and LCD mode: 38 μA (LCD charge pump enabled) Reference: 1.2 V ± 0.1% (10 ppm/°C drift) 64-lead RoHS package options

Lead frame chip scale package (LFCSP) Low profile quad flat package (LQFP)

Operating temperature range: −40°C to +85°C

ENERGY MEASUREMENT FEATURES

Proprietary analog-to-digital converters (ADCs) and digital

signal processing (DSP) provide high accuracy active (watt), reactive (var), and apparent energy (volt-ampere (VA)) measurement <0.1% error on active energy over a dynamic range of

1000 to 1 @ 25°C

<0.5% error on reactive energy over a dynamic range of

1000 to 1 @ 25°C (ADE7169 and ADE7569 only)

<0.5% error on root mean square (rms) measurements

over a dynamic range of 500 to 1 for current (I

100 to 1 for voltage (V

) @ 25°C

rms

Supports IEC 62053-21, IEC 62053-22, and IEC 62053-23;

EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16 Differential input with programmable gain amplifiers (PGAs)

supports shunts, current transformers, and di/dt current sensors (ADE7169 and ADE7569 only)

2 current inputs for antitamper detection in the

ADE7116/ADE7156/ADE7166/ADE7169

High frequency outputs proportional to I

, active, reactive,

rms

or apparent power (AP)

Table 1. Features Available on Each Part

Feature Part No.

Antitamper ADE7116, ADE7156, ADE7166, ADE7169 Watt, VA, I

rms

, V

ADE7116, ADE7156, ADE7166, ADE7169,

rms

ADE7566, ADE7569 Var ADE7169, ADE7569 di/dt Sensor ADE7169, ADE7569

rms

) and

MICROPROCESSOR FEATURES

8052-based core

Single-cycle 4 MIPS 8052 core 8052-compatible instruction set

32.768 kHz external crystal with on-chip PLL 2 external interrupt sources External reset pin

Low power battery mode

Wake-up from I/O, temperature change

universal asynchronous receiver/transmitter (UART) LCD driver operation Temperature measurement

Real-time clock (RTC)

Counter for seconds, minutes, and hours Automatic battery switchover for RTC backup Operation down to 2.4 V Ultralow battery supply current: 1.5 μA Selectable output frequency: 1 Hz to 16 kHz Embedded digital crystal frequency compensation for

calibration and temperature variation of 2 ppm resolution

Integrated LCD driver

108-segment driver for the ADE7566/ADE7569 and

104-segment driver for the ADE7116/ADE7156/

ADE7166/ADE7169 2×, 3×, or 4× multiplexing LCD voltages generated internally Internal adjustable drive voltages up to 5 V independent

of power supply level

2

On-chip peripherals

UART interface

2

SPI or I

C

Watchdog timer

Power supply management with user-selectable levels Memory: 16 kB flash memory, 512 bytes RAM Development tools

Single-pin emulation IDE-based assembly and C-source debugging

1

Not available in the ADE7116.

2

Not available in the ADE7116 or ADE7156.

1

, alarm, and

2

or with external resistors

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

REVISION HISTORY

11/08—Rev. A to Re v. B

Added ADE7116/ADE7156 ......................................... Throughout

Changes to Table 1 ............................................................................ 1

Added Figure 2 .................................................................................. 5

Changes to Table 13 ........................................................................ 16

Added Figure 10 and Table 14; Renumbered Sequentially ........ 19

Added Exposed Pad Notation to Outline Dimensions ............148

Changes to Ordering Guide .........................................................149

12/07—Rev. 0 to Rev. A

Added ADE7166/ADE7169 .............................................. Universal

Changes to Table 1 ............................................................................ 1

Changes to Ordering Guide .........................................................144

11/07—Revision 0: Initial Version

RTC Calibration ........................................................................ 125

UART Serial Interface ................................................................... 126

UART SFRs ................................................................................ 126

UART Operation Modes .......................................................... 129

UART Baud Rate Generation .................................................. 130

UART Additional Features ...................................................... 132

Serial Peripheral Interface (SPI) .................................................. 133

SPI Registers .............................................................................. 133

SPI Pins ....................................................................................... 136

SPI Master Operating Modes .................................................. 137

SPI Interrupt and Status Flags ................................................. 138

I2C-Compatible Interface ............................................................. 139

Serial Clock Generation ........................................................... 139

Slave Addresses .......................................................................... 139

I2C Registers ............................................................................... 139

Read and Write Operations ..................................................... 140

I2C Receive and Transmit FIFOs ............................................. 141

I/O Ports ......................................................................................... 142

Parallel I/O ................................................................................. 142

I/O Registers .............................................................................. 143

Port 0 ........................................................................................... 146

Port 1 ........................................................................................... 146

Port 2 ........................................................................................... 146

Determining the Version of the Part .......................................... 147

Outline Dimensions ...................................................................... 148

Ordering Guide ......................................................................... 149

Rev. B | Page 3 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

GENERAL DESCRIPTION

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/

1

ADE7569

integrate the Analog Devices, Inc., energy (ADE) metering IC analog front end and fixed function DSP solution with an enhanced 8052 MCU core, an RTC, an LCD driver, and all the peripherals to make an electronic energy meter with an LCD display in a single part.

The ADE measurement core includes active, reactive, and apparent energy calculations, as well as voltage and current rms measurements. This information is accessible for energy billing by using the built-in energy scalars. Many power line supervisory features such as SAG, peak, and zero crossing are included in the energy measurement DSP to simplify energy meter design.

FUNCTIONAL BLOCK DIAGRAMS

The microprocessor functionality includes a single-cycle 8052 core, a real-time clock with a power supply backup pin, an SPI

2

or I

C® interface, and a UART interface. The ready-to-use information from the ADE core reduces the program memory size requirement, making it easy to integrate complicated design into 16 kB of flash memory.

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 also include a 108-/104-segment LCD driver. In the ADE7166/ADE7169/ADE7566/ADE7569, this driver generates voltages capable of driving LCDs up to 5 V.

1

Patents pending.

DGND

AGND

V

BAT

T1/P0.0)

A

K L C

S

SPI/I2C

SERIAL

USER RAM 256 BYTES

USER XRAM

256 BYTES

LDO

62

D T N

I

V

O S

I M

T A D S

/

I S O M

3 × 16-BIT COUNTER

LDO

59

V

1

T0T

TIMERS

POR

A T N

I

X

0 (BCTRL/I N

E 2

T2T

P0.

45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10

SINGLE

CYCLE

8052 MCU

1-PIN

EMULATOR

51

56

T E

EA

S E R

T U O

/ N

I

F E R

57

1.20V REF

+

52

I

P

PGA1

–

53

I

N

+

49

V

P

PGA2

–

50

V

N

63

54

TEMP

SENSOR

BATTERY

58

ADC

TEMP

ADC

POWER SUPPLY

CONTROL AND

MONIT ORING

64

60

N I

C D

V

2

1

F

C

43 42 39 38 7 638 39 40 41

INTERFACE

ENERGY

MEASUREMENT

DSP

PROGRAM MEMORY

16kB FLASH

VDCIN

ADC

61

D D

V

T U O

W S

V

AL

.1/FP19P0.2/CF1/RTCC

0.3/CF2

P0

P

DOWNLOADER

DEBUGGER

UART

TIMER

44

N E D S

TA

/SCLK/T0

5/MISO

.7/SS/T1

.4/MOSI/SDA

P0

P0.6

P0.

P0

P1.0/RxD

ADE7566/ADE7569

CHARGE PUMP

108-SEGMENT

WATCHDOG

TIMER

UART

SERIAL

PORT

37

36

D

x

T

R

P24

/TxD

P1.1

P1.2/FP25

P1.3/T2EX/F

3V/5V LCD

LCD DRIVER

PLL

RTC

OSC

1 L A T X

2/FP23

P1.6/FP21P1.7

P1.4/T

P1.5/FP22

4647 48 45

2 L A T X

/FP20

0 T N

I

12

P2.0/FP18

13

P2.1/FP17

14

P2.2/FP16

44

P2.3 (SDEN/P2.3) LCDVP2

16

18

LCDVA

LCDVB

17

LCDVC

15

4

COM0

. .

...

.

COM3

1

FP0

35

. .

...

.

FP15

20

FP16

14

13

FP17

12

FP18

FP19

11

10

FP20

FP21

9

8

FP22

FP23

7

6

FP24

5

FP25

55

FP26

1

FP27

2

FP28

1 T N

I

06353-001

Figure 1. ADE7566/ADE7569 Functional Block Diagram

Rev. B | Page 4 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

.0)

A

I

DGND

AGND

V

BAT

K L C

S

SPI/I2C

SERIAL

USER RAM 256 BYTES

USER XRAM

256 BYTES

LDO

62

D T N

I

V

O S

I M

T A D S

/

I S O M

LDO

59

1

T2T

T0T

3 × 16-BIT COUNTER

TIMERS

POR

A T N

I

V

T U O

/ N

I

1.20V REF

F E R

57

2

1

F

C

43 42 39 38 7 638 39 40 41

INTERFACE

+

52

PA

I

N

PB

V

P

V

N

PGA1

–

53

–

PGA1

55

+

49

PGA2

50

–

63

54

TEMP

SENSOR

BATTERY

58

ADC

TEMP

ADC

POWER SUPPLY

CONTROL AND

MONITORING

64

60

N I

C

V

D

V

ENERGY

MEASUREMENT

61

D D

DSP

PROGRAM MEMORY

16kB FLASH

VDCIN

ADC

T U O

W S

V

RL/INT1/P0

/RTCCAL

X E 2

P0.0 (BCT

P0.1/FP19P0.2/CF1

45 11 43 42 41 40 39 38 37 36 5 6 7 8 9 10

K/T0

SI/SDATA

2

P0.3/CF

/T1

1.0/RxD

P0.7/SS

P0.6/SCL

P0.5/MISOP0.4/MO

P

ADE7116/ADE7156/ADE7166/ADE7169

CHARGE PUMP

104-SEGME NT

56

SINGLE

CYCLE

T E S E R

8052 MCU

1-PIN

51

EA

EMULATOR

UART

TIMER

44

WATCHDOG

TIMER

DOWNLOADER

DEBUGGER

UART

SERIAL

PORT

36

N E D S

D x T

37

D x

R

LCD DRIVER

RTC

/FP25

/T2EX/ FP24

.1/TxD P1

P1.2

P1.3

3V/5V LCD

P1.4/T2/FP23P1.5

PLL

OSC

4647 48 45

1 L A T X

20

/FP22

P1.6/FP21

P1.7/FP

12

P2.0/FP18

13

P2.1/FP17

14

P2.2/FP16

44

P2.3 (SDEN/P2.3)

LCDVP1

19

LCDVP2

16

LCDVA

18

17

LCDVB

LCDVC

15

4

COM0

.

...

.

COM3

1

FP0

35

.

...

.

FP15

20

FP16

14

13

FP17

12

FP18

FP19

11

10

FP20

FP21

9

8

FP22

FP23

7

6

FP24

5

FP25

1

FP27

2

FP28

2

1

0

L

T

A

N

I

T X

06353-119

Figure 2. ADE7116/ADE7156/ADE7166/ADE7169 Functional Block Diagram

Rev. B | Page 5 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

SPECIFICATIONS

VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, T

ENERGY METERING

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

MEASUREMENT ACCURACY

Phase Error Between Channels

PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37° PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°

Active Energy Measurement Error

AC Power Supply Rejection

Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms

DC Power Supply Rejection

Output Frequency Variation 0.01 % Active Energy Measurement Bandwidth Reactive Energy Measurement Error V

Measurement Error

rms

V

Measurement Bandwidth

rms

I

Measurement Error

rms

I

Measurement Bandwidth

rms

ANALOG INPUTS

Maximum Signal Levels ±400 mV peak VP − VN differential input

ADE7566/ADE7569 ±400 mV peak IP − IN differential input

ADE7116/ADE7156/ADE7166/ADE7169 ±250 mV peak IPA − IN and IPB − IN differential inputs Input Impedance (DC) 770 kΩ ADC Offset Error

2

±1 mV PGA1 = 16

Gain Error

2

Current Channel ±3 % IPA = IPB = 0.4 V dc or IP = 0.4 V dc

Voltage Channel ±3 +3 % VP − VN = 0.4 V dc Gain Error Match ±0.2 %

CF1 AND CF2 PULSE OUTPUT

Maximum Output Frequency 13.5 kHz

Duty Cycle 50 % If CF1 or CF2 frequency, >5.55 Hz Active High Pulse Width 90 ms If CF1 or CF2 frequency, <5.55 Hz

FAU LT D ETEC T ION

4

Fault Detection Threshold

Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active Input Swap Threshold

Inactive Input > Active Input 6.25 % of active IPA or IPB active Accuracy Fault Mode Operation

IPA Active, IPB = AGND 0.1 % of reading Over a dynamic range of 500 to 1

IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1 Fault Detection Delay 3 Seconds Swap Delay 3 Seconds

1

These specifications are not production tested but are guaranteed by design and/or characterization data on production release.

2

See the Terminology section for definition.

3

This function is not available in the ADE7166 or ADE7566.

4

This function is not available in the ADE7566 or ADE7569.

1

2

V

2

V

2, 3

2

0.5 % of reading Over a dynamic range of 100 to 1 at 25°C

1

3.9 kHz

2

0.5 % of reading Over a dynamic range of 500 to 1 at 25°C

1

3.9 kHz

±10 mV PGA1 = PGA2 = 1

0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C

1

8 kHz

0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C

MIN

to T

= −40°C to +85°C, unless otherwise noted.

MAX

= 3.3 V + 100 mV rms/120 Hz

DD

= 3.3 V ± 117 mV dc

DD

− VN = 400 mV peak, IPA − IN = 250 mV,

V

P

PGA1 = 2 sine wave

Rev. B | Page 6 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ANALOG PERIPHERALS

Table 3.

Parameter Min Typ Max Unit Test Conditions/Comments

INTERNAL ADCs (BATTERY, TEMPERATURE, V

Power Supply Operating Range 2.4 3.7 V Measured on V No Missing Codes Conversion Delay

2

3

ADC Gain

V

Measurement 15.3 mV/LSB

DCIN

V

Measurement 14.6 mV/LSB

BAT

Temperature Measurement 0.78 °C/LSB

ADC Offset

V

Measurement at 3 V 206 LSB

DCIN

V

Measurement at 3.7 V 205 LSB

BAT

Temperature Measurement at 25°C 129 LSB

V

Analog Input

DCIN

Maximum Signal Levels 0 3.3 V Input Impedance (DC) 1 MΩ Low V

Detection Threshold 1.09 1.2 1.27 V

DCIN

POWER-ON RESET (POR)

VDD POR

Detection Threshold 2.5 2.95 V POR Active Timeout Period 33 ms

V

POR

SWOUT

Detection Threshold 1.8 2.2 V POR Active Timeout Period 20 ms

V

POR

INTD

Detection Threshold 2.0 2.25 V POR Active Timeout Period 16 ms

V

POR

INTA

Detection Threshold 2.05 2.25 V POR Active Timeout Period 120 ms

BATTERY SWITCHOVER

Voltage Operating Range (V VDD to V

Switching

BAT

) 2.4 3.7 V

SWOUT

Switching Threshold (VDD) 2.5 2.95 V Switching Delay 10 ns When VDD to V 30 ms When VDD to V

V

to VDD Switching

BAT

Switching Threshold (VDD) 2.5 2.95 V Switching Delay 30 ms Based on VDD > 2.75 V

V

to V

SWOUT

LCD, CHARGE PUMP ACTIVE

Leakage Current 10 nA V

BAT

4

Charge Pump Capacitance Between LCDVP1 and

LCDVP2 LCDVA, LCDVB, LCDVC Decoupling Capacitance 470 nF LCDVA 0 1.75 V LCDVB 0 3.5 V 1/3 bias mode LCDVC 0 5.3 V 1/3 bias mode V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 V3 Segment Line Voltage LCDVC − 0.1 DC Voltage Across Segment and COMx Pin 50 mV

DCIN

1

)

SWOUT

8 Bits 38 μs

switch activated by VDD

BAT

= 0 V, V

BAT

switch activated by V

BAT

= 3.43 V, TA = 25°C

SWOUT

DCIN

100 nF

LCDVB V Current on segment line = −2 μA LCDVC V Current on segment line = −2 μA

LCDVC − LCDVB, LCDVC − LCDVA, or LCDVB − LCDVA

Rev. B | Page 7 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Parameter Min Typ Max Unit Test Conditions/Comments

LCD, RESISTOR LADDER ACTIVE

Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 μA V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 μA V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 μA

ON-CHIP REFERENCE

Reference Error ±0.9 mV TA = 25°C Power Supply Rejection 80 dB Temperature Coefficient

1

This function is not available in the ADE7116.

2

These specifications are not production tested but are guaranteed by design and/or characterization data on production release.

3

Delay between ADC conversion request and interrupt set.

4

This function is not available in the ADE7116 or ADE7156.

DIGITAL INTERFACE

Table 4.

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS

All Inputs Except XTAL1, XTAL2, BCTRL,

INT0 Input High Voltage, V Input Low Voltage, V

BCTRL, INT0, INT1, RESET

Input High Voltage, V Input Low Voltage, V

Input Currents

RESET Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or V

−3.75 −8.5 μA Internal pull-up enabled, input = 0 V, V Input Capacitance 10 pF All digital inputs

FLASH MEMORY

Endurance Data Retention

CRYSTAL OSCILLATOR

Crystal Equivalent Series Resistance 30 50 kΩ Crystal Frequency 32 32.768 33.5 kHz XTAL1 Input Capacitance 12 pF XTAL2 Output Capacitance 12 pF

MCU CLOCK RATE (f 32 kHz Crystal = 32.768 kHz and CD bits = 111 LOGIC OUTPUTS

Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%

I

SOURCE

Output Low Voltage, V

I

SINK

START-UP TIME

PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution From Power Saving Mode 1 (PSM1)

PSM1 to PSM0 130

From Power Saving Mode 2 (PSM2)

PSM2 to PSM1 48 PSM2 to PSM0 186

1

, INT1, RESET

2

3

80 μA

2 mA

6

2

10 50 ppm/°C

2.0 V

INH

0.8 V

INL

1.3 V

INH

0.8 V

INL

100 nA

RESET

= V

SWOUT

= 3.3 V

20,000 Cycles 20 Years TJ = 85°C

4

) 4.096 MHz Crystal = 32.768 kHz and CD bits = 000

CORE

5

OL

0.4 V VDD = 3.3 V ± 5%

ms VDD at 2.75 V to PSM0 code execution

ms Wake-up event to PSM1 code execution ms VDD at 2.75 V to PSM0 code execution

SWOUT

= 3.3 V

Rev. B | Page 8 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY INPUTS

VDD 3.13 3.3 3.46 V V

2.4 3.3 3.7 V

BAT

INTERNAL POWER SUPPLY SWITCH (V

V

to V

BAT

VDD to V V

to/from VDD Switching Open Time 40 ns

BAT

On Resistance 22 Ω V

SWOUT

On Resistance 10.2 Ω VDD = 3.13 V

SWOUT

BCTRL State Change and Switch Delay 18 μs V

Output Current Drive 6 mA

SWOUT

POWER SUPPLY OUTPUTS

V

2.3 2.70 V

INTA

V

2.3 2.70 V

INTD

V

Power Supply Rejection 60 dB

INTA

V

Power Supply Rejection 50 dB

INTD

POWER SUPPLY CURRENTS

Current in Normal Mode (PSM0) 4 5.3 mA f

2.1 mA f

1.6 mA f 3 3.9 mA

Current in PSM1 3.2 5.05 mA f 880 μA f Current in PSM2 38 μA LCD active with charge pump at 3.3 V + RTC, V

1.5 μA RTC only, TA = 25°C, V

1

Specifications guaranteed by design.

2

Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.

3

Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.

4

Recommended crystal specifications.

5

Test carried out with all the I/Os set to a low output level.

6

Delay between power supply valid and execution of first instruction by 8052 core.

)

SWOUT

= 2.4 V

BAT

= 4.096 MHz, LCD and meter active

CORE

= 1.024 MHz, LCD and meter active

CORE

= 32.768 kHz, LCD and meter active

CORE

= 4.096 MHz, metering ADC and DSP powered

f

CORE

down

= 4.096 MHz, LCD active, V

CORE

= 1.024 MHz, LCD active

CORE

BAT

= 3.3 V

= 3.7 V

BAT

= 3.3 V

BAT

Rev. B | Page 9 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TIMING SPECIFICATIONS

AC inputs during testing were driven at V and at 0.45 V for Logic 0. Timing measurements were made at V minimum for Logic 1 and at V

maximum for Logic 0, as shown in

IL

− 0.5 V for Logic 1

SWOUT

IH

Figure 3.

For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to

V

– 0.5V

SWOUT

0.45V

0.2V

SWOUT

TEST POINTS

0.2V

SWOUT

+ 0.9V

– 0.1V

Figure 3. Timing Waveform Characteristics

Table 5. Clock Input (External Clock Driven XTAL1) Parameter

32.768 kHz External Crystal

Parameter Description Min Typ Max Unit

tCK XTAL1 period 30.52 μs t

XTAL1 width low 6.26 μs

CKL

t

XTAL1 width high 6.26 μs

CKH

t

XTAL1 rise time 9 ns

CKR

t

XTAL1 fall time 9 ns

CKF

1/t

Core clock frequency

CORE

1

The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can

operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).

1

float when a 100 mV change from the loaded V

OH/VOL

level

occurs, as shown in Figure 3.

C

for all outputs is equal to 80 pF, unless otherwise noted.

LOAD

V

= 2.7 V to 3.6 V; all specifications T

DD

MIN

to T

MAX

, unless

otherwise noted.

V

LOAD

V

LOAD

– 0.1V

+ 0.1V

TIMING

REFERENCE

POINTS

V

LOAD

V

LOAD

– 0.1V

V

LOAD

06353-002

1.024 MHz

Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)

Parameter Description Typ Uni t

t

Bus-free time between stop condition and start condition 1.3 μs

BUF

tL SCLK low pulse width 1.36 μs tH SCLK high pulse width 1.14 μs t

Start condition hold time 251.35 μs

SHD

t

Data setup time 740 ns

DSU

t

Data hold time 400 ns

DHD

t

Setup time for repeated start 12.5 ns

RSU

t

Stop condition setup time 400 ns

PSU

tR Rise time of both SCLK and SDATA 200 ns tF Fall time of both SCLK and SDATA 300 ns

1

t

SUP

1

Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.

SDATA (I/O)

Pulse width of spike suppressed 50 ns

t

SCLK (I)

PSU

PS

STOP

CONDITI ON

BUF

START

CONDITI ON

t

DSU

t

SHD

MSB

1

t

DHD

2TO 7

Figure 4. I

2

C-Compatible Interface Timing

t

SUP

LSB ACK MSB

t

DSU

t

H

89 1

t

SUP

L

t

RSU

t

DHD

S(R)

REPEATED

START

t

F

t

R

t

F

t

R

06353-003

Rev. B | Page 10 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 7. SPI Master Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2 tSH SCLK high pulse width 2 t

Data output valid after SCLK edge 3 × t

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

t

DAV

t

SH

t

SL

MSB

t

DF

SPIR

CORE

t

DR

BITS [6:1]

1

× t

CORE

1

× t

CORE

1

ns

= 2CD/4.096 MHz.

CORE

t

SR

ns ns

1

ns

CORE

t

SF

LSB

MISO

MSB IN

t

DSU

DHD

BITS [6:1]

LSB IN

06353-004

Figure 5. SPI Master Mode Timing (SPICPHA = 1)

Rev. B | Page 11 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

tSL SCLK low pulse width 2 tSH SCLK high pulse width 2 t

Data output valid after SCLK edge 3 × t

DAV

t

Data output setup before SCLK edge 75 ns

DOSU

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MOSI

t

DOSU

MSB

t

SH

t

SL

t

DAV

t

DF

t

DR

BITS [6:1]

SPIR

CORE

1

× t

CORE

1

× t

(SPIR + 1) × t

CORE

1

ns

= 2CD/4.096 MHz.

CORE

t

SR

(SPIR + 1) × t

LSB

t

SF

1

ns

CORE

1

CORE

ns

1

ns

CORE

MISO

t

DSU

MSB IN

t

BITS [6:1]

DHD

LSB IN

6353-005

Figure 6. SPI Master Mode Timing (SPICPHA = 0)

Rev. B | Page 12 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 9. SPI Slave Mode Timing (SPICPHA = 1) Parameters

Parameter Description Min Typ Max Unit

t

SS

SS to SCLK edge

tSL SCLK low pulse width 6 × t tSH SCLK high pulse width 6 × t t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns t

SFS

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

high after SCLK edge

SS

t

SS

145 ns

1

CORE

1

ns

CORE

1

+ 0.5 μs μs

CORE

ns

0 ns

= 2CD/4.096 MHz.

CORE

t

SFS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MISO

MOSI

t

SH

t

DAV

t

DSU

MSB IN

MSB

t

DHD

t

SL

t

SR

t

DF

t

DR

BITS

[6:1]

t

SF

LSB

LSB IN

06353-006

Figure 7. SPI Slave Mode Timing (SPICPHA = 1)

Rev. B | Page 13 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 10. SPI Slave Mode Timing (SPICPHA = 0) Parameters

Parameter Description Min Typ Max Unit

t

SS

SS to SCLK edge

tSL SCLK low pulse width 6 × t tSH SCLK high pulse width 6 × t t

Data output valid after SCLK edge 25 ns

DAV

t

Data input setup time before SCLK edge 0 ns

DSU

t

Data input hold time after SCLK edge 2 × t

DHD

tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns t

DOSS

t

SFS

1

t

depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); t

CORE

Data output valid after SS

high after SCLK edge

SS

edge

SS

t

SS

145 ns

1

CORE

1

ns

CORE

1

+ 0.5 μs μs

CORE

ns

0 ns 0 ns

= 2CD/4.096 MHz.

CORE

t

SFS

SCLK

(SPICPOL = 0)

SCLK

(SPICPOL = 1)

MISO

MOSI

t

DOSS

t

DSU

MSB IN

MSB

t

DHD

t

SH

t

DF

t

DAV

t

SL

t

DR

BITS [6:1]

BITS [ 6:1]

t

LSB IN

LSB

t

SF

06353-007

SR

Figure 8. SPI Slave Mode Timing (SPICPHA = 0)

Rev. B | Page 14 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 11.

Parameter Rating

VDD to DGND −0.3 V to +3.7 V V

to DGND −0.3 V to +3.7 V

BAT

V

to DGND −0.3 V to V

DCIN

Input LCD Voltage to AGND, LCDVA,

LCDVB, LCDVC

1

Analog Input Voltage to AGND, VP, VN,

, IPA, IPB, and IN

I

P

−0.3 V to V

−2 V to +2 V

Digital Input Voltage to DGND −0.3 V to V Digital Output Voltage to DGND −0.3 V to V Operating Temperature R ange

−40°C to +85°C

SWOUT

+ 0.3 V + 0.3 V

(Industrial) Storage Temperature Range −65°C to +150°C 64-Lead LQFP, Power Dissipation

Lead Temperature (Soldering, 30 sec) 300°C

1

When used with external resistor divider.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 12. Thermal Resistance

Package Type θJA θ

Unit

JC

64-Lead LQFP 60 20.5 °C/W 64-Lead LFCSP 27.1 2.3 °C/W

ESD CAUTION

Rev. B | Page 15 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

T

DCIN

INTDVSWOUTVDDVINTAVBAT

V

DGND

V

646362616059585756555453525150

PIN 1

COM1 COM0

LCDVC

LCDVP2

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

ADE7566/ADE7569

171819202122232425262728293031

FP15

LCDVA

LCDVB

LCDVP1

COM3/FP27 COM2/FP28

P1.2/FP25

P1.3/T2EX/FP24

P1.4/T2/FP23

P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16

NOTES

1. IT IS RECOMMENDED THAT THE EXPO SED PAD ON THE BO TTOM OF THE L FCSP BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

Figure 9. Pin Configuration for the ADE7566/ADE7569

IN/OU

REF

TOP VIEW

(Not to Scale)

FP11

FP14

FP13

FP12

RESET

FP10

FP26

AGND

FP9

FP8

INIPVNV

EA

FP7

FP6

FP5

FP4

P

49

32

FP3

48

INT0

47

XTAL1

46

XTAL2

45

BCTRL/INT1/P0.0

44

SDEN/P2.3

43

P0.2/CF1/RTCCAL

42

P0.3/CF2

41

P0.4/MOSI/SDATA

40

P0.5/MISO

39

P0.6/SCLK/T0

38

P0.7/SS/T1

37

P1.0/RxD

36

P1.1/TxD

35

FP0

34

FP1

33

FP2

06353-120

Table 13. Pin Function Descriptions

Pin No. Mnemonic Description

1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. 15 LCDVC

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, it is internally connected to V

. A resistor should be connected

DD

between this pin and LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section).

16 LCDVP2

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section).

17 LCDVB

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally connected (see the LCD Driver section).

Rev. B | Page 16 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

18 LCDVA

19 LCDVP1

20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38

P0.7/SS

/T1 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. 42 P0.3/CF2

43 P0.2/CF1/RTCCAL

44

45

/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial

SDEN

BCTRL/INT1

/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

46 XTAL2

47 XTAL1

48

INT0

49, 50 VP, VN

51

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

EA

52, 53 IP, IN

54 AGND This pin provides the ground reference for the analog circuitry. 55 FP26 LCD Segment Output 26. 56

57 REF

58 V

59 V

RESET

IN/OUT

BAT

INTA

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section).

This pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, I

, or apparent power information.

rms

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I

, or apparent information. The RTCCAL

rms

logic output gives access to the calibrated RTC output.

download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3).

input connects V open, the connection between V

DD

or V

BAT

to V

internally when set to logic high or logic low, respectively. When left

SWOUT

or V

BAT

and V

DD

is selected internally.

SWOUT

A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7566/ADE7569. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7566/ADE7569. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

External Interrupt Input 0. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

internal program memory locations. The ADE7566/ADE7569 do not support external code memory. This pin should not be left floating.

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA.

Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V

when

DD

the battery is selected as the power supply for the ADE7566/ADE7569. This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

Rev. B | Page 17 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

60 VDD

3.3 V Power Supply Input from the Regulator. This pin is connected internally to V selected as the power supply for the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

61 V

SWOUT

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7566/ADE7569. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

62 V

INTD

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to

this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor. 63 DGND Ground Reference for Digital Circuitry. 64 V

DCIN

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V

AGND. This pin is used to monitor the preregulated dc voltage. EP Exposed Pad

The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected

to ground inside the package. It is recommended that the exposed pad be connected to the ground plane

on the board.

when the regulator is

SWOUT

with respect to

SWOUT

Rev. B | Page 18 of 152

ADE7169/ADE7566/ADE7569ADE7116/ADE7156/ADE7166/

TOP VIEW

(Not to Scale)

151413 FPFPFP

IN/OUT

REF

121110 FPFPFP

RESET

IPBAGND

FP9

FP8

INIPAVNV

EA

FP7

FP6

FP5

FP4

P

49

48

INT0

47

XTAL1

46

XTAL2

45

BCTRL/INT1/P0.0

44

SDEN/P2.3

43

P0.2/CF1/RTCCAL

42

P0.3/CF2

41

P0.4/MOSI/SDATA

40

P0.5/MISO

39

P0.6/SCLK/T0

38

P0.7/SS/T1

37

P1.0/RxD

36

P1.1/TxD

35

FP0

34

FP1

33

FP2

32

FP3

06353-120

DCIN

INTDVSWOUTVDDVINTAVBAT

V

DGND

V

646362616059585756555453525150

PIN 1

COM1 COM0

LCDVC

LCDVP2

1

INDICATOR

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

ADE7116/ADE7156/

ADE7166/ADE7169

171819202122232425262728293031 B

P1

VA

LCD

LCDV

COM3/FP27 COM2/FP28

P1.2/FP25

P1.3/T2EX/FP24

P1.4/T2/FP23

P1.5/FP22 P1.6/FP21 P1.7/FP20 P0.1/FP19 P2.0/FP18 P2.1/FP17 P2.2/FP16

NOTES

1. IT IS RECOMMENDED THAT THE EXPO SED PAD ON THE BO TTOM OF THE L FCSP BE CONNECTED TO THE GROUND PL ANE ON THE BOARD.

Figure 10. Pin Configuration for the ADE7116/ADE7156/ADE7166/ADE7169

Table 14. Pin Function Descriptions

Pin No. Mnemonic Description

1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane. 2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane. 3 COM1 Common Output 1. COM1 is used for the LCD backplane. 4 COM0 Common Output 0. COM0 is used for the LCD backplane. 5 P1.2/FP25 General-Purpose Digital I/O Port 1.2/LCD Segment Output 25. 6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24. 7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23. 8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22. 9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21. 10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20. 11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19. 12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18. 13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17. 14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16. 15 LCDVC

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, it is internally connected to V

. A resistor should be connected between this pin and

DD

LCDVB to generate the two highest voltages for the LCD waveforms (see the LCD Driver section).

16 LCDVP2

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116 and ADE7156, this pin is always an analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP1. When this pin is an analog input, it is internally connected to LCDVP1 (see the LCD Driver section).

17 LCDVB

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVC to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVA to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVB and LCDVA are internally connected (see the LCD Driver section).

Rev. B | Page 19 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

18 LCDVA

19 LCDVP1

20 to 35 FP15 to FP0 LCD Segment Output 0 to LCD Segment Output 15. 36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous). 37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receiver Data Input (Asynchronous). 38

P0.7/SS

/T1 39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input. 40 P0.5/MISO General-Purpose Digital I/O Port 0.5/Data Input for SPI Port. 41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line. 42 P0.3/CF2

43 P0.2/CF1/RTCCAL

44

45

/P2.3 Serial Download Mode Enable/General-Purpose Digital I/O Port 2.3. This pin is used to enable serial

SDEN

BCTRL/INT1

/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic

46 XTAL2

47 XTAL1

48

INT0

49, 50 VP, VN

51

This pin is used as an input for emulation. When held high, this input enables the device to fetch code from

EA

52, 53 IPA, IN

54 AGND This pin provides the ground reference for the analog circuitry. 55 IPB

56 57 REF

58 V

RESET

IN/OUT

BAT

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, it should be decoupled with a 470 nF capacitor. When this pin is an analog input, a resistor should be connected between this pin and LCDVP1 to generate an intermediate voltage for the LCD driver. In 1/3 bias LCD mode, another resistor must be connected between this pin and LCDVB to generate another intermediate voltage. In 1/2 bias LCD mode, LCDVA and LCDVB are internally connected (see the LCD Driver section).

In the ADE7166/ADE7169, this pin can be either an analog input when the LCD resistor driver is enabled or an analog output when the LCD charge pump is enabled. In the ADE7116/ADE7156, this pin is always an analog input. When this pin is an analog output, a 100 nF capacitor should be connected between this pin and LCDVP2. When this pin is an analog input, a resistor should be connected between this pin and LCDVA to generate an intermediate voltage for the LCD driver. Another resistor must be connected between LCDVP1 and DGND to generate another intermediate voltage (see the LCD Driver section).

General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input.

General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives instantaneous active, reactive, I

, or apparent power information.

rms

General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1/RTC Calibration Frequency Logic Output. The CF1 logic output gives instantaneous active, reactive, I

, or apparent power information. The

rms

RTCCAL logic output gives access to the calibrated RTC output.

download mode through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3).

or V

input connects V

DD

BAT

to V

open, the connection between V

internally when set to logic high or logic low, respectively. When left

SWOUT

or V

BAT

and V

DD

is selected internally.

SWOUT

A crystal can be connected across this pin and XTAL1 to provide a clock source for the ADE7116/ADE7156/ ADE7166/ADE7169. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.

An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected across XTAL1 and XTAL2 to provide a clock source for the ADE7116/ADE7156/ADE7166/ADE7169. The clock frequency for specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.

External Interrupt Input 0. Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum

differential level of ±400 mV for specified operation. This channel also has an internal PGA.

internal program memory locations. The ADE7116/ADE7156/ADE7166/ADE7169 do not support external code memory. This pin should not be left floating.

Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum differential level of ±400 mV for specified operation. This channel also has an internal PGA.

Analog Input for Second Current Channel (I level of ±400 mV, referred to I

for specified operation. This channel also has an internal PGA.

N

). This input is fully differential with a maximum differential

PB

Reset Input, Active Low. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of

1.2 V ± 0.1% and a maximum temperature coefficient of 50 ppm/°C. This pin should be decoupled with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.

Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V

when

DD

the battery is selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169.

Rev. B | Page 20 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Pin No. Mnemonic Description

59 V

60 VDD

61 V

62 V

63 DGND Ground Reference for Digital Circuitry. 64 V

EP Exposed Pad

INTA

SWOUT

INTD

DCIN

This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Input from the Regulator. This pin is connected internally to V

when the regulator is

SWOUT

selected as the power supply for the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the ADE7116/ADE7156/ADE7166/ADE7169. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.

Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V

with respect to

SWOUT

AGND. This pin is used to monitor the preregulated dc voltage. The exposed pad on the bottom of the LFCSP enhances thermal performance and is electrically connected

to ground inside the package. It is recommended that the exposed pad be connected to the ground plane on the board.

Rev. B | Page 21 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TYPICAL PERFORMANCE CHARACTERISTICS

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5 +25°C; PF = 1

0

–0.5

ERROR (% of Reading)

–1.0

MID CLASS C

+85°C; PF = 1

–40°C; PF = 1

2.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.5

1.0

0.5

0

–0.5

ERROR (% of Reading)

–1.0

+85°C; PF = 0.866 +25°C; PF = 0.866 –40°C; PF = 0 .866

+85°C; PF = 0 +25°C; PF = 0 –40°C; PF = 0

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

1.5 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.0

0.5

–0.5

ERROR (% of Reading)

–1.0

–1.5

+25°C; PF = 1 +85°C; PF = 1 –40°C; PF = 1

0

+25°C; PF = 0.5 +85°C; PF = 0.5 –40°C; PF = 0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

2.0 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE

1.5

1.0

0.5

0

–0.5

ERROR (% of Read ing)

–1.0

+85°C; PF = 0 +25°C; PF = 0 –40°C; PF = 0

–1.5

–2.0

0.1 1 10 100

06353-107

CURRENT CHANNEL (% of Full Scale)

06353-115

Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

+25°C; PF = 1

0

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

–2.0

0.1 1 10 100

06353-108

+85°C; PF = 1

–40°C; PF = 1

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

06353-109

Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 1 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

0

–0.5

ERROR (% of Reading)

–1.0

+25°C; PF = 1 +25°C; PF = 0.5

–40°C; PF = 1 –40°C; PF = 0.5

MID CLASS C

+85°C; PF = 1 +85°C; PF = 0.5

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)

over Temperature with Internal Reference, Integrator Off

06353-114

Rev. B | Page 22 of 152

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full S cale)

MID CLASS C

Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)

over Power Factor with Internal Reference, Integrator Off

06353-110

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

0.5 GAIN = 1 INTEGRATOR OFF

0.4 INTERNAL REFERENCE

0.3

0.2

0.1

I

0

–0.1

–0.2

ERROR (% of Read ing)

–0.3

–0.4

–0.5

0.1 1 10 100

rms

I

; 3.3V

rms

; 3.43V

I

; 3.13V

rms

CURRENT CHANNEL (% of Full S cale)

V

; 3.3V

rms

V

; 3.43V

rms

V

; 3.13V

rms

06353-111

Figure 17. Voltage and Current RMS Error as a Percentage of Reading (Gain = 1)

over Power Supply with Internal Reference, Integrator Off

1.0 GAIN = 1

INTEGRATOR OFF

0.8

INTERNAL REFERENCE

0.6

0.4

0.2

PF = 0.5

0

–0.2

–0.4

ERROR (% of Read ing)

–0.6

–0.8

–1.0

40 45 50 55 60 65 70

PF = 1

MID CLASS B

LINE FREQ UENCY (Hz)

06353-112

Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)

over Frequency with Internal Reference, Integrator Off

0.5 GAIN = 1 INTEGRATOR OFF

0.4 INTERNAL REFERENCE

0.3

0.2

VAR; 3.3V

0.1

0

–0.1

–0.2

ERROR (% of Reading)

–0.3

–0.4

–0.5

0.1 1 10 100

VAR; 3.43V

W; 3.3V

VAR; 3.13V

W; 3.13V

CURRENT CHANNEL (% of Full Scale)

W; 3.43V

06353-113

Figure 19. Active and Reactive Energy Error as a Percentage of Reading

(Gain = 1) over Power Supply with Internal Reference, Integrator Off

1.5 GAIN = 8 INTEGRATOR OFF INTERNAL REFE RENCE

1.0

0.5

PF = 1

0

–0.5

ERROR (% of Reading)

–1.0

–1.5

0.1 1 10 100

PF = –0.5

PF = +0.5

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

1.0

GAIN = 8 INTEGRATO R OFF

0.8

INTERNAL REFERENCE

0.6

0.4

PF = 1

0.2

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

PF = +0.5

0

PF = –0.5

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

1.5 GAIN = 8 INTEGRATO R OFF INTERNAL REFERENCE

1.0

0.5

PF = 1

0

–0.5

ERROR (% of Read ing)

–1.0

–1.5

0.1 1 10 100

PF = +0.5

PF = –0.5

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)

over Power Factor with Internal Reference, Integrator Off

06353-094

06353-095

06353-096

Rev. B | Page 23 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFE RENCE

1.0

0.5

+25°C; PF = 1

0

–0.5

ERROR (% of Reading)

–1.0

–1.5

–2.0

–40°C; PF = 1

+85°C; PF = 1

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFE RENCE

1.0

0.5

0

–0.5

ERROR (% of Reading)

–1.0

+85°C; PF = 0.5 +25°C; PF = 1 +25°C; PF = 0.5

+85°C; PF = 1 –40°C; PF = 1 –40°C; PF = 0 .5

MID CLASS C

1.0 GAIN = 16 INTEGRATOR OFF

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1 10 100

06353-097

CURRENT CHANNEL (% of Full Scale)

–40°C; PF = 0 +85°C; PF = 0 +85°C; PF = 0.866 –40°C; PF = 0. 866

+25°C; PF = 0.866 +25°C; PF = 0

06353-100

Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5

INTERNAL REFERENCE

1.0

0.5

–40°C; PF = 1

0

–0.5

+85°C; PF = 1

ERROR (% of Reading)

–1.0

+25°C; PF = 1

MID CLASS C

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

1.0 GAIN = 16

INTEGRATOR OFF

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Reading)

–0.6

–0.8

–1.0

0.1 1 10 100

+85°C; PF = 0

–40°C; PF = 0

+25°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

–1.5

–2.0

0.1 1 10 100

06353-098

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-101

Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)

over Temperature with Internal Reference, Integrator Off

2.0

GAIN = 16 INTEGRATOR OFF

1.5 INTERNAL REFERENCE

1.0

0.5

0

–0.5

ERROR (% o f Readi ng)

–1.0

–1.5

–2.0

0.1 1 10 100

06353-099

–40°C; PF = 1 +25°C; PF = 1 –40°C; PF = 0. 5

+85°C; PF = 0.5 +25°C; PF = 0.5 +85°C; PF = 1

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-102

Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator Off

Rev. B | Page 24 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY

2.0

GAIN = 16 INTEGRATOR ON

1.5 INTERNAL REFERENCE

1.0

0.5

0

–0.5

ERROR (% o f Readi ng)

–1.0

–40°C; PF = 1 +85°C; PF = 0.5 +25°C; PF = 0.5 –40°C; PF = 0. 5

+25°C; PF = 1 +85°C; PF = 1

MID CLASS C

2.0

GAIN = 16 INTEGRATOR ON

1.5 INTERNAL REFERENCE

1.0

+25°C; PF = 1 +25°C; PF = 0.5 +85°C; PF = 0.5

0.5

+85°C; PF = 1 –40°C; PF = 0. 5

0

–0.5

ERROR (% of Reading)

–1.0

MID CLASS C

–40°C; PF = 1

–1.5

–2.0

0.1 1 10 100

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

1.0 GAIN = 16

INTEGRATOR ON

0.8 INTERNAL REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

ERROR (% of Read ing)

–40°C; PF = 0.866

–0.6

–0.8

–1.0

0.1 1 10 10 0

+25°C; PF = 0 +85°C; PF = 0.866 –40°C; PF = 0 +25°C; PF = 0.866

+85°C; PF = 0

CURRENT CHANNEL (% of Full Scale)

Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

–1.5

–2.0

0.1 1 10 100

06353-103

CURRENT CHANNEL (% of Full Scale)

MID CLASS C

06353-105

Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)

over Power Factor with Internal Reference, Integrator On

06353-104

Rev. B | Page 25 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

TERMINOLOGY

Measurement Error

The error associated with the energy measurement made by the ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 is defined by the following formula:

Percentage Error =

⎛ ⎜

⎜ ⎝

Phase Error Between Channels

The digital integrator and the high-pass filter (HPF) in the current channel have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phase correction networks are placed in the current channel: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between current channel and voltage channel to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz.

Power Supply Rejection (PSR)

PSR quantifies the ADE7116/ADE7156/ADE7166/ADE7169/ ADE7566/ADE7569 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when an ac (100 mV rms/120 Hz) signal is introduced onto the supplies. Any error introduced by this ac signal is expressed as a percentage of reading (see the Measurement Error definition).

−

EnergyTrue

⎞

EnergyTrueRegisterEnergy

⎟

⎟ ⎠

(1)

%100×

For the dc PSR measurement, a reading at nominal supplies (3.3 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading.

ADC Offset Error

ADC offset error is the dc offset associated with the analog inputs to the ADCs. It means that, with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection (see the Typi ca l Per f o r ma n c e Characteristics section). However, when HPF1 is switched on, the offset is removed from the current channel, and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration (see the Analog Inputs section).

Gain Error

Gain error is the difference between the measured ADC output code (minus the offset) and the ideal output code (see the Current Channel ADC section and Voltage Channel ADC section). It is measured for each of the gain settings on the current channel (1, 2, 4, 8, and 16). The difference is expressed as a percentage of the ideal code.

Rev. B | Page 26 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

SPECIAL FUNCTION REGISTER (SFR) MAPPING

Table 15.

Mnemonic Address Description

INTPR 0xFF

Interrupt pins configuration

(see Table 17). SCRATCH4 0xFE Scratch Pad 4 (see Table 25). SCRATCH3 0xFD Scratch Pad 3 (see Table 24). SCRATCH2 0xFC Scratch Pad 2 (see Table 23). SCRATCH1 0xFB Scratch Pad 1 (see Table 22). BATVTH 0xFA

Battery detection threshold

(see Table 52). STRBPER 0xF9

Peripheral ADC strobe period

(see Table 49). IPSMF 0xF8

Power management interrupt flag

(see Table 18). TEMPCAL 0xF7

RTC temperature compensation

(see Table 135). RTCCOMP 0xF6

RTC nominal compensation

(see Table 134). BATPR 0xF5

Battery switchover configuration (see

Table 19). PERIPH 0xF4

Peripheral configuration

(see Table 20). DIFFPROG 0xF3

Temperature and supply delta

(see Table 50). B 0xF0 Auxiliary math (see Table 56). VDCINADC 0xEF V

ADC value (see Table 53).

DCIN

LCDSEGE2 0xED LCD Segment Enable 2 (see Table 98). IPSME 0xEC

Power management interrupt enable

(see Table 21). SPISTAT 0xEA SPI interrupt status (see Table 150). SPI2CSTAT 0xEA I2C interrupt status (see Table 154). SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 149). I2CADR 0xE9 I2C slave address (see Table 153). SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 148). I2CMOD 0xE8 I2C mode (see Table 152). WAV2H 0xE7 Selection 2 sample MSB (see Table 31). WAV2 M 0xE 6

Selection 2 sample middle byte

(see Table 31). WAV2L 0xE5 Selection 2 sample LSB (see Table 31). WAV1H 0xE4 Selection 1 sample MSB (see Table 31). WAV1 M 0xE 3

Selection 1 sample middle byte (see

Table 31). WAV1L 0xE2 Selection 1 sample LSB (see Table 31). ACC 0xE0 Accumulator (see Table 56). BATADC 0xDF Battery ADC value (see Table 54). MIRQSTH 0xDE Interrupt Status 3 (see Table 42). MIRQSTM 0xDD Interrupt Status 2 (see Table 41). MIRQSTL 0xDC Interrupt Status 1 (see Table 40). MIRQENH 0xDB Interrupt Enable 3 (see Table 45). MIRQENM 0xDA Interrupt Enable 2 (see Table 44). MIRQENL 0xD9 Interrupt Enable 1 (see Table 43). ADCGO 0xD8 Start ADC measurement (see Table 51).

Mnemonic Address Description

TEMPADC 0xD7 Temperature ADC value (see Table 55). IRMSH 0xD6 I IRMSM 0xD5

measurement MSB (see Table 31).

rms

measurement middle byte

I

rms

(see Table 31). IRMSL 0xD4 I VRMSH 0xD3 V VRMSM 0xD2

measurement LSB (see Table 31).

rms

measurement MSB (see Table 31).

rms

measurement middle byte

V

rms

(see Table 31). VRMSL 0xD1 V

measurement LSB (see Table 31).

rms

PSW 0xD0 Program status word (see Table 57). TH2 0xCD Timer 2 high byte (see Table 120). TL2 0xCC Timer 2 low byte (see Table 121). RCAP2H 0xCB

Timer 2 reload/capture high byte

(see Table 122). RCAP2L 0xCA

Timer 2 reload/capture low byte

(see Table 123). T2CON 0xC8 Timer/Counter 2 control (see Table 115). EADRH 0xC7 Flash high byte address (see Table 110). EADRL 0xC6 Flash low byte address (see Table 109). POWCON 0xC5 Power control (see Table 26). KYREG 0xC1 Key (see Table 126). WDCON 0xC0 Watchdog timer (see Table 85). PROTR 0xBF Flash read protection (see Table 108). PROTB1 0xBE

Flash Write/Erase Protection 1

(see Table 107). PROTB0 0xBD

Flash Write/Erase Protection 0

(see Table 106). EDATA 0xBC Flash data (see Table 105). PROTKY 0xBB Flash protection key (see Table 104). FLSHKY 0xBA Flash key (see Table 103). ECON 0xB9 Flash control (see Table 102). IP 0xB8 Interrupt priority (see Table 79). PINMAP2 0xB4

Port 2 weak pull-up enable

(see Table 159). PINMAP1 0xB3

Port 1 weak pull-up enable

(see Table 158). PINMAP0 0xB2

Port 0 weak pull-up enable

(see Table 157). LCDCONY 0xB1 LCD Configuration Y (see Table 91). CFG 0xAF Configuration (see Table 63). LCDDAT 0xAE LCD data (see Table 97). LCDPTR 0xAC LCD pointer (see Table 96). IEIP2 0xA9

Interrupt Enable and Priority 2

(see Table 80). IE 0xA8 Interrupt enable (see Table 78). DPCON 0xA7 Data pointer control (see Table 76). INTVAL 0xA6 RTC alarm interval (see Table 133). HOUR 0xA5 RTC hours counter (see Table 132). MIN 0xA4 RTC minutes counter (see Table 131). SEC 0xA3 RTC seconds counter (see Table 130).

Rev. B | Page 27 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Mnemonic Address Description

HTHSEC 0xA2

TIMECON 0xA1 RTC configuration (see Table 128). P2 0xA0 Port 2 (see Table 162). EPCFG 0x9F

SBAUDT 0x9E

SBAUDF 0x9D

LCDCONX 0x9C LCD Configuration X (see Tab le 89). SPI2CRx 0x9B SPI/I2C receive buffer (see Table 147). SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 146). SBUF 0x99 Serial port buffer (see Table 141). SCON 0x98

LCDSEGE 0x97 LCD segment enable (see Table 95 ). LCDCLK 0x96 LCD clock (see Table 92). LCDCON 0x95 LCD configuration (see Table 88). MDATH 0x94

RTC hundredths of a second counter (see Table 129).

Extended port configuration (see Table 156).

Enhanced serial baud rate control (see Table 142).

UART timer fractional divider (see Table 143).

Serial communications control (see Table 140).

Energy measurement pointer data MSB (see Tab le 31).

Mnemonic Address Description

MDATM 0x93

MDATL 0x92

MADDPT 0x91

P1 0x90 Port 1 (see Table 161). TH1 0x8D Timer 1 high byte (see Table 118). TH0 0x8C Timer 0 high byte (see Table 116). TL1 0x8B Timer 1 low byte (see Table 119). TL0 0x8A Timer 0 low byte (see Table 117). TMOD 0x89

TCON 0x88

PCON 0x87 Program control (see Table 58 ). DPH 0x83 Data pointer high (see Tab le 60). DPL 0x82 Data pointer low (see Table 5 9). SP 0x81 Stack pointer (see Tab le 62). P0 0x80 Port 0 (see Table 160).

Energy measurement pointer data middle byte (see Table 31).

Energy measurement pointer data LSB (see Tab le 31).

Energy measurement pointer address (see Tab le 30).

Timer/Counter 0 and Timer/Counter 1 mode (see Table 113).

Timer/Counter 0 and Timer/Counter 1 control (see Table 114).

Rev. B | Page 28 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

POWER MANAGEMENT

The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ ADE7569 have elaborate power management circuitry that manages the switchover from regular power supply to battery

Table 16. Power Management SFRs

SFR Address R/W Mnemonic Description

0xEC R/W IPSME Power management interrupt enable (see Tabl e 21). 0xF5 R/W BATPR Battery switchover configuration (see Table 19 ). 0xF8 R/W IPSMF Power management interrupt flag (see Tabl e 18). 0xFF R/W INTPR Interrupt pins configuration (see Table 1 7). 0xF4 R/W PERIPH Peripheral configuration (see Tab le 20). 0xC5 R/W POWCON Power control (see Table 26). 0xFB R/W SCRATCH1 Scratch Pad 1 (see Ta ble 22 ). 0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23). 0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 2 4). 0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25).

POWER MANAGEMENT REGISTER DETAILS

Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)

Bit Mnemonic Default Description

7 RTCCAL 0

[6:5] FSEL 00 Sets RTC calibration output frequency and calibration window.

4 Reserved N/A [3:1] INT1PRG 000

0 INT0PRG 0

Controls RTC calibration output. When set, the RTC calibration frequency selected by the FSEL bits is output on the P0.2/CF1/RTCCAL pin.

FSEL Result (Calibration Window, Frequency)

00 30.5 sec, 1 Hz 01 30.5 sec, 512 Hz 10 0.244 sec, 500 Hz 11 0.244 sec, 16 kHz

Controls the function of INT1

INT1PRG Result

X00 GPIO enabled X01 BCTRL enabled 01X 11X

Controls the function of INT0

INT0PRG Result 0 1

INT1 INT1

INT0 INT0

.

input disabled input enabled

.

input disabled input enabled

and manages power supply failures. The power management functionalities can be accessed directly through the 8052 SFRs (see Tabl e 16 ).

Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)

To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to INTPR. KYREG (see Table 126) should be set to 0xEA to unlock this SFR and reset to 0 after a timekeeping register is written to. The RTC registers can be written using the following 8052 assembly code:

MOV KYREG, #0EAh MOV INTPR, #080h

Rev. B | Page 29 of 152

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569

Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)

Bit Bit Address Mnemonic Default Description

7 0xFF FPSR 0

Power supply restored interrupt flag. Set when the V This occurs when the source of V

changes from V

SWOUT

6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs. 5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs. 4 0xFC Reserved 0 This bit must be kept at 0 for proper operation. 3 0xFB FVADC

1

0

VDCINADC monitor interrupt flag. Set when V

DCIN

measurement is ready. 2 0xFA FBAT 1 0xF9 FBSO 0 Battery switchover interrupt flag. Set when V 0 0xF8 FVDCIN

1

This feature is not available in the ADE7116.

1

0 V

1

0 V

monitor interrupt flag. Set when V

BAT

monitor interrupt flag. Set when V

DCIN

falls below BATVTH or when V

BAT

SWOUT

falls below 1.2 V.

DCIN

Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)

Bit Mnemonic Default Description

[7:2] Reserved 00 These bits must be kept at 0 for proper operation. [1:0] BATPRG 00 Control bits for battery switchover.

BATPRG Result

00 Battery switchover enabled on low VDD 01 Battery switchover enabled on low VDD and low V 1X Battery switchover disabled

power supply has been restored.

DD

to VDD.

BAT

changes by VDCIN_DIFF or when V

measurement is ready.

BAT

switches from VDD to V

DCIN

BAT.

DCIN

Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)

Bit Mnemonic Default Description

7 RXFLAG 0 If set, indicates that an Rx edge event triggered wake-up from PSM2. 6 VSWSOURCE 1 Indicates the power supply that is internally connected to V

SWOUT

(0: V

SWOUT

= V

BAT

; 1: V

SWOUT

= VDD). 5 VDD_OK 1 If set, indicates that VDD power supply is ready for operation. 4 PLL_FLT 0

If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (see Table 51) in the start ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the PLL_FLT bit.

3 REF_BAT_EN 0

Set this bit to enable internal voltage reference in PSM2 mode. This bit should be set if LCD is on in

PSM1 and PSM2 mode. 2 Reserved 0 This bit must be kept at 0 for proper operation. [1:0] RXPROG 00 Controls the function of the P1.0/RxD pin.

RXPROG Result

00 GPIO 01 RxD with wake-up disabled 11 RxD with wake-up enabled

Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)

Bit Mnemonic Default Description

7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set. 6 Reserved 0 Reserved. 5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set. 4 Reserved 0 This bit must be kept at 0 for proper operation. 3 EVADC 2 EBAT1 0 Enables a PSM interrupt when the V

1

0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.

monitor interrupt flag (FBAT) is set.

BAT

1 EBSO 0 Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set. 0 EVDCIN1 0 Enables a PSM interrupt when the V

1

This feature is not available in the ADE7116.

monitor interrupt flag (FVDCIN) is set.

DCIN

Rev. B | Page 30 of 152

ANALOG DEVICES ADE7116, ADE7156, ADE7166, ADE7169, ADE7569 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL FEATURES

ENERGY MEASUREMENT FEATURES

MICROPROCESSOR FEATURES

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

SPECIFICATIONS

ENERGY METERING

ANALOG PERIPHERALS

DIGITAL INTERFACE

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

PERFORMANCE CURVES FOR THE ADE7169 AND ADE7569 ONLY

TERMINOLOGY

SPECIAL FUNCTION REGISTER (SFR) MAPPING

POWER MANAGEMENT

POWER MANAGEMENT REGISTER DETAILS

Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)