ANALOG DEVICES ADD8754 Service Manual

www.BDTIC.com/ADI

FEATURES

Step-up switching regulator with 2 A power switch

650 kHz or 1.2 MHz switching frequency
Output adjustable to 20 V

350 mA logic voltage regulator

Selectable output voltages: 2.5 V, 2.85 V, 3.3 V

amplifier with 300 mA drive

V

COM

Gate pulse modulation circuitry

Independently adjustable delay and falling slope

General

3 V to 5.5 V input
Undervoltage lockout
Thermal shutdown
24-lead, Pb-free LFCSP package

APPLICATIONS

TFT LCD panels for monitors, TVs, and notebooks

LCD Panel Power, V

and

G

FUNCTIONAL BLOCK DIAGRAM

ADD8754

FB
FREQ
SHDN

VDD_2

OUT

STEP-UP SWITCHING

REGULATOR

UNDER VOLTAGE LOCKOUT

AND THERMAL PROTECTION

LOGIC VOLTAGE

REGULATOR

VCOM AMPLIFIER

GATE PULSE

MODULATION

COM

ate Modulation

ADD8754

VIN_2VIN_1SSCOMP

LX

LDO_OUT
ADJ

POS
NEG

,

GENERAL DESCRIPTION

The ADD8754 is optimized for use in TFT LCD applications,
requiring only external charge pump components to provide all
the requirements for panel power, V
Included in a single chip are a high frequency step-up dc-to-dc
switching regulator, logic voltage regulator, V
gate pulse modulation circuitry.

The step-up dc-to-dc converter provides up to 20 V output and

cludes a 2 A internal switch. Either a 650 kHz or 1.2 MHz step-

in
up switching regulator frequency can be chosen, allowing easy
filtering and low noise operation. It achieves 93% efficiency and
features soft start to limit the inrush current at startup.

The internal voltage regulator operates with an input voltage

nge of 3 V to 5.5 V and delivers a load current of up to

ra

, and gate modulation.

COM

amplifier, and

COM

VGH VGH_M VDD_1 CE RE VFLK VDPM

Figure 1.

05110-001

350 mA. Three selectable output voltages are available: 2.5 V,

2.85 V, and 3.3 V.

The proprietary V

amplifier can deliver a peak output

COM

current of 300 mA and is specifically designed to drive TFT
panel loads.

The gate pulse modulator allows shaping of the TFT gate high

oltage to improve image quality. The integrated switches

v
provide the ability to independently control the delay and slope
for the gate drive voltage.

The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and
is

specified over the industrial temperature range of −40 to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2005 Analog Devices, Inc. All rights reserved.

ADD8754

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Current-Mode, Step-Up Switching Regulator Operation..... 12

Step-Up Switching Regulator Specifications............................. 3

LDO Regulator Specifications .................................................... 4

V

Amplifier Specifications .................................................... 5

COM

Gate Pulse Modulator Specifications......................................... 6

General Specifications ................................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 12

REVISION HISTORY

4/05—Revision 0: Initial Version

V

Amplifier ........................................................................... 16

COM

Gate Pulse Modulator Circuit................................................... 16

Power-Up Sequence ................................................................... 17

Shutdown..................................................................................... 17

UVLO........................................................................................... 17

Power Dissipation....................................................................... 18

Layout Guidelines....................................................................... 19

Typical Application C i r c uits ......................................................... 20

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

Rev. 0 | Page 2 of 28

ADD8754

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SPECIFICATIONS

STEP-UP SWITCHING REGULATOR SPECIFICATIONS

VIN_1 = VIN_2 =

SHDN

= 5 V, V

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY

Input Voltage Range VIN 3.0 5.5 V

OUTPUT

1

Output Voltage Range V
Load Regulation 10 mA ≤ I
Line Regulation I
Load Regulation 10 mA ≤ I
Line Regulation I
Overall Regulation Line, load, temperature (−40°C ≤ TA ≤ +85°C) −3 +3 %

REFERENCE

Feedback Voltage VFB 1.200 1.211 1.220 V

ERROR AMPLIFIER

Transconductance G
Gain A
Input Bias Current I

SWITCH

On Resistance R
Leakage Current I
Peak Current Limit I

OSCILLATOR

Oscillator Frequency F
FREQ = VIN_1 1.2 MHz
Maximum Duty Cycle D

SOFT START

Peak Current SS = GND 2.5 μA

1

Refer to the Figure 23.

1

= VDD_1 = VDD_2 = 14 V, TA = 25°C, FREQ = GND, unless otherwise noted.

OUT

OUT

MEA

V

B

DS (ON)

LKG

CL

OSC

MAX

1

20 V

≤ 150 mA, V

LOAD

= 350 mA, 4.5 V ≤ VIN_1 ≤ 5.5 V mV

LOAD

≤ 150 mA, V

LOAD

= 150 mA, 3.0 V ≤ VIN_1 ≤ 5.5 V mV

LOAD

1

= 10 V 200 μV/mA

OUT

1

= 10 V 200 μV/mA

OUT

100 μA/V
1000 V/V
225 nA

170 mΩ
VLX = 14 V, SHDN = GND

0.5 μA

2.6 A

FREQ = GND 650 kHz

VFB = 1 V 90 95 %

Rev. 0 | Page 3 of 28

ADD8754

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LDO REGULATOR SPECIFICATIONS

VIN_1 = VIN_2 =

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

INPUT

Input Voltage Range VIN

ADJ = OPEN

ADJ = GND

OUTPUT

= 5 V, ADJ = LDO_OUT,1 CLDO = 2.2 μF, TA = 25°C, unless otherwise noted.

SHDN

2

ADJ = LDO_OUT

1

3

4

3.0 5.5 V

3.35 5.5 V

3.8 5.5 V

Output Voltage LDO_OUT I

I

I

I

I

I

Voltage Accuracy I

Line Regulation I

Load Regulation I

Dropout Voltage V

Current Limit I

1

Sets LDO_OUT(NOM) to 2.5 V.

2

VIN = VIN_1 = VIN_2.

3

Sets LDO_OUT(NOM) to 2.85 V.

4

Sets LDO_OUT(NOM) to 3.3 V.

DROP

LDPK

= 1 mA, ADJ = GND 3.31 V

LDO

= 350 mA, ADJ = GND 3.29 V

LDO

= 1 mA, ADJ = OPEN 2.86 V

LDO

= 350 mA, ADJ = OPEN 2.84 V

LDO

= 1 mA, ADJ = LDO_OUT 2.51 V

LDO

= 350 mA, ADJ = LDO_OUT 2.49 V

LDO

= 1 mA to 350 mA, −40°C ≤ TA ≤ +85°C −3 +3 %

LDO

= 1 mA 3 mV/V

LDO

= 1 mA to 350 mA 20 mV

LDO

LDO_OUT = 98% of LDO_OUT(NOM), I

= 350 mA 300 500 mV

LDO

350 mA

Rev. 0 | Page 4 of 28

ADD8754

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V

AMPLIFIER SPECIFICATIONS

COM

VIN_1 = VIN_2 =

Table 3.

Parameter Symbol Conditions Min Typ Max Unit

INPUT CHARACTERISTICS

Offset Voltage V
Noninverting Input Bias Current I

Input Voltage Range 2 VDD_2 − 3 V
Common-Mode Rejection Ratio CMRR VCM = 2 V to (VDD_2 − 3) V 60

OUTPUT CHARACTERISTICS

Output Voltage Swing V

V

Output Current

1

POWER SUPPLY

Supply Voltage VDD_2 8 18 V
Power Supply Rejection Ratio PSRR 7.5 V ≤ VDD_2 ≤ 18.5 V 65 70 dB

Supply Current I

DYNAMIC PERFORMANCE

Slew Rate

2

Gain Bandwidth GBW −3 dB, RL = 10 kΩ, CL = 10 pF 1.95 MHz

1

Not short-circuit protected.

2

Slew rate is the average of the rising and the falling slew rates.

= 5 V, VDD_2 = 14 V, POS = 4.0 V, NEG = OUT, TA = 25°C, unless otherwise noted.

SHDN

OS

B

OH

OL

I

OUT

SY

SR RL = 10 kΩ, CL = 10 pF 105

19 mV
50 300 nA

I

(source) = 50 mA VDD_2 − 0.5 V

OUT

I

(sink) = 50 mA 50 mV

OUT

No load, POS = VDD_2 /2 2 mA

dB

±300 mA

V/μs

Rev. 0 | Page 5 of 28

ADD8754

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GATE PULSE MODULATOR SPECIFICATIONS

VIN_1 = VIN_2 =

Table 4.

Parameter Symbol Condition Min Typ Max Unit

INPUT CHARACTERISTICS

VGH Voltage VGH 7 30 V
VGH Input Current I
VDD_1 Voltage 7 VGH V

VDD_1 Input Current I

CONTROL INPUT CHARACTERISTICS

VFLK Voltage Low V

VFLK Voltage High V

VFLK Input Current I

VDPM Voltage Low V

VDPM Voltage High V

VDPM Input Current I

SWITCHING CHARACTERISTICS

VGH to VGH_M On Resistance R
VGH_M Discharge Current

DELAY CHARACTERISTICS

Delay Time

1

Discharge current = 302.5/(RE + 5000).

2

Delay time = CE × 4200.

2

= 5 V, VGH = 20 V, VDD_1 = 14 V, TA = 25°C, unless otherwise noted.

SHDN

VGH

VDD_1

LOWFLK

HIGHFLK

FLK

LOWDPM

HIGHDPM

VDPM

1

VGH

I

VGH_M

T

CE = 470 pF, RE = 33 kΩ 1.88 μs

DELAY

VFLK = GND, VDPM = LDO_OUT 95 μA

VFLK = VDPM = LDO_OUT 0.02 μA

0.8 V

2.2 V

0.9 ≤ VFLK ≤ LDO_OUT −1 +1 μA

0.8 V

2.2 V

0.9 ≤ VDPM ≤ LDO_OUT −1 +1 μA

VDPM = VFLK = LDO_OUT 60 Ω
VFLK < 0.8 V, RE = 33 kΩ 8.0 mA

GENERAL SPECIFICATIONS

VIN_1 = VIN_2 =

Table 5.

Parameter Symbol Conditions Min Typ Max Unit

SHUTDOWN

Input Voltage Low V

Input Voltage High V

Shutdown Pin Input Current

Total Ground Current

Total VIN Current (I

UNDERVOLTAGE LOCKOUT

UVLO Rising Threshold V
UVLO Falling Threshold V

QUIESCENT CURRENT

Step-Up Regulator in Nonswitching State I
Step-Up Regulator in Switching State I

= 5 V, TA = 25°C, unless otherwise noted.

SHDN

IL

IH

+ I

VIN_1

)

VIN_2

UVLOR

UVLOF

Q

QSW

0.8

2.2
GND ≤ SHDN

SHDN

SHDN

= GND

= GND

≤ 5.5 V

−1 +1

2.0

−1 +1

V
V

μA
μA

μA

VIN_1 rising 2.8 V
VIN_1 falling 2.6 V

300 500 μA
2 3 mA

Rev. 0 | Page 6 of 28

ADD8754

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ABSOLUTE MAXIMUM RATINGS

T = 25°C, unless otherwise noted.

A

Table 6.

Parameter Symbol Rating

RE, CE, FB, SHDN

COMP, SS, VIN_
ADJ, VDPM, VFLK to GND,
PGND, and AGND

OUT, NEG and POS to GND,

PGND, and AG
LX to GND, PGND, and AGND −0.5 V to +22 V
VDD_2 and OUT to GND, PGND,

and AGND
Voltage Between GND and

AGND, GND

AGND and PGND
VDD_1, VGH, and VGH_M to

GND, PGND,
Differential Voltage Between

POS and NEG
Package Power Dissipation P
Thermal Resistance θ
Maximum Junction Temperature T
Operating Temperature Range T
Storage Temperature Range T
Reflow Peak Temperature

(20 sec to 40 sec)

, VIN_2, FREQ,

1, LDO_OUT,

ND

and PGND, and

and AGND

−0.5 V to +16 V

±0.5 V

D

JA

max 125°C

J

A

S

250°C

−0.5 V to +6.5 V

−0.5 V to +18.5
V

−0.5 V to +32 V

±5 V

(TJ max − TA)/θ
38°C/W

−40°C to +85°C

−65°C to +150°C

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Absolute maximum ratings apply individually only, not in
combination.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 28

ADD8754

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

VGH_M

VFLK

VDPM
VDD_1
VDD_2

VGHRECE

24

23 22 21 20 19

1

2

3

4

5

6

789101112

OUT

PGND

ADD8754

TOP VIEW

(Not to Scale)

POS

NEG

AGND

FB

ADJ

LDO_OUT SHDN

18

LX

17

VIN_2

16

FREQ

15

COMP

14

SS

13

VIN_1

05110-002

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin Mnemonic Description

1 GND Ground.
2 VGH_M Gate Pulse Modulator Output. This pin supplies the gate drive signal.
3 VFLK

4 VDPM

Gate Pulse Modulator Control Input.
Gate Pulse Modulator Enable. VGH_M is enabled when the voltage on this pin is more than 2.2 V. VGH_M goes to

GND when this pin is connected to GND.
5 VDD_1 Gate Pulse Modulator Low Voltage Input.
6 VDD_2
7 OUT V Amplifier Output.
8 NEG Inverting Input of V Amplifier.
9 POS Noninverting Input of V Amplifier.

V Amplifier Supply.

COM

COM

COM

COM

10 AGND Analog Ground.
11 ADJ
12 LDO_OUT
13 VIN_1
14 SS

15 COMP

16 FREQ

17 VIN_2

LDO Output Voltage Select. Refer to Table 13 for details.

LDO Output.

Supply Input. This pin supplies power to the LDO and step-up switching regulator. Typically connected to VIN_2.

Soft Start. A capacitor must be connected between GND and this pin to set the soft start time.

Compensation for the Step-Up Converter. A capacitor and resistor are connected in series between GND and this

pin for stable operation.

Frequency Select. Set the switching frequency with a logic level. The step-up switching regulator operates at 650 kHz

when this pin is connected to GND and at 1.2 MHz when connected to VIN_1.

Step-Up Switching Regulator Power Supply. This pin supplies power to the driver for the switch. Typically

connected to VIN_1.
18 LX Step-Up Switching Regulator Switch Node.

19

SHDN

20 FB
21 PGND
22 CE
23 RE
24 VGH Gate Pulse Modulator High Voltage Input.

Device Shutdown Pin. This pin allows users to shut the device off when connected to GND. The normal operating

mode is to pull this pin to VIN_1.

Feedback Voltage Sense to Set the Output Voltage of the Step-Up Switching Regulator.

Step-Up Switching Regulator Power Ground.

GPM Time Delay. A capacitor must be connected between GND and this pin to set the delay time.

GPM Negative Ramp Rate. A resistor must be connected between GND and this pin to set the negative ramp rate.

Rev. 0 | Page 8 of 28

ADD8754

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TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

40

30

20

10

0

1 10 100 1k

FREQ = GND

FREQ = VIN

(mA)

I

LOAD

VIN = 5V
V

OUT

Figure 3. Efficiency vs. Load Current (mA) Figure 6. LDO Output Voltage vs. Load Current, VIN = 3.3 V

= 10V

05110-049

2.90

2.85

2.80

2.75

2.70

2.65

2.60

OUTPUT VOLTAGE (V)

2.55

2.50

2.45
0 50 100 150 200 250 300 350 400

3.4

ADJ = OPEN

ADJ = LDO_OUT

LOAD CURRENT (mA)

05110-050

T

1

CH1 = V
CH2 = IL 1A/DIV

CH3 = SD 5V/DIV

2

3

OUT

5V/DIV

Figure 4. Start-Up Response from Shutdown, C

T

VIN = 5V

CH1 = V

1

CH2 = IL 1A/DIV
CH3 = SD 5V/DIV

2

OUT

5V/DIV

V
I
C

OUT

= 10V

OUT

= 200mA

= 10nF

SS

VIN = 5V

= 10V

V

OUT

= 200mA

I

OUT

= 0F

C

SS

= 0 F

SS

05110-026

3.3
ADJ = GND

3.2

3.1

3.0

OUTPUT VOLTAGE (V)

2.9

2.8

0 50 100 150 200 250 300 350 400

ADJ = OPEN

LOAD CURRENT (mA)

Figure 7. LDO Output Voltage vs. Load Current, VIN = 5 V

6

5

4

3

OUTPUT

750nF

2

VOLTS (V)

OUTPUT

1

0

2.2μF
CAP

CAP

10μF OUTPUT
CAP

SD PIN

05110-051

3

Figure 5. Start-Up Response from Shutdown, C

= 10 F

SS

05110-027

Rev. 0 | Page 9 of 28

–1

–80 –40 0 40 80 120 160 200 240

TIME (μs)

Figure 8. LDO Power-Up Response from Shutdown

280

05110-052

ADD8754

V

www.BDTIC.com/ADI

6

5

4

750nF

3

OUTPUT

CAP

2

VOLTS (V)

2.2μF OUTPUT

1

0

–1

–80 –40 0 40 80 120 160 200 240

CAP

10μF OUTPUT
CAP

SD PIN

TIME (μs)

Figure 9. LDO Power-Up Response from Shutdown

6

280

05110-053

I

LOAD

3.32

3.30

(V)

V

OUT

3.28

3.26

400

(mA)

200

0

T

LOAD STEP FROM 30kΩ TO 10Ω

ADJ = GND

V

= 20mV/DIV

OUT

I

= 200mA/DIV

OUT

= 3.3 V Figure 12. LDO Load Transient Response, V

OUT

05110-056

5

4

3

2

VOLTS (V)

750nF

OUTPUT

1

CAP

0

–1

–80 –40 0 40 80 120 160 200 240

10μF OUTPUT
CAP

SD PIN

2.2μF OUTPUT
CAP

TIME (μs)

Figure 10. LDO Power-Up Response from Shutdown

2.52

2.50

V

(V)

OUT

2.48

2.46

300

200

I

(mA)

LOAD

100

0

ADJ = LDO_OUT

V

OUT

I

= 100mA/DIV

OUT

100μs

= 2.5 V Figure 11. LDO Load Transient Response, V

OUT

280

= 20mV/DIV

05110-054

05110-055

V

IN LOW

IN LOW

T

= 3.8V

T

= 3.8V

ADJ = GND

= 3.3 V Figure 13. LDO Line Transient Response, V

OUT

ADJ = LDO_OUT

= 2.5 V Figure 14. LDO Line Transient Response, V

OUT

05110-057

05110-058

V

= 5.5V

IN HIGH

(V)

V

IN

4V

3V

V

(V)

OUT

2V

1V

V

= 5.5V

IN HIGH

V

(V)

IN

V

4V

3V

2.5V
2V

(V)

OUT

1V

Rev. 0 | Page 10 of 28

ADD8754

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5.0

T

1

Ch1 2.00 V A Ch1 12.0 VM 40.0ns

Rising Slew Rate, VDD_2 = 14 V Figure 15. V

COM

T

Δ: 8.00V

@: 5.04V

Δ: 102ns

@: –83.2ns

Δ: 8.08V

@: 9.08V

Δ: 60.8ns

@: 1.88μs

05110-059

4.5

4.0

3.5

3.0

2.5

2.0

DELAY TIME (μs)

1.5

1.0

0.5

0

0 100 200 300 400 500 600 700

0kΩ

5kΩ

10kΩ

25kΩ

50kΩ

CAPACITANCE CE (pF)

Figure 17. GPM Delay Time vs. CE Capacitance

05110-061

1

Ch1 2.00 V A Ch1 5.16 VM 40.0ns

Falling Slew Rate, VDD_2 = 14 V Figure 16. V

COM

05110-060

Rev. 0 | Page 11 of 28

ADD8754

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THEORY OF OPERATION

VIN_2VIN_1SSCOMP

ADD8754

REF

g

FB

SLOPE

COMP

FREQ
SHDN

DD_2

AGND

OUT

VGH VGH_M VDD_1 CE RE VFLK VDPM

m

OSC

UVLO AND

THERMAL

PROTECTION

VIN_1

VDD_2

AGND

GATE HIGH

MOD. CIRCUIT

Figure 18. Detailed Functional Block Diagram

BIAS

F/F
R

Q

S

REF

V

COM

LX

PGND

LDO_OUT

ADJ

GND

POS

NEG

05110-048

CURRENT-MODE, STEP-UP SWITCHING REGULATOR OPERATION

The ADD8754 uses current mode to regulate the output
voltage. This current-mode regulation system allows fast
transient response while maintaining a stable output voltage. By
selecting the proper resistor-capacitor network from COMP to
GND, the regulator response can be optimized for a wide range
of input voltages, output voltages, and load conditions.

Frequency Selection

The ADD8754’s frequency is user-selectable to operate either at
650 kHz to optimize the regulator for high efficiency or at

1.2 MHz for small external components. Connect FREQ to
VIN_2 for 1.2 MHz operation, or connect FREQ to GND for
650 kHz operation.

Soft Start Capacitor

The voltage at SS ramps up slowly by charging the soft start
capacitor (C
lists the values for the soft start period based on maximum
output current and maximum switching frequency.

) with an internal 2.5 μA current source. Tabl e 8

SS

A 20 nF soft start capacitor results in negligible input-current
overshoot at startup, making it suitable for most applications.
However, if an unusually large output capacitor is used, a longer
soft start period is required to prevent large input inrush current.

Table 8. Typical Soft Start Period

V

(V) V

IN

(V) C

OUT

(μF) CSS (nF) tSS (ms)

OUT

3.3 9 10 20 2.5

3.3 9 10 100 8.2

3.3 12 10 20

3.3 12 10 100
5 9 10 20
5 9 10 100
5 12 10 20

3.5
15

0.4

1.5

0.62

5 12 10 100 2

On/Off Control

The

input turns the ADD8754 on or off. When the step-

SHDN
up dc-to-dc converter is turned off, there is a dc path from the
input to the output through the inductor and output diode. This
causes the output voltage to remain slightly below the input
voltage by the forward voltage of the diode, preventing the
output voltage from dropping to zero when the regulator is shut
down. See
dis

Figure 25 for the typical application circuit to

connect the output voltage from the input voltage at

shutdown.

Setting the Output Voltage

The ADD8754 features an adjustable output voltage range of

+ 2 V) to 20 V. The output voltage is set by the resistive

(V

IN

voltage divider from the output voltage (V

) to the 1.21 V

OUT

feedback input at FB. Use the following formula to determine
the output voltage:

= 1.21 V × (1 + R1/R2) (1) V

OUT

Use an R2 resistance of 10 kΩ or less to prevent output voltage
errors due to the 10 nA FB input bias current. Choose R1 based
on the following formula:

R1 = R2 ×

⎛

−VVV

OUT

⎜
⎜

21.1

⎝

⎞

21.1

⎟
⎟
⎠

For example, R1 = 75.8 kΩ

The soft start capacitor limits the rate of voltage rise on the
C

OMP pin, which in turn limits the peak switch current at
startup. Tabl e 8 shows a typical soft start period, t
maximum output current, I

, for several conditions.

OUT_MAX

, at the

SS

Rev. 0 | Page 12 of 28

OUT

= 10 V and R2 = 10 kΩ (2) with V

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V

×

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Inductor Selection

The inductor is an integral part of the step-up converter. It

tores energy during the switch-on time and transfers that

s
energy to the output through the output diode during the
switch-off time. Use inductance in the range of 1 μH to 22 μH.
In general, lower inductance values have higher saturation
current and lower series resistance for a given physical size.
However, lower inductance results in higher peak current,
which can lead to reduced efficiency and greater input and/or
output ripple and noise. Peak-to-peak inductor ripple current at
close to 30% of the maximum dc input current typically yields
an optimal compromise.

For determining the inductor ripple current, the input (V
output (V

) voltages determine the switch duty cycle (D) by

OUT

) and

IN

the following equation:

VV −

OUT

D =

Using the duty cycle and switching frequency, f

IN

V

(3)

OUT

, determine

SW

the on time by using the following equation:

D

t = (4)

ON

f

SW

The inductor ripple current (

t

IN

I = (5)

Δ

L

ON

L

Solving for the inductance value,

t

IN

L = (6)

ON

I

Δ

L

ΔI

) in steady state is

L

L,

Make sure that the peak inductor current (the maximum input

urrent plus half of the inductor ripple current) is less than the

c
rated saturation current of the inductor. In addition, ensure that
the maximum rated rms current of the inductor is greater than
the maximum dc input current to the regulator.

For duty cycles greater than 50% that occur with input voltages

reater than half the output voltage, slope compensation is

g
required to maintain stability of the current-mode regulator.
For stable current-mode operation, ensure that the selected
inductance is equal to or greater than L

VV

IN

LL

MIN

OUT

=>

A8.1

(7)

f

×

SW

MIN

:

Table 9. Inductor Manufacturers

Vendor Part L (μH) Max DC Current Max DCR (mΩ) Height (mm)

Sumida

www.sumida.com

Coilcraft

www.coilcraft.com

Toko

www.tokoam.com

CMD4D11-2R2MC 2.2 0.95 116 1.2
CMD4D11-4R7MC 4.7 0.75 216 1.2
CDRH4D28-100 10 1.00 128
CDRH5D18-220 22 0.80 290
CR43-4R7 4.7 1.15 109
CR43-100 10 1.04 182
DS1608-472 4.7 1.40 60
DS1608-103 10 1.00 75
D52LC-4R7M 4.7 1.14 87
D52LC-100M 10 0.76 150 2.0

3.0

2.0

3.5

3.5

2.9

2.9

2.0

Rev. 0 | Page 13 of 28

ADD8754

−

I

V

V

www.BDTIC.com/ADI

Choosing the Input and Output Capacitors Diode Selection

The ADD8754 requires input and output bypass capacitors to
supply transient currents while maintaining a constant input
and output voltage. Use a low effective series resistance (ESR)
10 μF or greater input capacitor to prevent noise at the
ADD8754 input. Place the capacitors between VIN_1, VIN_2,
and GND and as close as possible to the ADD8754. Ceramic
capacitors are preferred because of their low ESR character­istics. Alternatively, use a high value, medium ESR capacitor in
parallel with a 0.1 μF low ESR capacitor as close as possible to
the ADD8754.

The output capacitor maintains the output voltage and supplies
c

urrent to the load while the ADD8754 switch is on. The value
and characteristics of the output capacitor greatly affect the
output voltage ripple and stability of the regulator. Use a low
ESR output capacitor; ceramic dielectric capacitors are
preferred.

The output diode conducts the inductor current to the output
capacitor and load while the switch is off. For high efficiency,
minimize the forward voltage drop of the diode. Schottky
diodes are recommended. However, for high voltage, high
temperature applications, where the Schottky diode reverse
leakage current becomes significant and can degrade efficiency,
use an ultrafast junction diode.

The diode must be rated to handle the average output load
c

urrent. Many diode manufacturers derate the current
capability of the diode as a function of the duty cycle. Verify
that the output diode is rated to handle the average output load
current with the minimum duty cycle. The minimum duty cycle
of the ADD8754 is

VV

MAXIN

OUT

= (12)

D

MIN

_

V

OUT

For very low ESR capacitors such as ceramic capacitors, the
r

ipple current due to the capacitance is calculated as follows.
Because the capacitor discharges during the on time, t
charge removed from the capacitor, Q

, is the load current

C

ON

, the

multiplied by the on time. Therefore, the output voltage ripple
(

ΔV

) is

OUT

t

Q

V

OUT

C

C

OUT

×

L

ON

==Δ

(8)

C

OUT

where:

C

is the output capacitance.

OUT

I

is the average inductor current.

L

D

(9)

=

t

ON

f

SW

−

IN

OUT

=

D

V

(10)

OUT

Choose the output capacitor based on the following equation:

OUT

IN

(11)

VVf

Δ××

OUTOUT

OUT

SW

L

≥

C

)(

VVI

−×

Table 10. Capacitor Manufacturers

Vendor Web Address

AVX www.avxcorp.com
Murata www.murata.com
Sanyo www.sanyovideo.com
Taiyo Yuden www.t-yuden.com

where V

For example, D

is the maximum input voltage.

IN_MAX

= 0.45 when V = 10 V and V

MIN

OUT IN_MAX

= 5.5 V

Table 11. Schottky Diode Manufacturers

Vendor Web Address

ON Semiconductor www.onsemi.com

Diodes, Inc. www.diodes.com

Central Semiconductor Corp. www.centralsemi.com

Sanyo www.sanyovideo.com

Loop Compensation

Use of external components to compensate the regulator loop
allows optimization of the loop dynamics for a given application.
A step-up converter produces an undesirable right-half plane
zero in the regulation feedback loop. This requires compensat­ing the regulator such that the crossover frequency occurs well
below the frequency of the right-half plane zero. The right-half
plane zero is determined by the following equation:

⎛

V

IN

RHPF

Z

⎜

=2)(

⎜

V

OUT

⎝

R

LOAD

⎟

×

⎟
⎠

(13)

L

×π

2

⎞

where:

F

(RHP) is the right-half plane zero.

Z

R

is the equivalent load resistance, or the output voltage

LOAD

divided by the load current.

Rev. 0 | Page 14 of 28

ADD8754

VVV

VVV

C

×

www.BDTIC.com/ADI

To stabilize the regulator, make sure that the regulator crossover
frequency is less than or equal to one-fifth of the right-half
plane zero and less than or equal to one-fifteenth of the
switching frequency.

The regulator loop gain is

A ×××××=

VL

FB

OUT

IN

V

OUT

CSCOMPMEA

(14)

ZGZG

OUT

where:

A

is the loop gain.

VL

V

is the feedback regulation voltage, 1.210 V.

FB

V

is the regulated output voltage.

OUT

V

is the input voltage.

IN

G

is the error amplifier transconductance gain.

MEA

Z

is the impedance of the series RC network from COMP to

COMP

GND.

G

is the current sense transconductance gain (the inductor

CS

current divided by the voltage at COMP), which is internally set
by the ADD8754.

Z

is the impedance of the load and output capacitor.

OUT

For V

= 1.21 V, G

FB

=

R

C

= 100 μs, and G = 2 sec,

MEA

4

1055.2

C

V

IN

CS

×××××

VVCf

OUTOUTOUT

(17)

Once the compensation resistor is known, set the zero formed
b

y the compensation capacitor and resistor to one-fourth of the

crossover frequency, or

2

C

where C

=

C

is the compensation capacitor.

C

(18)

Rf

××π

CC

ERROR AMP

REF

FB

Figure 19. Compensation Components

G

MEA

R

C

C2

C

C

05110-007

To determine the crossover frequency, it is important to note

at at that frequency the compensation impedance (Z

th
dominated by the resistor and the output impedance (Z

COMP

OUT

) is

) is
dominated by the impedance of the output capacitor. Therefore,
when solving for the crossover frequency, (by definition of the
crossover frequency) the equation is simplified to

IN

A

FB

VL

OUT

V

OUT

GRG

×××××=

CSCMEA

1

2

Cf

××π

C

OUT

(15)

1

=

where:

f

is the crossover frequency.

C

R

is the compensation resistor.

C

The capacitor C2 is chosen to cancel the zero introduced by
output capacitance ESR.

Solving for C2,

ESR

C2

= (19)

OUT

R

C

For low ESR output capacitance, such as with a ceramic capaci­tor, C2 is optional. For optimal transient performance, the R
and C

might need to be adjusted by observing the load

C

C

transient response of the ADD8754. For most applications, the
compensation resistor should be in the range of 30 kΩ to
400 kΩ, and the compensation capacitor should be in the range

Solving for R

R

,

C

VVCf

2

=

C

C

INFB

××××π

OUTOUTOUT

(16)

GGVV

×××

CSMEA

of 100 pF to 1.2 nF. Ta bl e 12 shows external component values
f

or several applications.

Table 12. Recommended External Components for Various Input/Output Voltage Conditions

VIN (V) V

(V) fSW L (μH) C

OUT

(μF) CIN (μF) R1 (kΩ) R2 (kΩ) RC (kΩ) Cc (pF) I

OUT

OUT_MAX

(mA)

5 9 650 kHz 10 10 10 63.4 10 84.5 390 450

5 9 1.2 MHz 4.7 10 10 63.4 10 178 100 450
5 12 650 kHz 10 10 10 88.7 10 140 220

5 12 1.2 MHz 4.7 10 10 88.7 10 300 100

350

350

3.3 9 650 kHz 10 10 10 63.4 10 71.5 820 350

3.3 9 1.2 MHz 4.7 10 10 63.4 10 150 180 350

3.3 12 650 kHz 10 10 10 88.7 10 130 420

250

3.3 12 1.2 MHz 4.7 10 10 88.7 10 280 100 250

Rev. 0 | Page 15 of 28

ADD8754

V

www.BDTIC.com/ADI

V

AMPLIFIER

COM

The output of the V
voltage on the V

amplifier is designed to control the

COM

plane of the LCD display. The V

COM

COM

amplifier is designed to source and sink the capacitive pulse
current and ensure stable operation with high load capacitance.

Input Overvoltage Protection

Whenever the input exceeds the supply voltage, attention must
b

e paid to the input overvoltage characteristics. When an
overvoltage occurs, the amplifier can be damaged, depending
on the voltage level and the magnitude of the fault current.
When the input voltage exceeds the supply voltage by more
than 0.6 V, the internal pin junctions allow current to flow from
the input to the supplies. This input current is not inherently
damaging to the device, provided it is 5 mA or less.

Short-Circuit Output Conditions

The V

amplifier does not have internal short-circuit protection

COM

circuitry. As a precaution, do not short the output directly to the
positive power supply or to the ground.

GATE PULSE MODULATOR CIRCUIT

The gate pulse modulator is used for LCD applications in which
shaping of the gate high voltage signal improves image quality.
A charge pump is used to generate the on voltage, VGH. A lower
gate voltage level, VDD_1, is desired during the last portion of
the gate’s on time and is provided by VOUT. The integrated gate
pulse modulator circuit provides control over the slope and delay
of the transition between these two TFT on-voltage levels.

The gate pulse modulator circuit has four input pins (VGH,
VDD_1, VDPM, and VFLK) and one output pin (VGH_M).
VFLK is a digital control signal, usually provided by the timing
controller, whose high or low level determines which of the two
input voltages, VGH or VDD_1, is passed through to VGH_M.
The gate high modulator circuit becomes active when the voltage
on pin VDPM exceeds the turn-on threshold value of 2.2 V.

When the control voltage VFLK switches from logic low to logic
high during normal operation with VDPM at logic high (see
Figure 21), the output voltage VGH_M transitions from VDD_1

o VGH. When the control voltage VFK switches from logic

t
high to logic low, the output voltage VGH_M transitions from
VGH to VDD_1 after a time delay determined by the size of a
capacitor from the CE pin to the GND and a slew rate
determined by the size of resistor from the RE pin to the GND.

The delay capacitance in farad is calculated using the following
equation:

CE = (De

lay Time) × 0.000238

The RE in ohms is calculated using the following equation:

RE

=

()

302

×

eCapacitancLoadRateSlew

−

5000

When the voltage on the VDPM pin is less than the turn-on

hreshold value, the CE pin is internally connected to GND to

t
discharge the delay capacitor.

VIN_1

DPM

VFLK

S4

GND

DELAY

CAPACITOR

Figure 20. Gate Pulse Modulator Functional Block Diagram

ENABLE – VDPM

CONTROL SIGNAL – VFLK

OUTPUT SIGNAL – VGH_M

WITH LOAD

CAPACITANCE CL

Figure 21. Gate Pulse Modulator Timing Diagram

GATE HIGH

MOD. CIRCUIT

L
O
G

S3

I

C

GND

REF

CE RE

DELAY CONTROLLED

LOW

LOW

LOW

RAMP

RESISTOR

S1

S2

T1 T2

T1 T2

BY CE

VGH

VGH_M

CL

VDD_1

GND

SLOPE CONTROLLED BY RE

/VGH

V

OUT

VGH

VDD_1

05110-008

05110-009

Rev. 0 | Page 16 of 28

ADD8754

www.BDTIC.com/ADI

POWER-UP SEQUENCE

Most LCD panels require that when VIN is applied, LDO_OUT,

L, BO OST_OUT, VGH, and VGH_M are established

VG
sequentially, as indicated in Figure 22. ADD8754 provides this
s

equence with appropriate capacitors for the VGL and VGH

charge pumps.

VIN

SHDN

VDPM

VGH

VGL

Figure 22. Power-Up Sequence Timing Diagram

LDO Regulator

The ADD8754 low dropout (LDO) regulator has three preset

t voltage settings. As shown in Tab l e 1 3 , by tying the ADJ

outpu
p

in low, a 3.3 V nominal output is selected. By tying ADJ to the
output voltage, a 2.5 V nominal output is selected. By leaving
ADJ as an open circuit, a nominal voltage of 2.85 V is selected.

Table 13. LDO Output Voltage Selection

LDO Output Voltage ADJ Pin

2.5 V LDO_OUT

2.85 V No connection

3.3 V GND

SHDN THRESHOLD LEVEL

BOOST_OUT

LDO_OUT

VGH_M

05110-010

LDO Input Capacitor Selection

For the input voltage of the ADD8754 LDO regulator (VIN_1),
a local bypass capacitor is recommended. The input capacitor
provides bypassing for the internal amplifier used in the voltage
regulation loop. Use at least a 1 μF low ESR capacitor. Larger
input capacitance and lower ESR provide better supply noise
rejection. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size.

LDO Output Capacitor Selection

The output capacitor improves the regulator response to sudden
load changes. The output capacitor helps determine the perfor­mance of any LDO. The ADD8754 LDO requires at least a 2.2 μF
capacitor. Transient response is a function of output capacitance,
in that larger values of output capacitance decrease peak devia­tions, providing improved transient response for large load
current changes.

Choose the capacitors by comparing their lead inductance, ESR,

nd dissipation factor. Output capacitance affects stability, and a

a
larger cap provides a greater phase margin for the ADD8754
LDO. MLCC capacitors provide the best combination of low
ESR and small size.

Note that the capacitance of some capacitor types show wide
variations over temperature. A good quality dielectric X7R or
better capacitor is recommended.

SHUTDOWN

Applying a TTL high signal to the shutdown pin (tying it to the
VIN_1) turns on all outputs. Pulling

down to 0.4 V or

SHDN

below (tying it to GND) turns off all outputs. In shutdown
mode, quiescent current is reduced to a typical value of 300 μA.

UVLO

An undervoltage lockout (UVLO) circuit is included with a
built in hysteresis. ADD8754 turns on when VIN_1 rises above

2.8 V and shuts down when VIN_1 falls below 2.6 V.

Rev. 0 | Page 17 of 28

ADD8754

www.BDTIC.com/ADI

V

Amplifier

POWER DISSIPATION

The ADD8754’s maximum power dissipation depends on the
thermal resistance from the IC die to the ambient environment
and the ambient temperature. The thermal resistance depends
on the IC package, PC board copper area, other thermal mass,
and airflow. The ADD8754, with the exposed backside pad
soldered to a 2-layer PC board with nine 12 mil-diameter
thermal vias, can dissipate about 1.5 W into 65°C still air before
the die exceeds 125°C. More PC board copper, cooler ambient
air, and more airflow increase the dissipation capability, whereas
less copper or warmer air decreases the IC’s dissipation capability.
The major contributors to the power dissipation are the LDO
regulator and the V

Step-Up Converter

The largest portions of power dissipation in the step-up
converter are the internal MOSFET, the inductor, and the output
diode. For a 90% efficiency step-up converter, about 3% to 5% of
the power is lost in the internal MOSFET, about 3% to 4% in the
inductor, and about 1% in the output diode. The rest of the 1%
to 3% is distributed among the input and output capacitors and
the PC board traces. For an input power of about 3 W, the
power lost in the internal MOSFET is about 90 mW to 150 mW.

LDO

The power dissipated in the LDO depends on the output
current, the output voltage, and the supply voltage:

PD

= (VIN_1 − LDO_OUT) × I

LDO

amplifier.

COM

LDO_OUT

COM

The power dissipated in the V

amplifier depends on the

COM

output current, the output voltage, and the supply voltage:

PD

PD

SOURCE

= I

SINK

(source) × (VDD_2 − V

OUT

(sink) × V

OUT

OUT

OUT

)

= I

where:

I

(source) is the output current sourced by the V

OUT

COM

amplifier.

I

(sink) is the output current that the V

OUT

amplifier sinks to

COM

AGND.

In a typical case where the supply voltage is 12 V and the output

oltage is 6 V with an output source current of 20 mA, the

v
power dissipated is 120 mW.

Thermal Overload Protection

Thermal overload protection prevents excessive power dissipation
from overheating the ADD8754. When the junction temperature
exceeds T

= 145°C, a thermal sensor immediately activates the

J

fault protection, which shuts down the device, allowing the IC
to cool. The device self-starts once the die temperature falls
below T

= 105°C.

J

Thermal overload protection protects the controller in the event
o

f fault conditions. For continuous operation, do not exceed the

absolute maximum junction temperature rating of T

= 125°C.

J

Rev. 0 | Page 18 of 28

ADD8754

www.BDTIC.com/ADI

LAYOUT GUIDELINES

When designing a high frequency, switching, regulated power
supply, layout is very important. Using a good layout can solve
many problems associated with these types of supplies. Some of
the main problems are loss of regulation at high output current
and/or large input-to-output voltage differentials, excessive
noise on the output and switch waveforms, and instability.
Using the following guidelines can help minimize these
problems.

Make all power (high current) traces as short, direct, and thick
as possible. It is good practice on a standard PCB board to make
the traces an absolute minimum of 15 mil (0.381 mm) per
Ampere. The inductor, output capacitors, and output diode
should be as close to each other as possible. This helps reduce
the EMI radiated by the power traces that is due to the high
switching currents through them. This also reduces lead
inductance and resistance, which in turn reduce noise spikes,
ringing, and resistive losses that produce voltage errors.

The grounds of the IC, input capacitors, output capacitors, and

utput diode (if applicable), should be connected close together,

o
directly to a ground plane. It is also a good idea to have a ground
plane on both sides of the printed circuit board (PCB). This
reduces noise by reducing ground-loop errors and absorbing
more of the EMI radiated by the inductor.

For multilayer boards of more than two layers, a ground plane
ca
components) and the signal plane (feedback, compensation,
and components) for improved performance. On multilayer
boards, the use of vias is required to connect traces and different
planes. If a trace needs to conduct a significant amount of current
from one plane to the other, it is good practice to use one standard
via per 200 mA of current. Arrange the components so that the
switching current loops curl in the same direction.

Due to the how switching regulators operate, there are two

ower states: one state when the switch is on, and one when the

p
switch is off. During each state, there is a current loop made by
the power components currently conducting. Place the power
components so that the current loop is conducting in the same
direction during each of the two states. This prevents magnetic
field reversal caused by the traces between the two half cycles
and reduces radiated EMI.

n be used to separate the power plane (power traces and

Layout Procedure

To achieve high efficiency, good regulation, and stability, a good
PCB layout is required. It is recommended that the reference
board layout be followed as closely as possible because it is
already optimized for high efficiency and low noise.

Use the following general guidelines when designing PCBs:

1.

Keep CIN close to the IN and GND leads of the ADD8754.

2.

Keep the high current path from CIN (through L1) to the

SW and PGND leads as short as possible.

Keep the high current path from CIN (through L1), D1,

3.
and COUT as short as possible.

4.

Keep high current traces as short and wide as possible.

5.

Keep nodes connected to SW away from sensitive traces

such as FB or COMP to prevent coupling of the traces. If
these traces need to be run near each other, place a ground
trace between the two as a shield.

6.

Place the feedback resistors as close as possible to the FB pin

to prevent noise pickup.

7.

Place the compensation components as close as possible to

the COMP pin.

Avoid routing noise-sensitive traces near the high current

8.
traces and components.

9.

Use a thermal pad size that is the same as the dimension of

the exposed pad on the bottom of the package.

Heat Sinking

When using a surface-mount power IC or external power
switches, the PCB can often be used as the heat sink. This is
done by simply using the copper area of the PCB to transfer
heat from the device.

Rev. 0 | Page 19 of 28

ADD8754

www.BDTIC.com/ADI

TYPICAL APPLICATION CIRCUITS

R5

1kΩ

BAV99 BAV99

D3 D2D5 D4

+14V FROM

V

OUT

R7

250kΩ

TO GATE

DRIVER

VFLK

R8

100kΩ

VCOM

+4.0V

VGL

–5V

C8

0.1μF

+14V FROM

V

VZ2

BZX84C28

VZ1

BZX84C5V1

1

2

3

4

5

6

OUT

GND

VGH_M

VFLK

VGH

C7
1μF

C10

0.47μF

RE
33kΩ

RE

300Ω

C3
1μF

R6

C6

0.1μF

CE
390pF

CE

ADD8754

VDPM

VDD_1

VDD_2

OUT

78 9101112

C9

1μF

NEG

250kΩ

POS

R3

100kΩ

R4

R2

9.5kΩ

PGND

AGND

C2

0.1μF

BAV99

D6

FB

ADJ

C4

0.47μF

0.1μF

D7

R1

100kΩ

192021222324

SHDN

LX

VIN_2

FREQ

COMP

SS

VIN_1

OUT

LDO_

CLDO

4.7μF

C1

0.1μF

C5

R9
10Ω

V

OUT

R

C

180kΩ

C

C

470pF

+14V

C

SD

10μF

VIN
+5V

C

SS

10nF

R
180kΩ

V

LOGIC

+3.3V

COUT
20μF

SD

D1
1N5818

L

CIN
10μF

10μH

18

17

16

15

14

13

+14V FROM

V

OUT

Figure 23. 1.2 MHz Application Circuit for TFT LCD Panel with Charge Pumps for VGH and VGL

Rev. 0 | Page 20 of 28

05110-003

ADD8754

www.BDTIC.com/ADI

+12V FROM

V

OUT

R7

250kΩ

100kΩ

TO GATE

DRIVER

VFLK

R8

VCOM

+30V
VGH

VZ2

1N7451A

192021222324

FB

ADJ

R1

91kΩ

SHDN

OUT

LDO_

CLDO

4.7μF

1N5818

LX

VIN_2

FREQ

COMP

SS

VIN_1

D1

D3

1N914

18

17

16

15

14

13

+4.0V

C8

0.1μF

+12V FROM

V

OUT

1

2

3

4

5

6

1μF

C9

CVGH

10μF

CE

RE

390pF

33kΩ

RE

VGH

GND

VGH_M

VFLK

CE

ADD8754

VDPM

VDD_1

VDD_2

OUT

78 9101112

+12V FROM

V

OUT

NEG

R4

7.5kΩ

R12
1kΩ

POS

R3

4.7kΩ

R2

10kΩ

PGND

AGND

Figure 24. 1.2 MHz Application Circuit for TFT LCD Display with Transformer for VGH and VGL

CIN
10μF

RVGH
75Ω

T

RVGL

50Ω

VZ1

BZX84C5V1

C

SS

10nF

V

LOGIC

+3.3V

COUT
20μF

D2

1N914

CVGL

0.1μF

R

C

180kΩ

C

C

470pF

T = TRANSTEK MAGNETICS
TMS60059CS

VIN
+5V

V

OUT

+12V

VGL
–5V

05110-004

Rev. 0 | Page 21 of 28

ADD8754

www.BDTIC.com/ADI

+14V FROM

V

OUT

R7

250kΩ

100kΩ

TO GATE

DRIVER

VFLK

R8

VGL

–5V

C8

0.1μF

VZ2

BZX84C28

VZ1

BZX84C5V1

1

2

VGH_M

3

4

5

6

VGH

+28V

GND

VFLK

VDPM

VDD_1

VDD_2

VGH

C7
1μF

300Ω

C10

0.47μF

RE
33kΩ

RE

R5

1kΩ

R6

0.1μF

ADD8754

C6

CE
390pF

CE

BAV99 BAV99

C3
1μF

R2

9.5kΩ

PGND

D6

C2

0.01μF

BAV99

FB

D7

R1

100kΩ

192021222324

SHDN

C4

0.47μF

0.01μF

LX

VIN_2

FREQ

COMP

SS

VIN_1

D3 D2D5 D4

C1

0.01μF

C5

R9
10Ω

V

OUT

D1
1N5818

18

17

16

15

14

13

10μH

C
10nF

COUT
20μF

R

SD

180kΩ

L

R

C

180kΩ

SS

C

C

470pF

+14V

C

SD

10μF

FDC6331

R10
10kΩ

VIN
+5V

+14V FROM

V

VCOM

+4.0V

OUT

OUT

78 9101112

C9

1μF

NEG

R4

250kΩ

+14V FROM

V

OUT

POS

100kΩ

R3

AGND

ADJ

Figure 25. 1.2 MHz Application Circuit for TFT LCD Display with Ch

OUT

LDO_

CLDO

4.7μF

arge Pumps with Input Power Disconnect Switch

CIN
10μF

V

LOGIC

+3.3V

ENABLE

05110-005

Rev. 0 | Page 22 of 28

ADD8754

www.BDTIC.com/ADI

+14V FROM

VGH

+28V

VZ2

BZX84C28

VGL

–5V

VZ1

BZX84C5V1

1

GND

TO GATE

DRIVER

VFLK

V

OUT

R7

250kΩ

R8

100kΩ

C8

0.1μF

VCOM

+4.0V

+14V FROM

2

VGH_M

3

VFLK

4

VDPM

5

VDD_1

6

VDD_2

V

OUT

78 9101112

C9

1μF

VGH

OUT

C7
1μF

300Ω

C10

0.47μF

RE
33kΩ

RE

NEG

250kΩ

R5

1kΩ

R6

0.1μF

ADD8754

R4

BAV99 BAV99

C6

CE
390pF

CE

POS

R3

100kΩ

C3
1μF

R2

9.5kΩ

PGND

AGND

D6

2021222324

C2

0.01μF

BAV99

FB

ADJ

D7

19

100kΩ

SHDN

OUT

LDO_

CLDO

4.7μF

R1

C4

0.47μF

0.01μF

LX

VIN_2

FREQ

COMP

SS

VIN_1

D3 D2D5 D4

C1

0.01μF

C5

R9
10Ω

V

OUT

COUT

20μF

D1
1N5818

L

CIN
10μF

10μH

C

SS

10nF

R

C

180kΩ

C

C

470pF

V

LOGIC

+3.3V

Q1
2N7000

R10
10kΩ

18

17

16

15

14

13

+14V

VIN
+5V

BOOST AND
CHARGE PUMP
ENABLE

+14V FROM

V

OUT

05110-047

Figure 26. 1.2 MHz Application Circuit for TFT LCD Display with LDO_ALWAYS_ ON

Rev. 0 | Page 23 of 28

ADD8754

A

H

www.BDTIC.com/ADI

ADD8754

OUT

ADJ

AGND

VDD

VLOGIC

SCL

SDA

GND AD0 AD1

LDO_

R10

C9

2.2kΩ

0.1μF

controller or I

R11

2.2kΩ

SIGNAL FROM FACTORY PC,
SOFTWARE PROVIDED BY ADI

COM

2

C programmer can be used to provide the

05110-006

control signal for the AD5259, but ADI provides programming
software that simplifies the calibration process. The software
can be installed in the factory computer, and two tester probes
can be connected to the computer’s parallel port to implement the
V

programming.

COM

The V

voltage can be calculated as

COM

D

256

= 7

V ××

COM

+×

RR

3

AB

++

RRR

34

AB

V

OUT

where:

D

is the decimal code of the AD5259 programmable resistance

between the W-to-B terminals.

is the AD5259 nominal resistance.

R

AB

VCOM

4.0V

DJUSTABLE FROM 3V TO 5V WIT

15mV PER STEP ADJUSTMENT

OUT

C10

2.2pF

6kΩ

R

B

NEG

R
1kΩ

POS

V

OUT

14V

R4
315kΩ

R3

10kΩ

AD5259BRMZ10
A
W

B

A

Figure 27. ADD8754 with Programmable V

The V

calibration for flicker reduction is one of the essential

COM

steps in the panel manufacturing process. In a typical panel
production environment, such a process can take additional
time to complete and, therefore, impacts production throughput.
One additional concern is that a potentiometer typically used
only for calibration offers limited resolution. The resistance can
drift over time and can be noticeable after a few years of operation.
The production throughput, image quality, and panel reliability
concerns can all be solved by using a digital potentiometer. As
shown in
tio
V

COM

Figure 27, AD5259, a low cost 256-step digital poten-

meter with nonvolatile memory, can calibrate the ADD8754

voltage precisely, reliably, and time efficiently.

In the worst case, where the temperature, aging effect, and
r

esistance tolerance of the AD5259 are all accounted for, the

circuit in Figure 27 makes the V

voltage adjustable from

COM

3.0 V to 5.0 V with 15 mV per step adjustment. A micro-

Rev. 0 | Page 24 of 28

ADD8754

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

4.00

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

BSC SQ

TOP

VIEW

0.80 MAX

0.65TYP

COMPLIANT TOJEDEC STANDARDS MO-220-VGGD-2

0.30

0.23

0.18

3.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

Figure 28. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm Body, Very Thin Quad

4 ×

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option Quantity

ADD8754ACPZ-Reel −40°C to +85°C 24-Lead LFCSP_VQ CP-24-1 5,000
ADD8754ACPZ-Reel7 −40°C to +85°C 24-Lead LFCSP_VQ CP-24-1 1,500

1

Z = Pb-free part.

1

1

0.60 MAX

19

18

EXPOSED

(BOTTOM VIEW)

13

12

PAD

24

6

7

1

2.50 REF

PIN 1
INDICATOR

2.25

2.10 SQ

1.95

0.25 MIN

Rev. 0 | Page 25 of 28

ADD8754

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 26 of 28

ADD8754

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 27 of 28

ADD8754

www.BDTIC.com/ADI

NOTES

©2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05110–0–4/05(0)

Rev. 0 | Page 28 of 28