650 kHz or 1.2 MHz switching frequency
Output adjustable to 20 V
350 mA logic voltage regulator
Selectable output voltages: 2.5 V, 2.85 V, 3.3 V
amplifier with 300 mA drive
V
COM
Gate pulse modulation circuitry
Independently adjustable delay and falling slope
General
3 V to 5.5 V input
Undervoltage lockout
Thermal shutdown
24-lead, Pb-free LFCSP package
APPLICATIONS
TFT LCD panels for monitors, TVs, and notebooks
LCD Panel Power, V
and
G
FUNCTIONAL BLOCK DIAGRAM
ADD8754
FB
FREQ
SHDN
VDD_2
OUT
STEP-UP SWITCHING
REGULATOR
UNDER VOLTAGE LOCKOUT
AND THERMAL PROTECTION
LOGIC VOLTAGE
REGULATOR
VCOM AMPLIFIER
GATE PULSE
MODULATION
COM
ate Modulation
ADD8754
VIN_2VIN_1SSCOMP
LX
LDO_OUT
ADJ
POS
NEG
,
GENERAL DESCRIPTION
The ADD8754 is optimized for use in TFT LCD applications,
requiring only external charge pump components to provide all
the requirements for panel power, V
Included in a single chip are a high frequency step-up dc-to-dc
switching regulator, logic voltage regulator, V
gate pulse modulation circuitry.
The step-up dc-to-dc converter provides up to 20 V output and
cludes a 2 A internal switch. Either a 650 kHz or 1.2 MHz step-
in
up switching regulator frequency can be chosen, allowing easy
filtering and low noise operation. It achieves 93% efficiency and
features soft start to limit the inrush current at startup.
The internal voltage regulator operates with an input voltage
nge of 3 V to 5.5 V and delivers a load current of up to
ra
, and gate modulation.
COM
amplifier, and
COM
VGH VGH_M VDD_1 CE RE VFLKVDPM
Figure 1.
05110-001
350 mA. Three selectable output voltages are available: 2.5 V,
2.85 V, and 3.3 V.
The proprietary V
amplifier can deliver a peak output
COM
current of 300 mA and is specifically designed to drive TFT
panel loads.
The gate pulse modulator allows shaping of the TFT gate high
oltage to improve image quality. The integrated switches
v
provide the ability to independently control the delay and slope
for the gate drive voltage.
The ADD8754 is offered in a 24-lead, Pb-free LFCSP package and
is
specified over the industrial temperature range of −40 to +85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Output Voltage Range V
Load Regulation 10 mA ≤ I
Line Regulation I
Load Regulation 10 mA ≤ I
Line Regulation I
Overall Regulation Line, load, temperature (−40°C ≤ TA ≤ +85°C) −3 +3 %
REFERENCE
Feedback Voltage VFB 1.200 1.211 1.220 V
ERROR AMPLIFIER
Transconductance G
Gain A
Input Bias Current I
SWITCH
On Resistance R
Leakage Current I
Peak Current Limit I
OSCILLATOR
Oscillator Frequency F
FREQ = VIN_1 1.2 MHz
Maximum Duty Cycle D
VDPM = VFLK = LDO_OUT 60 Ω
VFLK < 0.8 V, RE = 33 kΩ 8.0 mA
GENERAL SPECIFICATIONS
VIN_1 = VIN_2 =
Table 5.
Parameter Symbol Conditions Min Typ Max Unit
SHUTDOWN
Input Voltage Low V
Input Voltage High V
Shutdown Pin Input Current
Total Ground Current
Total VIN Current (I
UNDERVOLTAGE LOCKOUT
UVLO Rising Threshold V
UVLO Falling Threshold V
QUIESCENT CURRENT
Step-Up Regulator in Nonswitching State I
Step-Up Regulator in Switching State I
= 5 V, TA = 25°C, unless otherwise noted.
SHDN
IL
IH
+ I
VIN_1
)
VIN_2
UVLOR
UVLOF
Q
QSW
0.8
2.2
GND ≤ SHDN
SHDN
SHDN
= GND
= GND
≤ 5.5 V
−1 +1
2.0
−1 +1
V
V
μA
μA
μA
VIN_1 rising 2.8 V
VIN_1 falling 2.6 V
300 500 μA
2 3 mA
Rev. 0 | Page 6 of 28
ADD8754
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
T = 25°C, unless otherwise noted.
A
Table 6.
Parameter Symbol Rating
RE, CE, FB, SHDN
COMP, SS, VIN_
ADJ, VDPM, VFLK to GND,
PGND, and AGND
OUT, NEG and POS to GND,
PGND, and AG
LX to GND, PGND, and AGND −0.5 V to +22 V
VDD_2 and OUT to GND, PGND,
and AGND
Voltage Between GND and
AGND, GND
AGND and PGND
VDD_1, VGH, and VGH_M to
GND, PGND,
Differential Voltage Between
POS and NEG
Package Power Dissipation P
Thermal Resistance θ
Maximum Junction Temperature T
Operating Temperature Range T
Storage Temperature Range T
Reflow Peak Temperature
(20 sec to 40 sec)
, VIN_2, FREQ,
1, LDO_OUT,
ND
and PGND, and
and AGND
−0.5 V to +16 V
±0.5 V
D
JA
max 125°C
J
A
S
250°C
−0.5 V to +6.5 V
−0.5 V to +18.5
V
−0.5 V to +32 V
±5 V
(TJ max − TA)/θ
38°C/W
−40°C to +85°C
−65°C to +150°C
JA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
ADD8754
www.BDTIC.com/ADI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
VGH_M
VFLK
VDPM
VDD_1
VDD_2
VGHRECE
24
23 22 21 20 19
1
2
3
4
5
6
789101112
OUT
PGND
ADD8754
TOP VIEW
(Not to Scale)
POS
NEG
AGND
FB
ADJ
LDO_OUTSHDN
18
LX
17
VIN_2
16
FREQ
15
COMP
14
SS
13
VIN_1
05110-002
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin Mnemonic Description
1 GND Ground.
2 VGH_M Gate Pulse Modulator Output. This pin supplies the gate drive signal.
3 VFLK
4 VDPM
Gate Pulse Modulator Control Input.
Gate Pulse Modulator Enable. VGH_M is enabled when the voltage on this pin is more than 2.2 V. VGH_M goes to
GND when this pin is connected to GND.
5 VDD_1 Gate Pulse Modulator Low Voltage Input.
6 VDD_2
7 OUT V Amplifier Output.
8 NEG Inverting Input of V Amplifier.
9 POS Noninverting Input of V Amplifier.
V Amplifier Supply.
COM
COM
COM
COM
10 AGND Analog Ground.
11 ADJ
12 LDO_OUT
13 VIN_1
14 SS
15 COMP
16 FREQ
17 VIN_2
LDO Output Voltage Select. Refer to Table 13 for details.
LDO Output.
Supply Input. This pin supplies power to the LDO and step-up switching regulator. Typically connected to VIN_2.
Soft Start. A capacitor must be connected between GND and this pin to set the soft start time.
Compensation for the Step-Up Converter. A capacitor and resistor are connected in series between GND and this
pin for stable operation.
Frequency Select. Set the switching frequency with a logic level. The step-up switching regulator operates at 650 kHz
when this pin is connected to GND and at 1.2 MHz when connected to VIN_1.
Step-Up Switching Regulator Power Supply. This pin supplies power to the driver for the switch. Typically
connected to VIN_1.
18 LX Step-Up Switching Regulator Switch Node.
19
SHDN
20 FB
21 PGND
22 CE
23 RE
24 VGH Gate Pulse Modulator High Voltage Input.
Device Shutdown Pin. This pin allows users to shut the device off when connected to GND. The normal operating
mode is to pull this pin to VIN_1.
Feedback Voltage Sense to Set the Output Voltage of the Step-Up Switching Regulator.
Step-Up Switching Regulator Power Ground.
GPM Time Delay. A capacitor must be connected between GND and this pin to set the delay time.
GPM Negative Ramp Rate. A resistor must be connected between GND and this pin to set the negative ramp rate.
Rev. 0 | Page 8 of 28
ADD8754
www.BDTIC.com/ADI
TYPICAL PERFORMANCE CHARACTERISTICS
100
90
80
70
60
50
40
30
20
10
0
1101001k
FREQ = GND
FREQ = VIN
(mA)
I
LOAD
VIN = 5V
V
OUT
Figure 3. Efficiency vs. Load Current (mA) Figure 6. LDO Output Voltage vs. Load Current, VIN = 3.3 V
= 10V
05110-049
2.90
2.85
2.80
2.75
2.70
2.65
2.60
OUTPUT VOLTAGE (V)
2.55
2.50
2.45
050100150200250300350400
3.4
ADJ = OPEN
ADJ = LDO_OUT
LOAD CURRENT (mA)
05110-050
T
1
CH1 = V
CH2 = IL 1A/DIV
CH3 = SD 5V/DIV
2
3
OUT
5V/DIV
Figure 4. Start-Up Response from Shutdown, C
T
VIN = 5V
CH1 = V
1
CH2 = IL 1A/DIV
CH3 = SD 5V/DIV
2
OUT
5V/DIV
V
I
C
OUT
= 10V
OUT
= 200mA
= 10nF
SS
VIN = 5V
= 10V
V
OUT
= 200mA
I
OUT
= 0F
C
SS
= 0 F
SS
05110-026
3.3
ADJ = GND
3.2
3.1
3.0
OUTPUT VOLTAGE (V)
2.9
2.8
050100150200250300350400
ADJ = OPEN
LOAD CURRENT (mA)
Figure 7. LDO Output Voltage vs. Load Current, VIN = 5 V
6
5
4
3
OUTPUT
750nF
2
VOLTS (V)
OUTPUT
1
0
2.2μF
CAP
CAP
10μF OUTPUT
CAP
SD PIN
05110-051
3
Figure 5. Start-Up Response from Shutdown, C
= 10 F
SS
05110-027
Rev. 0 | Page 9 of 28
–1
–80 –4004080120 160 200 240
TIME (μs)
Figure 8. LDO Power-Up Response from Shutdown
280
05110-052
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