Analog Devices ADD8502 Datasheet

Integrated LCD

FEATURES Two Mask Programmable Sets of Five Reference Levels Dual 10-Bit DACs for Flicker Offset and Range Adjustment Integrated V Single-Supply Operation: 5.0 V Low Supply Current: 300 A Global Power Save Mode: 1 A Max Fast Settling Time for Load Change: 20 s Stable with 20 nF/100  Loads CMOS/TTL Input Levels

APPLICATIONS Color TFT Cell Phones Color TFT PDAs

GENERAL DESCRIPTION

The ADD8502 is an integrated, high accuracy, programmable grayscale generator. Two sets of five output reference voltages are mask programmed to 0.2% resolution. The outputs switch between the two sets of five levels. The reference levels are selected from a 512 tap resistor network using a via mask.

ADD8502 includes two serially addressable, 10-bit digital-toanalog converters (DACs) and five fast, low current buffers. The dual DACs set the endpoint voltages applied to the resistor network to adjust for flicker and range. The two power save modes can reduce the total current to less than 1 µA and feature fast recovery time from Shutdown/Sleep Mode. The ADD8502 accepts CMOS or TTL inputs for all controls, including the common drive circuit levels.

ADD8502 operates over the industrial temperature range from –40°C to +85°C and is available in a space-saving 24-lead 4 mm  4 mm frame chip scale package.

Switching

COM

SCK

CS-LD

PSK

GS1

GS2

Grayscale Generator

ADD8502

FUNCTIONAL BLOCK DIAGRAM

REV2

VREF+

VREF–

VREF+

VREF–

10-BIT DAC A

DIGITAL

CORE

POWER

SAVE

LOGIC

INTERFACE LOGIC

10-BIT DAC B

VN4

VN0

VDD/2

VP0

VN0

VP0

MUX

VP4

VN4

VP4

COM

LOGIC

GND

COM

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

CMREV1COM_M

CV4

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

ADD8502–SPECIFICATIONS

(@ VDD = 5.0 V, 40C ≤ TA ≤ 85C, unless otherwise noted.)

Parameter Symbol Conditions Min Typ Max Unit

SYSTEM ACCURACY

Error 320 mV

OUT

Swing Error Mean Error Mean Error between Adjacent Channels Mean Error between V0 and V4

(VPn – VNn) – (VPi – VNi)117mV (VPn+ VNn)/2 – (VPi + VNi)/2) 3 21 mV

321 mV 325 mV

DAC ACCURACY

Resolution 10 Bits Differential Nonlinearity DNL ±0.25 LSB Integral Nonlinearity

INL ±0.5 LSB Offset Error ±0.4 % of FSR Gain Error ±0.15 % of FSR

OUTPUT CHARACTERISTICS

Output Current I Short Circuit Current I Output Leakage Current in High-Z Mode I

OUT

LEAKAGE

Slew Rate SR R Settling Time to 1% t Slew Rate Settling Time to 1%

SR LD =100 Ω Series 16 nF 0.7 V/µs

(VDD – 1 V) 25 mA Short to Ground 60 mA High-Z Mode 0.01 1.0 µA

= 100 kΩ 1.25 V/µs

V0 to V4 Step Size 8 12 µs

Phase Margin φo67Degrees

SWITCHES ACTIVE IMPEDANCE

COM

COM to V

Z See Table IV 25 50 Ω COM to GND Z 25 50 Ω COM to COM_M Z I = 20 mA 25 50 Ω COM to V4 Z 25 50 Ω

MASK PROGRAMMABLE

RESISTOR CHAIN

Resistor Matching R

MATCH

Any Two Segments between 1 % 512 Resistor String

POWER SUPPLY

Supply Voltage V Supply Current I Shutdown Supply Current I Sleep Supply Current I

SY-GLB

SY-GS1-3

VDD = 5 V; No Load 190 270 400 µA Full Shutdown Mode 0.2 1 µA Mid 3 Buffers Shutdown 140 175 210 µA

4.5 5 5.5 V

Shutdown Recovery Time Global PD to 1% 23 30 µs Sleep Recovery Time V1–V3 Off to 1% 10 15 µs

LOGIC SUPPLY

Logic Input Voltage Level V Logic Input Current I

2.3 3.3 5.5 V

0.01 1 µA

DIGITAL I/O

Digital Input High Voltage V Digital Input Low Voltage V Digital Input Current I Digital Input Capacitance C

NOTES

Swing error is a comparison of measured V

Mean error is measured V

Mean errors between two adjacent channels versus theoretical (see Figure 3).

Mean errors between V0 and V4 versus theoretical (see Figure 3).

Slew rate and settling time are measured between the output resistor and the capacitor (see Figure 1) .

Specifications subject to change without notice.

mean versus theoretical V

OUT

step versus theoretical V

OUT

mean (see Figure 3).

OUT

GND ≤ VIN ≤ 5.5 V ±1 µA

step. Theoretical values can be found on the Mask Tap Point Option sheet.

OUT

100

16nF

COM

VL  0.7 V

VL  0.3 V

10 pF

Figure 1. Slew Rate Diagram

–2–

REV. 0

Table I. Serial Data Timing Characteristics

Parameter Symbol Min Typ Max Unit

SCK Cycle Time t SCK High Time t SCK Low Time t CS-LD Setup Time t Data Setup Time t Data Hold Time t LSB SCK High to CS-LD High t Minimum CS-LD High Time t SCK to CS-LD Active Edge Setup Time t CS-LD High to SCK Positive Edge t

100 ns 45 ns 45 ns 20 ns 5ns 5ns 5ns 10 ns 5ns 10 ns

SCK Frequency (Square Wave) 10 MHz

NOTES

All input signals are specified with rise/fall time –5 ns (10% to 90% of VDD) and timed from a voltage level of (VS + VIH)/2.

See Figure 2.

ADD8502

SCK

CS-LD

C3 C2 X1 X0D

Figure 2. Serial Write Interface

SEE NOTE 2 ON SPECIFICATIONS TABLE

V0 – V1

SEE NOTE 3 ON SPECIFICATIONS TABLE

SEE NOTE 4 ON

SPECIFICATIONS TABLE

VP0

VN0

VP1

VN1

VN2

VP2

REV. 0

VN3

SEE NOTE 1 ON SPECIFICATIONS TABLE

VP3

VN4

VP4

Figure 3. Output Wave Form Diagram

–3–

ADD8502

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V

OUT

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD +0.3 V

COM

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature Range (Soldering, 10 sec)

Package Type 

24-Lead LFCSP (ACP) 34.8 13 °C/W

NOTES

θJA is specified for worst-case conditions, i.e., θ

in circuit board for surface-mount packages.

ψJB is applied for calculating the junction temperature by reference to the board

temperature.

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 300°C

*Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Model Range Description Option

ORDERING GUIDE

Temperature Package Package

ADD8502ACP –40°C to +85°C24-Lead LFCSP CP-24

Available in 7” reel only.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADD8502 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.



is specified for device soldered

Unit

–4–

REV. 0

ADD8502

PIN CONFIGURATION

REV2

COM

COM_M

GND

DD.

input into the

when REV1 is HIGH and will output

PSK

GS1

GS2

23 22 21 20 19

PIN 1

IDENTIFIER

SCK

CS-LD

CV4

ADD8502

TOP VIEW

(Not to Scale)

789101112

REV1

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Name I/O Description

Logic Select Pin I Logic Supply Voltage. Connect to supply used for system logic. Can accept 2.7 V to V

2DINSerial Data Input I When CS is LOW, the input on this pin is shifted into the internal shift register on

the rising edge of SCK.

3 SCK Serial Clock I Accepts up to 10 MHz input. The rising edge on this clock will shift the data on

Pin into the internal shift registers.

4 CS-LD Load I When CS-LD is LOW, SCK is enabled for shifting data on the D

internal shift register on the rising edge of SCK. Data is loaded MSB first.

5CMLogic Control 2 I When CM is LOW, COM will output the voltage level input on COM_M.

for V

COM

When CM is HIGH, COM levels will be determined by the input on REV1.

6 CV4 Logic Control V4 I If CV4 is HIGH, V4 output is the output of the op amp A4. If CV4 is LOW, V4 is

connected to COM and op amp A4 is shut down. Refer to Table II.

7 REV1 Logic Control 1 I With CM HIGH, a HIGH on REV1 will cause COM to output the voltage level

for V

COM

input at VDD. A LOW on REV1 will cause COM to output the voltage level input

at GND. 8NCNo Connect Unused Pin 9NCNo Connect Unused Pin 10 COM Common Output O If CM is LOW, COM will output the voltage input at COM_M. If CM is HIGH,

COM will output the voltage input at V

the voltage input at GND when REV1 is LOW. Refer to Table II. 11 COM_M Common System I COM_M is a system voltage reference input between 2.5 V and 3.5 V. This may

REF

be the system 3.3 V supply. 12 NC No Connect Unused Pin 13 GND Ground I Ground. Nominally 0 V. 14 V4 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).

When PSK is LOW, these outputs will be Hi-Z. 15 V3 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).

When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 16 V2 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).

When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 17 V1 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).

When PSK is LOW or GS1 and GS2 = HIGH, these outputs will be Hi-Z. 18 V0 Output O Buffers are rail-to-rail buffers that can drive high capacitive loads (>16.5 nF).

When PSK is LOW, these outputs will be Hi-Z. 19 V

Supply I Supply Voltage. Nominally 5 V.

20 NC No Connect Unused Pin

REV. 0

–5–

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