Datasheet ADD5203 Datasheet (ANALOG DEVICES)

8-String, White LED Driver with SMBus and

FEATURES

White LED driver based on inductive boost converter

Integrated 50 V MOSFET with 2.9 A peak current limit
Input voltage range: 6 V to 21 V
Maximum output adjustable up to 45 V
350 kHz to 1 MHz adjustable operating frequency
Overvoltage protection (OVP) up to typical 47.5 V
Built-in soft start for boost converter

Drives up to eight LED current strings

LED current adjustable up to 30 mA for each channel
Headroom control to maximize efficiency
Adjustable dimming frequency: 200 Hz to 10 kHz
LED open and short fault protection

Selectable dimming control interface methods

PWM input
SMBus serial input

Selectable dimming modes

Fixed delay PWM dimming control with 8-bit resolution
No delay PWM dimming control with 8-bit resolution
Direct PWM dimming control
DC current dimming control with 8-bit resolution

General

Thermal shutdown
Undervoltage lockout
28-lead, 4 mm × 4 mm × 0.75 mm LFCSP_WQ

PWM Input for LCD Backlight Applications

ADD5203

FUNCTIONAL BLOCK DIAGRAM

STEP-UP SWITCHING REGULATOR

EIGHT CURRENT S OURCES

PWM DUTY EXTRACTOR

8-BIT BRIGHTNESS CONTROL LOGIC

FIXED DELAY/NO DELAY DIRECT PWM /

DC CURRENT DIMMING CONTROL

WITH PWM AND/OR SMBus INTERFACE

UNDERVOLTAGE LOCKOUT

INTERNAL SOF T START

THERMAL PROTECTI ON

OVERVOLTAGE PROTECTION

AUTODISABLE F OR LED OP EN/SHORT

08717-001

Figure 1.

APPLICATIONS

Notebook PCs, UMPCs, and monitor displays

GENERAL DESCRIPTION

The ADD5203 is a white LED driver for backlight applications
based on high efficiency, current-mode, step-up converter tech­nology. It is designed with a 0.15 , 2.9 A internal switch and a
pin-adjustable operating frequency between 350 kHz and 1 MHz.

The ADD5203 contains eight regulated current sources for
uniform brightness intensity. Each current source can be driven
up to 30 mA, and the LED driving current is pin adjustable by
an external resistor. The ADD5203 drives up to eight parallel
strings of multiple series connected LEDs with a ±1.5% current
matching between strings.

The ADD5203 provides various dimming modes. Each
dimming mode is selectable with an external dimming mode
selection pin. The LED dimming control interface can be
achieved through PWM input and/or SMBus. The device

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

provides adjustable output dimming frequency range from
200 Hz to 10 kHz by an external resistor and capacitor. The
ADD5203 operates over an input voltage range of 6 V to 21 V,
but the device can function with a voltage as low as 5.6 V.

The ADD5203 also has multiple safety protection features to
prevent damage during fault conditions. If any LED is open or
short, the device automatically disables the faulty current source.
The internal soft start prevents inrush current during startup.
Thermal shutdown protection prevents thermal damage.

The ADD5203 is available in a low profile, thermally enhanced,
4 mm × 4 mm × 0.75 mm, 28-lead, RoHS-compliant lead frame
chip scale package (LFCSP_WQ) and is specified over the
industrial temperature range of −25°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2010 Analog Devices, Inc. All rights reserved.

ADD5203

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Circuit Diagram ................................................................................ 3

Specifications ..................................................................................... 4

Step-Up Switching Regulator Specifications ............................. 4

LED Current Regulation Specifications .................................... 4

SMBus Specifications ................................................................... 5

General Specifications ................................................................. 6

Absolute Maximum Ratings ............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 11

Current-Mode, Step-Up Switching Regulator Operation ..... 11

Internal 3.3 V Regulator ............................................................ 11

Boost Converter Switching Frequency .................................... 11

Dimming Frequency (f

Current Source ............................................................................ 11

Dimming Control Interface ...................................................... 11

PWM Dimming Mode .............................................................. 12

Safety Features ............................................................................ 12

SMBus Interface.......................................................................... 13

SMBus Register Description ..................................................... 15

External Component Selection Guide ..................................... 17

Layout Guidelines....................................................................... 18

Typical Application Circuits ......................................................... 20

Outline Dimensions ....................................................................... 23

Ordering Guide .......................................................................... 23

) ...................................................... 11

PWM

REVISION HISTORY

5/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

ADD5203

CIRCUIT DIAGRAM

VIN VDDIO SHDN NC OVP

26 4 25 16 22

COMP

I

SET

FB1

28

17

7

UVP
REF

REF

CURRENT

REFERENCE

LINEAR

REGULATOR

VOLTAGE

REFERENCE

UVP

COMP

ERROR

AMP

GM

HEADROOM CONTROL

CURRENT SOURCE 1

REF

LL

ADD5203

LIGHT LOAD

PWM

COMP

SHUTDOWN

DCOMP

TSD FAULT

LED OPEN/S HORT
FAU LT D ET EC TO R

DREF

THERMAL

SHUTDOWN

OCP FAULT

OSC

+

∑

+

R

S

CURRENT SENSE

SOFT START

TSD FAULT

OCP FAULT

OCP
REF

23

SW

OVP
REF

Q

R

SENSE

24

27

20

21

SW

FSLCT

PGND

PGND

8

FB2

FB3

FB4

FB5

FB6

FB7

9

10

12

13

14

15

CURRENT SOURCE 2

CURRENT SOURCE 3

CURRENT SOURCE 4

CURRENT SOURCE 5

CURRENT SOURCE 6

CURRENT SOURCE 7

CURRENT SOURCE 8FB8

11

AGND

REGISTER

REGISTER

ID REGISTER

FAU LT/STAT US

CURRENT SOURCE CONT ROLLER

REGISTER

DEVICE CONTRO L

BRIGHTNESS CONTROL

SMBus INTERFACE
DUTY GENERATOR

PWMI DUTY

EXTRACTOR

OPERATION

MODE

SELECTION

PWM

OSCILLATOR

5

6

1

2

3

19

18

SDA

SCL

PWMI

SEL1

SEL2

C_FPWM

R_FPWM

08717-002

Figure 2. Circuit Diagram

Rev. 0 | Page 3 of 24

ADD5203

SPECIFICATIONS

STEP-UP SWITCHING REGULATOR SPECIFICATIONS

VIN = 12 V,

Table 1.

Parameter Symbol Test Conditions Min Typ Max Unit

SUPPLY

Input Voltage Range VIN 6 21 V

BOOST OUTPUT

Output Voltage V

SWITCH

On Resistance R
Leakage Current I
Peak Current Limit ICL Duty cycle (D) = D

OSCILLATOR

Switching Frequency fSW R
f
Maximum Duty Cycle D

SOFT START

Soft Start Time tSS 1.5 ms

OVERVOLTAGE PROTECTION

Overvoltage Rising Threshold on OVP Pin V
Overvoltage Falling Threshold on OVP Pin V

SHDN

= high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.

45 V

OUT

DS(ON)

44 70 μA

LKG

R

SW

R

MAX

1.154 1.20 1.267 V

OVPR

1.050 1.12 1.188 V

OVPF

VIN = 12 V, ISW = 100 mA 150 210 mΩ

2.9 A

MAX

= 150 kΩ 800 1000 1200 kHz

F

= 470 kΩ 350 kHz

F

= 470 kΩ 85 92 %

F

LED CURRENT REGULATION SPECIFICATIONS

VIN = 12 V,

Table 2.

Parameter Symbol Test Conditions Min Typ Max Unit

CURRENT SOURCE

I

SET

Adjustable LED Current1 I
Constant Current Sink of 20 mA2 I
Minimum Headroom Voltage2 V
Current Matching Between Strings2 R
LED Current Accuracy2 R
Current Source Leakage Current 1 μA

FPWM GENERATOR

Dimming Frequency Range
Dimming Frequency f

LED FAULT DETECTION

Open Fault Delay1 T

1

These electrical specifications are guaranteed by design.

2

Tested at TA = +25°C.

SHDN

= high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.

Pin Voltage V

6 V ≤ VIN ≤ 21 V 1.16 1.2 1.24 V

SET

0 30 mA

LED

R

LED20

R

HR20

R

PWM

= 141.56 kΩ 19.4 20 20.6 mA

SET

= 141.56 kΩ 0.65 0.85 V

SET

= 141.56 kΩ −1.5 +1.5 %

SET

= 141.56 kΩ −3 +3 %

SET

6 V ≤ VIN ≤ 21 V 200 10,000 Hz

FPWM

= 50 kΩ, C

= 150 pF 820 1000 1180 Hz

FPWM

D_OPENFAULT

6.5 μs

Rev. 0 | Page 4 of 24

ADD5203

SMBUS SPECIFICATIONS

VIN = 12 V,

Table 3.

Parameter1 Symbol Test Conditions Min Typ Max Unit

SMBus INTERFACE

Data, Clock Input Low Level VIL 0.8 V
Data, Clock Input High Level VIH 2.1 5.5 V
Data, Clock Output Low Level VOL 0.4 V

SMBus TIMING SPECIFICATIONS

Clock Frequency
Bus-Free Time Between Stop and Start Condition
Hold Time After Start Condition2

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time

Data Setup Time

Clock Low Period

Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

1

These electrical specifications are guaranteed by design.

2

After this period, the first clock is generated.

SHDN

= high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.

f

SMB

t

BUF

t

HD:STA

t

SU:STA

t

SU:STO

t

HD:DAT

t

SU:DAT

t

LOW

t

HIGH

tF

t

R

4.7 μs

1 us

10 100 kHz

4.0 μs

4.7 μs

4.0 μs

300 ns

250 ns

4.7 μs

4.0 50 μs

300 ns

Rev. 0 | Page 5 of 24

ADD5203

GENERAL SPECIFICATIONS

VIN = 12 V,

Table 4.

Parameter Symbol Test Conditions Min Typ Max Unit

SUPPLY

Input Voltage Range VIN 6 21 V
Quiescent Current IQ

Shutdown Supply Current ISD

VDD REGULATOR

VDD Regulated Output V

PWM INPUT

PWM Voltage High V
PWM Voltage Low V
PWM Input Range 200 10,000 Hz

THERMAL SHUTDOWN

Thermal Shutdown Threshold1 T
Thermal Shutdown Hysteresis1 T

UVLO

VIN Falling Threshold V
VIN Rising Threshold V

SHDN CONTROL

Input Voltage High VIH 2.0 V
Input Voltage Low VIL 1.0 V
SHDN Pin Input Current

1

These electrical specifications are guaranteed by design.

SHDN

= high, TA = −25°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.

6 V ≤ V
6 V ≤ V

6 V ≤ VIN ≤ 21 V 3.18 3.3 3.42 V

VDD_REG

≤ 21 V, SHDN = high

IN

≤ 21 V, SHDN = low

IN

2.2 5.5 V

PWM_HIGH

0.8 V

PWM_LOW

SD

30 °C

SDHYS

V

UVLOF

V

UVLOR

falling 4.2 4.6 V

IN

rising 5.0 5.6 V

IN

I

SHDN

SHDN

= 3.3 V

4.2 6.5 mA
40 160 μA

160 °C

6 μA

Rev. 0 | Page 6 of 24

ADD5203

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 5.

Parameter Rating

VIN −0.3 V to +23 V
SW −0.3 V to +50 V
SHDN, SDA, SCL, PWMI, SEL1, and SEL2
I

, FSLCT, COMP, R_FPWM, and C_FPWM −0.3 V to +3.6 V

SET

VDDIO −0.3 V to +3.7 V
FB1, FB2, FB3, FB4, FB5, FB6, FB7, and FB8 −0.3 V to +50 V
OVP −0.3 V to +3 V
Maximum Junction Temperature (TJ max) 150°C
Operating Temperature Range (TA) −25°C to +85°C
Storage Temperature Range (TS) −65°C to +150°C
Reflow Peak Temperature (20 sec to 40 sec) 260°C

−0.3 V to +6 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 6. Thermal Resistance

Package Type θJA θ

28-Lead LFCSP_WQ 32.6 1.4 °C/W

Unit

JC

ESD CAUTION

Rev. 0 | Page 7 of 24

ADD5203

V

T

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

COMP

VIN

FSLC

28

26

27

1PWMI

2SEL1

3SEL2

DDIO

4

5SDA

6SCL

7FB1

NOTES

1. NC = NO CONNEC T.

2. CONNECT THE EXPOSED PADDLE TO GND.

ADD5203

TOP VIEW

(Not to Scale)

8

9

10

FB2

FB3

FB4

VP

SW

O

SHDN

SW

23

22

24

25

21 PGND

20 PGND
19 C_FPWM

18 R_FPWM

17 I

SET

16 NC

15 FB8

11

12

13

14

FB5

FB6

FB7

AGND

08717-003

Figure 3. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 PWMI PWM Signal Input.
2 SEL1 Dimming Mode Selection 1.
3 SEL2 Dimming Mode Selection 2.
4 VDDIO Internal Linear Regulator Output. This regulator provides power to the ADD5203.
5 SDA Serial Data Input/Output.
6 SCL Serial Clock Input.
7 FB1 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin.
8 FB2 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin.
9 FB3 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin.
10 FB4 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin.
11 AGND Analog Ground.
12 FB5 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND.
13 FB6 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND.
14 FB7 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND.
15 FB8 Regulated Current Sink. Connect the bottom cathode of the LED string to this pin. If unused, connect to GND.
16 NC No Connection.
17 I

Full-Scale LED Current Set. A resistor from this pin to ground sets the LED current up to 30 mA.

SET

18 R_FPWM Dimming frequency adjustment pin with an external resistor.
19 C_FPWM Dimming frequency adjustment pin with an external capacitor.
20 PGND Power Ground.
21 PGND Power Ground.
22 OVP Overvoltage Protection.
23 SW Drain Connection of the Internal Power FET.
24 SW Drain Connection of the Internal Power FET.
25

SHDN

Shutdown Control for PWM Input Operation Mode. Active low.
26 VIN Supply Input. Must be locally bypassed with a capacitor to ground.
27 FSLCT Frequency Select. A resistor from this pin to ground sets the boost switching frequency from 350 kHz to 1 MHz.
28 COMP

Compensation for Boost Converter. A capacitor and a resistor are connected in series between ground and

this pin for stable operation and an optional capacitor can be connected from this pin to ground.
EP Exposed Paddle. Connect the exposed paddle to ground.

Rev. 0 | Page 8 of 24

ADD5203

TYPICAL PERFORMANCE CHARACTERISTICS

94

I

= 20mA

LED

BRIGHTNESS = 100%

92

f

= 600kHz

SW

90

8 PARALLEL × 8 SERIES

88

86

84

82

BOOST CONVERTER EFFICIENCY (%)

80

10 PARALLEL × 8 SERIES

25

20

15

10

LED CURRENT (mA)

5

78

5101520

INPUT VOLTAG E (V)

Figure 4. Boost Converter Efficiency vs. Input Voltage

32

30

28

26

24

22

20

18

16

LED CURRENT (mA)

14

12

10

8

85 105 125 145 165 185 205 225 245 265

Figure 5. LED Current vs. R

20

15

(kΩ)

R

SET

SET

25

08717-004

08717-005

0

02225200175150125100755025

SMBus BRIGHTNESS SETTING

Figure 7. LED Current vs. SMBus Brightness Setting

25

20

15

10

LED CURRENT (mA)

5

0

5 101520

Figure 8. LED Current vs. Input Voltage (I

INPUT VOLTAGE (V)

= 20 mA)

LED

VIN = 15V
BRIGHTNESS = 100%
LEDs = 12 SERI ES × 8 PARALLEL

50

08717-007

08717-008

V

OUT

20V/DIV

V

SW

20V/DIV

10

LED CURRENT (mA)

5

0

0 10 20 30 40 50 60 70 80 90 100

PWM DUTY CYCLE (%)

Figure 6. LED Current vs. PWM Input Duty Cycle

08717-006

Rev. 0 | Page 9 of 24

Figure 9. Start-Up Waveforms (Brightness = 100%)

SHDN
3V/DIV

I

L

1A/DIV

08717-009

ADD5203

VIN = 7V,

f

= 1MHz

SW

BRIGHTNESS = 100%
LEDs = 10 SERIES × 8 PARALLEL

Figure 10. Switching Waveforms (VIN = 7 V)

VIN = 21V,

V

= 1MHz
BRIGHTNESS = 100%
LEDs = 10 SERIES × 8 PARALLEL

SW

Figure 11. Switching Waveforms (VIN = 21 V)

V

OUT

200mV/DIV
AC

V

SW

20V/DIV

I

L

500mA/DIV

V

OUT

200mV/DIV
AC

V

SW

20V/DIV

I

L

500mA/DIV

PWM
3V/DIV

V

FB1

5V/DIV

I

FB1

VIN = 12V
BRIGHTNESS = 0.39%

08717-010

LEDs = 10 SERIE S × 8 PARALLEL

10mA/DIV

08717-012

Figure 12. LED Current Waveforms (Brightness = 0.39%)

PWM
3V/DIV

V

FB1

5V/DIV

I

FB1

10mA/DIV

VIN = 12V
BRIGHT NESS = 25%

08717-011

LEDs = 10 SERIES × 8 PARALLEL

Figure 13. LED FBx Waveforms (Brightness = 10%)

08717-013

Rev. 0 | Page 10 of 24

ADD5203

THEORY OF OPERATION

CURRENT-MODE, STEP-UP SWITCHING REGULATOR OPERATION

The ADD5203 uses a current-mode PWM boost regulator to
provide the minimal voltage needed to enable the LED string at
the programmed LED current. The current-mode regulation
system allows fast transient response while maintaining a stable
output voltage. By selecting the proper resistor-capacitor network
from COMP to GND, the regulator response can be optimized for
a wide range of input voltages, output voltages, and load conditions.
The ADD5203 can provide a 45 V maximum output voltage and
drive up to 13 LEDs (3.4 V/30 mA type of LEDs) for each channel.

INTERNAL 3.3 V REGULATOR

The ADD5203 contains a 3.3 V linear regulator. The regulator is
used for biasing internal circuitry. The internal regulator requires
a 1 F bypass capacitor. Place this bypass capacitor between
VDDIO (Pin 4) and GND, as close as possible to Pin VDDIO.

BOOST CONVERTER SWITCHING FREQUENCY

The ADD5203 boost converter switching frequency is user
adjustable, between 350 kHz to 1 MHz, by using an external
resistor, R
the regulator for high efficiency, and a frequency of 1 MHz is
recommended for small external components.

See Figure 14 for considerations when selecting a switching
frequency and an adjustment resistor (R

DIMMING FREQUENCY (f

The ADD5203 contains an internal oscillator to generate the
PWM dimming signal for LED brightness control. The LED
dimming frequency (f
to 10 kHz, by using an external resistor (R
(C

FPWM

and the C

. A frequency of 350 kHz is recommended to optimize

F

).

F

1100

1000

900

800

700

600

500

SWITCHING FREQUENCY (kHz)

400

300

120 170 220 270 320 370 420 470

Figure 14. Switching Frequency vs. R

) is adjustable, in the f

PWM

). The R

FPWM

should be in the range of 13 k to 110 k,

FPWM

should be in the range of 20 pF to 390 pF.

R

F

PWM

(kΩ)

)

F

range of 200 Hz

PWM

) and capacitor

FPWM

08717-014

Table 8. R

Dimming Freq (f

200 Hz 110 390
500 Hz 75 200
1 kHz 50 150
5 kHz 18 47
10 kHz 13 20

CURRENT SOURCE

The ADD5203 contains eight current sources to provide accurate
current sinking for each LED string. String-to-string tolerance is
kept within ±1.5% at 20 mA. Each LED string current is adjusted
up to 30 mA by an external resistor.

The ADD5203 contains an LED open and short fault protection
circuit for each channel. If the headroom voltage of the current
source remains below 200 mV while the boost converter output
reaches the OVP level, the ADD5203 recognizes that the current
source has an open load fault for the current source, and the current
source is disabled. If the headroom voltage of the current source
goes above 7.2 V, the current source is disabled for short protection.

If an application requires four LED strings, each LED string
should be connected using FB1 to FB4. Tie the unused FB pins
(FB5 to FB8) to GND.

The ADD5203 contains hysteresis to prevent the LED current
change that is caused by a ±0.195% jitter of the PWM input.

Programming the LED Current

As shown in Figure 2, the ADD5203 has an LED current set pin

). A resistor (R

(I

SET

current up to 30 mA. LED current level can be set with the
following equation:

I

LED

DIMMING CONTROL INTERFACE

The ADD5203 dimming control interface method is selectable
between the SMBus serial input and/or the external PWM input.
The LED dimming modes supported by ADD5203 can be
controlled externally through these dimming control interfaces.
The SEL1 and SEL2 pins should be set based on the application
conditions (see Tabl e 9).

Table 9. Brightness Control Mode Selection

SEL1 SEL2 Dimming Mode Interface

High High Fixed delay PWM SMBus
Low No delay PWM SMBus
Open High Fixed delay PWM PWM
Low No delay PWM PWM
Low High DC current SMBus
Open DC current PWM
Low Direct PWM PWM

=

FPWM

2831

R

SET

and C

A

Recommendation

FPWM

) R

PWM

) from this pin to ground adjusts the LED

SET

)(

(kΩ) C

FPWM

FPWM

(pF)

Rev. 0 | Page 11 of 24

ADD5203

t

PWM DIMMING MODE

The ADD5203 supports an 8-bit resolution to control brightness;
therefore, the LED dimming duty is generated with 256 steps through
the PWM input duty value in the range of 0% to 100%. In addition,
if the PWM input duty cycle is 0% longer than 10 ms, the
ADD5203 is disabled.

Note that the ADD5203 has immunity when the PWM input
duty cycle is converted to 256 steps. Even the PWM input has
±0.195% jitter.

Fixed Delay PWM Dimming

Fixed delay PWM mode is selected when SEL1 is open and SEL2 is
high for a PWM application, or when SEL1 is high and SEL2 is high
for an SMBus application. In this mode, each current source has a
fixed turn-on time delay between adjacent strings. The fixed delay
time is set by the FPWM frequency. Each channel delay time is set by
the following equation:

2

FPWM

t×=

D

FPWM

(DUTY = 60 %)

t

1

t

D

2

7 ×

8

= 1/f

DUTY = 60%

t

FPWM

t

OFF

ON

t

D

where t

PWMI

f

PWM

I

LED

I

LED

I

LED

No Delay PWM Dimming

No-delay PWM mode is selected when SEL1 is open and SEL2 is low
for a PWM application or when SEL1 is high and SEL2 is low for an
SMBus application. In this mode, each current source turns on and
off at the same time without any phase delay.

DUTY = 60%

PWMI

DUTY = 60%

f

PWM

t

ON

t

OFF

I

1

LED

I

2

LED

I

8

LED

256

PWM

, and f

is the LED dimming frequency.

PWM

Figure 15. Fixed-Delay PWM Dimming Timing

Figure 16. No Delay PWM Dimming Timing

08717-015

08717-016

Direct PWM Dimming

Direct PWM mode is selected when SEL1 is low and SEL2 is low
for a PWM application. In this mode, the PWM input controls
the ADD5203 LED dimming logic. It turns the current sources on
and off without any duty extraction. In addition, each current
source has no phase delay in this mode. The LED brightness is
changed by the PWM input duty ratio.

DUTY = 60%

PWMI

DUTY = 60%

I

1

LED

I

2

LED

I

3

LED

I

8

LED

08717-017

Figure 17. Direct PWM Dimming Timing

DC Current Dimming

DC current mode is selected when SEL1 is low and SEL2 is open
for a PWM application, or when SEL1 is low and SEL2 is high for
an SMBus application. In this mode, the maximum LED current
is set by the value of R

. Once the maximum LED current is set,

SET

the LED current can be changed with 256 steps through PWM
input or SMBus.

DUTY = 80% DUT Y = 60% DUT Y = 40% DUTY = 20%

PWMI

I

LED MAX

0.8 × I

I

LED

0A

LED MAX

0.6 × I

LED MAX

0.4 × I

LED MAX

0.2 × I

LED MAX

08717-018

Figure 18. DC Current Dimming Timing

SAFETY FEATURES

The ADD5203 contains several safety features to provide stable
operation.

Soft Start

The ADD5203 contains an internal soft start function to reduce
inrush current at startup. The soft start time is typically 1.5 ms.

Overvoltage Protection (OVP)

The ADD5203 contains OVP circuits to prevent boost converter
damage if the output voltage becomes excessive for any reason. To
keep a safe output level, the integrated OVP circuit monitors the
output voltage. When the OVP pin voltage is reached by the OVP
rising threshold, the boost converter stops switching, causing the
output voltage to drop. When the OVP pin voltage goes lower than
the OVP falling threshold, the boot converter begins switching,
causing the output to rise. There is about 7.5% hysteresis between
the rising and falling thresholds. The OVP level can be calculated
with the following equation:

Rev. 0 | Page 12 of 24

ADD5203

V

2.1

V

OVP

V

R1

R2R1

+×=

)(

In general, the suitable OVP level is 5 V higher than the nominal
boost switching regulator output. Large resistors, up to 1 M, can
be used for R2 to minimize power loss. In addition, some applications
require C1 to prevent noise interference at the OVP pin in the
range of 10 pF to 30 pF.

OVP

R2

OVP
REF

22

R1

C1

08717-019

OVP

DETECTIO N

OVP

COMP

Figure 19. Overvoltage Protection Circuit

Open Load Protection (OLP)

The ADD5203 contains a headroom control circuit to minimize
power loss at each current source. Therefore, the minimum
feedback voltage is achieved by regulating the output voltage of
the boost converter. If any LED string is opened during normal
operation, the current source headroom voltage (V

) is pulled to

HR

GND. In this condition, open load protection (OLP) is activated if

is less than 200 mV until the boost converter output voltage

V

HR

rises up to the OVP level.

Short-Circuit Protection (SCP)

The ADD5203 contains the short circuit protection (SCP). If a
few LEDs at any strings are shorted during normal operation, the
current source headroom voltage (V
condition, SCP is activated if V

) is increasing. In this

HR

is higher than 7.2 V; therefore,

HR

the string that includes short LEDs is disabled.

Undervoltage Lockout (UVLO)

An undervoltage lockout circuit is included with built-in hysteresis.
The ADD5203 turns on when VIN rises above 5 V (typical) and
shuts down when VIN falls below 4.6 V (typical).

Thermal Overload Protection

Thermal overload protection prevents excessive power dissipation
from overheating the ADD5203. When the junction temperature

) exceeds 160°C, a thermal sensor immediately activates the

(T

J

fault protection, which shuts down the device, allowing the IC to
cool. The device self-starts when the junction temperature (T

) of

J

the die falls below 130°C.

SMBUS INTERFACE

SMBus mode can be selected using the SEL1 and SEL2 mode
selection pins. When in SMBus mode, the ADD5203 can be
controlled with an SMBus serial interface.

Read Byte

As shown in Figure 21, the read byte protocol is four bytes long and
starts with the slave address followed by the command code, which
translates to the register index. Then, the bus direction turns around
with the rebroadcast of the slave address, with Bit 0 indicating a read
cycle. The fourth byte contains the data being returned by the
backlight controller. The byte value in the data byte should reflect the
value of the register being queried at the command code index. Note
the bus directions, which are shaded in Figure 21 and are used on
cycles where the slaved backlight controller drives the data line. All
other cycles are driven by the host master.

Write Byte

The write byte protocol is only three bytes long. The first byte
starts with the slave address followed by the command code,
which translates to the register index being written. The third
byte contains the data byte that must be written into the register
selected by the command code. Note the bus directions, which
are shaded in Figure 22 and are used on cycles where the slaved
backlight controller drives the data line. All other cycles are driven
by the host master.

Rev. 0 | Page 13 of 24

ADD5203

Slave Device Address

As shown in Figure 23, the ADD5203 address consists of seven

W

address bits plus one read/write (R/

) bit. If the device is in write

mode, the LSB is set to 0 and the slave address byte is 0x58. If the

t

SCL

SDA

LOW

V

IH

V

IL

t

t

HD:STA

V

IH

V

IL

t

BUF

HD:DAT

t

R

t

HIGH

Figure 20. SMBus Interface

device is in read mode, the LSB is set to 1 and the slave address byte
is 0x59.

t

F

t

SU:STA

t

SU:DAT

t

SU:STO

PSSP

08717-020

SSRAAAWSLAVE ADDRESS COMMAND CODE SLAVE ADDRESS DATA BYTE P

MASTER TO SLAVE

SLAVE TO MASTER

A

08717-021

Figure 21. Read Byte Protocol

SWAASLAVE ADDRESS COMMAND CODE DATA BYTE AP

MASTER TO SLAVE

SLAVE TO MASTER

08717-022

Figure 22. Write Byte Protocol

R/W0011010

08717-023

Figure 23. Slave Address Definition

Rev. 0 | Page 14 of 24

ADD5203

SMBUS REGISTER DESCRIPTION

The ADD5203 has four registers to control and monitor
brightness, fault status, identifications, and operating mode.
Those registers are one byte wide and accessible via the SMBus
read/write byte protocols.

Brightness Control Register (Address 0x00)

This register consists of eight bits, BRT7 to BRT0, which are used
to control the LED brightness level in 256 steps. An SMBus write
byte cycle to this register sets the brightness level if the device is
in SMBus mode. In addition, a write byte cycle to this register sets
the brightness level if the device is in SMBus mode. Furthermore,
a write byte cycle to this register has no effect when the device is
in a mode other than SMBus mode. The operating mode is
selected by the device control register (Address 0x01).

An SMBus read byte cycle to this register returns the current
brightness level, regardless of the value of PWM_SEL. An SMBus
setting of 0xFF for this register sets the device to the maximum
brightness output, and a setting of 0x00 sets the device to the
minimum brightness output.

This register is both readable and writable for all bits. The default
value is 0xFF.

Device Control Register (Address 0x01)

This register has three bits. Two bits control the operation mode
of the device, and a single bit controls the backlight on/off state.
This register is both readable and writable for Bit 0 to Bit 2. Bit 0,
named BL_CTL, is used as on/off control for the output LEDs.
Bit 1 and Bit 2, named PWM_SEL and PWM_MD, control the
operating mode of the device, respectively. If the BL_CRT bit is
set to 1, the device turns on the backlight within 10 ms after the
write cycle. If the BL_CRT bit is set to 0, the device turns off the
backlight immediately. The ADD5203 output operating mode is
selected by the combination of Bit 1 and Bit 2 (see Tab le 1 0 ).

The PWM_MD bit selects the manner in which the PWM input is to
be interpreted. When this bit is 0, the PWM input reflects a percent
change in the current brightness (that is, DPST mode) and should be
as follows:

DPST Brightness = CBT × (PWM)

where:

C

is the current brightness setting from SMBus without influence

BT

from the PWM.

PWM is the percent duty cycle.

The PWM signal starts from 100% when operating in DPST mode.

When PWM_MD is 1, the PWM input has no effect on the
brightness setting, unless the ADD5203 is in PWM mode. In
addition, when operating in PWM mode, this bit is a do not care (see
Table 10). The PWM_SEL bit determines whether the SMBus or
PWM input should drive brightness.

The relationship between these two control bits can be thought of as
specifying an operating mode for the ADD5203. The defined modes
are shown in Tab l e 1 0 . Note that depending on the setting of some
bits, other bits have no effect and are do not cares, shown as X
in Tabl e 10 .

Table 10. Operating Modes Selected by Device Control
Register Bit 1 and Bit 2

PWM_SEL (Bit 1) PWM_MD1 (Bit 2) Mode

1 X PWM mode
0 1 SMBus mode
0 0 SMBus mode with DPST

1

X is don’t care.

All reserved bits return to 0 when read, and the bits are ignored when
written. This default value of the register is 0x00.

Table 11. Brightness Control Register (Address 0x00) Bit Map

MSB
Bit 7 (R/

BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 0xFF

) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)

W

LSB

Default Value

Table 12. Brightness Control Register (Address 0x00) Bit Description

Bit Name Description

BRT[7:0] 256 steps of brightness levels

Table 13. Device Control Register (Address 0x01) Bit Map

MSB LSB

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

Reserved Reserved Reserved Reserved Reserved PWM_MD PWM_SEL BL_CTL 0x00

Bit 2 (R/

) Bit 1 (R/W) Bit 0 (R/W)

W

Default Value

Rev. 0 | Page 15 of 24

ADD5203

Table 14. Device Control Register (Address 0x01) Bit Description

Bit Name Description

PWM_MD

PWM_SEL

BL_CTL

Fault/Status Register (Address 0x02)

This register has six status bits that allow monitoring of the
ADD5203 operating state. Bit 0, named fault, is a logical OR of
all fault codes to simplify error detection. In the operation of the
ADD5203, Bit 1, named THRM_SHDN, is set to 1 when a
thermal shutdown event occurs. Bit 3, named BL_STAT, is the
backlight status indicator. This bit is set to 1 whenever the backlight
is on and is set to 0 whenever the backlight is off. Bit 4, named
1_CH_SD, is set to 1 if one or more current sources are disabled.
In addition, Bit 5, named 2_CH_SD, is set to 1 if two or more
current sources are disabled due to an LED open event during
normal operation. All reserved bits return to 0 when read and
ignore the bit value when written. All of the bits in this register
are read only. The default value for Register 0x02 is 0x00.

PWM mode select
1 = absolute brightness, 0 = percent change (default)

Brightness control select
1 = control by PWM, 0 = control by SMBus (default)

Backlight on/off
1 = on, 0 = off (default)

Identification Register (Address 0x03)

The ID register contains two bit fields to denote the manufacturer
and silicon revision of the ADD5203. The bit field widths were
chosen to allow up to 16 vendors with up to eight silicon revisions
each. To ensure that the number of silicon revisions remains low,
the revision field should not be updated until the part is sent to
the factory of the end-customer. Therefore, if during the engineering
development process, three silicon spins are needed before the device
is released to the factory of the end-customer, the next available
revision ID is used for these three spins. The manufacturer ID of
Analog Devices, Inc., is 6 (Bit[6:3] = 0110b). In addition, the initial
value of REVx is 0, and subsequent REVx values are incremented
by 1. This register is read only.

Table 15. Fault/Status Register (Address 0x02) Bit Map

MSB LSB
Bit 7 Bit 6 Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R) Bit 0 (R) Default Value

Reserved Reserved 2_CH_SD 1_CH_SDS BL_STAT OV_CURR THRM_SHDN Fault 0x00

Table 16. Fault/Status Register (Address 0x01) Bit Description

Bit Name Description

2_CH_SD_, 1_CH_SD

BL_STAT

OV_CURR

THRM_SHDN

Fault Fault occurred. Logic OR of all the fault conditions.

The number of faulted strings is reported in these bits.
00 = no faults, 01 = one string fault, 11 = two or more strings faulted.

Backlight status.
1 = backlight on, 0 = backlight off (default).

Input overcurrent.
1 = overcurrent condition, 0 = current ok (default).

Thermal shutdown.
1 = thermal fault, 0 = thermal ok (default).

Table 17. Identification Register (Address 0x03) Bit Map

MSB
Bit 7 Bit 6 Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R) Bit 0 (R) Default Value

LED panel MFG3 MFG2 MFG1 MFG0 REV2 REV1 REV0 0xB0

LSB

Table 18. Identification Register (Address 0x03) Bit Description

Bit Name Description

LED Panel Display panel using LED backlight, Bit 7 = 1.
MFG[3:0] Manufacturer ID (Analog Devices ID is 6).
REV[2:0] Silicon revision (Revision 0 to Revision 7 are allowed for silicon spins).

Rev. 0 | Page 16 of 24

ADD5203

t

t

−

(

)

×

EXTERNAL COMPONENT SELECTION GUIDE

Inductor Selection

The inductor is an integral part of the step-up converter. It stores
energy during the switch-on time and transfers that energy to
the output through the output diode during the switch-off time.
An inductor in the range of 4.7 µH to 22 µH is recommended.
In general, lower inductance values result in higher saturation
current and lower series resistance for a given physical size.
However, lower inductance results in higher peak current, which
can lead to reduced efficiency and greater input and/or output
ripple and noise. Peak-to-peak inductor ripple current at close
to 30% of the maximum dc input current typically yields an
optimal compromise.

The input (V

) and output (V

IN

switch duty cycle (D), which in turn can be used to determine
the inductor ripple current.

VVD−

IN

OUT

=

V

OUT

Use the duty cycle and switching frequency (f
the on time.

D

t =

ON

f

SW

The inductor ripple current (I

V

×

IN

ON

I

=Δ

L

L

Solve for the inductance value (L).

V

×

IN

ON

L

=

Δ

I

L

Make sure that the peak inductor current (that is, the maximum
input current plus half of the inductor ripple current) is less
than the rated saturation current of the inductor. In addition,
ensure that the maximum rated rms current of the inductor is
greater than the maximum dc input current to the regulator.

For duty cycles greater than 50% that occur with input voltages
greater than half the output voltage, slope compensation is required
to maintain stability of the current-mode regulator. The inherent
open-loop stability causes subharmonic instability when the
duty ratio is greater than 50%. To avoid subharmonic instability,
the slope of the inductor current should be less than half of the
compensation slope.

Inductor manufacturers include Coilcraft, Inc., Sumida
Corporation, and Toko.

Input and Output Capacitors Selection

The ADD5203 requires input and output bypass capacitors to
supply transient currents while maintaining a constant input
and output voltage. Use a low effective series resistance (ESR)
10 F or greater capacitor for the input capacitor to prevent noise
at the ADD5203 input. Place the input between the VIN and
GND, as close as possible to the ADD5203. Ceramic capacitors

) voltages determine the

OUT

) to determine

SW

) in a steady state is

L

Rev. 0 | Page 17 of 24

are preferred because of their low ESR characteristics.
Alternatively, use a high value, medium ESR capacitor in
parallel with a 0.1 F low ESR capacitor as close as possible to
the ADD5203.

The output capacitor maintains the output voltage and supplies
current to the load while the ADD5203 switch is on. The value
and characteristics of the output capacitor greatly affect the
output voltage ripple and stability of the regulator. Use a low
ESR output capacitor; ceramic dielectric capacitors are preferred.

For very low ESR capacitors, such as ceramic capacitors, the
ripple current due to the capacitance is calculated as follows.
Because the capacitor discharges during the on time (t
charge removed from the capacitor (Q

) is the load current

C

ON

), the

multiplied by the on time. Therefore, the output voltage ripple
(V

) is

OUT

Q

V

OUT

C

C

OUT

tI

×

L

ON

==Δ

C

OUT

where:

C

is the output capacitance.

OUT

IL is the average inductor current.

Using the duty cycle and switching frequency (f

), users can

SW

determine the on time with the following equation:

D

t =

ON

The input (V

f

SW

) and output (V

IN

) voltages determine the

OUT

switch duty cycle (D) with the following equation:

VV

IN

OUT

=

D

V

OUT

Choose the output capacitor based on the following equation:

VVI

−

OUT

IN

VVf

Δ××

OUTOUT

L

≥

C

OUT

SW

Capacitor manufacturers include Murata Manufacturing Co.,
Ltd., AVX, Sanyo, and Taiyo Yuden Co., Ltd.

Diode Selection

The output diode conducts the inductor current to the output
capacitor and loads while the switch is off. For high efficiency,
minimize the forward voltage drop of the diode. Schottky diodes
are recommended. However, for high voltage, high temperature
applications, where the Schottky diode reverse leakage current
becomes significant and can degrade efficiency, use an ultrafast
junction diode. The output diode for a boost regulator must be
chosen depending on the output voltage and the output current.
The diode must be rated for a reverse voltage equal to or greater
than the output voltage used. The average current rating must
be greater than the maximum load current expected, and the peak
current rating must be greater than the peak inductor current.
Using Schottky diodes with lower forward voltage drop decreases
power dissipation and increases efficiency. The diode must be
rated to handle the average output load current. Many diode

ADD5203

manufacturers derate the current capability of the diode as a
function of the duty cycle. Verify that the output diode is rated
to handle the average output load current with the minimum
duty cycle.

The minimum duty cycle of the ADD5203 is

=

MIN

V

where

IN_MAX

For example, D

OUT

V

OUT

is the maximum input voltage.

is 0.5 when V

MIN

is 30 V and V

OUT

IN_MAX

is 15 V.

VVD−

IN_MAX

Schottky diode manufacturers include ON Semiconductor,
Diodes Incorporated, Central Semiconductor Corp., and Sanyo.

Loop Compensation

The external inductor, output capacitor, and the compensation
resistor and capacitor determine the loop stability. The inductor
and output capacitor are chosen based on performance, size, and
cost. The compensation resistor (R

) at the COMP pin are selected to optimize control loop

(C

C

) and compensation capacitor

C

stability.

For most applications, the compensation resistor should be in
the range of 500  to 30 k , and the compensation capacitor
should be in the range of 100 pF to 330 nF.

REF

Figure 24. Compensation Components

G

V

MEA

HR

R

C

C

C2

C

08717-024

A step-up converter produces an undesirable right-half plane
zero in the regulation feedback loop. Capacitor C2 is chosen
to cancel the zero introduced by output capacitance ESR.
Solving for C2

CESRC2×

OUT

=

R

C

For low ESR output capacitance, such as with a ceramic
capacitor, C2 is optional.

LAYOUT GUIDELINES

When designing a high frequency, switching, regulated power
supply, layout is very important. Using a good layout can solve
many problems associated with these types of supplies. The
main problems are loss of regulation at high output current
and/or large input-to-output voltage differentials, excessive
noise on the output and switch waveforms, and instability.
Using the following guidelines can help minimize these
problems.

Make all power (high current) traces as short, direct, and thick
as possible. It is good practice on a standard printed circuit
board (PCB) to make the traces an absolute minimum of 15 mil
(0.381 mm) per ampere. Place the inductor, output capacitors,
and output diode as close to each other as possible. This helps
reduce the EMI radiated by the power traces that are due to the
high switching currents through them. This also reduces lead
inductance and resistance, which, in turn, reduce noise spikes,
ringing, and resistive losses that produce voltage errors. The
grounds of the IC, input capacitors, output capacitors, and
output diode (if applicable), should be connected close together,
directly to a ground plane. It is also a good idea to have a ground
plane on both sides of the PCB. This reduces noise by reducing
ground loop errors and by absorbing more of the EMI radiated
by the inductor.

For multilayer boards of more than two layers, a ground plane
can be used to separate the power plane (power traces and com­ponents) and the signal plane (feedback, compensation, and
components) for improved performance. On multilayer boards,
the use of vias is required to connect traces and different planes.
If a trace needs to conduct a significant amount of current from
one plane to the other, it is good practice to use one standard
via per 200 mA of current. Arrange the components so that the
switching current loops curl in the same direction.

Due to how switching regulators operate, there are two power
states: one state when the switch is on, and one when the switch
is off. During each state, there is a current loop made by the
power components currently conducting. Place the power
components so that the current loop is conducting in the same
direction during each of the two states. This prevents magnetic
field reversal caused by the traces between the two half cycles
and reduces radiated EMI.

Rev. 0 | Page 18 of 24

ADD5203

Layout Procedure

To achieve high efficiency, good regulation, and stability, a good
PCB layout is required. It is recommended that the reference
board layout be followed as closely as possible because it is
already optimized for high efficiency and low noise.

Use the following general guidelines when designing PCBs:

• Keep C

• Keep the high current path from C

close to the VIN and GND leads of the ADD5203.

IN

(through L1) to the

IN

SW and GND leads as short as possible.

• Keep the high current path from C

as short as possible.

C

OUT

(through L1), D1, and

IN

• Keep high current traces as short and wide as possible.

• Keep nodes connected to SW away from sensitive traces,

such as COMP, to prevent coupling of the traces. If such
traces need to be run near each other, place a ground trace
between the two as a shield.

• Place the compensation components as close as possible to

the COMP pin.

• Place the LED current setting resistors as close as possible

to each pin to prevent noise pickup.

• Avoid routing noise sensitive traces near high current

traces and components, especially the LED current setting

SET

).

node (I

• Use a thermal pad size that is the same dimension as the

exposed pad on the bottom of the package.

Heat Sinking

When using a surface-mount power IC or external power
switches, the PCB can often be used as the heat sink. This is
accomplished by using the copper area of the PCB to transfer
heat from the device. Users should maximize this area to optimize
thermal performance.

Rev. 0 | Page 19 of 24

ADD5203

2

TYPICAL APPLICATION CIRCUITS

NC

25

SHDN

150kΩ

10µH

I

SET

R3

L1

ADD5203

COMP

C5

100nF

23 24 22

SW SW OVP

2817

R4

5.6kΩ

NC

FB1

FB2

FB3

FB4

FB5

FB6

FB7

FB8

PGND

PGND

AGND

C6
OPEN

D1

R1

1.2MΩ

R2

40kΩ

16

7

8

9

10

12

13

14

15

20

21

11

C3
30pF

Figure 25. Typical Application Circuit for SMBus Interface

with No Delay Dimming Mode

C4
4µF

V

OUT

UP TO 45V

08717-025

V

IN

6V TO 21V

C1

µF

0.1µF

C3

1µF

C2

10kΩ

20pF

26

VIN

1

PWMI

6

SCL

5

SDA

4

VDDIO

R7

2

SEL1

3

SEL2

19

C_FPWM

18

27

R_FPWM

FSLCT

C7

R6

15kΩ

R5

470kΩ

Rev. 0 | Page 20 of 24

ADD5203

2

V

IN

6V TO 21V

C1

µF

0.1µF

C8

1µF

C2

20pF

L1

10µH

NC

25

SHDN

26

VIN

1

PWMI

6

NC

NC

C7

R6

15kΩ

470kΩ

SCL

5

SDA

4

VDDIO

2

SEL1

3

SEL2

19

C_FPWM

18

R_FPWM

27

FSLCT

R5

I

SET

R3

150kΩ

23 24 22

SW SW OVP

ADD5203

COMP

2817

C5

100nF

R4

5.6kΩ

NC

FB1

FB2

FB3

FB4

FB5

FB6

FB7

FB8

PGND

PGND

AGND

C6
OPEN

D1

16

10

12

13

14

15

20

21

11

7

8

9

40kΩ

R1

1.2MΩ

R2

C3
30pF

C4
4µF

V

OUT

UP TO 45V

08717-026

Figure 26. Typical Application Circuit for PWM Interface

with DPWM Dimming Mode

Rev. 0 | Page 21 of 24

ADD5203

2

V

IN

6V TO 21V

C1

µF

0.1µF

C8

1µF

C2

20pF

L1

10µH

NC

25

SHDN

26

VIN

1

PWMI

6

5

4

2

3

19

18

27

SCL

SDA

VDDIO

SEL1

SEL2

C_FPWM

R_FPWM

FSLCT

150kΩ

I

SET

R3

NC

NC

NC

C7

R6

15kΩ

R5

470kΩ

23 24 22

SW SW OVP

ADD5203

COMP

2817

C5

100nF

R4

5.6kΩ

NC

FB1

FB2

FB3

FB4

FB5

FB6

FB7

FB8

PGND

PGND

AGND

C6
OPEN

D1

R1

1.2MΩ

R2

40kΩ

16

7

8

9

10

12

13

14

15

20

21

11

C3
30pF

C4
4µF

V

OUT

UP TO 45V

08717-027

Figure 27. Typical Application Circuit for PWM Interface

with DC Current Dimming Mode

Rev. 0 | Page 22 of 24

ADD5203

S

C

OUTLINE DIMENSIONS

0.25

0.20

0.15

22

21

15

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

P

N

1

I

A

N

I

D

C

28

EXPOSED

PAD

814

FOR PROPER CO NNECTION O F
THE EXPOSED PAD, REFER T O
THE PIN CONF IGURATIO N AND
FUNCTION DESCRI PTIONS
SECTION OF THIS DATA SHEET.

I

1

2.70

2.60 SQ

2.50

7

R

O

T

INDI

EATING

PLANE

PIN 1

ATO R

0.80

0.75

0.70

4.00

BSC SQ

0.40

BSC

0.45

0.40

0.35

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANTTOJEDEC STANDARDS MO-220-WGGE.

112108-A

Figure 28. 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

4 mm × 4 mm × 0.75 mm Body, Very Very Thin Dual

(CP-28-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Package Description Package Option

ADD5203ACPZ-RL −25°C to +85°C 28-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-28-5

1

Z = RoHS Compliant Part.

Rev. 0 | Page 23 of 24

ADD5203

NOTES

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