ANALOG DEVICES ADCMP608, ACMP609 Service Manual

Rail-to-Rail, Fast, Low Power, 2.5 V to 5.5 V,

Single-Supply TTL/CMOS Comparators

Preliminary Technical Data

FEATURES

10 mV sensitivity rail to rail at VCC = 2.5 V
Input common-mode voltage from −0.2 V to V
Low glitch CMOS-/TTL-compatible output stage
30 ns propagation delay
1 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection >60 dB

−40C° to +125C° operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators

+ 0.2 V

CC

ADCMP608/ACMP609

FUNCTIONAL BLOCK DIAGRAMS

NONINVERTI NG

INPUT

INVERTING

INPUT

NONINVERTI NG

INPUT

INVERTING

INPUT

+

ADCMP608

–

S

DN

+

ADCMP609

–

S

LE/HYS

Figure 1.

Q OUTPUT

Q OUTPUT

Q OUTPUT

DN

05918-001

GENERAL DESCRIPTION

The ADCMP608 and ADCMP609 are fast comparators
fabricated on Analog Devices’ proprietary XFCB2 process.
These comparators are exceptionally versatile and easy to use.
Features include an input range from V
low noise, TTL-/CMOS-compatible output drivers, and latch
inputs with adjustable hysteresis and/or shutdown inputs.

The devices offer 30 ns propagation delays driving a 15 pF load
with 5 mV overdrive on 350/400 A typical supply current. A
flexible power supply scheme allows the devices to operate with
a single +2.5 V positive supply and a −0.5 V to +3.0 V input
signal range up to a +5.5 V positive supply with a −0.5 V to +6V
input signal range. Split input/output supplies, with no
sequencing restrictions on the ADCMP609, support a wide
input signal range while allowing independent output swing
control.

− 0.5 V to VCC + 0.5 V,

EE

The TTL-/CMOS-compatible output stage is designed to drive
up to 15 pF with full rated timing specs and to degrade in a
graceful and linear fashion as additional capacitance is added.
The comparator input stage offers robust protection against
large input overdrive, and the outputs do not phase reverse
when the valid input signal range is exceeded. High speed latch
and programmable hysteresis features are also provided in a
unique single-pin control option.

The ADCMP608 is available in a tiny 6-lead SC70 package with
single-ended output and a shutdown pin.

The ADCMP609, available in an 8-lead MSOP package, features
a shutdown pin, single pin latch, and hysteresis control.

+

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADCMP608/ADCMP609

TABLE OF CONTENTS

Features.............................................................................................. 1

Preliminary Technical Data

Application Information...................................................................9

Applications....................................................................................... 1

Functional Block Diagrams............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

REVISION HISTORY

2/06—Revision PrA: Preliminary Version

Power/Ground Layout and Bypassing........................................9

TTL-/CMOS-Compatible Output Stage.........................................9

Using/Disabling the Latch Feature..............................................9

Optimizing Performance..............................................................9

Comparator Propagation Delay Dispersion ........................... 10

Comparator Hysteresis .............................................................. 10

Crossover Bias Point .................................................................. 11

Minimum Input Slew Rate Requirement ................................ 11

Typical Application Circuits ......................................................... 12

Timing Information....................................................................... 13

Rev. PrA | Page 2 of 16

Preliminary Technical Data

ADCMP608/ADCMP609

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, VN VCC = 2.5 V to 5.5 V −0.5 VCC + 0.5 V V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC + 0.2 V V
Differential Voltage VCC = 2.5 V to 5.5 V VCC V
Offset Voltage VOS −5.0 +5.0 mV
Bias Current IP, IN −2.0 ±1 +2.0 µA
Offset Current −0.5 +0.5 µA
Capacitance CP, CN TBD pF
Resistance, Differential Mode 0.1 V to VCC 150 kΩ
Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 kΩ
Active Gain AV 80 dB
Common-Mode Rejection CMRR

Hysteresis

LATCH ENABLE PIN CHARACTERISTICS

ADCMP609 only
VIH Hysteresis is shut off 2.0 V
VIL Latch mode guaranteed −0.2 0.4 0.8 V
LIH V
IOL V

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current sink 0 A 1.08 1.25 1.35 V
Minimum Resistor Value Hysteresis = 60 mV 60 kΩ
Latch Setup Time tS V
Latch Hold Time tH V
Latch to Output Delay t
Latch Minimum Pulse Width tPL V

SHUTDOWN PIN CHARACTERISTICS

VIH Comparator is operating 2.0 VCC V
VIL Shutdown guaranteed −0.2 0.4 0.6 V
IIH V
IOL V
Sleep Time tSD I
Wake-Up Time tH V

DC OUTPUT CHARACTERISTICS V

Output Voltage High Level VOH I
Output Voltage Low Level VOL I

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

V

PLOH, tPLOL

= 2.5 V, V

CCI

V

= −0.2 V to 2.7 V

CM

= 5.5 V, V

V

CCI

V

= −0.2 V to 5.7 V

CM

= ∞

R

HYS

= V

IH

CCO

= 0.4 V −0.1 mA

IL

= 100 mV 15 ns

OD

= 100 mV 20 ns

OD

VOD = 100 mV 20 ns

= 100 mV 20 ns

OD

= VCC 0.05 mA

IH

= 0 V −0.05 mA

IL

< 100 A 0.6 ns

CC

= 10 mV, output valid 3 ns

OD

= 2.5 V to 6 V

CCO

= 1.6 mA V

OH

= 1.6 mA V

OL

= 2.5 V,

CCO

= 5.5 V,

CCO

50 dB

60 dB

0.1 mV

+ 0.2 V

CCO

+ 0.2 V 0.1 mA

= 2.5 V VCC − 0.4 V

CCO

= 2.5 V 0.4 V

CCO

Rev. PrA | Page 3 of 16

ADCMP608/ADCMP609

Preliminary Technical Data

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE V

Propagation Delay, CL = 15 pF tPD

Propagation Delay Skew—Rising to

V

= V

CCI

V

CCO

V

OD

V

CCO

V

OD

OD

= 2.5 V to 5.5 V

CCO

= 5.5 V to 2.5 V,

30 ns

= 10 mV

= 2.5 V/5.5 V,

25/30 ns

= 200 mV
= 10 mV 2 ns

Falling Transition
Overdrive Dispersion 10 mV < VOD < 500 mV 4 ns
Slew Rate Dispersion

Small Signal
10% − 90% Duty Cycle Dispersion

Common-Mode Dispersion

10 V/s to 0.1 V/ns
200 mV p-p single ended

1.25 V, 50 V/s,

V

OD

V

= 1.25 V

CM

= 0 V to VCC

V

CM

1 ns

1 ns

0.5 ns

200 m p-p single ended

Toggle Rate

>50% output swing

= 15 pF V

C

L

CCI

= 5 V
RMS Random Jitter RJ VOD = 200 mV, 5 V/ns
Minimum Pulse Width PW
Rise Time tR

Fall Time tF

∆tPD/∆PW < 500 ps 35 ns

MIN

10% to 90% C
V

= 2.5 V to 5 V

CCI

10% to 90% C

= 2.5 V to 5 V

V

CCI

= 15 pF,

LOAD

= 15 pF,

LOAD

TBD Mbps

TBD

25 to 40

ns

ns

25 to 40

ns

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential

2.5 5.5 V

CCI

2.5 5.5 V

CCO

− V

V

CCI

Operating −3 +3 V

CCO

(ADCMP609)

Positive Supply Differential

V

− V

CCI

Nonoperating −5.5 +5.5 V

CCO

(ADCMP609)
Positive Supply Current I
Positive Supply Current I
Input Section Supply Current

V

VCC

V

VCC

V

I

VCCi

CC

CC

CCI

= 2.5 V 400 A
= 5.5 V 500 A

= 2.5 V 270 mA

(ADCMP609)
Output Stage Supply Current

V

VCCO

= 2.5 V 130 mA

CCO

I

(ADCMP609)
Power Dissipation PD V
Shutdown Current ISD V
Power Supply Rejection PSRR V

= 2.5 V 1 mW

CC

=2.5 V to 5.5 V 50 A

CC

= 2.5 V to 5 V >50 dB dB

CCI

Rev. PrA | Page 4 of 16

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltages

Input Supply Voltage (V
Output Supply Voltage

(V

to GND)

CCO

Positive Supply Differential

− V

CCO

)

(V

CCI

to GND) −0.5 V to +6.0 V

CCI

−0.5 V to +6.0 V

−6.0 V to +6.0 V

Input Voltages

Input Voltage −0.5 V to V
Differential Input Voltage

Maximum Input/Output Current

±(V

CCI

±50mA

CCI

+ 0.5 V)

+ 0.5 V

Shutdown Control Pin

Applied Voltage (HYS to GND) −0.5 V to Vcco + 0.5 V
Maximum Input/Output Current

±50 mA

Latch/Hysteresis Control Pin

Applied Voltage (HYS to GND) −0.5 V to V
Maximum Input/Output Current

Output Current

±50 mA
±50 mA

+ 0.5 V

CCO

Temperature

Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C

Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θ

ADCMP608 SC70 6-lead 426 °C/W
ADCMP609 MSOP 8-lead 130 °C/W

1

Measurement in still air.

ADCMP608/ADCMP609

1

JA

Unit

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrA | Page 5 of 16

ADCMP608/ADCMP609

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Q

1

ADCMP608

V

2

TOP VIEW

EE

(Not to Scale)

3

V

P

Figure 2. ADCMP608 Pin Configuration Figure 3. ADCMP609 Pin Configuration

Table 4. ADCMP608 Pin Function Descriptions

Pin No. Mnemonic Description

1 Q

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V

analog voltage at the inverting input, V
2 VEE Negative Supply Voltage.
3 VP Noninverting Analog Input.
4 Vn Inverting Analog Input.
5 SDN Shutdown. Drive this pin low to shutdown the device.
6 VCC V

Supply.

CC

Table 5. ADCMP609 Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Vcc Supply.

CCI/VCCO

2 VP Noninverting Analog Input.
3 Vn Inverting Analog Input.
4 SDN Shutdown. Drive this pin low to shutdown the device.
5 LE/HYS Latch/Hysteresis Control. Bias with resistor or current source for hysteresis; drive TTL low to latch.
6 VEE Negative Supply Voltage.
7 Q

Noninverting Output. Q is at logic low if the analog voltage at the noninverting input, V
analog voltage at the inverting input, V

8

Q Inverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog

voltage at the inverting input, VN, provided the comparator is in compare mode.

V

6

CC

S

5

DN

4

V

N

05918-002

.

N

, provided the comparator is in compare mode.

N

V

CC

V

P

V

N

S

DN

1

ADCMP609

2

TOP VIEW

3

(Not to Scale)

4

Q

8

7

Q

6

V

EE

5

LE/HYS

, is greater than the

P

, is greater than the

P

05918-003

Rev. PrA | Page 6 of 16

Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

CCI

= 3.3 V, TA = 25°C, unless otherwise noted.

CCO

Figure 4. Propagation Delay vs. Input Overdrive Figure 7. Hysteresis vs. Vcc

ADCMP608/ADCMP609

Figure 5. Propagation Delay vs. Input Common Mode Figure 8. Hysteresis vs. R

Figure 6. Propagation Delay vs. Temperature

Figure 9. Input Bias Current vs. Input Common Mode

Rev. PrA | Page 7 of 16

Control Resistor

HYS

ADCMP608/ADCMP609

Preliminary Technical Data

Figure 10. Input Bias Current vs. Temperature Figure 12 Latch/Hysteresis Control Pin I/V Characteristic.

Figure 11. Input Offset Voltage vs. Temperature

Rev. PrA | Page 8 of 16

Preliminary Technical Data

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP608 and ADCMP609 comparators are high speed
devices. Despite the low noise output stage, it is essential to use
proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated
amplifiers, feedback in any phase relationship is likely to cause
oscillations or undesired hysteresis. Of critical importance is the
use of low impedance supply planes, particularly the output
supply plane (V
supply planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.

It is also important to adequately bypass the input and output
supplies. A 0.1 µF bypass capacitor should be placed as close as
possible to each V
connected to the GND plane with redundant vias placed to
provide a physically short return path for output currents
flowing back from ground to the V
bypass capacitors should be carefully selected for minimum
inductance and ESR. Parasitic layout inductance should also be
strictly controlled to maximize the effectiveness of the bypass at
high frequencies.

TTL-/CMOS-COMPATIBLE OUTPUT STAGE

Specified propagation delay performance can be achieved only
by keeping the capacitive load at or below the specified mini­mums. The outputs of the ADCMP608 and ADCMP609 are
designed to directly drive one Schottky TTL or three low power
Schottky TTL loads or equivalent. For large fan outs, buses, or
transmission lines, an appropriate buffer should be used to
maintain the excellent speed and stability of the part.

With the rated 15 pF load capacitance applied, even at 2.5 V

, more than half of the total device propagation delay is

V

CC

output stage slew time. Because of this, the total prop delay will
decrease as V
may show up as excess delay dispersion.

This delay is measured to the 50% point for whatever supply is
in use, so the fastest times will be observed with the V
at 2.5 V, and larger values will be observed when driving loads,
that switch at other levels. Overdrive and input slew rate
dispersions are not significantly affected by output loading and
V

variations.

CC

The TTL/CMOS-compatible output stage is shown in the
simplified schematic diagram of
inherent symmetry and generally good behavior, this output
stage is readily adaptable for driving various filters and other
unusual loads.

) and the ground plane (GND). Individual

CCO

supply pin. The capacitor should be

CC

pin. High frequency

CC

decreases and instability in the power supply

CCO

Figure 12. Because of its

supply

CC

ADCMP608/ADCMP609

V

LOGIC

A1

+IN

A

V

–IN

A2

GAIN STAGE

OUTPUT STAGE

Figure 13. Simplified Schematic Diagram
of TTL/CMOS-COMPATIBLE Output Stage

USING/DISABLING THE LATCH FEATURE

The latch input of the ADCMP609 is designed for maximum
versatility. It can safely be left floating or pulled to TTL high for
normal comparator operation with no hysteresis, or it can be
driven low by any standard TTL/CMOS device as a high speed
latch.

In addition, the pin can be operated as a hysteresis control pin
with a bias voltage of 1.25 V nominal and an input resistance of
approximately 7000 . This allows the comparator hysteresis to
be easily and accurately controlled by either a resistor or an
inexpensive CMOS DAC.

Hysteresis control and latch mode can be used together if an
open drain, a collector, or a three-state driver is connected in
parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature,the logic threshold
of the latch pin is approximately 1.1 V regardless of V

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified
performance. Stray capacitance, inductance, common power
and ground impedances, or other layout issues can severely limit
performance and often cause oscillation. The source impedance
should be minimized as much as is practicable. High source
impedance, in combination with the parasitic input capacitance
of the comparator, will cause an undesirable degradation in
bandwidth at the input, thus degrading the overall response.
Higher impedances encourage undesired coupling.

Q1

Q2

OUTPUT

CC

05918-012

.

Rev. PrA | Page 9 of 16

ADCMP608/ADCMP609

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP608 and ADCMP609 comparator is designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to V
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (how far or how fast the input
signal exceeds the switching threshold).

Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communication, automatic test and measurement, and instru­mentation. It is also important in event-driven applications,
such as pulse spectroscopy, nuclear instrumentation, and
medical imaging. Dispersion is defined as the variation in
propagation delay as the input overdrive conditions are changed
(see

Figure 14 and Figure 15).

ADCMP608 and ADCMP609 dispersion is typically <5 ns as
the overdrive varies from 5 mV to 500 mV, and the input slew
rate varies from 2 V/ns to 10 V/ns. This specification applies to
both positive and negative signals because the device has very
closely matched delays for both positive-going and negative­going inputs, and very low output skews. Remember to add the
actual device offset to the overdrive for repeatable dispersion
measurements.

INPUT VOLTAGE

Q/Q OUTPUT

Figure 14. Propagation Delay—Overdrive Dispersion

INPUT VOLTAGE

Q/Q OUTPUT

Figure 15. Propagation Delay—Slew Rate Dispersion

− 1 V. Propagation delay dispersion is the

CCI

500mV OVERDRIVE

10mV OVERDRIVE

± V

V

N

OS

DISPERSION

05918-013

1V/ns

V

± V

N

10V/ns

DISPERSIO N

OS

05918-014

Preliminary Technical Data

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in
voltage approaches the threshold (0.0 V, in this example) from
below the threshold region in a positive direction, the
comparator switches from a low to a high when the input crosses
+V

/2. The new switching threshold becomes −VH/2. The

H

comparator remains in the high state until the threshold −V
is crossed from below the threshold region in a negative
direction. In this manner, noise or feedback output signals
centered on 0.0 V input cannot cause the comparator to switch
states unless it exceeds the region bounded by ±V

OUTPUT

V

V

OL

–V

H

2

Figure 16. Comparator Hysteresis Transfer Function

0

The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. One limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance, and can even
induce oscillation in some cases.

The ADCMP609 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND, varies the amount of hysteresis
in a predictable and stable manner. Leaving the LE/HYS pin
disconnected or driving it high removes the hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV.

Figure 17 illustrates the amount of
hysteresis applied as a function of external resistor value.
Figure TBD illustrates hysteresis as a function of current.

Figure 16. As the input

OH

INPUT

+V

H

2

H

/2.

/2

H

05918-015

Rev. PrA | Page 10 of 16

Preliminary Technical Data

The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7k ± 20% throughout the
hysterisis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability,
reduced component count, and maximum versatility. An
external bypass capacitor is not recommended on the HYS pin
because it would likely degrade the jitter performance of the
device and impair the latch function. As described in
Using/Disabling the Latch Feature, hysteresis control need not
compromise the latch function.

Figure 17. Hysteresis vs. R

Control Resistor

HYS

ADCMP608/ADCMP609

CROSSOVER BIAS POINT

Rail-to-rail inputs of this type, in both op amps and compara­tors have a dual front-end design. Certain devices are active
near the V
predetermined point in the common-mode range, a crossover
occurs. At this point, normally V
current reverses and there are changes in measured offset
voltages and currents.

With V
but with V
follows V
5 V. This means that the comparator input characteristics will
more closely resemble the inputs of non rail-to rail ground
sensing comparators such as the AD8611.

MINIMUM INPUT SLEW RATE REQUIREMENT

(Remove if device is stable.)

As with most high speed comparators, without hysteresis a
minimum slew rate must be met to ensure that the device does
not oscillate as the input signal crosses the threshold. This
oscillation is due to the high gain bandwidth of the comparator
in combination with feedback parasitics inherent in the package
and PC board. A minimum slew rate of TBD. V/µs ensures
clean output transitions from the ADCMP608/ADCMP609
comparators without hysteresis. In many applications,
chattering is not harmful.

rail and others are active near the VEE rail. At some

CC

/2, the direction of the bias

CC

less than 4 V, this crossover is at the expected VCC/2,

CC

greater than 4 V, the crossover point instead

CC

1:1, bringing it to approximately 3 V with VCC at

CC

Rev. PrA | Page 11 of 16

ADCMP608/ADCMP609

V

V

V

V

V

V

TYPICAL APPLICATION CIRCUITS

2.5V TO 5

0.1µF

INPUT

2kΩ

2kΩ

ADCMP608

0.1µF

Figure 18. Self-Biased 50% Slicer

OUTPUT

Preliminary Technical Data

2.5

CMOS

ADCMP608

INPUT

1.25V

±50mV

INPUT

1.25V
REF

10kΩ

10kΩ

ADCMP609

10kΩ

05918-017

220pF

LE/HYS

100kΩ

Figure 21. Oscillator and Pulse Width Modulator

5

PWM
OUTPUT

5918-020

100ΩLVDS

ADCMP608

Figure 19. LVDS to CMOS Receiver

5

39kΩ

ADCMP609

39kΩ

CONTROL

VOLTAGE

0V TO 2.5

470pF

Figure 20. Voltage Controlled Oscillator

20kΩ

LE/HYS

150kΩ150kΩ

CMOS
V

DD

2.5V TO 5V

OUTPUT

OUTPUT

INPUT

ADCMP609

V

REF

05918-018

0.1µF
LE/HYS

10kΩ

0.02µF

10kΩ

+

OUTPUT

–

05918-021

Figure 22. Duty Cycle to Differential Voltage

2.5V TO 5

ADCMP609

DIGITAL

INPUT

05918-019

HYSTERESIS

CURRENT

74AHC

1G07

10kΩ

LE/HYS

05918-022

Figure 23. DAC Hysteresis Adjustment with Latch

Rev. PrA | Page 12 of 16

Preliminary Technical Data

ADCMP608/ADCMP609

TIMING INFORMATION

Figure 24 illustrates the ADCMP608/ADCMP609 latch timing relationships. Tab le 6 provides definitions of the terms found in the figure.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

R

t

PL

t

F

Figure 24. System Timing Diagram

Table 6. Timing Descriptions

Symbol Timing Description

t

PDH

Input to output high
delay

t

PDL

Input to output low
delay

t

PLOH

Latch enable to output
high delay

t

PLOL

Latch enable to output
low delay

tH Minimum hold time

Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output low-to-high transition.

Propagation delay measured from the time the input signal crosses the reference (± the input offset
voltage) to the 50% point of an output high-to-low transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to
the 50% point of an output low-to-high transition.

Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to
the 50% point of an output high-to-low transition.

Minimum time after the negative transition of the latch enable signal that the input signal must
remain unchanged to be acquired and held at the outputs.

tPL

Minimum latch enable

Minimum time that the latch enable signal must be high to acquire an input signal change.

pulse width

tS Minimum setup time

Minimum time before the negative transition of the latch enable signal occurs that an input signal
change must be present to be acquired and held at the outputs.

tR Output rise time

Amount of time required to transition from a low to a high output as measured at the 20% and 80%
points.

tF Output fall time

Amount of time required to transition from a high to a low output as measured at the 20% and 80%
points.

VOD Voltage overdrive Difference between the input voltages VA and VB.

t

PLOH

t

PLOL

V

N

50%

50%

± V

OS

05918-023

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ADCMP608/ACMP609 Preliminary Technical Data

NOTES

Rev. PrA | Page 14 of 16

Preliminary Technical Data

NOTES

ADCMP608/ADCMP609

Rev. PrA | Page 15 of 16

ADCMP608/ACMP609 Preliminary Technical Data

NOTES

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PR05918-0-2/06(PrA)

Rev. PrA | Page 16 of 16