ANALOG DEVICES ADCMP606 Service Manual

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

FEATURES

Fully specified rail to rail at V
Input common-mode voltage from −0.2 V to V
CML-compatible output stage

1.25 ns propagation delay
50 mW @ 2.5 V power supply
Shutdown pin
Single-pin control for programmable hysteresis and latch

(ADCMP607 only)

Power supply rejection > 60 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

= 2.5 V to 5.5 V

CCI

+ 0.2 V

CCI

Single-Supply CML Comparators

ADCMP606/ADCMP607

GENERAL DESCRIPTION

The ADCMP606 and ADCMP607 are very fast comparators
fabricated on XFCB2, an Analog Devices, Inc., proprietary
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from V
V

+ 0.2 V, low noise, CML-compatible output drivers, and

CCI

TTL-/CMOS-compatible latch inputs with adjustable hysteresis
and/or shutdown inputs.

The devices offer 1.25 ns propagation delay with 2.5 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.

A flexible power supply scheme allows the devices to operate
with a single +2.5 V positive supply and a −0.5 V to +2.7 V
input signal range up to a +5.5 V positive supply with a −0.5 V
to +5.7 V input signal range. The ADCMP607 features split
input/output supplies with no sequencing restrictions to
support a wide input signal range with independent output
swing control and power savings.

The CML-compatible output stage is fully back-matched for
superior performance. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. On
the ADCMP607, latch and programmable hysteresis features are
also provided with a unique single-pin control option.

The ADCMP606 is available in a 6-lead SC70 package and the
ADCMP607 is available in a 12-lead LFCSP package.

− 0.5 V to

EE

FUNCTIONAL BLOCK DIAGRAM

NONINVERTING

P

V

N

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

INVERTING

INPUT

INPUT

ADCMP606/

ADCMP607

V

CCI

Figure 1.

CCO

(ADCMP607 ONLY )

CML

LE/HYS I NPUT (ADCMP 607 ONLY)

S

INPUT (ADCMP607 O NLY)

DN

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

Q OUTPUT

Q OUTPUT

05917-001

ADCMP606/ADCMP607

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics ............................................................. 3

Timing Information..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 8

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Changes to Specifications Section.................................................. 3

Changes to Table 3............................................................................ 6

Changes to Ordering Guide.......................................................... 14

10/06—Revision 0: Initial Version

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

CML-Compatible Output Stage ............................................... 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 10

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Points................................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Application Circuits ......................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP606/ADCMP607

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, VN V
Common-Mode Range V
Differential Voltage V
Offset Voltage VOS −5.0 +5.0 mV
Bias Current IP, IN −5.0 ±2 +5.0 µA
Offset Current −2.0 2.0 µA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.1 V to V
Resistance, Common Mode −0.5 V to V
Active Gain AV 85 dB

Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS

(ADCMP607 Only)
VIH Hysteresis is shut off 2.0 V
VIL Latch mode guaranteed −0.2 +0.4 +0.8 V
IIH V
IIL V

HYSTERESIS MODE AND TIMING

Hysteresis Mode Bias Voltage Current sink 0 A 1.145 1.25 1.35 V
Minimum Resistor Value Hysteresis = 120 mV 55 75 110 kΩ
Latch Setup Time tS V
Latch Hold Time tH V
Latch-to-Output Delay t
Latch Minimum Pulse Width tPL V

SHUTDOWN PIN CHARACTERISTICS

(ADCMP607 Only)
VIH Comparator is operating 2.0 V
VIL Shutdown guaranteed −0.2 +0.4 +0.6 V
IIH V
IIL V
Sleep Time tSD 10% output swing <1 ns
Wake-Up Time tH V

DC OUTPUT CHARACTERISTICS V

Output Voltage High Level VOH 50 Ω terminate to V
Output Voltage Low Level VOL 50 Ω terminate to V
Output Voltage Differential 50 Ω terminate to V

= 2.5 V, TA = −40°C to +125°C, typical at TA = 25°C, unless otherwise noted.

CCO

= 2.5 V to 5.5 V −0.5 V

CCI

= 2.5 V to 5.5 V −0.2 V

CCI

= 2.5 V to 5.5 V V

CCI

200 700 kΩ

CCI

+ 0.5 V 100 350 kΩ

CCI

V

= 2.5 V, V

CCI

V

= −0.2 V to +2.7 V

CM

= 2..5 V, V

V

CCI

= ∞ <0.1 mV

HYS

= 2.5 V,

CCO

= 5.5 V 50 dB

CCO

= V

−6 +6 µA

IH

CCO

= 0.4 V −0.1 +0.1 mA

IL

= 50 mV −1.5 ns

OD

= 50 mV 2.3 ns

OD

, t

PLOH

VOD = 50 mV 30 ns

PLOL

= 50 mV 25 ns

OD

= V

−6 +6 µA

IH

CCO

= 0 V −0.1 mA

IL

= 100 mV, output valid 35 ns

OD

= 2.5 V to 5.5 V

CCO

+ 0.2 V

CCI

+ 0.2 V

CCI

V

CCI

50 dB Common-Mode Rejection Ratio CMRR

V

CCO

V

CCO

V

CCO

V

CCO

300 400 500 mV

CCO

− 0.1 V

CCO

− 0.6 V

CCO

− 0.05 V

CCO

− 0.45 V

CCO

V

CCO

− 0.3 V

CCO

Rev. A | Page 3 of 16

ADCMP606/ADCMP607

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time/Fall time tR/tF

Propagation Delay tPD

Propagation Delay Skew—Rising to

Falling Transition
Overdrive Dispersion 10 mV < VOD < 125 mV 2.3 ns
Common-Mode Dispersion −0.2 V < VCM < VCC + 0.2 V 150 ps
Input Stage Bandwidth 750 MHz
RMS Random Jitter RJ VOD = 200 mV, 0.5 V/ns 2 ps
Minimum Pulse Width PW

Output Skew Q to Q

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential (ADCMP607) V
V
Positive Supply Current (ADCMP606) I
V
Input Section Supply Current (ADCMP607) I
Output Section Supply Current (ADCMP607) I
I
Power Dissipation PD V
P
Power Supply Rejection Ratio PSRR V
Shutdown Mode I
Shutdown Mode I

1

VIN = 100 mV square input at 50 MHz, VCM = 2.5 V, V

1

10% to 90%,

= V

V

CCI

V

CCI

V

OD

V

CCI

V

OD

T

PINSKEW

MIN

VOD = 50 mV 40 ps

V

CCI

PW

T

DIFFSKEW

2.5 5.5 V

CCI

2.5 5.5 V

CCO

− V

CCI

− V

CCI

VCCI/V CCO

V

VCCI

V

VCCO

V

VCCO

V

D

V

CCI

V

CCO

= V

= 2.5 V, unless otherwise noted.

CCI

CCO

50%

Operating −3.0 +3.0 V

CCO

Nonoperating −6 +6 V

CCO

V

CCI

CCI

CCI

CCO

CCO

CCI

CCI

CCI

CCI

CCI

= 2.5 V to 5.5 V

CCO

= V

= 2.5 V to 5.5 V,

CCO

= 50 mV
= V

= 2.5 V,

CCO

= 10 mV

= V

= 5.5 V,

CCO

= 90% of PWIN

OUT

= V

= 2.5 V 11 17.5 21 mA

CCO

= V

= 5.5 V 16 20.5 26 mA

CCO

= 2.5 V 0.5 1.1 1.5 mA

= 2.5 V 10 15.8 18 mA
= 5.5 V 16 18 25 mA

= V

= 2.5 V 30 46 55 mW

CCO

= V

= 5.5 V 90 110 150 mW

CCO

= 2.5 V to 5 V −50 dB
= V

= 2.5 V to 5 V 200 240 800 µA

CCO

= V

= 2.5 V to 5 V −30 30 µA

CCO

160 ps

1.2 ns

2.1 ns

1.1 ns

20 ps

Rev. A | Page 4 of 16

ADCMP606/ADCMP607

TIMING INFORMATION

Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Tabl e 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

DIFFERENTIAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

t

S

t

H

V

IN

V

OD

t

PDL

t

PDH

t

t

R

t

PL

t

PLOH

F

t

PLOL

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

tF Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.

tH Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.

t

Input to output high delay

PDH

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

t

Input to output low delay

PDL

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

tPL Minimum latch enable pulse width

Minimum time that the latch enable signal must be high to acquire an input signal
change.

t

Latch enable to output high delay

PLOH

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t

Latch enable to output low delay

PLOL

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

tR Output rise time

Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.

tS Minimum setup time

Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.

VOD Voltage overdrive Difference between the input voltages VA and VB.

V

50%

50%

± V

N

OS

05917-025

Rev. A | Page 5 of 16