Datasheet ADCMP604 Datasheet (ANALOG DEVICES)

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

FEATURES

Fully specified rail to rail at V
Input common-mode voltage from −0.2 V to V
Low glitch LVDS-compatible output stage

1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

= 2.5 V to 5.5 V

CCI

+ 0.2 V

CCI

Single-Supply LVDS Comparators

ADCMP604/ADCMP605

FUNCTIONAL BLOCK DIAGRAM

CCO

(ADCMP605 ONLY)

LVDS

DN

INPUT

(ADCMP605

Q OUTPUT

Q OUTPUT

ONLY)

NONINVERTING

P

V

INVERTING

N

INPUT

INPUT

V

CCI

ADCMP604/

ADCMP605

Figure 1.

LE/HYS INPUT

S

05916-001

GENERAL DESCRIPTION

The ADCMP604/ADCMP605 are very fast comparators
fabricated on the Analog Devices, Inc. proprietary XFCB2
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from V

0.2 V, low noise, LVDS-compatible output drivers, and
TTL/CMOS latch inputs with adjustable hysteresis and/or shut­down inputs.

The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

− 0.5 V to V

EE

CCI

+

A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions on the ADCMP605, support a wide input signal
range with greatly reduced power consumption.

The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.

The ADCMP604 is available in a 6-lead SC70 package, and the
ADCMP605 is available in a 12-lead LFCSP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADCMP604/ADCMP605

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Information ......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics .............................................8

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Changes to Features and General Description ............................. 1

Changes to Electrical Characteristics Section .............................. 3

Changes to Table 3............................................................................ 6

Changes to Layout............................................................................ 7

Changes to Figure 8.......................................................................... 8

Changes to Figure 14........................................................................ 9

Changes to Power/Ground Layout and Bypassing Section, and

Using/Disabling the Latch Feature Section................................. 10

Changes to Comparator Hysteresis Section................................ 11

Changes to Crossover Bias Points Section ..................................12

Changes to Ordering Guide.......................................................... 14

10/06—Revision 0: Initial Version

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

LVDS-Compatible Output Stage .............................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 10

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Points................................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Applicat i o n C i rc uits ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP604/ADCMP605

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, V
Common-Mode Range V
Differential Voltage V
Offset Voltage V
Bias Current IP, I
Offset Current −2.0 +2.0 μA
Capacitance CP, C
Resistance, Differential Mode −0.1 V to V
Resistance, Common Mode −0.5 V to V
Active Gain A
Common-Mode Rejection Ratio CMRR

V
Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS (ADCMP605 ONLY )

V
V
I

IH

I

IL

HYSTERESIS MODE AND TIMING (ADCMP605 ONLY)

Hysteresis Mode Bias Voltage Current sink −1 μA 1.145 1.25 1.40 V
Minimum Resistor Value Hysteresis = 120 mV 30 110 kΩ
Hysteresis Current Hysteresis = 120 mV −25 −8 μA
Latch Setup Time t
Latch Hold Time t
Latch-to-Output Delay t
Latch Minimum Pulse Width t

SHUTDOWN PIN CHARACTERISTICS (ADCMP605 ONLY)

V
V
I

IH

I

IL

Sleep Time t

Wake-Up Time t
DC OUTPUT CHARACTERISTICS V
V

Differential Output Voltage Level V

ΔV

Common-Mode Voltage V

Peak-to-Peak Common-Mode Output V

= 2.5 V, TA = −40°C to +125°C, typical at TA = 25 °C, unless otherwise noted.

CCO

V

N

OS

N

N

V

IH

IL

Hysteresis is shut off 2.0 V
Latch mode guaranteed −0.2 +0.4 +0.8 V
V
V

S

H

, t

PLOH

PLOLVOD

PL

IH

IL

Comparator is operating 2.0 V
Shutdown guaranteed −0.2 +0.4 +0.6 V
V
V

SD

H

OD

OD

R

OCI

OC (p-p)

= 2.5 V to 5.5 V −0.5 V

CCI

= 2.5 V to 5.5 V −0.2 V

CCI

= 2.5 V to 5.5 V V

CCI

−5.0 +5.0 mV

−5.0 ±2 +5.0 μA

1 pF

62 dB

= 2.5 V, V

V

CCI

V

= −0.2 V to +2.7 V

CM

= 2.5 V, V

CCI

= ∞ <0.1 mV

HYS

= V

IH

= 0.4 V −0.1 +0.1 mA

IL

VOD = 50 mV −2 ns
VOD = 50 mV 2.7 ns

= 50 mV 20 ns

VOD = 50 mV 24 ns

= V

IH

= 0 V −0.1 mA

IL

10% output swing 1.4 ns
VOD = 50 mV, output valid 25 ns

= V

CCI

= 2.5 V to 5.0 V (ADCMP605)

CCO

R

LOAD

LOAD

R

LOAD

R

LOAD

+ 0.2 V

CCI

+ 0.2 V

CCI

CCI

CCI

+ 0.5 V 100 370 4000 kΩ

CCI

= 2.5 V,

CCO

= 5.0 V 50 dB

CCO

+ 0.2 V −6 +6 μA

CCO

−6 +6 μA

CCO

= 2.5 V to 5.0 V (ADCMP604)

CCO

200 750 7500 kΩ

50 dB

CCO

CCO

V

V

V

= 100 Ω 245 350 445 mV
= 100 Ω 50 mV
= 100 Ω 1.125 1.375 V
= 100 Ω 50 mV

Rev. A | Page 3 of 16

ADCMP604/ADCMP605

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time/Fall Time tR, t
Propagation Delay t

V
Propagation Delay Skew—Rising to Falling Transition t
Propagation Delay Skew—Q to QB V
Overdrive Dispersion 10 mV < VOD < 125 mV 1.6 ns
Common-Mode Dispersion VCM = −0.2 V to V
Input Bandwidth 500 MHz
Minimum Pulse Width PW

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential (ADCMP605) V
V
Positive Supply Current (ADCMP604) I
Input Section Supply Current (ADCMP605) I
Output Section Supply Current (ADCMP605) I
Power Dissipation P
V
Power Supply Rejection Ratio PSRR V
Shutdown Mode I
Shutdown Mode I

1

VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, V

1

V

CCI

CCO

F

PD

PINSKEW

MIN

CCI

CCO

− V

CCI

− V

CCI

VCCI/V CCO

VCCI

VCCO

D

V

= V

CCI

CCO

10% to 90% 600 ps
V

= V

CCI

= 50 mV

V

OD

= V

CCI

V

= V

CCI

= V

CCI

V

= V

CCI

PW

OUT

= 2.5 V to 5.0 V,

CCO

= 2.5 V, VOD = 10 mV 3.0 ns

CCO

= 2.5 V to 5.0 V 70 ps

CCO

= 2.5 V to 5.0 V 70 ps

CCO

+ 0.2 V 250 ps

CCI

= 2.5 V to 5.0 V,

CCO

= 90% of PW

IN

1.6 ns

1.3 ns

2.5 5.5 V

2.5 5.0 V
Operating −3 +3 V

CCO

Nonoperating −5.0 +5.0 V

CCO

V

= V

CCI

V

CCI

V

CCO

V

CCI

CCI

CCI

CCI

CCI

= 2.5 V, unless otherwise noted.

= 2.5 V to 5.0 V 15 21 mA

CCO

= 2.5 V to 5.5 V 1.6 3.0 mA

= 2.5 V to 5.0 V 15 23 mA

= V

= 2.5 V 37 55 mW

CCO

= V

= 5.0 V 95 120 mW

CCO

= V

= 2.5 V to 5.0 V −50 dB

CCO

= V

= 2.5 V to 5.0 V 0.92 1.1 mA

CCO

= V

= 2.5 V to 5.0 V −30 +30 μA

CCO

Rev. A | Page 4 of 16

ADCMP604/ADCMP605

TIMING INFORMATION

Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Tabl e 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

t

S

V

DIFFERENT IAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

IN

V

OD

t

PDL

t

PDH

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

PDH

Input-to-Output High Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

t

PDL

Input-to-Output Low Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t

PLOH

Latch Enable-to-Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t

PLOL

Latch Enable-to-Output Low Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

t

H

Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.

t

PL

t

S

Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum Setup Time

Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.

t

R

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.

t

F

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.

V

OD

Voltage Overdrive Difference between the input voltages, VA and VB. B

t

PL

t

H

± V

V

N

OS

t

PLOH

50%

t

F

50%

t

PLOL

t

R

05916-025

Rev. A | Page 5 of 16

ADCMP604/ADCMP605

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

Supply Voltages

Input Supply Voltage (V
Output Supply Voltage (V
Positive Supply Differential (V

to GND) −0.5 V to +6.0 V

CCI

to GND) −0.5 V to +6.0 V

CCO

− V

CCI

) −6.0 V to +6.0 V

CCO

Input Voltages

Input Voltage −0.5 V to V
Differential Input Voltage ±(V

CCI

CCI

+ 0.5 V)

+ 0.5 V

Maximum Input/Output Current ±50 mA

Shutdown Control Pin

Applied Voltage (SDN to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA

Latch/Hysteresis Control Pin

Applied Voltage (HYS to GND) −0.5 V to V

+ 0.5 V

CCO

Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature

Operating Temperature Range, Ambient −40°C to +125°C

Operating Temperature, Junction 150°C

Storage Temperature Range −65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

1

JA

Unit

6-Lead SC70 (KS-6) 426 °C/W
12-Lead LFCSP_VQ (CP-12-1) 62 °C/W

1

Measurement in still air.

ESD CAUTION

Rev. A | Page 6 of 16

ADCMP604/ADCMP605

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

Q

ADCMP604

2

TOP VIEW

EE

(Not to Scale)

3

V

P

Figure 3. ADCMP604 Pin Configuration

Table 5. ADCMP604 Pin Function Descriptions (6-Lead SC70)

Pin No. Mnemonic Description

1 Q

2 V
3 V
4 V
5 V
6

EE

P

N

CCI/VCCO

Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog

Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, V
analog voltage at the inverting input, V

N

Negative Supply Voltage.
Noninverting Analog Input.
Inverting Analog Input.
Input Section Supply/Output Section Supply. V

voltage at the inverting input, VN.

V

1

CCO

CCI

V

EE

ADCMP605

2

3

TOP VIEW

(Not to Scale)

V

.

12 Q

11 VEE10 Q

PIN 1
INDICATOR

6

5

4

CCI

Q

V

CCI/VCCO

V

N

and V

9 V

8 LE/HYS

7 S

05916-002

are shared pin.

CCO

EE

DN

, is greater than the

P

4

5

6

P

N

EE

V

V

V

05916-003

Figure 4. ADCMP605 Pin Configuration

Table 6. ADCMP605 Pin Function Descriptions (12-Lead LFCSP_VQ)

Pin No. Mnemonic Description

1 V
2 V
3, 5, 9, 11 V
4 V
6 V
7 S

CCO

CCI

EE

P

N

DN

Output Section Supply.
Input Section Supply.
Negative Supply Voltages.
Noninverting Analog Input.
Inverting Analog Input.

Shutdown. Drive this pin low to shut down the device.
8 LE/HYS Latch/Hysteresis Control. Bias with resistor or current for hysteresis; drive low to latch.
10

Q Inverting Output. Q is at Logic low if the analog voltage at the noninverting input, VP, is greater than

the analog voltage at the inverting input, VN, if the comparator is in compare mode.
12 Q

Heat Sink Paddle V

EE

Noninverting Output. Q is at Logic high if the analog voltage at the noninverting input, V

than the analog voltage at the inverting input, V

, if the comparator is in compare mode.

N

The metallic back surface of the package is electrically connected to VEE. It can be left floating

because Pin 3, Pin 5, Pin 9, and Pin 11 provide adequate electrical connection. It can also be

soldered to the application board if improved thermal and/or mechanical stability is desired.

, is greater

P

Rev. A | Page 7 of 16

ADCMP604/ADCMP605

TYPICAL PERFORMANCE CHARACTERISTICS

V

= V

CCI

= 2.5 V, TA = 25°C, unless otherwise noted.

CCO

800

1.60

600

400

200

0

–200

CURRENT (µA)

–400

–600

–800

–1012345 6 7

LE/HYS PIN (V)

VCC = 5.5VVCC = 2.5V

Figure 5. LE/HYS Pin Current vs. Voltage

200

150

100

VCC = 5.5VVCC = 2.5V

50

0

CURRENT (µA)

–50

–100

–150

–1 0 1 2 3 4 5 6 7

Figure 6. S

SDN PIN (V)

Pin Current vs. Voltage

DN

10

8

6

4

2

0

(µA)

B

I

–2

–4

–6

–8

–10

–1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

AT VCC = 2.5V

V

CM

+125°C

+25°C

–40°C

Figure 7. Input Bias Current vs. Input Common-Mode Voltage

1.50

1.40

1.30

1.20

OUTPUT (V)

1.10

1.00

0.90

05916-010

2.9 3.9 4.9 5.9

2.4 3.4 4.4 5.4

Figure 8. LVDS Output Level vs. V

850

800

750

700

650

600

RISE/ FALL (ps)

550

500

450

400

2.40 2.80 3.20 3.60 4.00 4.40 4. 80 5.20 5.60 6.00

05916-006

05916-009

Figure 9. LVDS Output Rise/Fall Time vs. V

250

200

150

100

HYSTERESIS (mV)

50

0

50 100 150 200 250 300 350 400 450 500

VCC = 2.5V

VCC = 5.5V

HYSTERESIS RESISTOR (kΩ)

Figure 10. Hysteresis vs. Hysteresis Resistor

OUTPUT HI

OUTPUT V

OUTPUT LO

V

(V)

CCO

+125°C

+25°C

–40°C

V

(V)

CCO

CM

05916-011

(V)

CCO

05916-007

(V)

CCO

05916-008

Rev. A | Page 8 of 16

ADCMP604/ADCMP605

350

300

+125°C

0.44

0.43

250

200

150

HYSTERESIS (mV)

100

50

0

HYS PIN CURRENT (µ A)

+25°C

–40°C

–18–16–14–12–10–8–6–4–20

05916-012

Figure 11. Hysteresis vs. HYS Pin Current

0.42

0.41

0.40

0.39

OUTPUT SWING (V)

0.38

0.37

0.36

2.4 3.4 4.4 5.4
V

(V)

CCO

Figure 14. LVDS Output Swing vs. V

CCO

(V)

05916-013

3.5

3.0

2.5

2.0

PROPAGATION DELAY (n s)

1.5

PROPAGATION

DELAY

1.425V
Q

Q

1.0
0 1020304050607080 90100

OVERDRIVE (mV)

Figure 12. Propagation Delay vs. Input Overdrive

1.6

PROPAGATI ON
DELAY RISE ns

1.5

PROPAGATI ON

DELAY (ns)

1.4

1.3
–0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0

DELAY FALL ns

VCM AT VCC (2.5V)

Figure 13. Propagation Delay vs. Input Common-Mode Voltage

925.0mV 1.000ns/DI V

05916-004

Figure 15. 50 MHz Output Voltage Waveform at V

CCO

= 2.5 V

05916-014

1.543V

1.043V 1.000n s/DIV

05916-005

Figure 16. 50 MHz Output Voltage Waveform at V

Q

Q

05916-015

= 5.5 V

CCO

Rev. A | Page 9 of 16

ADCMP604/ADCMP605

APPLICATION INFORMATION

POWER/GROUND LAYOUT AND BYPASSING

The ADCMP604/ADCMP605 comparators are very high speed
devices. Despite the low noise output stage, it is essential to use
proper high speed design techniques to achieve the specified
performance. Because comparators are uncompensated amplifiers,
feedback in any phase relationship is likely to cause oscillations
or undesired hysteresis. The use of low impedance supply
planes is of critical importance particularly the output supply
plane (V
planes are recommended as part of a multilayer board.
Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.

It is also important to adequately bypass the input and output
supplies. Multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the V
pins and should be connected to the GND plane with redundant
vias. At least one of these should be placed to provide a physically
short return path for output currents flowing back from ground
to the V
should be carefully selected for minimum inductance and ESR.
Parasitic layout inductance should also be strictly controlled to
maximize the effectiveness of the bypass at high frequencies.

If the package allows, and the input and output supplies have
been connected separately (V
of these supplies separately to the GND plane. Do not connect a
bypass capacitor between these supplies. It is recommended that
the GND plane separate the V
circuit board layout is designed to minimize coupling between
the two supplies to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output supplies
are used. If the input and output supplies are connected together
for single-supply operation (V
two supplies is unavoidable; however, careful board placement
can help keep output return currents away from the inputs.

) and the ground plane (GND). Individual supply

CCO

and V

CCI

pin and the V

CCI

pin. High frequency bypass capacitors

CCO

≠ V

CCI

CCI

CCI

), be sure to bypass each

CCO

and V

= V

planes when the

CCO

), coupling between the

CCO

CCO

supply

LVDS-COMPATIBLE OUTPUT STAGE

Specified propagation delay dispersion performance is only
achieved by keeping parasitic capacitive loads at or below the
specified minimums. The outputs of the ADCMP604 and
ADCMP605 are designed to directly drive any standard LVDS­compatible input.

USING/DISABLING THE LATCH FEATURE

The latch input is designed for maximum versatility. It can
safely be left floating or it can be driven low by any standard
TTL/CMOS device as a high speed latch. In addition, the pin
can be operated as a hysteresis control pin with a bias voltage of

1.25 V nominal and an input resistance of approximately
70 kΩ. This allows the comparator hysteresis to be easily
controlled by either a resistor or an inexpensive CMOS DAC.
Driving this pin high or floating the pin disables all hysteresis.

Hysteresis control and latch mode can be used together if an
open drain, an open collector, or a three-state driver is connected in
parallel to the hysteresis control resistor or current source.

Due to the programmable hysteresis feature, the logic threshold
of the latch pin is approximately 1.1 V, regardless of V

CCO

.

OPTIMIZING PERFORMANCE

As with any high speed comparator, proper design and layout
techniques are essential for obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit performance
and often cause oscillation. Large discontinuities along input
and output transmission lines can also limit the specified pulse­width dispersion performance. The source impedance should
be minimized as much as is practicable. High source impedance,
in combination with the parasitic input capacitance of the
comparator, causes an undesirable degradation in bandwidth at
the input, thus degrading the overall response. Thermal noise
from large resistances can easily cause extra jitter with slowly
slewing input signals. Higher impedances encourage undesired
coupling.

Rev. A | Page 10 of 16

ADCMP604/ADCMP605

COMPARATOR PROPAGATION DELAY DISPERSION

The ADCMP604/ADCMP605 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to V
variation in propagation delay that results from a change in the
degree of overdrive or slew rate (how far or how fast the input
signal is driven past the switching threshold).

Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications, such as data
communications, automatic test and measurement, and instru­mentation. It is also important in event-driven applications, such
as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
delay as the input overdrive conditions are changed (see
and

Figure 18).

The ADCMP604/ADCMP605 dispersion is typically <1.6 ns as
the overdrive varies from 10 mV to 125 mV. This specification
applies to both positive and negative signals because each of
the ADCMP604 and ADCMP605 has substantially equal delays
for positive-going and negative-going inputs and very low
output skews.

− 1 V. Propagation delay dispersion is the

CCI

Figure 17

500mV OVERDRIVE

COMPARATOR HYSTERESIS

The addition of hysteresis to a comparator is often desirable in a
noisy environment, or when the differential input amplitudes
are relatively small or slow moving. The transfer function for a
comparator with hysteresis is shown in
voltage approaches the threshold (0 V, in this example) from
below the threshold region in a positive direction, the comparator
switches from low to high when the input crosses +V
new switching threshold becomes −V
in the high state until the threshold, −V
below the threshold region in a negative direction. In this manner,
noise or feedback output signals centered on 0 V input cannot
cause the comparator to switch states unless it exceeds the region
bounded by ±V

H

/2.

OUTPUT

V

V

OL

Figure 19. As the input

/2. The comparator remains

H

/2, is crossed from

H

OH

/2. The

H

INPUT VOLTAGE

10mV OVERDRIVE

± V

V

N

–V

2

Figure 19. Comparator Hysteresis Transfer Function

OS

The customary technique for introducing hysteresis into a

0V

H

INPUT

+V

H

2

05916-018

comparator uses positive feedback from the output back to
the input. One limitation of this approach is that the amount

DISPERSION

Q/Q OUTPUT

Figure 17. Propagation Delay—Overdrive Dispersion

05916-016

INPUT VOLTAGE

10V/ns

1V/ns

V

± V

N

OS

of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and induce
oscillation in some cases.

The ADCMP605 comparator offers a programmable hysteresis
feature that significantly improves accuracy and stability.
Connecting an external pull-down resistor or a current source
from the LE/HYS pin to GND varies the amount of hysteresis
in a predictable and stable manner. Leaving the LE/HYS
pin disconnected or driving it high removes hysteresis. The

DISPERSIO N

Q/Q OUTPUT

Figure 18. Propagation Delay—Slew Rate Dispersion

05916-017

maximum hysteresis that can be applied using this pin is
approximately 160 mV.
hysteresis applied as a function of external resistor value.

Figure 20 illustrates the amount of

Figure 11

illustrates hysteresis as a function of current.

Rev. A | Page 11 of 16

ADCMP604/ADCMP605

The hysteresis control pin appears as a 1.25 V bias voltage
seen through a series resistance of 70 kΩ ± 20% throughout the
hysteresis control range. The advantages of applying hysteresis
in this manner are improved accuracy, improved stability, reduced
component count, and maximum versatility. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device and impair the
latch function. As described in the
Feature

section, hysteresis control need not compromise the

Using/Disabling the Latch

latch function.

250

200

150

100

HYSTERESIS (mV)

50

0

50 100 150 200 250 300 350 400 450 500

VCC = 2.5V

VCC = 5.5V

HYSTERESIS RESISTOR (kΩ)

Figure 20. Hysteresis vs. R

Control Resistor

HYS

05916-026

CROSSOVER BIAS POINTS

Rail-to-rail inputs of this type, in both op amps and comparators,
have a dual front-end design. Certain devices are active near
the V

rail and others are active near the VEE rail. At some pre-

CCI

determined point in the common-mode range, a crossover
occurs. At this point, normally V

/2, the direction of the bias

CCI

current reverses and there are changes in measured offset
voltages and currents.

MINIMUM INPUT SLEW RATE REQUIREMENT

With the rated load capacitance and normal good PCB design
practice, as discussed in the
these comparators should be stable at any input slew rate with
no hysteresis. Broadband noise from the input stage is observed
in place of the violent chattering seen with most other high
speed comparators. With additional capacitive loading or poor
bypassing, oscillation is observed. This oscillation is due to the
high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PCB. In many applications,
chattering is not harmful.

Optimizing Performance section,

Rev. A | Page 12 of 16

ADCMP604/ADCMP605

V

V

V

V

V

V

V

V

TYPICAL APPLICATION CIRCUITS

2.5V TO 5

0.1µF

2.5

INPUT

DIGITAL

INPUT

2kΩ

2kΩ

ADCMP604

0.1µF

Figure 21. Self-Biased, 50% Slicer

2.5V TO 3. 3

100ΩLVDS LVDS

ADCMP604

Figure 22. LVDS to Repeater

2.5V TO 5

ADCMP605

74VHC

1G07

150kΩ

LE/HYS

CMOS
OUTPUT

LVDS

ADCMP604

INPUT

05916-019

1.25V

±50m

INPUT

1.25V
REF

10kΩ

10kΩ

PWM
OUTPUT

ADCMP601

10kΩ

05916-020

82pF

LE/HYS

100kΩ

05916-023

Figure 25. Oscillator and Pulse-Width Modulator

2.5V TO 5

ADCMP605

DIGITAL

INPUT

74AHC

1G07

LE/HYS

CONTROL
VOLTAGE

0V TO 2.5V

150kΩ

Figure 23. Hysteresis Adjustment with Latch

2.5

10kΩ

82pF

ADCMP605

LE/HYS

CONTROL
VOLTAGE

0V TO 2.5

150kΩ

10kΩ

150kΩ

LVDS
OUTPUT

05916-021

05916-022

HYSTERESIS

CURRENT

10kΩ

Figure 26. Hysteresis Adjustment with Latch

05916-024

Figure 24. Voltage-Controlled Oscillator

Rev. A | Page 13 of 16

ADCMP604/ADCMP605

OUTLINE DIMENSIONS

2.20

2.00

1.80

2.40

1.35

1.25

1.15

PIN 1

1.30 BSC

1.00

0.90

0.70

0.10 MAX

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 27. 6-Lead Thin Shrink Small Outline Transistor Package (SC70)

3.00

BSC SQ

PIN 1

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

12° MAX

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

*

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1

EXCEPT FO R EXPOSED PAD DI MENSION.

Figure 28. 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ)

4 5 6

2.10

3 2 1

1.80

0.65 BSC

0.40

0.10

0.22

0.08

0.30

0.15

1.10

0.80

SEATING
PLANE

(KS-6)

Dimensions shown in millimeters

0.60 MAX

10

9

8

7

6

0.50

BSC

COPLANARITY

0.08

2.75

BSC SQ

0.20 REF

0.45

EXPOSED PAD

(BOTTOM VIEW )

0.05 MAX

0.02 NOM

3 mm × 3 mm Body, Very Thin Quad

(CP-12-1)

Dimensions shown in millimeters

0.46

0.36

0.26

0.75

0.55

0.35

11

12

1

2

3

5

4

PIN 1
INDICATOR

*

1.45

1.30 SQ

1.15

0.25 MIN

ORDERING GUIDE

Package

Model Temperature Range Package Description

ADCMP604BKSZ-R2

1

−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 G0Q
ADCMP604BKSZ-REEL71−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 G0Q
ADCMP604BKSZ-RL
ADCMP605BCPZ-WP
ADCMP605BCPZ-R2
ADCMP605BCPZ-R7
EVAL-ADCMP605BCPZ

1

Z = RoHS Compliant Part.

1

1

1

−40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package (SC70) KS-6 G0Q

1

−40°C to +125°C 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-12-1 G0K

−40°C to +125°C 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-12-1 G0K

−40°C to +125°C 12-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-12-1 G0K

1

Evaluation Board

Rev. A | Page 14 of 16

Option

Branding

ADCMP604/ADCMP605

NOTES

Rev. A | Page 15 of 16

ADCMP604/ADCMP605

NOTES

©2006–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05916-0-8/07(A)

T

Rev. A | Page 16 of 16

TTT