ANALOG DEVICES ADCMP604 Service Manual

Rail-to-Rail, Very Fast, 2.5 V to 5.5 V,

V

V

FEATURES

Fully specified rail to rail at V
Input common-mode voltage from −0.2 V to V
Low glitch LVDS-compatible output stage

1.6 ns propagation delay
37 mW at 2.5 V
Shutdown pin
Single-pin control for programmable hysteresis and latch
Power supply rejection > 60 dB

−40°C to +125°C operation

APPLICATIONS

High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
Pulse spectroscopy
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators
Automatic test equipment (ATE)

= 2.5 V to 5.5 V

CCI

+ 0.2 V

CCI

Single-Supply LVDS Comparators

ADCMP604/ADCMP605

FUNCTIONAL BLOCK DIAGRAM

CCO

(ADCMP605 ONLY)

LVDS

DN

INPUT

(ADCMP605

Q OUTPUT

Q OUTPUT

ONLY)

NONINVERTING

P

V

INVERTING

N

INPUT

INPUT

V

CCI

ADCMP604/

ADCMP605

Figure 1.

LE/HYS INPUT

S

05916-001

GENERAL DESCRIPTION

The ADCMP604/ADCMP605 are very fast comparators
fabricated on the Analog Devices, Inc. proprietary XFCB2
process. These comparators are exceptionally versatile and easy
to use. Features include an input range from V

0.2 V, low noise, LVDS-compatible output drivers, and
TTL/CMOS latch inputs with adjustable hysteresis and/or shut­down inputs.

The devices offer 1.5 ns propagation delays with 1 ps rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 50 ps.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

− 0.5 V to V

EE

CCI

+

A flexible power supply scheme allows the devices to operate
with a single 2.5 V positive supply and a −0.5 V to +2.7 V input
signal range up to a 5.5 V positive supply with a −0.5 V to +5.7 V
input signal range. Split input/output supplies, with no sequencing
restrictions on the ADCMP605, support a wide input signal
range with greatly reduced power consumption.

The LVDS-compatible output stage is designed to drive any
standard LVDS input. The comparator input stage offers robust
protection against large input overdrive, and the outputs do not
phase reverse when the valid input signal range is exceeded. High
speed latch and programmable hysteresis features are also provided
in a unique single-pin control option.

The ADCMP604 is available in a 6-lead SC70 package, and the
ADCMP605 is available in a 12-lead LFCSP.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2007 Analog Devices, Inc. All rights reserved.

ADCMP604/ADCMP605

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Information ......................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics .............................................8

REVISION HISTORY

8/07—Rev. 0 to Rev. A

Changes to Features and General Description ............................. 1

Changes to Electrical Characteristics Section .............................. 3

Changes to Table 3............................................................................ 6

Changes to Layout............................................................................ 7

Changes to Figure 8.......................................................................... 8

Changes to Figure 14........................................................................ 9

Changes to Power/Ground Layout and Bypassing Section, and

Using/Disabling the Latch Feature Section................................. 10

Changes to Comparator Hysteresis Section................................ 11

Changes to Crossover Bias Points Section ..................................12

Changes to Ordering Guide.......................................................... 14

10/06—Revision 0: Initial Version

Application Information................................................................ 10

Power/Ground Layout and Bypassing..................................... 10

LVDS-Compatible Output Stage .............................................. 10

Using/Disabling the Latch Feature........................................... 10

Optimizing Performance........................................................... 10

Comparator Propagation Delay Dispersion ........................... 11

Comparator Hysteresis .............................................................. 11

Crossover Bias Points................................................................. 12

Minimum Input Slew Rate Requirement................................ 12

Typical Applicat i o n C i rc uits ......................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADCMP604/ADCMP605

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

V

= V

CCI

Table 1.

Parameter Symbol Conditions Min Typ Max Unit

DC INPUT CHARACTERISTICS

Voltage Range VP, V
Common-Mode Range V
Differential Voltage V
Offset Voltage V
Bias Current IP, I
Offset Current −2.0 +2.0 μA
Capacitance CP, C
Resistance, Differential Mode −0.1 V to V
Resistance, Common Mode −0.5 V to V
Active Gain A
Common-Mode Rejection Ratio CMRR

V
Hysteresis R

LATCH ENABLE PIN CHARACTERISTICS (ADCMP605 ONLY )

V
V
I

IH

I

IL

HYSTERESIS MODE AND TIMING (ADCMP605 ONLY)

Hysteresis Mode Bias Voltage Current sink −1 μA 1.145 1.25 1.40 V
Minimum Resistor Value Hysteresis = 120 mV 30 110 kΩ
Hysteresis Current Hysteresis = 120 mV −25 −8 μA
Latch Setup Time t
Latch Hold Time t
Latch-to-Output Delay t
Latch Minimum Pulse Width t

SHUTDOWN PIN CHARACTERISTICS (ADCMP605 ONLY)

V
V
I

IH

I

IL

Sleep Time t

Wake-Up Time t
DC OUTPUT CHARACTERISTICS V
V

Differential Output Voltage Level V

ΔV

Common-Mode Voltage V

Peak-to-Peak Common-Mode Output V

= 2.5 V, TA = −40°C to +125°C, typical at TA = 25 °C, unless otherwise noted.

CCO

V

N

OS

N

N

V

IH

IL

Hysteresis is shut off 2.0 V
Latch mode guaranteed −0.2 +0.4 +0.8 V
V
V

S

H

, t

PLOH

PLOLVOD

PL

IH

IL

Comparator is operating 2.0 V
Shutdown guaranteed −0.2 +0.4 +0.6 V
V
V

SD

H

OD

OD

R

OCI

OC (p-p)

= 2.5 V to 5.5 V −0.5 V

CCI

= 2.5 V to 5.5 V −0.2 V

CCI

= 2.5 V to 5.5 V V

CCI

−5.0 +5.0 mV

−5.0 ±2 +5.0 μA

1 pF

62 dB

= 2.5 V, V

V

CCI

V

= −0.2 V to +2.7 V

CM

= 2.5 V, V

CCI

= ∞ <0.1 mV

HYS

= V

IH

= 0.4 V −0.1 +0.1 mA

IL

VOD = 50 mV −2 ns
VOD = 50 mV 2.7 ns

= 50 mV 20 ns

VOD = 50 mV 24 ns

= V

IH

= 0 V −0.1 mA

IL

10% output swing 1.4 ns
VOD = 50 mV, output valid 25 ns

= V

CCI

= 2.5 V to 5.0 V (ADCMP605)

CCO

R

LOAD

LOAD

R

LOAD

R

LOAD

+ 0.2 V

CCI

+ 0.2 V

CCI

CCI

CCI

+ 0.5 V 100 370 4000 kΩ

CCI

= 2.5 V,

CCO

= 5.0 V 50 dB

CCO

+ 0.2 V −6 +6 μA

CCO

−6 +6 μA

CCO

= 2.5 V to 5.0 V (ADCMP604)

CCO

200 750 7500 kΩ

50 dB

CCO

CCO

V

V

V

= 100 Ω 245 350 445 mV
= 100 Ω 50 mV
= 100 Ω 1.125 1.375 V
= 100 Ω 50 mV

Rev. A | Page 3 of 16

ADCMP604/ADCMP605

Parameter Symbol Conditions Min Typ Max Unit

AC PERFORMANCE

Rise Time/Fall Time tR, t
Propagation Delay t

V
Propagation Delay Skew—Rising to Falling Transition t
Propagation Delay Skew—Q to QB V
Overdrive Dispersion 10 mV < VOD < 125 mV 1.6 ns
Common-Mode Dispersion VCM = −0.2 V to V
Input Bandwidth 500 MHz
Minimum Pulse Width PW

POWER SUPPLY

Input Supply Voltage Range V
Output Supply Voltage Range V
Positive Supply Differential (ADCMP605) V
V
Positive Supply Current (ADCMP604) I
Input Section Supply Current (ADCMP605) I
Output Section Supply Current (ADCMP605) I
Power Dissipation P
V
Power Supply Rejection Ratio PSRR V
Shutdown Mode I
Shutdown Mode I

1

VIN = 100 mV square input at 50 MHz, VOD = 50 mV, VCM = 1.25 V, V

1

V

CCI

CCO

F

PD

PINSKEW

MIN

CCI

CCO

− V

CCI

− V

CCI

VCCI/V CCO

VCCI

VCCO

D

V

= V

CCI

CCO

10% to 90% 600 ps
V

= V

CCI

= 50 mV

V

OD

= V

CCI

V

= V

CCI

= V

CCI

V

= V

CCI

PW

OUT

= 2.5 V to 5.0 V,

CCO

= 2.5 V, VOD = 10 mV 3.0 ns

CCO

= 2.5 V to 5.0 V 70 ps

CCO

= 2.5 V to 5.0 V 70 ps

CCO

+ 0.2 V 250 ps

CCI

= 2.5 V to 5.0 V,

CCO

= 90% of PW

IN

1.6 ns

1.3 ns

2.5 5.5 V

2.5 5.0 V
Operating −3 +3 V

CCO

Nonoperating −5.0 +5.0 V

CCO

V

= V

CCI

V

CCI

V

CCO

V

CCI

CCI

CCI

CCI

CCI

= 2.5 V, unless otherwise noted.

= 2.5 V to 5.0 V 15 21 mA

CCO

= 2.5 V to 5.5 V 1.6 3.0 mA

= 2.5 V to 5.0 V 15 23 mA

= V

= 2.5 V 37 55 mW

CCO

= V

= 5.0 V 95 120 mW

CCO

= V

= 2.5 V to 5.0 V −50 dB

CCO

= V

= 2.5 V to 5.0 V 0.92 1.1 mA

CCO

= V

= 2.5 V to 5.0 V −30 +30 μA

CCO

Rev. A | Page 4 of 16

ADCMP604/ADCMP605

TIMING INFORMATION

Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Tabl e 2 provides definitions of the terms shown in Figure 2.

1.1V

LATCH ENABLE

t

S

V

DIFFERENT IAL

INPUT VOLTAGE

Q OUTPUT

Q OUTPUT

IN

V

OD

t

PDL

t

PDH

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol Timing Description

t

PDH

Input-to-Output High Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.

t

PDL

Input-to-Output Low Delay

Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.

t

PLOH

Latch Enable-to-Output High Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.

t

PLOL

Latch Enable-to-Output Low Delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.

t

H

Minimum Hold Time

Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.

t

PL

t

S

Minimum Latch Enable Pulse Width Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum Setup Time

Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.

t

R

Output Rise Time

Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.

t

F

Output Fall Time

Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.

V

OD

Voltage Overdrive Difference between the input voltages, VA and VB. B

t

PL

t

H

± V

V

N

OS

t

PLOH

50%

t

F

50%

t

PLOL

t

R

05916-025

Rev. A | Page 5 of 16